TFP501_14 [TI]
PanelBus HDCP Digital Receiver;
| 型号： | TFP501_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PanelBus HDCP Digital Receiver |
| 文件： | 总24页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ
ꢆꢇꢈ ꢂ ꢇꢉ ꢊꢉ ꢀꢋꢌ ꢍ ꢎꢈ ꢎꢉ ꢏ ꢎ ꢍ
PanelBus
SLDS127B – JULY 2001 – REVISED AUGUST 2002
D
D
Supports UXGA Resolution (Output Pixel
Rates up to 165 MHz)
D
D
4x Over-Sampling for Reduced Bit-Error
Rates and Better Performance Over Longer
Cables
Digital Visual Interface (DVI) and
High-Bandwidth Digital Content Protection
Reduced Power Consumption From 1.8-V
Core Operation With 3.3-V I/O’s and
1
(HDCP) Specification Compliant
2
Supplies
D
D
Encrypted External HDCP Device Key
Storage for Exceptional Security and Ease
of Implementation
D
D
Reduced Ground-Bounce Using Time
Staggered Pixel Outputs
True-Color, 24 Bits/Pixel, 48-bit Dual Pixel
Output Mode, 16.7M Colors at 1 or 2 Pixels
Per Clock
Lowest Noise and Best Power Dissipation
Using TI 100-pin TQFP PowerPAD
Packaging
D
D
Laser Trimmed (50-Ω) Input Stage for
Optimum Fixed Impedance Matching
D
D
Advanced Technology Using TI’s 0.18-µm
EPIC-5 CMOS Process
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
Supports Hot Plug Detection
description
The TFP501 is a Texas Instruments PanelBus flat panel display product, part of a comprehensive family of
end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors,
and digital TVs, the TFP501 finds applications in any design requiring high-speed digital interface with the
additional benefit of an extremely robust and innovative encryption scheme for digital content protection.
The TFP501 supports display resolutions up to UXGA, including the standard HDTV formats, in 24-bit true color
pixel format. The TFP501 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN
panels, and provides an option for time staggered pixel outputs for reduced ground-bounce.
PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultra-low
ground inductance.
The TFP501 combines PanelBus circuit innovation and unique implementation for HDCP key protection with
TI’s advanced 0.18 µm EPIC-5 CMOS process technology to achieve a completely secure, reliable,
low-powered, low noise, high-speed digital interface solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Footnotes:
1. The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high–speed
digital connection to digital displays. The high–bandwidth digital content protection system (HDCP) is an industry standard for protecting
DVI outputs from being copied. HDCP was developed by Intel Corporation and is licensed by the Digital Content Protection, LLC. The
TFP501 is compliant to the DVI Rev. 1.0 and HDCP Rev. 1.0 specifications.
2. The TFP501 has an internal voltage regulator that provides the 1.8 V core power supply from the externally supplied 3.3 V supplies.
PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
TQFP PACKAGE
(TOP VIEW)
OGND
QO23
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
QO1
QO0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
OV
HSYNC
VSYNC
DE
OGND
ODCK
DD
AGND
Rx2+
Rx2–
AV
Rx1+
DD
OV
DD
Rx1–
RSVD
CTL2
CTL1
DGND
AV
Rx0+
DD
Rx0–
AV
RxC+
DV
DD
DD
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
RxC–
AV
DD
DDC_SCL
DDC_SDA
DDC_SA
PROM_SCL
PROM_SDA
PV
1
OV
DD
DD
PGND
PV
OGND
QE15
QE14
2
DD
OCK_INV
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
functional block diagram
3.3 V
3.3 V
1.8 V
Regulator
Internal 50 Ω
Termination
RED[7:0]
CTL2
RED[7:0]
CTL2
QE[23:0]
QO[23:0]
Channel 2
Channel 1
CH2[9:0]
Rx2+
Rx2-
+
_
Latch
Latch
ODCK
DE
GRN[7:0]
CTL1
GRN[7:0]
CTL1
CH1[9:0]
CH0[9:0]
HDCP
Decryption
Rx1+
Rx1-
+
_
T.M.D.S.
Decoder
Panel
Interface
SCDT
CTL2
CTL1
VSYNC
HSYNC
BLU[7:0]
VSYNC
HSYNC
BLU[7:0]
VSYNC
HSYNC
Channel 0
Rx0+
Rx0-
+
_
Latch
PLL
RxC+
RxC-
+
_
PROM_SCL
PROM_SDA
2
I C Master I/F
for EEPROM
RAM Block
Key Decryption
DDC_SCL
DDC_SDA
DDC_SA
2
2
I C Slave I/F
for DDC
I C Control
Registers
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
Terminal Functions
TERMINAL
NAME NO.
AGND
AV
I/O
DESCRIPTION
79
Analog ground—Ground reference and current return for analog circuitry.
82, 85,
88, 91
Analog V —Power supply for analog circuitry. Nominally 3.3 V.
DD
DD
CAP
67
O
O
Bypass capacitor—4.7 µF tantalum and 0.01 µF ceramic capacitors connected to ground.
CTL[2:1]
41, 40
General purpose control signals—Used for user defined control. In normal mode CTL1 is not powered down
via PDO.
2
2
DDC_SA
94
92
I
Display data channel_serial address—I C Slave address bit A0 for display data channel (DDC). Refer to I C
Interface section for more details.
2
DDC_SCL
I/O Display data channel_serial clock—I C Clock for the DDC. External pullup resistors = 10 kΩ and 3.3 V
tolerant.
2
I/O Display data channel_serial data—I C Data for the DDC. External pullup resistors = 10 kΩ and 3.3 V tolerant.
DDC_SDA
DE
93
46
O
Output data enable—Used to indicate time of active video display versus nonactive display or blanking
interval.Duringblanking, onlyHSYNC, VSYNCandCTL1–2aretransmitted. Duringtimesofactivedisplay, or
nonblanking, only pixel data, QE[23:0] and QO[23:0], is transmitted.
High: active display interval
Low: blanking interval
DFO
1
I
Outputclockdataformat—Controlstheoutputclock(ODCK)formatforeitherTFTorDSTNpanelsupport.For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; other-
wise, ODCK is held low when DE is low.
High: DSTN support/ODCK held low when DE = low.
Low: TFT support/ODCK runs continuously.
DGND
5, 39, 68
6, 38
48
Digital ground—Ground reference and current return for digital core.
DV
Digital V —Power supply for digital core. Nominally 3.3 V.
DD
DD
HSYNC
O
I
Horizontal sync output
OCK_INV
100
ODCK Polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1–2 ) are latched.
Normal mode:
High: latches output data on rising ODCK edge.
Low: latches output data on falling ODCK edge.
ODCK
OGND
44
O
Output data clock—Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with
DE, HSYNC, VSYNC and CTL[2:1] are synchronized to this clock.
19, 28,
45, 58,
76
Output driver ground—Ground reference and current return for digital output drivers.
OV
PD
18, 29,
43, 57,
78
Output driver V —Power supply for output drivers. Nominally 3.3 V.
DD
DD
2
I
I
Power down—An active low signal that controls the TFP501 power-down state. During power down all output
buffers are switched to a high-impedance state and brought low through a weak pulldown. All analog circuits
are powered down and all inputs are disabled, except for PD.
If PD is left unconnected, an internal pullup defaults the TFP501 to normal operation.
High: normal operation
Low: power down
PDO
9
Output drive power down—An active low signal that controls the power-down state of the output drivers.
During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance
state. A weak pulldown slowly pulls these outputs to a low level. When PDO is left unconnected an internal
pullup defaults the TFP501 to normal operation.
High: normal operation/output drivers on.
Low: output drive power down.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
Terminal Functions (Continued)
TERMINAL
NAME NO.
PGND
I/O
DESCRIPTION
98
4
PLL ground – Ground reference and current return for internal PLL.
PIXS
I
Pixel select—Selects between one or two pixel per clock output modes. During 2-pixel/clock mode, both even
pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1 pixel/clock,
even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus,
QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.)
High: 2 pixel/clock
Low: 1 pixel/clock
2
PROM_SCL
PROM_SDA
95
96
I/O EEPROM_serial clock—I C clock for EEPROM interface data. External pullup resistors = 10 kΩ and 3.3 V
tolerant.
2
I/O EEPROM_serial data—I C data for EEPROM interface data. External pullup resistors = 10 kΩ and 3.3 V
tolerant.
PV
DD
(1, 2)
97, 99
PLL V —Power supply for internal PLL. Nominally 3.3 V.
DD
QE[0:7]
10–17
O
O
O
O
O
O
Even blue pixel output—Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
QE[8:15]
QE[16:23]
QO[0:7]
20–27
30–37
49–56
59–66
Even green pixel output—Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8/pin 20
MSB: QE15/pin 27
Even red pixel output—Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
Odd blue pixel output—Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
QO[8:15]
QO[16:23]
Odd green pixel output—Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
69–75,
Odd red pixel output—Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
77
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
RSVD
Rx2+
42
80
O
I
Reserved—Must be tied high for normal operation.
Channel-2 positive receiver input—Positive side of channel-2 T.M.D.S. low voltage signal differential input
pair. Channel-2 receives red pixel data in active display and CTL2 control signal during blanking.
Rx2–
Rx1+
Rx1–
Rx0+
Rx0–
81
83
84
86
87
I
I
I
I
I
Channel-2 negative receiver input—Negative side of channel-2 T.M.D.S. low voltage signal differential input
pair.
Channel-1 positive receiver input—Positive side of channel-1 T.M.D.S. low voltage signal differential input
pair. Channel–1 receives green pixel data in active display and CTL1 control signal during blanking.
Channel-1 negative receiver input—Negative side of channel-1 T.M.D.S. low voltage signal differential input
pair.
Channel-0 positive receiver input—Positive side of channel-0 T.M.D.S. low voltage signal differential input
pair. Channel-0receivesbluepixeldatainactivedisplayandHSYNC, VSYNCcontrolsignalsduringblanking.
Channel-0 negative receiver input—Negative side of channel-0 T.M.D.S. low voltage signal differential input
pair.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
Terminal Functions (Continued)
TERMINAL
NAME NO.
RxC+
I/O
DESCRIPTION
89
90
8
I
Clock positive receiver input—Positive side of reference clock T.M.D.S. low voltage signal differential input
pair.
RxC–
I
Clock negative receiver input—Negative side of reference clock T.M.D.S. low voltage signal differential input
pair.
SCDT
O
Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is
activelyswitching. TheTFP501monitorsthestateDEtodeterminelinkactivity. SCDTcanbetiedexternallyto
PDO to power down the output drivers when the link is inactive.
High: active link
Low: inactive link
ST
3
7
I
I
Outputdrivestrengthselect—Selectsoutputdrivestrengthforhighorlowcurrentdrive. (seedcspecifications
for I
and I
vs ST state.)
OL
OH
High: high drive strength
Low: low drive strength
STAG
Staggeredpixel select– An active low signal used in 2 pixel/clock pixel mode (PIXS = high). Timestaggersthe
even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
High: normal simultaneous even/odd pixel output.
Low: time staggered even/odd pixel output.
VSYNC
47
O
Vertical sync output
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, DV , AV , OV , PV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
DD
DD
DD
DD
Input voltage, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD protection, all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Human Body Model
JEDEC latch-up (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX
3.6
40
UNIT
V
Supply voltage, V
DD
(DV , AV , OV , PV
DD DD DD DD
)
3
6.06
45
3.3
Pixel time, t
(see Note 1)
ns
(pixel)
Single-ended analog input termination resistance, R (see Note 2)
50
25
55
Ω
T
Operating free-air temperature, T
0
70
°C
A
NOTES: 1. t
(pixel)
is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to t when
(pixel)
in 1-pixel/clock mode and 2 t
when in 2-pixel/clock mode.
(pixel)
2. The TFP501 is internally optimized using a laser trim process to precisely fix the single-ended termination impedance, R , to 50 Ω
T
±10%.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
dc digital I/O specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High level digital input voltage (CMOS Inputs)
(see Note 3)
V
V
0.7 V
V
IH
DD
Low level digital input voltage (CMOS Inputs)
(see Note 3)
0.3 V
V
V
IL
DD
DV
OH
= 3 V,
ST = High,
ST = Low,
ST = High,
ST = Low
DD
= – 5 mA
2.4
2.4
I
V
V
High level digital output voltage (see Note 4)
Low level digital output voltage (see Note 4)
OH
DV
OH
= 3 V,
DD
= – 3 mA
I
DV
= 3.6 V,
= 10 mA
DD
0.4
0.4
I
OL
V
OL
DV
OL
= 3.6 V,
= 5 mA
DD
I
ST = High,
ST = Low,
ST = High,
ST = Low,
V
V
V
V
= 2.4V
= 2.4V
= 0.4V
= 0.4V
–5
–3
10
5
–12
–7
13
7
–18
–12
19
mA
mA
mA
mA
µA
OH
OH
OL
OL
I
I
High level output drive current (see Note 4)
Low level output drive current (see Note 4)
OH(D)
OL(D)
11
I
I
I
High level digital input current (see Note 3)
Low level digital input current (see Note 3)
Hi-Z output leakage current
V
V
= DV
= 0.0
±20
±60
±20
IH
IH
DD
µA
IL
IL
PD = Low or PDO = Low
µA
OZ
NOTES: 3. Digital inputs are labeled I in I/O column of Terminal Functions Table.
4. Digital outputs are labeled O in I/O column of Terminal Functions Table.
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
V
V
V
Analog input differential voltage (see Note 5)
Analog input common mode voltage (see Note 5)
Open circuit analog input voltage
150
1200
ID(1)
AV –0.3
DD
AV –0.037
DD
IC
AV –0.01
DD
AV +0.01
DD
V
I(OC)
ODCK = 82.5 MHz
2-pix/clock
I
Normal 2-pix/clock power supply current (see Note 7)
460
10
mA
DD(2PIX)
I
I
Power down current (see Note 6)
PD = Low
mA
mA
(PD)
Output drive power down current (see Note 6)
PDO = Low
35
(PDO)
NOTES: 5. Specified as dc characteristic with no overshoot or undershoot.
6. Analog inputs are open circuit (transmitter is disconnected from TFP501.)
7. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE{23:0] and Q0[23:0] C = 10 pF.
L
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
Differential input sensitivity (see Note 8)
Maximum differential input
150
mVp–p
ID(2)
1560 mVp–p
ID(3)
Analog input intra–pair (+ to –) differential
skew (see Note 12)
0.4
t
ns
sk(D)
†
t
(bit)
Analog input inter–pair or channel to channel
skew (see Note 12)
1.0
t
(pixel)
t
ns
sk(CC)
‡
Worst case differential input clock jitter
tolerance (see Note 9 and 12)
112 MHz, 1 pixel/clock
200
ps
ns
ns
ns
ns
ST = Low,
ST = High,
ST = Low,
ST = High,
ST = Low,
ST = High,
ST = Low,
ST = High,
C
C
C
= 10 pF
= 10 pF
= 10 pF
1.9
Rise time of data and control signals (see
Notes 10 and 11)
L
L
L
t
t
t
t
r(1)
f(1)
r(2)
f(2)
1.9
1.9
1.9
1.9
1.9
1.9
1.9
Fall time of data and control signals
(see Notes 10 and 11)
CL = 10 pF
= 10 pF
C
L
Rise time of ODCK clock (see Note 10)
Fall time of ODCK clock (see Note 10)
CL = 10 pF
= 10 pF
C
L
CL = 10 pF
1 pixel/clock
PIXS = Low
ST=Low, C =10 pF
1.2
1.2
2.7
L
ns
ns
OCK_INV = Low
ST=High, C =10 pF
L
2 pixel/clock
PIXS = High
ST=Low, C =10 pF
L
Setup time, data and control signal to falling
edge of ODCK (see Note 11)
t
su(1)
STAG = High
OCK_INV = Low
ST=High, C =10 pF
2.7
1.7
1.7
L
2 pixel & STAG
PIXS = High
ST=Low, C =10 pF
L
ns
ns
ns
STAG = Low
OCK_INV = Low
ST=High, C =10 pF
L
1 pixel/clock
PIXS = Low
ST=Low, C =10 pF
0.9
0.9
2.9
L
OCK_INV = Low
ST=High, C =10 pF
L
Hold time, data and control signal to falling
edge of ODCK (see Note 11)
t
h(1)
2 pixel and STAG
PIXS = High
ST=Low, C =10 pF
L
STAG = Low
OCK_INV = Low
ST=High, C =10 pF
2.9
L
†
‡
t
t
is 1/10 the pixel time, t
(pixel)
(pixel)
(bit)
is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t
in 1-pixel/clock mode or 2 t
when
(pixel)
(pixel)
in 2-pixel/clock mode.
NOTES: 8. Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
9. Measured differentially at 50% crossing using ODCK output clock as trigger.
10. Rise and fall times measured as time between 20% and 80% of signal amplitude.
11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
12. By characterization
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
ac specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
1.9
1.9
2.9
TYP
MAX
UNIT
1 pixel/clock
PIXS = Low
ST=Low, C =10 pF
L
ns
OCK_INV = High ST=High, C =10 pF
L
2 pixel/clock
PIXS = High
ST=Low, C =10 pF
L
Setup time, data and control signal to
rising edge of ODCK (see Note 11)
ns
t
STAG = High
OCK_INV = High
su(2)
ST=High, C =10 pF
2.9
2.0
2.0
L
2 pixel & STAG
PIXS = High
ST=Low, C =10 pF
L
ns
ns
STAG = Low
OCK_INV = High
ST=High, C =10 pF
L
1 pixel/clock
PIXS = Low
ST=Low, C =10 pF
0.5
0.5
1.4
L
OCK_INV = High ST=High, C =10 pF
L
Hold time, data and control signal to rising
edge of ODCK (see Note 11)
t
f
2 pixel & STAG
PIXS = High
h(2)
ST=Low, C =10pF
L
ns
STAG = Low
OCK_INV = High
ST=High, C =10pF
1.4
L
PIXS = Low
PIXS = High
25
12.5
40%
165
82.5
60%
18
ODCK frequency
MHz
(ODCK)
ODCK duty-cycle
50%
t
t
Delay from PD low to Hi-Z outputs
Delay from PDO low to Hi-Z outputs
ns
ns
d(PDL)
18
d(PDOL)
Time between DE transitions to SCDT low
(see Note 13)
t
t
t
165 MHz
25
8
ms
(HSC)
t(FSC)
d(st)
Time from DE low to SCDT high (see Note
13)
trans
(DE)†
ODCK latching edge to QE[23:0] data
output
0.5
STAG = Low, PIXS = High
ns
t
(pixel)
†
trans
is one transition (low-to-high or high-to-low) of the DE signal.
NOTES: 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
(DE)
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
timing diagrams
t
t
f(2)
t
t
r(2)
r(1)
f(1)
80%
80%
80%
20%
80%
20%
QE[23:0], QO[23:0], DE,
CTL[2:1], HSYNC, VSYNC
ODCK
20%
20%
Figure 2. Rise and Fall Time of Data and Control Signals
Figure 1. Rise and Fall Time of ODCK
f
(ODCK)
ODCK
Figure 3. ODCK Frequency
t
t
su(2)
su(1)
t
t
h(2)
h(1)
V
V
OH
OH
ODCK
V
OL
V
OL
V
V
V
V
OH
QE[23:0], QO[23:0], DE,
CTL[2:1], HSYNC, VSYNC
OH
OH
OH
V
V
V
V
OL
OL
OL
OL
OCK_INV
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
V
OH
ODCK
t
sk(D)
t
d(st)
Tx+
Tx-
50%
QE[23:0]
50%
Figure 5. ODCK High to QE[23:0] Staggered
Data Output
Figure 6. Analog Input Intra-Pair
Differential Skew
PDO
PD
V
IL
V
IL
t
d(PDOL)
t
d(PDL)
QE[23:0], QO[23:0],
ODCK, DE, CTL[2:1],
HSYNC, VSYNC
QE[23:0], QO[23:0],
ODCK, DE, CTL[2:1],
HSYNC, VSYNC, SCDT
Figure 7. Delay From PD Low to Hi-Z Outputs
Figure 8. Delay From PDO Low to Hi-Z Outputs
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
timing diagrams (continued)
V
IH
PD
t
d(PDLM)
t
d(PDLA)
DFO, ST, PIXS, STAG,
Rx[2:0]+, Rx[2:0]–,
OCK_INV
V
IL
PD
Figure 10. Minimum Time PD Low
Figure 9. Delay From PD Low to High Before
Inputs Are Active
TX2
TX1
50%
t
sk(CC)
50%
TX0
Figure 11. Analog Input Channel-to-Channel Skew
t
t
(FSC)
(HSC)
DE
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
fundamental operation
The TFP501 is a DVI digital receiver that is used in digital display systems to receive and decode T.M.D.S.
encoded RGB pixel data streams. High-bandwidth digital content protection (HDCP) receiver functionality
provides decryption of the DVI input data streams encrypted at the transmitter, such as TI’s TFP510 HDCP
transmitter, to prevent unauthorized viewing or coping of digital content. In a digital display system a host,
usually a PC or consumer electronics device, contains a DVI compatible transmitter that receives 24-bit pixel
data along with appropriate control signals. The HDCP TFP510 transmitter encrypts and encodes the signals
into a high-speed, low-voltage, differential serial bit stream optimized for transmission over a twisted-pair cable
to a display device. The display device, usually a flat-panel monitor, requires a DVI and HDCP compatible
receiver like the TI TFP501 to decode and decrypt the serial bit stream back to the same 24-bit pixel data and
control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive
circuitry to produce an image on the display. Since the host and display can be separated by distances up to
five meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions
up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required.
T.M.D.S. pixel data and control signal encoding
T.M.D.S. stands for transition minimized differential signaling. Only one of two possible T.M.D.S. characters for
a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and
zeros previously sent, transmits the character that minimizes the number of transitions, and approximates a dc
balance of the transmission line.
Three T.M.D.S. channels are used to receive RGB pixel data during active display time, DE = High. These same
three channels are also used to receive HSYNC, VSYNC, CTL3, and two user definable control signals,
CTL[2:1], during inactive display or blanking interval (DE = Low). The following table maps the received input
data to the appropriate T.M.D.S. input channel in a DVI-compliant system.
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH
Output Pins
(Valid for DE = High)
T.M.D.S. INPUT CHANNEL
Channel – 2 (Rx2 ±)
Red[7:0]
QE[23:16] QO[23:16]
Green[7:0]
Blue[7:0]
Channel – 1 (Rx1 ±)
Channel – 0 (Rx0 ±)
QE[15:8] QO[15:8]
QE[7:0] QO[7:0]
RECEIVED CONTROL DATA
BLANKING DE = LOW
OUTPUT PINS
(VALID FOR DE = LOW)
T.M.D.S. INPUT CHANNEL
CTL[3:2] (see Note 13)
Channel – 2 (Rx2 ±)
Channel – 1 (Rx1 ±)
Channel – 0 (Rx0 ±)
CTL2
CTL1
CTL[1:0] (see Note 13)
HSYNC, VSYNC
HSYNC, VSYNC
NOTE 14: SomeDVI transmitterstransmitaCTL0signal. TheTFP501decodesandtransfersCTL[2:1]andignoresCTL0characters. CTL3
is used internally to enable HDCP decryption. CTL3 and CTL0 are not available as TFP501 outputs.
The TFP501 discriminates between valid pixel T.M.D.S. characters and control T.M.D.S. characters to
determine the state of active display vs blanking, i.e., state of DE.
high-bandwidth digital content protection (HDCP) overview
TI’s HDCP transmitters and receivers use up to three cipher engines to protect information that may be
externally accessible to the user.
The downstream encryption described in the specification high-bandwidth digital content protection system
Revision 1.0 is used to protect video data passing from the HDCP transmitter to the HDCP receiver via a DVI
link. The HDCP transmitter encrypts video data and the receiver decrypts the data as shown in Figure 13.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
high-bandwidth digital content protection (HDCP) overview (continued)
The HDCP keys must also be protected from access. TI has chosen to avoid the inconvenience and possible
circuit board damage from using epoxy or other barriers between the EEPROM and DVI receiver. An encryption
scheme is used to protect the HDCP device key values passing from an off-chip EEPROM to the HDCP receiver
2
via a dedicated I C interface. When the HDCP device keys are needed, the encrypted values are read from the
EEPROM,decrypted, andusedtoenableHDCPfunctionality. TI’sHDCPsolutionprovidesrealadvantageswith
respect to lower systems level cost, ease of implementation, high performance, and exceptional security.
S/W
TFP510
TFP501
Application
Program
DVI-HDCP TX
(PC’s DVI Output)
DVI-HDCP RX
(Display’s DVI Input)
Encrypted Keys
A Keys and KSV
D Keys and KSV
Upstream
Decrypt
Encrypted Keys
B Keys and KSV
PROM
PROM
C Keys and KSV
2
I C
2
I C
Input
Stream
HDCP Encrypted
TMDS Link
Output
Stream
Key
Key
DE
Decrypt
Channel 2
Channel 1
Channel 0
Channel C
Decrypt
DE
CPU
and
North
Pixel Data
Clock
Pixel Data
Clock
Bridge
and
Graphics
Controller
2
Upstream
Encrypt
I C
Slave I/F
2
I C
2
I C
Encrypted M
0
EDID
PROM
Control and Authentication and Key Exchange
KSV = Key Selection Vector
= 64-Bit Secret Value
M
0
Figure 13. TI’s HDCP Implementation for PC and Display System
TFP501 clocking and data synchronization
The TFP501 receives a clock reference from the DVI transmitter, such as the TFP510, that has a period equal
to the pixel time, t . The frequency of this clock is also referred to as the pixel rate. Since the T.M.D.S.
(pixel)
encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the
pixel rate. For example, the required pixel rate to support an UXGA resolution with 60 Hz refresh rate is
165 MHz. TheT.M.D.S. serialbitrateis10xthepixelrateor1.65Gb/s. Duetothetransmissionofthishighspeed
digital bit stream on three separate channels (or twisted-pair wires) of long distances (3–5 meters), phase
synchronization between the data steams and the input reference clock is not assured. In addition, skew
between the three data channels is common. The TFP501 uses a 4x oversampling scheme of the input data
streams to achieve reliable synchronization with up to 1-T
channel-to-channel skew tolerance.
(pixel)
Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of
high-speed serial data transmission. The TFP501 is designed for high jitter tolerance.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
TFP501 clocking and data synchronization (continued)
The input clock to the TFP501 is conditioned by a PLL (phase-locked-loop) to remove high frequency jitter from
the clock. The PLL provides four 10x clock outputs of different phases to locate and sync the T.M.D.S. data
streams (4x oversampling). During the active display interval, the pixel data is encoded to be transition
minimized; whereas, during the blanking interval, the control data is encoded to be transition maximized. A
DVI-compliant transmitter is required to transmit during the blanking interval for a minimum period of time,
128-t
, to ensure sufficient time for data synchronization when the receiver sees a transition maximized
(pixel)
code. Performing synchronization during the blanking interval, when the data is transition maximized, assures
reliable data bit boundary detection. Phase synchronization to the data streams is unique for each of the three
input channels and is maintained as long as the link remains active.
TFP501 T.M.D.S. input levels and input impedance matching
The T.M.D.S. inputs to the TFP501 receiver have a fixed single-ended input termination impedance to AV
.
DD
The TFP501 is internally optimized using a laser trim process to precisely fix the single-ended termination
impedance at 50 Ω. This fixed impedance eliminates the need for external termination resistors while providing
optimum impedance matching to standard DVI cables having a characteristic impedance of 100 Ω.
Figure 14 shows a conceptual schematic of a TFP510 transmitter and TFP501 receiver connection. The
TFP510 transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain type
output driver. The internal single-ended termination resistors, which are matched to the characteristic
impedance of the DVI cable, provide a pullup to AV . Naturally, when the transmitter is disconnected and the
DD
TFP501 DVI inputs are left unconnected, the TFP501 receiver inputs are pulled up to AV . The single-ended
DD
differential signal and full differential signal is shown in Figure 15. The TFP501 is designed to respond to
differential signal swings ranging from 150 mV to 1.56 V with common mode voltages ranging from
(AV –300 mV) to (AV –37 mV).
DD
DD
TI TFP510 Transmitter
TI TFP501 Receiver
AV
CC
DVI-Compliant Cable
Internal
Termination at 50 Ω
DATA
DATA
+
_
Current
Source
Figure 14. T.M.D.S. Differential Input and Transmitter Connection
V
ID
+ 1/2 V
ID
ID
1/2 V
ID
AV
CC
AV
CC
- 1/2 V
ID
- 1/2 V
b) Differential Input Signal
a ) Single-Ended Input Signal
Figure 15. T.M.D.S. Inputs
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
TFP501 modes of operation
The TFP501 provides system design flexibility and value by providing the system designer with configurable
options or modes of operation to support varying system architectures. The following table outlines the various
panel modes that can be supported along with appropriate external control pin settings.
PANEL
TFT or 16-bit DSTN
TFT or 16-bit DSTN
TFT
PIXEL RATE
1 pixel/clock
1 pixel/clock
2 pixel/clock
2 pixel/clock
1 pixel/clock
1 pixel/clock
2 pixel/clock
2 pixel/clock
ODCK LATCH EDGE
Falling
ODCK
Free run
DFO
PIXS
OCK_INV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Rising
Free run
Falling
Free run
TFT
Rising
Free run
24-bit DSTN
None
Falling
Gated Low
Gated Low
Gated Low
Gated Low
Rising
24-bit DSTN
24-bit DSTN
Falling
Rising
TFP501 output driver configurations
The TFP501 provides flexibility by offering various output driver features that can be used to optimize power
consumption, ground-bounce and power-supply noise. The following sections outline the output driver features
and their effects.
Output driver power down(PDO = low.) Pulling PDO low places all the output drivers, except CTL1 and SCDT,
into a high-impedance state. A weak pulldown (approximately 10 µA) gradually pulls these high-impedance
outputs to a low level to prevent the outputs from floating. The SCDT output, which indicates link-disabled or
link-inactive, can be tied directly to the PDO input to disable the output drivers when the link is inactive or when
the cable is disconnected. An internal pullup on the PDO pin defaults the TFP501 to the normal nonpower-down
output drive mode if left unconnected.
Drive strength (ST = high for high drive strength, ST = low for low drive strength.) The TFP501 allows for
selectable output drive strength on the data, control, and ODCK outputs. See the dc specifications table for the
valuesofI
andI currentdrivesforagivenSTstate. Thehighoutputstrengthoffersapproximatelytwotimes
OH
OL
the drive as the low output drive strength.
Time staggered pixel output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high.)
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 T
. (T
is the period of ODCK. The ODCK
(ODCK)
(ODCK)
period is 2 t
when in 2-pixel/clock mode.)
(pixel)
Dependingonsystemconstraintsofoutputload, pixelrate, panelinputarchitecture, andboardcost, theTFP501
drive strength and staggered pixel options allow flexibility to reduce system power supply noise, ground bounce
and EMI.
Power management. The TFP501 offers several system power management features. The output driver
power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers
exceptSCDTandCTL1aredriventoahigh-impedancestatewhiletherestofthedevicecircuitryremainsactive.
The TFP501 power down (PD = low) is a complete power down in that it powers down the digital core, the analog
circuitry and output drivers. All output drivers are placed into a high-impedance state. All inputs are disabled
except for the PD input. The TFP501 does not respond to any digital or analog inputs until PD is pulled high.
Both PDO and PD have internal pullups so if left unconnected they default the TFP501 to normal operating
modes.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
TFP501 output driver configurations (continued)
Sync detect. The TFP501 offers an output, SCDT, to indicate link activity. The TFP501 monitors activity on DE
to determine if the link is active. When 1 million pixel clock periods pass without a transition on DE, the TFP501
considers the link inactive and SCDT is driven low. SCDT goes high immediately after the first eight transitions
18
on DE. SCDT again goes low when no more transitions are seen after 2 oscillator clocks.
SCDT can be used to signal a system power management circuit to initiate a system power down when the link
is considered inactive. The SCDT can also be tied directly to the TFP501 PDO input to power down the output
drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in
complete power down, the analog inputs are ignored and the SCDT state does not change. An external, system
power management circuit to drive PD is preferred.
HDCP register map
2
2
TFP501 is a standard I C slave device. All the registers can be written and read through the I C interface. The
2
I C base address of TFP501 is dependent on pin 10 (A0) as shown below.
Pin 10
Write Address (Hex)
Read Address (Hex)
0
1
74
76
75
77
2
I C register map
BKSV
Subaddress = 00
Read Only
7
6
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
BKSV[7:0]
Subaddress = 01
Read Only
7
7
7
7
6
5
BKSV[15:8]
Subaddress = 02
Read Only
6
5
BKSV[23:16]
Subaddress = 03
Read Only
6
5
BKSV[31:24]
Subaddress = 04
Read Only
6
5
BKSV[39:32]
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
2
I C register map (continued)
Video receiver KSV. This value may be used to determine that the video receiver is HDCP capable. Valid KSVs
contain 20 ones and 20 zeros, a characteristic that is verified by video transmitter hardware before encryption
is enabled.
Ri’
Subaddress = 08
Read Only
7
6
5
4
3
2
1
0
Ri’ [7:0]
Subaddress = 09
Read Only
7
6
5
4
3
2
1
0
Ri’ [15:8]
th
Linkverificationresponse. Updatedevery128 frame. Itisrecommendedthatgraphicssystemsprotectagainst
2
errors in the I C transmission by re-reading this value when unexpected values are received. This value is
available at all times between updates.
AKSV
Subaddress = 10
Read/Write
Default = 00
Default = 00
Default = 00
Default = 00
Default = 00
7
7
7
7
7
6
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
AKSV[7:0]
Subaddress = 11
Read/Write
6
5
AKSV[15:8]
Subaddress = 12
Read/Write
6
5
AKSV[23:16]
Subaddress = 13
Read/Write
6
5
AKSV[31:24]
Subaddress = 14
Read/Write
6
5
AKSV[39:32]
Video transmitter KSV. Writing to 0x14 triggers the authentication sequence in the device.
An
Subaddress = 18
Read/Write
Default = 00
Default = 00
Default = 00
7
7
7
6
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
An[7:0]
Subaddress = 19
Read/Write
6
5
An[15:8]
Subaddress = 1A
Read/Write
6
5
An[23:16]
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
2
I C register map (continued)
Subaddress = 1B
Read/Write
Default = 00
Default = 00
Default = 00
Default = 00
Default = 00
7
7
7
7
7
6
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
An[31:24]
Subaddress = 1C
Read/Write
6
5
An[39:32]
Subaddress = 1D
Read/Write
6
5
An[47:40]
Subaddress = 1E
Read/Write
6
5
An[55:48]
Subaddress = 1F
Read/Write
6
5
An[63:56]
Session random number. This multibyte value must be written by the graphics system before the KSV is written.
Bcaps
Subaddress = 40
Read Only
Default = 10
7
6
5
4
3
2
1
0
Rsvd
Repeater
KSV-FIFO
Fast
Rsvd
Rsvd
Rsvd
Rsvd
Bit 6: REPEATER, Video repeater capability. This device is not a repeater. Read as ZERO.
Bit 5: READY, KSV FIFO ready. This device does not support repeater capability. Read as ZERO.
Bit 4: FAST. This device supports 400 kHz transfers. Read as ONE.
Bstatus
Subaddress = 41
Read Only
Default = 00
7
6
5
4
3
2
1
0
0
Bstatus[7:0]
Subaddress = 42
Read Only
Default = 00
7
6
5
4
3
2
1
Bstatus[15:8]
Bstatus. This device does not support repeater capability. All bytes read as 0x00.
KSV_FIFO
Subaddress = 43
Read Only
Default = 00
7
6
5
4
3
2
1
0
KSV_FIFO
Key selection vector FIFO. This device is not a repeater. All bytes read as 0x00.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
2
I C register map (continued)
VEN_ID
Subaddress = C0
Read Only
Default = 4C
7
6
5
4
4
3
3
2
2
1
1
0
0
VEN_ID[7:0]
Subaddress = C1
Read Only
Default = 01
7
6
5
VEN_ID[15:8]
This read-only register contains the 16-bit Texas Instruments vendor ID for the TFP501. VEN_ID[15:0] is
hardwired to 0x014C.
DEV_ID
Subaddress = C2
Read Only
Default = 01
7
6
5
4
3
2
1
0
DEV_ID[7:0]
Subaddress = C3
Read Only
Default = 05
7
6
5
4
3
2
1
0
DEV_ID[15:8]
This read-only register contains the 16-bit device ID for the TFP501. DEV_ID[15:0] is hardwired to 0x0501.
REV_ID
Subaddress = C4
Read Only
Default = 01
7
6
5
4
3
2
1
0
REV_ID[7:0]
This read-only register contains the 8-bit revision ID for the TFP501. REV_ID[7:0] is hardwired to 0x01.
2
I C interface
2
The I C interface is used to access the internal TFP501 registers. This two-pin interface consists of one clock
2
line, DDC_SCL, and one serial data line, DDC_SDA. The basic I C access cycles are shown in Figures 16
and 17.
DDC_SDA
DDC_SCL
Start Condition (S)
Stop Condition (P)
2
Figure 16. I C Start and Stop Conditions
The basic access cycle consists of the following:
D
D
D
D
D
A start condition
A slave address cycle
A subaddress cycle
Any number of data cycles
A stop condition
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
2
I C interface (continued)
The start and stop conditions are shown in Figure 16. The high to low transition of DDC_SDA while DDC_SCL
is high defines the start condition. The low to high transition of DDC_SDA while DDC_SCL is high defines the
stop condition. Each cycle, (data or address) consists of 8 bits of serial data followed by one acknowledge bit
generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 17.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
DDC_SCL
DDC_SDA
Stop
MSB
Slave Address
Sub Address
2
Data
Figure 17. I C Access Cycles
2
Following a start condition, each I C device decodes the slave address. The TFP501 responds with an
acknowledge by pulling the DDC_SDA line low during the ninth clock cycle if it decodes the address as its
address. During subsequent subaddress and data cycles the TFP501 responds with acknowledge as shown
in Figure 18. The subaddress is autoincremented after each data cycle.
The transmitting device must not drive the DDC_SDA signal during the acknowledge cycle so that the receiving
device may drive the DDC_SDA signal low. The not acknowledge, A, condition is indicated by the master by
keeping the DDC_SDA signal high just before it asserts the stop, P, condition. This sequence terminates a read
cycle as shown in Figure 19.
The slave address consists of 7 bits of address along with 1 bit of read/write information as shown below in
Figures 18, 19, and 20. For the TFP501, the possible slave addresses (including the r/w bit) are 0x74, 0x76 for
write cycles and 0x75 and 0x77 for read cycles. Refer to the register description section for additional base
address information.
In order to minimize the number of bits that must be transferred for the link integrity check, a second read format
is supported. This format, shown in Figure 20, has an implicit subaddress equal to 0x08, the starting location
of R ’.
i
S
Slave Address
W
A
Sub Address
A
Data
A
Data
A
P
A
S
Acknowledge
Start Condition
Stop Condition
Write
From Transmitter
From Receiver
P
W
2
Figure 18. I C Write Cycle
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
2
I C interface (continued)
S
Slave Address
W
A
Sub Address
A
Sr Slave Address
R
A
Data
A
Data
A
P
A
S
P
Acknowledge
Start Condition
Stop Condition
W
R
Write
Read
From Transmitter
From Receiver
Sr Restart Condition
A
Not Acknowledge (SDA High)
2
Figure 19. I C Read Cycle
S
Slave Address
R
A
Data
A
Data
A
P
A
S
P
R
Acknowledge
From Transmitter
From Receiver
Start Condition
Stop Condition
Read
A
Not Acknowledge (SDA High)
Figure 20. HDCP Port Link Integrity Message Read
PowerPAD 100-pin TQFP package
The TFP501 is packaged in TI’s thermally enhanced PowerPAD 100-pin TQFP packaging. The PowerPAD
package is a 14 mm × 14 mm × 1 mm TQFP outline with 0.5mm lead-pitch. The PowerPAD package has a
specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the
same outline. The TI 100-pin TQFP PowerPAD package offers a backside solder plane that connects directly
to the die mount pad for enhanced thermal conduction. Soldering the backside of the TFP501 to the application
board is not required thermally, as the device power dissipation is well within the package capability when not
soldered.
Soldering the backside of the device to the PCB ground plane is recommended for electrical considerations.
Since the die pad is electrically connected to the chip substrate and hence chip ground, connection of the
PowerPAD back side to a PCB ground plane helps to improve EMI, ground bounce, and power supply noise
performance.
The following table outlines the thermal properties of the TI 100-pin TQFP PowerPAD package. The 100-pin
TQFP non-PowerPAD package is included only for reference.
Table 1. TI 100-Pin TQFP (14 × 14 × 1 mm)/0.5 mm Lead Pitch
PowerPAD
NOT CONNECTED
TO PCB THERMAL
PLANE
PowerPAD
CONNECTED TO PCB
THERMAL PLANE
(see Note 14)
WITHOUT
PowerPAD
PARAMETER
R
R
P
Junction-to-ambient thermal resistance (see Notes 14 and 15)
Junction-to-case thermal resistance (see Notes 14 and 15)
Package power dissipation (see Notes 14, 15 and 16)
49.17°C/W
3.11°C/W
1.6 W
27.32°C/W
0.12°C/W
2.9 W
17.28°C/W
0.12°C/W
4.6 W
θJA
θJC
D
NOTES: 15. Specified with the PowerPAD bond pad on the backside of the package soldered to a 2 oz Cu plate PCB thermal plane.
16. Airflow is at 0 LFM (no airflow).
17. Specified at 150°C junction temperature and 70°C ambient temperature.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL PAD MECHANICAL DATA
PowerPAD™ PLASTIC QUAD FLATPACK
PZP (S-PQFP-G100)
www.ti.com
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B – JULY 2001 – REVISED AUGUST 2002
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
M
0,50
75
0,08
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
0,25
0,15
15,80
0°–ā7°
0,05
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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