THP210DGKT [TI]
THP210 Ultra-Low Offset, High-Voltage, Low-Noise, Precision, Fully-Differential Amplifier;
| 型号： | THP210DGKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | THP210 Ultra-Low Offset, High-Voltage, Low-Noise, Precision, Fully-Differential Amplifier |
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THP210
SBOS932B – FEBRUARY 2020 – REVISED OCTOBER 2020
THP210 Ultra-Low Offset, High-Voltage, Low-Noise, Precision,
Fully-Differential Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input offset voltage: ±40 µV (maximum)
The THP210 is an ultra-low-offset, low-noise, high-
voltage, precision, fully differential amplifier that easily
filters and drives fully differential signal chains. The
THP210 is also used to convert single-ended sources
to differential outputs as required by high-resolution
analog-to-digital converters (ADCs). Designed for
exceptional offset, low noise and THD, the bipolar
super-beta inputs yield a very-low noise figure at very-
low quiescent current and input bias current. This
device is designed for signal conditioning circuits
where low power offset and power consumption are
required, along with excellent signal-to-noise ratio
(SNR).
Input offset voltage drift: 0.35 µV/°C (maximum)
Low supply current: 950 µA at ±18 V
Low input bias current: 2 nA (maximum)
Low input bias current drift: 15 pA/°C (maximum)
Gain-bandwidth product: 9.2 MHz
Differential output slew rate: 15 V/µs
Low input voltage noise: 3.7 nV/√ Hz at 1 kHz
Low THD + N: –120 dB at 10 kHz
Wide input and output common-mode range
Wide single-supply operating range: 3 V to 36 V
Low supply current power-down feature: < 20 µA
Overload power limit
The THP210 features high-voltage supply capability,
allowing for supply voltages up to ±18 V. This
capability allows high-voltage differential signal chains
to benefit from the improved headroom and dynamic
range without adding separate amplifiers for each
polarity of the differential signal. Very-low voltage and
current noise enables the THP210 for use in high-gain
configurations with minimal impact to the signal
fidelity.
Current limit
Package: 8-pin VSSOP, 8-pin SOIC
Temperature range: –40°C to +125°C
2 Applications
•
•
•
•
•
Data acquisition (DAQ)
Analog input module
Substation automation
Semiconductor test
Device Information (1)
PART NUMBER
PACKAGE
VSSOP (8)
SOIC (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
4.9 mm x 3.91 mm
Lab and field instrumentation
THP210
(1) For all available packages, see the package option
addendum at the end of the datasheet.
40
35
30
25
20
15
10
5
+V
AINN
AINP
+
œ
ADC
THP210
+
œ
Precision, Low-Noise, Low-Power, Fully-
Differential Amplifier Gain Block and Interface
0
-50 -40 -30 -20 -10
0
10
20
30
40
50
D010
VIO (µV)
Low Input Voltage Offset
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THP210
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SBOS932B – FEBRUARY 2020 – REVISED OCTOBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................8
7 Parameter Measurement Information..........................15
7.1 Characterization Configuration................................. 15
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Applications.................................................. 27
10 Power Supply Recommendations..............................32
11 Layout...........................................................................33
11.1 Layout Guidelines................................................... 33
11.2 Layout Example...................................................... 33
12 Device and Documentation Support..........................34
12.1 Device Support....................................................... 34
12.2 Documentation Support.......................................... 34
12.3 Receiving Notification of Documentation Updates..34
12.4 Support Resources................................................. 34
12.5 Trademarks.............................................................34
12.6 Electrostatic Discharge Caution..............................34
12.7 Glossary..................................................................34
13 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2020) to Revision B (October 2020)
Page
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
Added D (SOIC-8) package and associated content..........................................................................................1
Changed Figure 7-1, Differential Source to a Differential Gain of a 1-V/V Test Circuit, for clarity....................15
Changed layout example circuit drawing for clarity.......................................................................................... 33
Changes from Revision * (February 2020) to Revision A (May 2020)
Page
•
Changed device status from advanced information (preview) to production data (active)................................. 1
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5 Pin Configuration and Functions
IN-
8
7
6
5
IN+
PD
1
2
3
4
VOCM
VS+
VS-
OUT+
OUT-
Figure 5-1. D (SOIC-8) and DGK (VSSOP-8) Packages, Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
IN–
NO.
1
I
Inverting (negative) amplifier input
Noninverting (positive) amplifier input
Inverting (negative) amplifier output
Noninverting (positive) amplifier output
IN+
8
I
OUT–
OUT+
5
O
O
4
Power down.
PD = logic low = power off mode.
PD = logic high = normal operation.
PD
7
I
The logic threshold is referenced to VS+.
If power down is not needed, leave PD floating.
VOCM
VS–
2
6
3
I
I
I
Output common-mode voltage control input
Negative power-supply input
VS+
Positive power-supply input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Single supply
VS
Supply voltage
Dual supply
±20
V
IN+, IN–, differential voltage(2)
±0.5
V
IN+, IN–, VOCM, PD, OUT+, OUT− voltage(3)
VVS– – 0.5
–10
VVS+ + 0.5
10
V
IN+, IN− current
mA
mA
OUT+, OUT− current
–50
50
Output short-circuit(4)
Continuous
150
TA
Operating temperature
Junction temperature
–40
–40
–65
°C
°C
°C
TJ
175
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins IN+ and IN– are connected with anti-parallel diodes in between the two terminals. Differential input signals that are greater
than 0.5 V or less than –0.5 V must be current-limited to 10 mA or less.
(3) Input terminals are diode-clamped to the supply rails (VS+, VS–). Input signals that swing more than 0.5 V greater or less the supply
rails must be current-limited to 10 mA or less.
(4) Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
36
UNIT
Single-supply
Dual-supply
VS
TA
Supply voltage
V
±1.5
–40
±18
125
Specified temperature
°C
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6.4 Thermal Information
THP210
THERMAL METRIC(1)
D (SOIC)
8 PINS
129.1
69.4
DGK (VSSOP)
8 PINS
181.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
68.3
72.5
102.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.7
10.6
ψJB
71.8
101.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = VICM = 0 V, RF = 2 kΩ, RL = 10 kΩ(1) , gain = –1 V/V, VPD = VVS+
(unless otherwise noted)
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
10
±40
±75
VIO
Input-referred offset voltage
Input offset voltage drift
µV
TA = –40°C to +125°C
TA = –40°C to +125°C
0.1
±0.35
±0.25
±0.5
µV/°C
µV/V
±0.025
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C
INPUT BIAS CURRENT
±0.2
±2
±4
IB
Input bias current
nA
pA/°C
nA
TA = –40°C to +125°C
TA = –40°C to +125°C
Input bias current drift
Input offset current
±2
±15
±1
±0.2
IOS
TA = –40°C to +125°C
TA = –40°C to +125°C
±3
Input offset current drift
1
±10
pA/°C
NOISE
f = 1 kHz
3.7
4
nV/√Hz
µVPP
en
Input differential voltage noise f = 10 Hz
f = 0.1 to 10 Hz
0.1
300
400
13.4
f = 1 kHz
fA/√Hz
pAPP
ei
Input current noise, each input f = 10 Hz
f = 0.1 to 10 Hz
INPUT VOLTAGE
Common-mode voltage range TA = –40°C to +125°C
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V
VVS– + 1
VVS+ – 1
V
140
140
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V
126
120
CMRR
Common-mode rejection ratio
dB
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V, TA
= –40°C to +125°C
INPUT IMPEDANCE
Input impedance differential
VICM = 0 V
1 || 1
GΩ || pF
mode
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at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = VICM = 0 V, RF = 2 kΩ, RL = 10 kΩ(1) , gain = –1 V/V, VPD = VVS+
(unless otherwise noted)
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ – 0.2 V
115
110
115
110
120
120
120
120
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ – 0.3 V,
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V,
TA = –40°C to +125°C
FREQUENCY RESPONSE
SSBW
GBP
FBP
SR
Small-signal bandwidth
VO = 100 mVPP
7
9.2
2.4
15
1
MHz
MHz
MHz
V/µs
Gain-bandwidth product
Full-power bandwidth
Slew rate
VO = 100 mVPP, gain = –10 V/V
VO = 1 VPP
10-V step
To 0.1% of final value, VO = 10-V step
To 0.01% of final value, VO= 10-V step
Settling time
µs
1.2
Total harmonic distortion and
noise
THD+N
THD+N
Differential input, f = 1 kHz, VO = 10 VPP
Single-ended input, f = 1 kHz, VO = 10 VPP
Differential input, f = 10 kHz, VO = 10 VPP
Single-ended input, f = 10 kHz, VO = 10 VPP
–120
–115
–112
–107
Total harmonic distortion and
noise
Total harmonic distortion and
noise
THD+N
dB
Total harmonic distortion and
noise
Differential input, f = 1 kHz, VO = 10 VPP
Single-ended input, f = 1 kHz, VO = 10 VPP
Differential input, f = 1 kHz, VO = 10 VPP
Single-ended input, f = 1 kHz, VO = 10 VPP
gain = –5 V/V, 2x output overdrive, dc-coupled
f = 100 kHz (differential)
–120
–126
–120
–119
3.3
Second-order harmonic
distortion
HD2
HD3
Third-order harmonic distortion
Overdrive recovery time
µs
Ω
ZO
Open-loop output impedance
14
Differential capacitive load, no output isolation
resistors, phase margin = 30°
CLOAD
OUTPUT
Capacitive load drive
50
pF
VS = ±2.5 V
100
100
230
270
100
100
230
270
±31
VS = ±2.5 V, TA = –40°C to +125°C
VS = ±18 V
Negative output voltage swing
from rail
VOL
VS = ±18 V, TA = –40°C to +125°C
VS = ±2.5 V
mV
mA
VS = ±2.5 V, TA = –40°C to +125°C
VS = ±18 V
Positive output voltage swing
from rail
VOH
VS = ±18 V, TA = –40°C to +125°C
ISC
Short-circuit current
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at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = VICM = 0 V, RF = 2 kΩ, RL = 10 kΩ(1) , gain = –1 V/V, VPD = VVS+
,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT COMMON-MODE VOLTAGE
Small-signal bandwidth from
VOCM pin
VVOCM = 100 mVPP
2
MHz
Large-signal bandwidth from
VOCM pin
VVOCM = 0.6 VPP
5.7
VVOCM = 0.5-V step, rising
VVOCM = 0.5-V step, falling
VVOCM fixed midsupply (VO = ±1 V)
VS = ±2.5 V
4.2
5.5
78
Slew rate from VOCM pin
DC output balance
V/µs
dB
V
VVS– + 1
VVS– + 2
VVS+ – 1
VVS+ – 2
VOCM Input voltage range
VS = ±18 V
VOCM input impedance
2.5 || 1
±1
MΩ || pF
mV
VOCM offset from mid-supply VVOCM pin floating, VO = VICM = 0 V
VVOCM = VICM, VO = 0 V
±1
±6
VOCM common-mode offset
voltage
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C
±10
VOCMcommon-mode offset
voltage drift
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C
±20
±60
µV/°C
mA
POWER SUPPLY
IQ Quiescent operating current
POWER DOWN
0.95
1.05
1.4
TA = –40°C to +125°C
VPD(HI)
Power-down enable voltage
TA = –40°C to +125°C
TA = –40°C to +125°C
VPD = VVS+ – 2 V
VVS+ – 0.5
V
VPD(LOW) Power-down disable voltage
PD bias current
VVS+ – 2.0
1
10
10
2
µA
µA
Powerdown quiescent current
Turn-on time delay
20
VIN = 100 mV, Time to VO = 90% of final value
µs
VIN = 100 mV, Time to VO = 10% of original
value
Turn-off time delay
15
(1) RL is connected differentially, from OUT+ to OUT–.
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6.6 Typical Characteristics
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
15
10
5
15
10
5
0
-200 -150 -100
0
-200 -150 -100
-50
0
50
100
150
200
-50
0
50
100
150
200
D001
D061
Input Offset Voltage (mV)
Input Offset Voltage (mV)
VS = ±1.5 V
VS = ±18 V
Figure 6-1. Input Offset Voltage Histogram
Figure 6-2. Input Offset Voltage Histogram
25
20
15
10
5
20
15
10
5
0
0
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
-6
-4
-2
0
2
4
6
D002
D006
Offset Voltage Drift (mV/èC)
Common-Mode Input Offset Voltage (mV)
VS = ±15 V
VS = ±18 V, VOCM = floating
Figure 6-3. Input Offset Voltage Drift Histogram
Figure 6-4. Output Common-Mode Offset Voltage
500
15
10
5
400
300
200
100
0
-100
-200
-300
-400
-500
IB-
IB+
IOS
0
-18
-14
-10
-6
-2
2
6
Input Common-Mode Voltage (V)
10
14
18
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
D007
D025
Common-Mode Input Offset Voltage (mV)
VS = ±18 V, VOCM = 0 V
Figure 6-6. Input Bias Current vs Input Common-Mode Voltage
Figure 6-5. Output Common Mode Voltage Offset
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6.6 Typical Characteristics (continued)
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
500
450
400
350
300
250
200
150
100
50
100
70
IB-
IB+
IOS
50
30
20
10
7
5
3
2
0
-50
-100
1
100m
3
6
9
12 15 18 21 24 27 30 33 36
Supply Voltage (V)
1
10
100
Frequency (Hz)
1k
10k
100k
D027
D013
Figure 6-7. Input Bias Current vs Supply Voltage
Figure 6-8. Input-Referred Voltage Noise vs Frequency
5000
-90
RL = 2 kW
RL = 10 kW
RL = 600 W
3000
2000
-95
-100
1000
700
-105
-110
-115
-120
-125
500
300
200
100
0.1
0.5
2 3 5 10 20
100
Frequency (Hz)
1000
10000 100000
10
100
1k
Frequency (Hz)
10k 20k
D014
D015
VOUT = 3 VRMS, VS = ±15 V
Figure 6-9. Current Noise vs Frequency
Figure 6-10. Total Harmonic Distortion + Noise vs Frequency
0.1
0.01
-60
180
160
140
120
100
80
200
160
120
80
RL = 2 kW
Gain
Phase
RL = 10 kW
-80
40
0.001
0.0001
1E-5
-100
-120
-140
0
60
-40
-80
-120
-160
-200
40
20
0
-20
10m
100m 1
Output Amplitude (VRMS
10
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
)
D016
D068
f = 1 kHz, VS = ±15 V
VS = ±15 V, CL = 50 pF
Figure 6-12. Open-Loop Gain vs Frequency
Figure 6-11. Total Harmonic Distortion + Noise vs Amplitude
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6.6 Typical Characteristics (continued)
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
50
40
30
20
10
0
180
160
140
120
100
80
60
40
G = 1
G = 10
G = 100
-10
-20
20
0
10m 100m
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
1k
10k
100k
Frequency (Hz)
1M
10M
D011
D009
VS = ±15 V
VS = ±15 V, CL = 50 pF
Figure 6-13. Closed-Loop Gain vs Frequency
Figure 6-14. Common-Mode Rejection Ratio vs Frequency
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
180
PSRR+
160
PSRR-
140
120
100
80
60
40
20
0
10m 100m
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
D030
D012
VS = ±15 V
Figure 6-15. Common-Mode Rejection Ratio vs Temperature
Figure 6-16. Power-Supply Rejection Ratio vs Frequency
-0.01
40
35
30
25
20
15
10
5
-0.02
-0.03
-0.04
-0.05
0
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
D019
D031
VS = ±15 V
Figure 6-18. Maximum Output Voltage vs Frequency
Figure 6-17. Power-Supply Rejection Ratio vs Temperature
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6.6 Typical Characteristics (continued)
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
10000
5000
2
1.8
1.6
1.4
1.2
1
3000
2000
1000
500
300
200
0.8
0.6
0.4
0.2
0
100
50
-40oC
25oC
85oC
125oC
30
20
10
3
6
9
12 15 18 21 24 27 30 33 36
Supply Voltage (V)
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D045
D017
VS = ±15 V
Figure 6-19. Output Impedance vs Frequency
Figure 6-20. Quiescent Current vs Supply Voltage
1.5
1.4
1.3
1.2
1.1
1
1.6
Vs = ê1.5 V
Vs = ê18 V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.9
0.8
0.7
0.6
0.5
VS = ê18 V
VS = ê1.5 V
-50
-25
0
25
50
75
100
125
150
0
0.5
1
1.5
2
2.5
3
3.5
VS+ Delta from Power Down (V)
4
4.5
5
Temperature (oC)
D065
D053
Figure 6-21. Quiescent Current vs Temperature
Figure 6-22. Quiescent Current vs Power-Down Delta
From Supply Voltage
250
200
150
100
50
30
28
26
-55oC
-40oC
25oC
85oC
125oC
150oC
0
24
-50
-100
-150
-200
-250
-40èC
17 V
-17 V
125èC
25èC
85èC
22
20
0
5
10
15
20
25
Output Current (mA)
30
35
40
-18
-14
-10 6
Input Common-Mode Voltage (V)
-6
-2
2
10
14
18
D028
D023
Figure 6-24. Output Voltage vs Output Current
Figure 6-23. Input Offset Voltage vs
Input Common-Mode Voltage
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6.6 Typical Characteristics (continued)
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
20
17.5
15
20
15
10
5
RISO = 0 W
RISO = 25 W
RISO = 50 W
RISO = 0 W
RISO = 25 W
RISO = 50 W
12.5
10
7.5
5
2.5
0
0
0
50
100
150
200
250
Capacitive Load (pF)
300
350
400
20
40
60
80
100
120
Capacitive Load (pF)
140
160
180
D037
D036
AV = 10
AV = 1
Figure 6-26. Small-Signal Overshoot vs Capacitive Load
Figure 6-25. Small-Signal Overshoot vs Capacitive Load
VIN
VOUT+
VOUT-
VIN
VOUT+
VOUT-
Time (500 ns/div)
Time (500 ns/div)
D043
D042
Figure 6-27. Small-Signal Step Response, Falling
Figure 6-28. Small-Signal Step Response, Rising
20
17
14
11
-20
-40èC
125èC
25èC
-22
85èC
-24
-26
-28
-30
8
Falling Edge
Rising Edge
5
-40
-35
-30
-25
-20
-15
Output Current (mA)
-10
-5
0
3
6
9
12 15 18 21 24 27 30 33 36
Supply Voltage (V)
D029
D041
Figure 6-30. Output Voltage vs Output Current
Figure 6-29. Output Slew Rate vs Supply Voltage
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6.6 Typical Characteristics (continued)
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
128
126
124
122
120
118
116
114
112
110
108
50
40
30
20
I
I
I
I
OUT+ (sinking)
OUT+ (sourcing)
OUT- (sourcing)
OUT- (sinking)
10
0
-10
-20
-30
-40
-50
25 èC
85 èC
125 èC
-40 èC
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
-25 -10
5
20
35
50
65
80
95 110 125
Temperature (oC)
Output Voltage Delta from Supply Voltage, VS+/VS- (V)
D049
D048
Figure 6-31. Open-Loop Gain vs Ouput Delta From Supply
Figure 6-32. Short-Circuit Current vs Temperature
3
2.5
2
1.1
1.08
1.06
1.04
1.02
1
1.5
1
0.5
VOUT+
VOUT-
0
-0.5
-1
0.98
0.96
0.94
0.92
0.9
-1.5
-2
VVOCM
(VOUT+ + VOUT-)/2
-2.5
-3
Time (1 ms/div)
Time (5 ms /div)
D044
D054
Figure 6-33. Large-Signal Step Response
Figure 6-34. Output Common-Mode Step Response, Rising
0.1
VVOCM
(VOUT+ + VOUT-)/2
+0.01%
Settling
Threshold
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.01%
Settling
Input
Transition
Threshold
-0.1
Time (250 ns/div)
Time (5 ms / div)
D046
D055
Figure 6-36. Output Settling Time to ±0.01%
Figure 6-35. Output Common-Mode Step Response, Falling
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6.6 Typical Characteristics (continued)
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise
noted)
18
15
12
9
0.3
18
15
12
9
0.3
0.2
0.1
0
VPD
VOUT
0.25
0.2
0.15
0.1
6
6
-0.1
-0.2
-0.3
-0.4
-0.5
3
0.05
0
3
0
0
VPD
VOUT
-3
-6
-0.05
-0.1
-3
-6
Time (1 ms/div)
Time (1 ms/div)
D050
D051
Figure 6-37. Power-Down Time ( PD Low to High)
Figure 6-38. Power-Down Time ( PD High to Low)
VIN
VOUT+
VOUT-
VIN
VOUT+
VOUT-
Time (20 ms/div)
Time (20 ms/div)
D039
D040
Figure 6-39. Output Negative Overload Recovery
Figure 6-40. Output Positive Overload Recovery
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7 Parameter Measurement Information
7.1 Characterization Configuration
The THP210 is a fully differential amplifier (FDA) configuration that offers high dc precision, very low noise and
harmonic distortion in a single, low-power amplifier. The FDA is a flexible device where the main aim is to
provide a purely differential output signal centered on a user-configurable, common-mode voltage that is usually
matched to the input common-mode voltage required by an analog-to-digital converter (ADC). The circuit used
for characterization of the differential-to-differential performance is seen in Figure 7-1
VINœ
RI
2 kꢀ
RF
2 kꢀ
VOUT+
VVS+
VINDIFF / 2
œ
+
+
+
VVOCM
+
RL
10 kꢀ
CL
DNP
VOUT
THP210
œ
+
VCM
+
œ
œ
VINDIFF / 2
RI
VVSœ VPD
2 kꢀ
VOUTœ
RF
2 kꢀ
All voltages except VIN and VOUT are
referenced to ground.
VIN+
Figure 7-1. Differential Source to a Differential Gain of a 1-V/V Test Circuit
A similar circuit is used for single-ended to differential measurements, as shown in Figure 7-2.
VINœ
RI
2 kꢀ
RF
2 kꢀ
VOUT+
VVS+
œ
+
VVOCM
+
RL
10 kꢀ
CL
DNP
VOUT
THP210
œ
+
œ
RI
2 kꢀ
VPD
VVSœ
VOUTœ
+
RF
2 kꢀ
VIN
œ
VIN+
All voltages except VOUT are
referenced to ground.
Figure 7-2. Single-ended Source to Differential Gain of 1-V/V Test Circuit
The characterization plots fix the RF (RF1 = RF2) value at 2 kΩ, unless otherwise noted. This value can be
adjusted to match the system design parameters with the following considerations in mind:
•
The current required to drive RF from the peak output voltage to the input common-mode voltage add to the
overall output load current. If the total current (current through RF + current through RL) exceeds the current
limit conditions, the device enters a current limit, causing the output voltage to collapse.
•
High feedback resistor values (RF > 100 kΩ) interact with the amplifier input capacitance to create a zero in
the feedback network. Compensation must be added to account for potential source of instability; see the TI
Precision Labs FDA Stability Training for guidance on designing an appropriate compensation network.
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8 Detailed Description
8.1 Overview
The THP210 is a low-noise, low-distortion fully-differential amplifier (FDA) that features Texas Instrument's
super-beta bipolar input devices. Super-beta input devices feature very low input bias current as compared to
standard bipolar technology. The low input bias current and current noise makes the THP210 an excellent choice
for high-performance applications that require low-noise, differential-signal processing without significant current
consumption. This device is also designed for analog-to-digital input circuits that require low offset and low noise
in a single fully-differential amplifier. The THP210 features high-voltage capability, which allows the device to be
used in ±15-V supply circuits without any additional voltage clamping or regulators. Because this device is unity-
gain stable, the device allows high-voltage input signals to be attenuated to the low-voltage ADC domain without
requiring additional compensation techniques.
8.2 Functional Block Diagram
VS+
OUT+
œ
INœ
Low Noise
Differential I/O
+
Amplifier
œ
IN+
+
OUTœ
VSœ
VS+
5 Mꢀ
œ
VCM
Error
1 µA
Amplifier
+
VOCM
PD
5 Mꢀ
VSœ
8.3 Feature Description
8.3.1 Super-Beta Input Bipolar Transistors
The THP210 is designed on a modern bipolar process that features TI's super-beta input transistors. Traditional
bipolar transistors feature excellent voltage noise and offset drift, but suffer a tradeoff in high input bias current (I
B) and high input bias current noise. Super-beta transistors offer the benefits of low voltage noise and low offset
drift with an order of magnitude reduction in input bias current and reduction in input bias current noise. For
many filter circuits, input bias current noise can dominate in circuits where higher resistance input resistors are
used. The THP210 enables a fully-differential, low-noise amplifier design without restrictions of low input
resistance at a power level unmatched by traditional single-ended amplifiers.
8.3.2 Power Down
The THP210 features a power-down circuit to disable the amplifier when a low-power mode is required by the
system. In the power-down state, the amplifier outputs are in a high-impedance state, and the amplifier total
quiescent current is reduced to less than 20 µA.
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8.3.3 Flexible Gain Setting
The THP210 offers considerable flexibility in the configuration and selection of resistor values. Low input bias
current and bias current noise allows for larger gain resistor values with minimal impact to noise or offset, see
Section 9.1.3 for more details.
The design starts with the selection of the feedback resistor value. The 2-kΩ feedback resistor value used for the
characterization curves is a good compromise among power, noise, and phase margin considerations. With the
feedback resistor values selected (and set equal on each side), the input resistors are set to obtain the desired
gain, with input impedance also set with these input resistors. Differential I/O designs provide an input
impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a
more complicated input impedance. Most characteristic curves implement the single-ended to differential design
as the more challenging requirement over differential-to-differential I/O designs.
8.3.4 Amplifier Overload Power Limit
During overload or fault conditions, many bipolar-based amplifiers draw significant (three to five times) quiescent
current if the output voltage is clipped (meaning the output voltage becomes limited by the negative or positive
supply rail).
The primary cause for this condition is that common-emitter output stages can consume excessive base current
(up to 100x) when overdriven into saturation. In addition, the overload condition causes the feedback to be
broken, which causes the slew boost to be permanently on. Depending on the slew boost circuit, this increases
the tail current up to 4x.
The THP210 has an intelligent overload detection scheme that eliminates this problem, meaning that there is
virtually no additional current consumption in the case of an overload event, represented in Figure 8-1. The
protection circuit continuously monitors both the input and output stages of the amplifier. Figure 8-1 shows a
measurements of the overload power limit behavior. If a large input voltage step (referred to as ΔVIN) is detected,
the protection circuit checks for the presence of a rapid change in the voltage at the output (referred to as ΔVO).
If the output is not changing because the output is clipped at supply rail, the protection circuit disables the slew-
boost circuit and limit the base current of the predriver to prevent output saturation. After the overload condition
is removed, the amplifier rapidly recovers to normal operating condition. Figure 8-1 indicates that in case of an
overloaded output the current consumption at the supply pins (referred to I(VS+) and I(VS–)) does not exceed the
limitations, and quickly recovers as soon as the overload condition has been removed.
6
2
5
1.5
1
4
3
0.5
0
DVIN
DVO
I(VS+)
2
I(VS-)
1
-0.5
-1
0
-1
-2
-1.5
-2
0.06
0.075
0.09
0.105
0.12
0.135
Time (s)
Figure 8-1. Supply Current Change With Overloaded Outputs
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8.3.5 Unity Gain Stability
The stability of the amplifiers is of key importance when designing application circuits with fully differential
amplifiers. This stability becomes especially important when driving capacitive loads, such as the input for
successive-approximation-register (SAR) analog-to-digital converters (ADCs). A trade-off is made between the
bandwidth of an amplifier and keeping power consumption low; in many cases, FDAs are not unity gain stable.
Currently, many FDAs are primarily designed to support high-speed ADCs, and thus, are typically
decompensated. This decompensation comes with the drawback that the noise performance degrades because
of noise gain peaking. Additional components and compensation techniques are required to handle these
challenges and prevent potential instability of the FDA. For detailed analysis of how stability is defined and
affected, see TI Precision Labs – Fully Differential Amplifiers – FDA Stability and Simulating Phase Margin.
The THP210 is unity-gain stable; therefore, this device can be used in gain configurations with gains > 1, and
also in attenuating configurations with gains < 1, without requiring compensation techniques and sacrificing
dynamic performance. This device can be of prime use for applications that need to interface large input signals
to the low-voltage ADC domain.
8.4 Device Functional Modes
The THP210 has two functional modes: normal operation and power-down. The power-down state is enabled
when the voltage on the power-down pin is lowered to less than the power-down threshold. In the power-down
state, the quiescent current is significantly reduced, and the output voltage is high-impedance. This high
impedance can lead to the input voltages (VIN+ and VIN–) separating.
Internal ESD protection diodes remain present across the input pins in both operating and power-down mode.
Large input signals during disable can forward-biasing the ESD protection diodes, thus producing a load current
in the supply, even in power-down. See Section 9.1.5 for guidance on power-down operation.
The VOCM control pin sets the output average voltage. If left open, VOCM defaults to an internal midsupply
value. Driving this high-impedance input with a voltage reference within the valid range sets a target for the
internal VCM error amplifier. If floated to obtain a default midsupply reference for VOCM, an external decoupling
capacitor must be added on the VOCM pin to reduce the otherwise high output noise for the internal high-
impedance bias.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Most applications for the THP210 strive to deliver the best dynamic range in a design that delivers the desired
signal processing along with adequate phase margin for the amplifier. The following sections detail some of the
design issues with analysis, and guidelines for improved performance.
9.1.1 I/O Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage for the THP210. For ac-coupled
signal paths, this voltage is often the default midsupply voltage to retain the most available output swing around
the voltage centered at the VOCM voltage. For dc-coupled signal paths, set this voltage to minimum of VVS± ±2 V
at VS = ± 18 V and VVS± ±1 V at VS = ± 2.5 V respectively. For precision ADC drivers, this output becomes the
input common mode voltage of the ADC.
From the target output VOCM, the next step is to verify that the desired output differential peak-to-peak voltage (V
OPP) stays within the supplies. For any desired differential VOPP, make sure that the absolute maximum voltage
at the output pins swings with Equation 1 and Equation 2 and confirm that these expressions are within the
supply rails minus the output headroom required for the RRO device.
VOPP
VOmax= VOCM
+
2
(1)
VOPP
VOmin= VOCM
-
2
(2)
Most designs do not run into an input range limit. However, using the approach shown in this section can allow a
quick assessment of the input V ICM range under the intended full-scale output condition. The TINA-TI™
simulation software can be used to plot the input voltages under the intended swings and application circuit to
verify that there is no limiting from this effect. Increasing the positive and negative supplies slightly in simulation
is an easy way to discover the simulated swings that might be going out of range.
9.1.2 DC Precision Analysis
9.1.2.1 DC Error Voltage at Room Temperature
Good dc linearity allows the designer to minimize the total dc output error of the system. In particular, this error
divides into two contributions: the initial error at the normal operating condition of 25°C, and the drift error over
temperature. The main sources of these errors typically arise from:
•
•
•
•
Voltage error due to the input offset voltage (VIO)
Voltage error due to noninverting and inverting bias current (IB–, IB+)
The common-mode rejection ratio (CMRR) of the FDA
Voltage error due to mismatch between input and output common-mode voltages (VVOCM – VICM
)
One major source of error comes from the effect of mismatched resistor values and the ratios on the two sides of
the FDA. For this analysis, this error term is neglected. The effects are described separately in Section 9.1.4.
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The THP210 super-beta input device features extremely-low input bias current, trimmed low input offset voltage,
and the lowest offset drift over the full temperature operating range. These features allow the device to produce
a negligible initial error band at 25°C, but also exceptional robust behavior over temperature. The red curve in
Figure 9-1 showcases a simulation of the total dc error voltage at 25°C versus different gain configurations
based on the application configuration shown in Figure 9-2.
5x10-3
3x10-3
2x10-3
1x10-3
500x10-6
300x10-6
200x10-6
100x10-6
50x10-6
30x10-6
20x10-6
VERR(FDA2)
VERR(THP210)
10x10-6
0
1
2
3
4
5
Gain (V/V)
6
7
8
9
10
Figure 9-1. TINA-TI™ Software Simulation of DC Error Voltage at Different Gain Settings (Variable R2)
R1
R2
1 kΩ
œ
+
œ
+
VID/2
VVS+
VIO
IBÞ
100 mV
VOUT+
VINÞ
œ
+
+
VVOCM
2.5 V
RL
VVS+
VVSÞ
CL
DNP
THP210
œ
+
VOD
10 kΩ
+
+
œ
VICM
1.5 V
VIN+
œ
+
5 V
œ
œ
0 V
œ
+
VID/2
VOUTÞ
IB+
100 mV
VVSœ VPD
R3
R2
1 kΩ
Figure 9-2. FDA DC Error Model
One use case at a differential input voltage of VID = 200 mV and a gain of 5 V/V (that corresponds to R2 = 5 kΩ)
reveals that the initial dc error of the THP210 is 4.5 µV. A comparable FDA2 with VIO = 200 µV,
IB = 650 nA, and IIO = 30 nA results in a 2.22-mV dc error voltage that results in a factor of approximately 500
higher dc error.
In addition, Figure 9-3 shows that the absolute dc accuracy of the THP210 nearly adds an error voltage on the
system. The dominant factors for the initial error band are mainly due to the feedback resistor mismatch that is
not considered in the simulation plot.
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9.1.2.2 DC Error Voltage Over Temperature
The THP210 offers excellent dc accuracy at room temperature. In many applications, calibration techniques are
used to minimize the initial dc error; however, performing calibration over temperature is time-consuming and
expensive.
The advanced drift specification of the THP210 helps to further mitigate the system error over temperature.
Figure 9-3 depicts the total error voltage at these given conditions:
•
•
•
Circuit configuration as shown in Figure 9-2
Temperature range from –40°C to +125°C
Resistor tolerance of 1%
1000
V(ERR_TEMPCO(FDA1))
V(ERR_TEMPCO(THP210))
V(ERR_TEMPCO(FDA2))
800
600
400
200
0
1
2
3
Gain (1 V/V)
4
5
Figure 9-3. Calculation of Error Voltage Over Temperature at Different Gain Settings (Variable R2)
The main contributors that are considered in this analysis are offset voltage drift, offset current drift, and bias
current drift. As a result of the ultra-low bias current drift of 15 pA/°C, the impact of higher gain resistors and
resistor tolerances marginally affects the error voltage with the THP210.
A use case at a gain of 5 V/V shows that the total dc error over temperature of the THP210 is at 66 µV, which is
at least a factor of 10 smaller compared to existing, state-of-the-art FDAs.
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9.1.3 Noise Analysis
An accurate output-noise calculation allows the designer to compare the performance of alternate FDA solutions.
The combination of differential spot noise at the output pins of the FDA with any passive filtering to the ADC
enables an accurate signal-to-noise ratio (SNR) calculation. This chapter incorporates key elements for an
output noise analysis.
The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground. Figure 9-4 shows the simplest analysis circuit with the FDA. This
circuit considers the thermal resistor noise terms of the external feedback network and the intrinsic input voltage
and current noise terms.
2
2
enRg
enRf
RF
RG
2
In+
+
2
eno
œ
2
Inœ
2
eni
2
2
enRg
enRf
RG
RF
Figure 9-4. FDA Noise Analysis Circuit
The noise powers are shown in Figure 9-4 for each term. When the RF and RG (or RI) terms are matched on
each side, the total differential output noise is the root sum squared (RSS) of these separate terms.
Using NG ≡ 1 + RF / RG as the noise gain, the total output noise density is given by Equation 3. Each resistor
noise term is a 4kT × R power (4kT = 1.6E-20 J at 290 K).
eo = e NG 2 + 2 i R 2 + 2 4kTR NG
ni
N
F
F
(3)
where:
•
•
eni is the differential input spot noise times the noise gain.
in x RF is the input current noise terms times the feedback resistor.
Because there are two uncorrelated current noise terms, the power is two times one of them.
•
enRF is the thermal output noise resulting from both the RF and RG resistors at twice the value for the output
noise power of each side added together.
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Figure 9-5 and Figure 9-6 provide a graphical comparison of the described noise densities versus different gain
settings. Each of the contributors are separately showcased in the graphs. As expected, lower feedback
resistors (in this case, 2 kΩ) show that the dominant factor of the total output noise is the intrinsic voltage noise
of the FDA (at gains > 2). For smaller gain settings, the thermal noise of the feedback resistors is dominating.
10Þ6
10Þ6
10Þ7
10Þ7
10Þ8
10Þ8
eo
eo
enRf
enRf
i
n × Rf
i
n × Rf
eni
eni
10Þ9
10Þ9
0.1
1
10
100
0.1
1
10
100
Gain (V/V)
Gain (V/V)
RF = 2 kΩ
RF = 10 kΩ
Figure 9-5. Calculated Noise Densities vs Gain
Settings
Figure 9-6. Calculated Noise Densities vs Gain
Settings
The advancement of the THP210 can be seen at higher feedback resistors (in this case 10 kΩ). Many FDAs
exhibit an input current noise density in the range of some pA/√Hz that, in cases for higher feedback resistors,
dictate the noise behavior. As a result of the superior current noise density of 300 fA/√Hz of the THP210, the
overall output noise is mainly dominated by the thermal noise of the resistors (here, up to gains of approximately
15).
The total output voltage noise density is important when using FDAs as ADC input driver stages. To evaluate the
compatibility between the input driver and the ADC from a noise perspective, compare the calculated RMS
output noise of the FDA with the least-significant bit (LSB) of the desired ADC application, in respect to the
effective number of bits (ENOB). Section 9.2.2 shows measurements of the THP210 in combination with state-
of-the-art SAR ADCs, and indicates the performance that is achieved.
9.1.4 Mismatch of External Feedback Network
The common-mode rejection ratio (CMRR) is one of the key elements when designing with fully differential
amplifiers. Although FDAs are designed to provide the best CMRR performance, poor selection of external gain
setting resistors, as well as careless board layout techniques, significantly degrade CMRR performance.
In an ideal world, the resistors in a typical circuit, as shown in the test circuit Figure 7-1, are chosen to be RF1 / R
F2 = RI1/RI2. Mismatch between these ratios causes the differential output to depend on the input common-mode
voltage (VVOCM), and that in turn produces an offset and excess noise on the differential output. As mentioned in
the previous section, the mismatch of the external resistor network primarily contributes to the dc error.
Generally, a resistor mismatch of 0.1% and a ratio of 1 V/V results in a CMRR of 60 dB. The natural degradation
of the external resistor network is minimized by the following guidelines:
•
Consider input impedance matching, as shown in the Input impedance matching with fully differential
amplifiers technical brief.
•
•
Follow layout guidelines, as provided in Section 11.1.
Use compensation techniques, as described in the Improving PSRR and CMRR in Fully Differential
Amplifiers application report
Despite the mismatch of the external feedback network, the internal common-mode feedback amplifier regulates
the outputs to remain balanced in amplitude and remain 180° out of phase. The output balance performance
stays unaffected by the CMRR degradation.
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9.1.5 Operating the Power-Down Feature
The power-down feature on the THP210 puts the device into a low power-consumption state, with quiescent
current minimized. To force the device into the low-power state, drive the PD pin lower than the power-down
threshold voltage (V VS+ – 2 V). Driving the PD pin lower than the power-down threshold voltage forces the
internal logic to disable both the differential and common-mode amplifiers. The PD pin has an internal pullup
current that allows the pin to be used in an open-drain MOSFET configuration without an additional pullup
resistor, as seen in Figure 9-7. In this configuration, the logic level can be referenced to the MOSFET, and the
voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type
MOSFET with a maximum BVDSS greater than the total supply voltage.
VS+
1 µA
To
amplifier
core
PD
Enabled
MOSFET
THRESHOLD
Powerdown
THP210
GND
Figure 9-7. Power-Down ( PD) Pin Interface With Low-Voltage Logic Level Signals
For applications that do not use the power-down feature, tie the PD pin to the positive supply voltage.
When PD is low (device is in power down) the output pins is in a high-impedance state.
9.1.6 Driving Capacitive Loads
In most ADC applications, an FDA is required to drive capacitive load of an RC charge kickback filter. Other
applications may require some other next-stage devices to be driven. The strong output stage of the THP210
drives higher capacitive loads compared to other FDAs. Figure 6-25 implies that the small-signal overshoot is
less then 20% at a direct capacitive load connection of 140 pF. To help avoid instability and drive higher
capacitive loads, add a small resistor (referred to as isolation resistor RISO in both this plot and Figure 6-26) at
the outputs of the THP210 before the capacitive load.
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9.1.7 Driving Differential ADCs
The THP210 provides a differential output interface to drive a variety of modern, high-performance ADCs. The
following section describes the key elements that must be considered when designing a differential input driver
for SAR ADCs.
9.1.7.1 RC Filter Selection (Charge Kickback Filter)
The sample-and-hold operating behavior of SAR ADCs causes charge transients at the input stage, and thus to
the output stage of the amplifier. The RC filter helps to attenuate the sampling charge injection from the switched
capacitor input stage of the ADC. A careful design is critical to meet linearity and noise performance of the ADC.
Figure 9-8 and Figure 9-9 show a single-ended and differential filter approach, respectively.
RF
RF
VOUT+
VOUT+
CF
AINN
AINP
AINN
AINP
VOUT
VOUT
CF
ADC
ADC
RF
RF
VOUTÞ
VOUTÞ
CF
Figure 9-9. Differential Filter
Figure 9-8. Single-Ended Filter
Choose the capacitor to be at least 10 times larger than the specified value of the SAR ADC sampling capacitor.
A trade-off must be considered for the isolation resistor, where a higher damping effect is achieved at higher
values, and lower value provide better THD at the input of the ADC. To select the best RC combination, use the
Analog Engineering Tool.
One important element to consider is that the small-signal bandwidth of the FDA (fSSBW_FDA) determines what
the cutoff frequency of the RC filter combination can be driven at the inputs of the ADC. Depending whether a
single-ended filter or a differential filter is used the minimum required small-signal bandwidth of the FDA (f
SSBW_FDA) can be estimated by Equation 4:
1
fSSBW_FDA
>
2Œ‡SEL‡RF‡CF
(4)
where:
SEL = 1 for single-ended filter, SEL = 2 for differential filter
•
Driving higher capacitive loads degrades the phase margin of the FDA, and causes instability issues. Best
practice is to perform a SPICE simulation using TINA-TI™ simulation software to confirm that the desired circuit
is stable; that is, the FDA has more than a 45° phase margin.
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9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
The RC filter between the amplifier and the ADC helps the amplifier drive the sampling capacitor during charging
(acquisition) and discharging (conversion) times. During the acquisition time, if the amplifier has a load transient
at the output, the time needed to recover (or settle) is commonly defined as the settling time. Typically, to
achieve minimal distortion, the end value to settle is within ½ of the ADC least significant bit (LSB).
The specified settling time of the FDA is the time required for the amplifier to recover from transients caused at
the THP210 output. Although the frequency response characteristics impact the settling time of the ADC
application, these characteristics are not the key element to consider. The settling time of the FDA to react to
load transients depends primarily on the output impedance of the amplifier at the required signal bandwidth.
Equation 5 calculates the settling time, considering the time constant of the RC combination:
1
≈
’
tsettle = -ln
ì 2
∆
«
÷
◊
2N ì SET
(5)
where:
•
•
•
N is the number of bits in the ADC application
τ equals RF × CF
SET = 2 for a settling of ½ LSB, SET = 4 for a settling of ¼ LSB, and so on.
In order to verify whether the chosen RC filter combination fulfills the settling behavior, simulate the desired
circuit with TINA-TI™ simulation software.
9.1.7.3 THD Performance
The input driver and the ADC both introduce harmonic distortion in the data acquisition block that generates
undesired signals in the output harmonically related to the input signal. Total harmonic distortion (THD) can be
very important in applications measuring ac signals. However, there are also ADC dc-measurement applications
that are only concerned with SNR and linearity. To make sure that the total system distortion performance is not
dominated by the front-end stage, the distortion of the driver circuitry must be at least 10 dB less than the
distortion of the ADC, as shown in Equation 6:
THDFDA ≤ THDADC – 10 dB
(6)
The harmonic distortion of an FDA mainly relates to the open-loop linearity in the output stage corrected by the
loop gain at the fundamental frequency. When the total load impedance decreases, including the effect of the
feedback resistors loadings, the output stage open-loop linearity degrades, and thus worsens the harmonic
distortion, as seen in Figure 6-10.
Another effect that results from the RC filter is that the load impedance changes over frequency, which also
influences the THD.
An additional dependency is given by the output voltage swing. Increasing the output voltage swing increases
the nonlinearities of the open-loop output stage, thus degrading the harmonic distortion.
In summary, the harmonic distortion is negatively affected not only with decreasing load impedance and
increasing output voltage swing, but also with increasing noise gain.
Section 9.2.2 provides an measurement results of the THD performance using the THP210 and the ADS891x
ADC series.
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9.2 Typical Applications
9.2.1 MFB Filter
A common application use case for fully-differential amplifiers is to easily convert a single-ended signal into a
differential signal to drive a differential input source, such as an ADC or class D amplifier. Figure 9-12 shows an
example of the THP210 used to convert a single-ended, low-voltage signal source, such as a small electric
microphone, and deliver a low-noise differential signal that is common-mode shifted to the center of the ADC
input range. A multiple-feedback (MFB) configuration is used to provide a Butterworth filter response, giving a
40‑dB/decade cutoff with a –3-dB frequency of 30 kHz.
RF1
3.65 kꢀ
CF1
1 nF
RG1
604 ꢀ
RI1
732 ꢀ
CA1
47 pF
RO1
20 ꢀ
RA1
100 ꢀ
+5
VIN
œ
+
CA2
1 nF
VOCM
FDA
6.2 nF
ADC
œ
+
PD
VS+
0
RO2
20 ꢀ
RA2
100 ꢀ
CA3
47 pF
RI2
732 ꢀ
RG2
604 ꢀ
CF2
1 nF
RF2
3.65 kꢀ
Figure 9-10. Example 30-kHz Butterworth Filter
9.2.1.1 Design Requirements
The requirements for this application are:
•
•
•
•
•
Single-ended to differential conversion
5-V/V gain
Active filter set to a Butterworth, 30-kHz response shape
Output RC elements set by SAR input requirements (not part of the filter design)
Filter element resistors and capacitors are set to limit added noise over the THP210
9.2.1.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note. The process includes:
•
•
•
•
•
Scale the resistor values to not meaningfully contribute to the output noise produced by the THP210.
Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design.
Set the output resistor to 10 Ω into a 1-nF differential capacitor.
Add 47-pF common-mode capacitors to the load capacitor to improve common noise filtering.
Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the
load capacitor.
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9.2.1.3 Application Curve
The gain and phase plots are shown in Figure 9-11. The MFB filter features a Butterworth responses feature
very flat passband gain, with a 2-pole rolloff at 30 kHz to eliminate any higher-frequency noise from
contaminating the signal chain and potentially alias back into the desired band.
20
16
12
8
120
90
60
30
4
0
0
-30
-60
-90
-120
-150
-180
-4
-8
-12
-16
-20
Gain
Phase
100
1k
Frequency (Hz)
10k
100k
C100
Figure 9-11. Gain and Phase Plot for a 30-kHz Butterworth Filter
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9.2.2 ADS891x With Single-Ended RC Filter Stage
The application circuit in Figure 9-12 shows the schematic of a complete reference driver circuit that generates a
full-scale range of 4.5 V at the ADC using a unipolar supply voltage of 5 V. This circuit is used to measure the
driving capability of the THP210 with the different variants of the ADS891x ADC.
To test the complete dynamic range of the circuit, the common-mode voltage VOCM of the input of the ADC is
established at a value of VREF / 2. To exclude distortion caused by reference voltage VREF and common-mode
voltage VOCM of the ADC, the test circuit uses the low-noise OPA2625 in an inverting gain configuration for V
OCM, and the high-precision, low-noise REF5050 for VREF. See the ADS8910BEVM-PDK user's guide for more
details.
R2 = 1k (0.1%)
R5 = 100 (1%)
+VS
VREF = 4.5 V
R1 = 1k (0.1%)
C2 = 100 pF
+VS
C5 = 1 nF
+
AINN
AINP
+
œ
+VS
VOD
VID
VOCM = 2.25 V
ADS891x
THP210
+
œ
+
5 V
œ
R5 = 100 (1%)
R3 = 1k (0.1%)
Circuit driving capability:
C6 = 1 nF
C4 = 100 pF
ñ
ñ
ñ
ADS8910B at 800 kSPS
ADS8912B at 500 kSPS
ADS8914B at 250 kSPS
R4 = 1k (0.1%)
Figure 9-12. Driving ADS891x With Single-Ended RC Filter Stage
9.2.2.1 Design Requirements
The requirements for this application are:
•
•
•
•
•
•
•
Differential to differential conversion
Unipolar supply voltage of 5 V
Full-scale range of ADC of FSR = ±4.5 V
Input signal amplitude of VREF –0.4 dB
Driver configuration in unity-gain buffer configuration (1-V/V gain)
Circuit bandwidth f(–3dB) = 935 kHz
Output RC elements set by SAR input requirements
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9.2.2.1.1 Measurement Results
The THP210 and the filter combination listed in Section 9.2.2.1 allow for the best trade-off between harmonic
distortion and maintaining stability of the FDA. Table 9-1 and Figure 9-13 through Figure 9-15 showcase the
device performance.
Table 9-1. THP210 + ADS891x: FFT Data Summary
ADC VERSION
ADS8910B
ADC SPECIFICATION
1-MSPS max, 18 bit
500 kSPS, 18 bit
SAMPLING RATE
SNR
THD(1)
SINAD
800 kSPS
100.37 dB
100.4 dB
100.37 dB
–118.4 dB
–118.44 dB
–118.72 dB
100.31 dB
100.33 dB
100.33 dB
ADS8912B
500 kSPS
ADS8914B
250 kSPS, 18 bit
250 kSPS
(1) THD can further be improved by providing a bipolar power supply for more headroom for the negative voltage swing. In the given
circuit, a negative supply of VS– = 0.23 V improved the THD to –120.5 dB.
0
-25
0
-20
-40
-50
-60
-75
-80
-100
-125
-150
-175
-200
-100
-120
-140
-160
-180
-200
0
100000
200000
Frequency (Hz)
300000
400000
0
50000
100000
Frequency (Hz)
150000
200000
250000
fIN = 2 kHz, 100.37 dB SNR, –118.4 dB THD
fIN = 2 kHz, 100.4 dB SNR, –118.44 dB THD
Figure 9-13. Noise Performance FFT Plot:
THP210 + ADS8910B, 800 kSPS, 18-Bit
Figure 9-14. Noise Performance FFT Plot:
THP210 + ADS8912B, 500 kSPS, 18-Bit
0
-50
-100
-150
-200
0
25000
50000 75000
Frequency (Hz)
100000
125000
fIN = 2 kHz, 100.37 dB SNR, –118.72 dB THD
Figure 9-15. Noise Performance FFT Plot:
THP210 + ADS8914B, 250 kSPS, 18-Bit
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9.2.3 Attenuation Configuration Drives the ADS8912B
Many applications require to level-shift high-voltage input signals down to the lower-voltage ADC domain. Figure
9-16 shows an example of the THP210 used to attenuate a ±10-V differential signal to drive a differential SAR
ADC with full-scale range of ±4.5V. The common-mode voltage is shifted to the center of the ADC input range. A
multiple-feedback (MFB) configuration as described in Section 9.2.1 is used to provide a Butterworth filter
response, giving a 40-dB/decade roll-off with a –3-dB frequency of 100 kHz. The THP210 is powered with a 5-V
supply and a –0.232-V negative supply generated by the low-noise negative bias generator (LM7705) allowing
additional headroom for output swing to GND with ultra-low distortion. Alternatively, the THP210 can be powered
using a unipolar 5-V supply with good distortion performance.
The circuit is able to drive the ADS8912B 18-Bit SAR ADC at full throughput of 500-kSPS.
R2 = 909Ω
C4 = 470p
R1 = 2.1kΩ
R4 = 2.74kΩ
R7 = 100Ω
+VS
VREF = 4.5 V
+
VS+
C5 = 1nF
+ VID/2
VSÞ
VS+
AINN
AINP
+
œ
+
ADS8912B
VOCM = 2.25 V
THP210
C1 = 1.1nF
+
+
+
Þ 0.232 V
+5 V
œ
C2 = 1uF
+VCM
œ
œ
C6 = 1nF
Þ VID/2
R3 = 2.1kΩ
VSÞ
R8 = 100Ω
Fs= 500 kSPS
R5 = 2.74kΩ
C3 = 470pF
R6 = 909Ω
COG Ceramic Capacitors
0.1% Resistors
Copyright © 2017, Texas Instruments Incorporated
Figure 9-16. Driving ADS8912B in Attenuation Configuration of 0.4333 V/V
9.2.3.1 Design Requirements
The requirements for this application are:
•
•
•
•
•
•
•
Differential to differential conversion
Second order Butterworth filter with corner frequency of 100 kHz, offering flat frequency response
Circuit accepts fully differential input signal of Vdiff = ± 10 V
Circuit Attenuation is set to 0.433 V/V (–7.273 dB)
Full-scale range of ADC of FSR = ±4.5 V
Filter elements set to limit added noise over THP210 while maintaining circuit stability
Output RC elements set by SAR input requirements
For a detailed design procedure, see Section 9.2.1.2.
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9.2.3.2 Measurement Results
Figure 9-17 and Figure 9-18 showcases the measured performance of the discussed circuit with SNR and THD
results.
Table 9-2. THP210 + ADS8912B in Attenuation – FFT Data Summary
ADC VERSION
ADS8912B
ADC SPECIFICATION
SAMPLING RATE
INPUT SIGNAL
SNR
THD
500 kSPS, 18 bit
500 kSPS
fIN = 2 kHz
100.4 dB
99.1 dB
–124.2 dB
–120.4 dB
ADS8912B
500 kSPS, 18 bit
500 kSPS
fIN = 10 kHz
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
Frequency (Hz)
Frequency (Hz)
fIN = 10 kHz, 99.1-dB SNR, –120.4-dB THD
fIN = 2 kHz, 100.4-dB SNR, –124.2-dB THD
Figure 9-17. Noise Performance FFT:
THP210 + ADS8914B in Attenuation,
500 kSPS, 18 Bit, fIN = 10 kHz
Figure 9-18. Noise Performance FFT:
THP210 + ADS8914B in Attenuation,
500 kSPS, 18 Bit, fIN = 2 kHz
10 Power Supply Recommendations
The THP210 operates from supply voltages of 3.0 V to 36 V (±1.5 V to ±18 V for dual supply). Connect ceramic
bypass capacitors from both VS+ and VS– to GND.
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11 Layout
11.1 Layout Guidelines
11.1.1 Board Layout Recommendations
•
•
•
•
•
Keep differential signals routed together to minimize parasitic impedance mismatch.
Connect a 0.1-µF capacitor to the supply nodes through a via.
If no external voltage is used, connect a 0.1-µF capacitor to the VOCM pin.
Keep any high-frequency nodes that can couple through parasitic paths away from the VOCM node.
Clean the printed circuit board (PCB) after assembly to minimize any leakage paths from excess flux into the
VOCM node.
11.2 Layout Example
RI
2 kꢀ
RF
2 kꢀ
VOUT+
VVS+
CVS+
VINDIFF / 2
œ
+
VVOCM
+
+
+
THP210
VOUT
œ
+
CCM
+
œ
œ
VINDIFF / 2
CVSÞ
VPD
VVSœ
VOUTœ
RF
2 kꢀ
RI
2 kꢀ
VIN+
VINÞ
Connect IN+/INœ through input
resistors on the top layer.
Maintain symmetry between
traces and routing to minimize
common mode coupling.
RI
RI
Route the VOCM pin connection
through a via. Connect a 0.1 µF
capacitor to VOCM if no external
voltage is used to set the output
common mode voltage.
Connect the powerdown pin
through a via. If powerdown is
not needed, leave floating.
+IN
1
2
3
4
œIN
8
7
6
5
RF
PD
VSÞ
PD
RF
VOCM
VS+
CCM
VOUTœ
OUTÞ
OUT+
CVSÞ
VOUT+
VOUTœ
CVS+
GND
GND
Connect bypass capacitors
through a via.
Copyright © 2017, Texas Instruments Incorporated
Figure 11-1. Example Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
•
•
•
•
THP210 TINA-TI™ model
TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter
TINA-TI 100kHz MFB filter LG test
TINA-TI Differential Transimpedance LG Sim
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, INA188 Precision, Zero-Drift, Rail-to-Rail Out, High-Voltage Instrumentation Amplifier data
sheet
Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-trim™ data sheet
Texas Instruments, OPA161x SoundPlus™ High-Performance, Bipolar-Input Audio Operational Amplifiers
data sheet
•
•
Texas Instruments, Design Methodology for MFB Filters in ADC Interface Applications application report
Texas Instruments, Design for Wideband Differential Transimpedance DAC Output application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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9-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DGK
DGK
D
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
THP210DGKR
THP210DGKT
THP210DR
ACTIVE
VSSOP
VSSOP
SOIC
8
8
8
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
1237
1237
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAUAG
Call TI
PREVIEW
2500
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Nov-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THP210DGKR
THP210DGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THP210DGKR
THP210DGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
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