THS1030_13 [TI]

3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER; 3 V至5.5 V ， 10位， 30MSPS CMOS模拟数字转换器


型号：	THS1030_13
厂家：	TEXAS INSTRUMENTS
描述：	3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER 3 V至5.5 V ， 10位， 30MSPS CMOS模拟数字转换器转换器
文件：	总39页 (文件大小：1187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

28-PIN TSSOP/SOIC PACKAGE

(TOP VIEW)

10-Bit Resolution, 30 MSPS

Analog-to-Digital Converter

Configurable Input: Single-Ended or

Differential

AGND

AIN

Differential Nonlinearity: 0.3 LSB

Signal-to-Noise: 57 dB

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

VREF

REFBS

REFBF

MODE

REFTF

REFTS

876M

Spurious Free Dynamic Range: 60 dB

Adjustable Internal Voltage Reference

Out-of-Range Indicator

Power-Down Mode

AGND

REFSENSE

Pin Compatible With TLC876

description

I/O9 12

OVR 13

17 STBY

16 OE

The THS1030 is a CMOS, low-power, 10-bit,

DGND 14

15 CLK

30 MSPS analog-to-digital converter (ADC) that

can operate with a supply range from 3 V to 5.5 V.

The THS1030 has been designed to give circuit

developers flexibility. The analog input to the THS1030 can be either single-ended or differential. The THS1030

provides a wide selection of voltage references to match the user’s design requirements. For more design

flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and

temperature drift requirements of the application. The out-of-range output is used to monitor any out-of-range

condition in THS1030’s input range.

The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video,

multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit

charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and

camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both

imaging and communications systems.

The THS1030C is characterized for operation from 0°C to 70°C, while the THS1030I is characterized for

operation from −40°C to 85°C

AVAILABLE OPTIONS

SPECIFIED

PACKAGE

LEAD

PACKAGE

DESGIGNATOR

PACKAGE

ORDERING

NUMBER

TRANSPORT MEDIA,

QUANTITY

PRODUCT

TEMPERATURE

RANGE

†

MARKINGS

THS1030CPW

THS1030CPWR

THS1030IPW

Tube, 50

Tube and Reel, 2000

Tube, 50

THS1030C

THS1030I

THS1030C

THS1030I

0°C to 70°C

−40°C to 85°C

0°C to 70°C

TH1030

TJ1030

TH1030

TJ1030

TSSOP−28

SOP−28

THS1030IPWR

THS1030CDW

THS1030CDWR

THS1030IDW

THS1030IDWR

Tube and Reel, 2000

Tube, 20

Tube and Reel, 1000

Tube, 20

−40°C to 85°C

Tube and Reel, 1000

†

For the most current specification and package information, refer to the TI web site at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢏ

ꢗ

ꢈ

ꢨ

ꢕ

ꢣ

ꢘ

ꢐ

ꢡ

ꢀ

ꢢ

ꢍ

ꢜ

ꢈ

ꢚ

ꢒ

ꢛ

ꢕ

ꢑ

ꢀ

ꢑ

ꢙ

ꢚ

ꢤ

ꢛ

ꢜ

ꢢ

ꢝ

ꢞ

ꢟ

ꢠ

ꢙ

ꢜ

ꢚ

ꢙ

ꢡ

ꢥ

ꢢ

ꢣ

ꢝ

ꢤ

ꢚ

ꢠ

ꢟ

ꢞ

ꢡ

ꢜ

ꢛ

ꢥ

ꢀꢤ

ꢣ

ꢦ

ꢡ

ꢧ

ꢙ

ꢢ

ꢟ

ꢡ

ꢠ

ꢙ

ꢠ

ꢜ

ꢝ

ꢚ

ꢣ

ꢨ

ꢟ

ꢚ

ꢠ

ꢤ

ꢡ

ꢊ

ꢝ

ꢜ

ꢢ

ꢠ

ꢜ

ꢝ

ꢞ

ꢠ

ꢜ

ꢡ

ꢥ

ꢙ

ꢛ

ꢙ

ꢢ

ꢤ

ꢝ

ꢠ

ꢩ

ꢠ

ꢤ

ꢝ

ꢜ

ꢛ

ꢪ

ꢟ

ꢍ

ꢚ

ꢞ

ꢤ

ꢡ

ꢠ

ꢟ

ꢚ

ꢨ

ꢟ

ꢝ

ꢨ

ꢫ

ꢟ

ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢊ

ꢝ

ꢟ

ꢚ

ꢠ

ꢬ

ꢊ

ꢏ

ꢝ

ꢜ

ꢨ

ꢣ

ꢢ

ꢠ

ꢙ

ꢜ

ꢚ

ꢥ

ꢝ

ꢜ

ꢢ

ꢤ

ꢡ

ꢙ

ꢚ

ꢭ

ꢨ

ꢜ

ꢤ

ꢡ

ꢚ

ꢜ

ꢠ

ꢚ

ꢤ

ꢢ

ꢤ

ꢡ

ꢟ

ꢝ

ꢙ

ꢧ

ꢬ

ꢙ

ꢚ

ꢢ

ꢧ

ꢣ

ꢨ

ꢤ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

functional block diagram

Core

ADC

AIN

Sample

and

Hold

Output

Buffer

I/O(0−9)

REFTS

REFBS

OVR

Internal

Reference

Buffer

MODE

REFTF

REFBF

Timing

Circuit

VBG

ORG

GND

REFSENSE

VREF

STBY

CLK

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AIN

NO.

1, 19

Analog ground

Analog input

Analog supply

Clock input

CLK

DGND

Digital ground

Digital driver supply

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

Digital I/O bit 0 (LSB)

Digital I/O bit 1

Digital I/O bit 2

Digital I/O bit 3

Digital I/O bit 4

Digital I/O bit 5

Digital I/O bit 6

Digital I/O bit 7

Digital I/O bit 8

Digital I/O bit 9 (MSB)

MODE

Mode input

High to 3-state the data bus, low to enable the data bus

Out-of-range indicator

OVR

REFBS

REFBF

REFSENSE

REFTF

REFTS

STBY

Reference bottom sense

Reference bottom decoupling

Reference sense

Reference top decoupling

Reference top sense

I/O

High = power-down mode, low = normal operation mode

Internal and external reference

VREF

876M

High = THS1030 mode, low = TLC876 mode (see section 4 for TLC876 mode)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range: AV

to AGND, DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 0.3 V

AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −6.5 V to 6.5 V

Mode input voltage range, MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV

Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . −0.3 V to AV

Analog input voltage range, AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV

Reference input voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV

Reference output voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV

Clock input voltage range, CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV

Digital input voltage range, digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV

Digital output voltage range, digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV

+ 0.3 V

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM

MAX

UNIT

Clock input

0.8 × AV

High-level input voltage, V

All other inputs

Clock input

0.8 × DV

0.2 × AV

0.2 × DV

Low-level input voltage, V

All other inputs

analog inputs

MIN

NOM

MAX

UNIT

Analog input voltage, V

I(AIN)

REFBS

REFTS

I(VREF)

Reference input voltage

I(REFTS)

I(REFBS)

AV −1

power supply

MIN NOM

MAX

5.5

UNIT

3.3

Supply voltage

Maximum sampling rate = 30 MSPS

5.5

REFTS, REFBS reference voltages (MODE = AV

)

MIN NOM

MAX

UNIT

Reference input voltage (top)

REFTS

REFBS

Reference input voltage (bottom)

Differential input voltage (REFTS − REFBS)

AV −1

Switched sampling input capacitance on REFTS or REFBS

0.6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

recommended operating conditions (continued)

sampling rate and resolution

PARAMETER

MIN NOM

MAX

UNIT

Sample frequency

Resolution

30 MSPS

Bits

electrical characteristics over recommended operating conditions, AV

= 3 V, DV

= 3 V, f = 30

DD s

MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,

T = T

to T (unless otherwise noted)

min

max

analog inputs

PARAMETER

MIN

TYP

MAX

UNIT

I(AIN)

Analog input voltage

REFBS

REFTS

Switched sampling input capacitance

Full power bandwidth (−3 dB)

DC leakage current (input = FS)

1.2

150

MHz

µA

lkg

VREF reference voltages

PARAMETER

MIN

TYP

MAX

1.05

2.10

UNIT

Internal 1-V reference voltage (REFSENSE = VREF)

Internal 2-V reference voltage (REFSENSE = AGND)

0.95

1.90

External reference voltage (REFSENSE = AV

)

Reference input resistance

680

Ω

REFTF, REFBF reference voltages

PARAMETER

TEST CONDITIONS

MIN

0.9

1.9

1.3

TYP

MAX

1.1

2.1

1.7

UNIT

Differential input voltage (REFTF − REFBF) (REFSENSE = VREF)

Differential input voltage (REFTF − REFBF) (REFSENSE = AGND)

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

1.5

2.5

Input common mode voltage (REFTF + REFBF)/2

VREF = 1 V

REFTF voltage (MODE = AV

REFBF voltage (MODE = AV

)

2.5

3.5

VREF = 2 V

VREF = 1 V

VREF = 2 V

)

0.5

1.5

600

1.2

Input resistance between REFTF and REFBF

Power up time for valid ADC conversions (t

Ω

)

See Note 1

µs

PUconv

NOTES: 1. Time from control register STBY pin returning low to the ADC conversion to be accurate within 0.1% of fullscale.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

electrical characteristics over recommended operating conditions, AV

= 3 V, DV

= 3 V, f = 30

DD s

MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,

T = T

to T (unless otherwise noted) (continued)

min

max

dc accuracy

PARAMETER

MIN

TYP

MAX

UNIT

LSB

INL

Integral nonlinearity (see Note 2)

Differential nonlinearity (see Note 3)

Offset error (see Note 4)

Gain error (see Note 5)

Missing code

DNL

0.3

0.4

1.4

1.4 %FSR

3.5 %FSR

No missing code assured

NOTES: 2. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The

deviation is measured from the center of each particular code to the true straight line between these two endpoints.

3. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure

indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under

test (i.e., (last transition level – first transition level) ÷ (2 – 2)). Using this definition for DNL separates the effects of gain and offset

error. A minimum DNL better than –1 LSB ensures no missing codes.

4. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the

bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by

the number of ADC output levels (1024).

5. Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5

LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references

divided by the number of ADC output levels (1024).

dynamic performance (See Note 6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 3.5 MHz

8.4

f = 3.5 MHz, AV

f = 15 MHz, 3 V

= 5 V

ENOB

SFDR

THD

Effective number of bits

Bits

7.8

f = 15 MHz, AV

f = 3.5 MHz

7.7

60.6

64.6

48.5

f = 3.5 MHz, AV

f = 15 MHz

Spurious free dynamic range

Total harmonic distortion

Signal-to-noise ratio

f = 15 MHz, AV

f = 3.5 MHz

−60

−66.9

−47.5

−53.1

−56

f = 3.5 MHz, AV

f = 15 MHz

f = 15 MHz, AV

f = 3.5 MHz

f = 3.5 MHz, AV

f = 15 MHz

SNR

53.1

49.4

f = 15 MHz, AV

f = 3.5 MHz

52.5

f = 3.5 MHz, AV

f = 15 MHz

SINAD Signal-to-noise and distortion

48.6

48.1

f = 15 MHz, AV

NOTES: 6. Input amplitude of single tone sine wave for dynamic tests is −0.5 dBFS.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

electrical characteristics over recommended operating conditions, AV

= 3 V, DV

= 3 V, f = 30

DD s

MSPS/50% duty cycle, MODE = AV , 2-V input span from 0.5 V to 2.5 V, external reference,

T = T

to T

(unless otherwise noted) (continued)

min

max

clock

PARAMETER

MIN

TYP

MAX

UNIT

Clock cycle

Pulse duration, clock high

Pulse duration, clock low

Clock to data valid, delay time

Output disable to Hi-Z output, disable time

Output enable to output valid, enable time

Pipeline latency

16.5

110

w(CKH)

w(CKL)

d(o)

d(DZ)

d(DEN)

Cycles

Aperture delay time

d(AP)

Aperture uncertainty (jitter)

power supply (See Note 7)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating supply current

= DV

= 3 V, MODE = AVDD

= 3 V

120

Power dissipation

Standby power

= 5 V

150

= 3 V, MODE = AVDD

D(STBY)

NOTES: 7. Mode and REFSENSE are set to AV . The internal reference buffer is powered up to buffer the externally applied 0.5 V REFBS

and 2.5 V REFTS. 1.5 VDC is applied at AIN while converting data at 30 MSPS.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PARAMETER MEASUREMENT INFORMATION

Sample 2

Sample 3

Sample 1

Sample 5

Sample 4

Analog Input

w(CKL)

w(CKH)

Input Clock

See

Note A

d(o)

Pipeline Latency

Digital Output

Sample 1

Sample 2

NOTE A: All timing measurements are based on 50% of edge transition.

Figure 1. Digital Output Timing Diagram

See Note A

d(DZ)

d(DEN)

Hi-Z

Output

I/O

NOTE A: All timing measurements are based on 50% of edge transition.

Figure 2. Output Enable Timing Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

TYPICAL CHARACTERISTICS

POWER

SAMPLING FREQUENCY

= DV

= 3 V

f = 3.5 MHz, −0.5 dBFS

= 25°C

− Sampling Frequency − MHz

Figure 3

EFFECTIVE NUMBER OF BITS

TEMPERATURE

10.0

9.5

9.0

8.5

8.0

7.5

7.0

= DV

= 3 V

f = 3.5 MHz, −0.5 dBFS

= 30 MSPS

−40

−15

− Temperature − °C

Figure 4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7.0

= DV

= 3 V

f = 3.5 MHz, −0.5 dBFS

= 25°C

− Sampling Frequency − MSPS

Figure 5

EFFECTIVE NUMBER OF BITS

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7.0

= 5 V

= 3 V

f = 3.5 MHz, −0.5 dBFS

= 25°C

− Sampling Frequency − MSPS

Figure 6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

SAMPLING FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7.0

= DV

= 5 V

f = 3.5 MHz, −0.5 dBFS

= 25°C

− Sampling Frequency − MSPS

Figure 7

DIFFERENTIAL NONLINEARITY

INPUT CODE

1.0

0.8

= 3 V

0.6

= 30 MSPS

0.4

0.2

−0.0

−0.2

−0.4

−0.6

−0.8

−1.0

128

256

384

512

640

768

896

1024

Input Code

Figure 8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

INPUT CODE

2.0

1.5

= 3 V

= 30 MSPS

1.0

0.5

0.0

−0.5

−1.0

−1.5

−2.0

128

256

384

512

640

768

896

1024

Input Code

Figure 9

FFT

FREQUENCY

−20

= 3 V

f = 3.5 MHz,

−40

−0.5dBFS

−60

−80

−100

−120

−140

f − Frequency − MHz

Figure 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC core, where

the process of analog to digital conversion is performed against ADC reference voltages, REFTF and REFBF.

Connecting the MODE pin to one of three voltages, AGND, AV

or AV /2 sets up operating configurations.

The three settings open or close internal switches to select one of the three basic methods of ADC reference

generation.

Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the

internal reference buffer or may be fed from completely external sources. Where the reference buffer is

employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external

voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and

REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user.

The ADC core drives out through output buffers to the data pins D0 to D9. The output buffers can be disabled

by the OE pin.

A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on

the rising edge of CLK, and corresponding data is output after following third rising edge.

The STBY pin controls the THS1030 power down.

The user-chosen operating configuration and reference voltages determine what input signal voltage range the

THS1030 can handle.

The following sections explain:

The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages

The ways in which the ADC reference voltages can be buffered internally, or externally applied

How to set the onboard reference generator output, if required, and several examples of complete

configurations

signal processing chain (sample and hold, ADC)

Figure 11 shows the signal flow through the sample and hold unit to the ADC core.

REFTF

VP+

AIN

REFTS

REFBS

Sample

and

Hold

ADC

Core

−1/2

VP−

REFBF

Figure 11. Analog Input Signal Flow

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

sample and hold

The analog input signal A is applied to the AIN pin, either dc-coupled or ac-coupled.

The differential sample and hold processes A with respect to the voltages applied to the REFTS and REFBS

−

pins, to give a differential output VP − VP = VP given by:

VP + A * VM

Where:

(REFTS ) REFBS)

VM +

(1)

For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if

MODE = AV /2 then REFTS and REFBS can be connected together to operate with AIN as a complementary

pair of differential inputs (see Figures 16 and 17).

analog-to-digital converter

In all operating configurations, VP is digitized against ADC reference voltages REFTF and REFBF, full-scale

values of VP being given by:

) (REFTF * REFBF)

VPFS )+

(2)

* (REFTF * REFBF)

VPFS *+

VP voltages outside the range VPFS− to VPFS+ lie outside the conversion range of the ADC. Attempts to

convert out-of-range inputs are signaled to the application by driving the OVR output pin high. VP voltages less

than VPFS− give ADC output code 0. VP voltages greater than VPFS+ give output code 1023.

complete system

Combining the above equations, the analog full scale input voltages at AIN which give VPFS+ and VPFS− at

the sample and hold output are:

(REFTF * REFBF)

+ FS )+ VM )

(3)

and

(REFTF * REFBF)

+ FS *+ VM *

(4)

(5)

The analog input span (voltage range) that lies within the ADC conversion range is:

[

]

Input span + (FS )) * (FS *) + (REFTF * REFBF)

The REFTF and REFBF voltage difference sets the device input range. The next sections describe in detail the

various methods available for setting voltages REFTF and REFBF to obtain the desired input span and ADC

performance.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

ADC reference generation

The THS1030 has three primary modes of ADC reference generation, selected by the voltage level applied to

the MODE pin.

Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC

reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum

power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the

possibility of Kelvin connection of the reference inputs to the THS1030 to eliminate any voltage drops from

remote references that may occur in the system. Only single-ended input is possible in this mode.

Connecting the MODE pin to AV /2 gives differential mode. In this mode, the ADC reference voltages REFTF

and REFBF are generated by the internal reference buffer from the voltage applied to the VREF pin. This mode

is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins.

A special case of differential mode is center span mode, in which the user applies a single-ended signal to AIN

and applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.

Connecting the MODE pin to AV

gives top/bottom mode. In this mode, the ADC reference voltages REFTF

and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS

pins. Only single-ended input is possible in top/bottom mode.

When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs

disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively. These nodes

are connected by the user to external sources to provide the ADC reference voltages. The internal connections

are designed for use in kelvin connection mode (Figure 14). When using external reference mode as shown

in Figure 13, REFTS must be shorted to REFTF and REFBS must be shorted to REFBF externally. The mean

of REFTF and REFBF must be equal to AV /2. See Figure 13.

Table 1. Typical Set of Reference Connections

VREF

VOLTAGE

REFERENCE MODE

MODE

REFSENSE

REFTS, REFBS

ANALOG INPUT FIGURES

Reference buffer powered

down, reference voltage

provided directly by REFT

and REFB

External

AGND

Disabled

Single-ended

12, 13, 14

15, 16, 17

VREF

AGND

1 V

2 V

Externally connect REFTS to

REFBS. This pair then forms

AIN− to the ADC.

Differential or

center span

Internal

AV /2

External

divider

1 + Ra/Rb

(see Figure 22)

External (through internal

reference buffer)

Disabled

Single-ended

(top-bottom

mode)

VREF

AGND

1 V

2 V

REFTS = V

REFBS = V

FS+

FS−

Output of VREF can be

externally tied to REFTS or

REFBS to provide one of the

reference voltages

18, 19

External

divider

1 + Ra/Rb

(see Figure 22)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

full external reference mode (mode = AGND)

REFTF

AIN+

REFTS

REFBS

Sample

and

Hold

ADC

Core

−1/2

REFBF

Internal

Reference

Buffer

Figure 12. ADC Reference Generation, Full External Reference Mode (MODE = AGND)

It is also possible to use REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode)

to overcome any voltage drops within the system. See Figure 14.

+FS

AIN

REFSENSE

−FS

REFTS

REFBS

DC SOURCE = + FS

DC SOURCE = −FS

0.1 µF

REFTF

REFBF

10 µF

0.1 µF

MODE

Figure 13. Full External Reference Mode

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

full external reference mode (mode = AGND) (continued)

+FS

AIN

REFSENSE

−FS

REFTS

REFBS

REFTF

REFT = +FS

REFB = −FS

0.1 µF

10 µF

0.1 µF

REFBF

MODE

Figure 14. Full External Reference With Kelvin Connections

differential input mode (MODE = AV /2)

+ VREF

REFTF =

AIN+

REFTS

REFBS

Sample

and

Hold

ADC

Core

−1/2

AIN−

− VREF

Internal

Reference

Buffer

VREF

REFBF =

AGND

Figure 15. ADC Reference Generation, MODE = AV /2

When MODE = AV /2, the internal reference buffer is enabled, its outputs internally switched to REFTF and

REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF

voltages are centered on AV /2 by the internal reference buffer and the voltage difference between REFTF

and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are

open in this mode, allowing REFTS and REFBS to form the AIN− to the sample and hold.

Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to

an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the section on onboard reference

generator configuration).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

differential input mode (MODE = AV /2) (continued)

+FS

AIN+

AIN

MODE

−FS

+FS

REFTS

AIN−

−FS

REFBS REFSENSE

0.1 µF

REFTF

REFBF

VREF

10 µF

0.1 µF

Figure 16. Differential Input Mode, 1-V Reference Span

+FS

−FS

AIN

MODE

REFTS

DC SOURCE = VM

REFBS

REFTF

0.1 µF

10 µF

0.1 µF

REFBF

REFSENSE

Figure 17. Center Span Mode, 2-V Reference Span

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

top/bottom mode (MODE = AV

)

REFTF = AV

+ (REFTS − REFBS)

AIN+

REFTS

REFBS

Sample

and

Hold

ADC

Core

−1/2

REFBF = AV

− (REFTS + REFBS)

Internal

Reference

Buffer

Figure 18. ADC Reference Generation Mode = AV

Connecting MODE to AV enables the internal reference buffer. Its inputs are internally switched to the REFTS

and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections

(REFTS to REFTF) and (REFBS to REFBF) are broken.

The REFTS and REFBS voltages set the analog input span limits FS+ and FS− respectively. Any voltages at

AIN greater than REFTS or less than REFBS will cause ADC over-range, which is signaled by OVR going high

when the conversion result is output.

Typically, REFSENSE is tied to AV

choose to use the ORG output to VREF as either REFTS or REFBS.

to disable the ORG output to VREF (as in Figure 19), but the user can

+FS

AIN

MODE

−FS

DC SOURCE = FS+

REFSENSE

REFTS

REFBS

DC SOURCE = FS−

0.1 µF

REFTF

REFBF

10 µF

0.1 µF

Figure 19. Top/Bottom Reference Mode

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

onboard reference generator configuration

The onboard reference generator (ORG) can provide a supply-voltage-independent and temperature-

independent voltage on pin VREF.

External connections to REFSENSE control the ORG’s output to the VREF pin as shown in Table 2.

Table 2. Effect of REFSENSE Connection on VREF Value

REFSENSE CONNECTION

VREF pin

ORG OUTPUT TO VREF

REFER TO:

Figure 20

Figure 21

Figure 22

Figure 23

1 V

2 V

AGND

External divider junction

(1 + R /R )

A B

Open circuit

REFSENSE = AV

powers the ORG down, saving power when the ORG function is not required.

If MODE = AV /2, the voltage on VREF determines the ADC reference voltages:

VREF

REFTF +

REFBF +

)

(6)

DD VREF

REFTF * REFBF + VREF

Internal

Reference

Buffer

Mode =

VREF = 1 V

REFSENSE

VBG

0.1 µF 1 µF

Tantalum

AGND

Figure 20. 1-V VREF Using ORG

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

Internal

Reference

Buffer

Mode =

VREF = 2 V

REFSENSE

VBG

0.1 µF 1 µF

Tantalum

10 kΩ

AGND

Figure 21. 2-V VREF Using ORG

Internal

Reference

Buffer

Mode =

VREF = 1 + (Ra/Rb)

VBG

0.1 µF 1 µF

Tantalum

REFSENSE

AGND

Figure 22. External Divider Mode

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

Internal

Reference

Buffer

Mode =

VREF = External

REFSENSE

VBG

AGND

Figure 23. Drive VREF Mode

operating configuration examples

This section provides examples of operating configurations.

Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF

to drive REFTS. Connecting the mode pin to AV puts the THS1030 in top/bottom mode. Connecting pin

REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and

AGND respectively to match the AIN pin input range to the voltage range of the input signal.

2 V

1 V

0 V

AIN

MODE

VREF = 2 V

REFTS

0.1 µF

REFTF

REFBF

REFSENSE

REFBS

10 µF

0.1 µF

Figure 24. Operation Configuration in Top/Bottom Mode

In Figure 25 the input signal is differential, so mode = AV /2 (differential mode) is set to allow the inverse signal

to be applied to REFTS and REFBS. The differential input goes from −0.8 V to 0.8 V, giving a total input signal

span of 1.6 V, REFTF−REFBF should therefore equal 1.6 V. REFSENSE is connected to resistors RA and RB

(external divider mode) to make VREF = 1.6 V, that is R /R = 0.6 (see Figure 22).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

operating configuration examples (continued)

1.4 V

1 V

AIN+

AIN−

AIN

MODE

0.6 V

1.4 V

1 V

REFTS

VREF = 1.6 V

REFSENSE

0.6 V

REFBS

REFTF

0.1 µF

10 µF

0.1 µF

REFBF

Figure 25. Differential Operation

Figure 26 shows a center span configuration for an input waveform swinging between 0.2 V and 1.9 V. Pins

REFTS and REFBS are connected to a voltage source of 1.05 V, equal to the mid-scale of the input waveform.

REFTF−REFBF should be set equal to the span of the input waveform, 1.7 V, so VREF is connected to an

external source of 1.7 V. REFSENSE must be connected to AV

Figure 23) to allow this external source to be applied.

to disable the ORG output to VREF (see

1.9 V

1.05 V

0.2 V

AIN

MODE

REFSENSE

REFTS

DC SOURCE = 1.05 V

REFBS

REFTF

0.1 µF

VREF

DC SOURCE = 1.7 V

10 µF

0.1 µF

REFBF

Figure 26. Center Span Operation

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

power management

In power-sensitive applications (such as battery-powered systems) where the THS1030 ADC is not required

to convert continuously, power can be saved between conversion intervals by placing the THS1030 into

power-down mode. This is achieved by setting pin 17 (STBY) to 1. In power-down mode, the device typically

consumes less than 1 mW of power (from AV

and DV ) in either top/bottom mode or center-span mode.

On power up, the THS1030 typically requires 5 ms of wake-up time before valid conversion results are available

in either top/bottom or center span modes.

Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by

1 mA analog I . This is achieved by connecting the REFSENSE pin to AV

output format and digital I/O

While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input

over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.

The ADC output data format is unsigned binary (output codes 0 to 1023).

driving the THS1030 analog inputs

driving AIN

Figure 26 shows an equivalent circuit for the THS1030 AIN pin. The load presented to the system at the AIN

pin comprises the switched input sampling capacitor, C

, and various stray capacitances, C and C

SAMPLE

CLK

1.2 pF

AIN

8 pF

1.2 pF

(Sample)

AGND

CLK

LAST

Figure 27. Equivalent Circuit of Analog Input AIN

In any single-ended input mode, V = the average of the previously sampled voltage at AIN and the average

LAST

of the voltages on pins REFTS and REFBS. In any differential mode, V

= the common mode input voltage.

LAST

The external source driving AIN must be able to charge and settle into C

to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution.

and the C and C strays

P1 P2

SAMPLE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

AIN input current and input load modeling

When CLK goes low, the source driving AIN must charge the total switched capacitance C = C

The total charge transferred depends on the voltage at AIN and is given by:

+ C

SAMPLE

+ (AIN * V

) C .

CHARGING

LAST

(7)

do not change between samples, the maximum amount of

For a fixed voltage at AIN, so that AIN and V

LAST

charge transfer occurs at AIN = FS− (charging current flows out of THS1030) and AIN = FS+ (current flows into

THS1030). If AIN is held at the voltage FS+, V = [(FS+) + VM]/2, giving a maximum transferred charge:

LAST

[

]

(FS )) * VM C

[

]

(FS )) * (FS )) ) VM

Q(FS) +

(8)

+ (1ń4 of the input voltage span) C

If the input voltage changes between samples, then the maximum possible charge transfer is

Q(max) + 3 Q(FS)

(9)

which occurs for a full-scale input change (FS+ to FS− or FS− to FS+) between samples.

The charging current pulses can make the AIN source jump or ring, especially if the source is slightly inductive

at high frequencies. Inserting a small series resistor of 20 Ω or less in the input path can damp source ringing

(see Figure 31). This resistor can be made larger than 20 Ω if reduced input bandwidth or distortion performance

is acceptable.

R < 20 Ω

AIN

Figure 28. Damping Source Ringing Using a Small Resistor

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

equivalent input resistance at AIN and ac-coupling to AIN

Some applications may require ac-coupling of the input signal to the AIN pin. Such applications can use an

ac-coupling network such as shown in Figure 29.

(Bias1)

AIN

(Bias2)

Figure 29. AC-Coupling the Input Signal to the AIN Pin

Note that if the bias voltage is derived from the supplies, as shown in Figure 29, then additional filtering should

be used to ensure that noise from the supplies does not reach AIN.

Working with the input current pulse equations given in the previous section is awkward when designing

ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent

resistance, R

, from the AIN pin to a voltage source VM where

AIN

VM = (REFTS + REFBS)/2 and R

= 1 / (C x f

)

AIN

clk

where f is the CLK frequency.

clk

The high-pass −3 dB cutoff frequency for the circuit shown in Figure 29 is:

(*3 dB)

2 p R tot

(10)

where R tot is the parallel combination of Rbias1, Rbias2, and R . This approximation is good provided that

AIN

the clock frequency, f , is much higher than f(−3 dB).

clk

Note also that the effect of the equivalent R

bias network dc level.

and VM at the AIN pin must be allowed for when designing the

AIN

details

The above value for R

is derived by noting that the average AIN voltage must equal the bias voltage supplied

AIN

by the ac coupling network. The average value of V

in equation 8 is thus a constant voltage

LAST

= V(AIN bias) – VM

LAST

For an input voltage Vin at the AIN pin,

Qin = (Vin – V ) x Cs

LAST

Provided that f (−3 dB) is much lower than f , a constant current flowing over the clock period can approximate

clk

the input charging pulse

Iin = Qin / t

clk

LAST

= Qin x f

= (Vin – V

) x C x f

S clk

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

details (continued)

The ac input resistance R

is then

AIN

= dIin / dVin

AIN

= 1 / (dVin / dIin)

= 1 / (C x f

)

clk

driving the VREF pin (differential mode)

Figure 30 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin

(MODE = AV /2 and REFSENSE = AV ).

VREF

REFSENSE = AV

14 kΩ

Mode = AV

AGND

+ VREF

Figure 30. Equivalent Circuit of VREF

The current flowing into I is given by

_DDǓ

3 VREF * AV

_INǓ

4 R

(11)

Note that the actual I may differ from this value by up to 50% due to device-to-device processing variations

and allowing for operating temperature variations.

The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground

and capable of driving I .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

driving the internal reference buffer (top/bottom mode)

Figure 31 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal

reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.

REFTS

REFBS

14 kΩ

Mode = AV

AGND

+ REFTS + REFBS

Figure 31. Equivalent Circuit of Inputs to Internal Reference Buffer

Equations for the currents flowing into REFTS and REFBS are:

3 REFTS * AV

* REFBS

TS +

_INǓ

4 R

(12)

(13)

3 REFBS * AV

* REFTS

BS +

_INǓ

4 R

These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving

the sample and hold. Tolerance on these currents are 50%.

driving REFTS and REFBS

CLK

0.6 pF

REFTS

REFBS

7 pF

0.6 pF

SAMPLE

AGND

Mode = AV

CLK

LAST

Internal

Reference

Buffer

Figure 32. Equivalent Circuit of REFTS and REFBS Inputs

This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also

driving a switched capacitor load like AIN, but with the sampling capacitor and C on each pin now being 0.6 pF

and about 0.6 pF respectively.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ

ꢅꢆ ꢇ ꢀꢈ ꢉ ꢊ ꢉꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅ ꢄ ꢎꢂ ꢏ ꢂ

ꢐ ꢎ ꢈꢂ ꢑ ꢒꢑ ꢓ ꢈꢔꢆꢀꢈ ꢆꢕꢍ ꢔ ꢍꢀꢑꢓ ꢐꢈ ꢒꢇ ꢖ ꢗꢀ ꢖꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

driving REFTF and REFBF (full external reference mode)

REFTF

To REFBS

(For Kelvin Connection)

AGND

680 R

REFBF

To REFTS

(For Kelvin Connection)

AGND

Figure 33. Equivalent Circuit of REFTF and REFBF Inputs

Note the need for off-chip decoupling.

driving the clock input

Obtaining good performance from the THS1030 requires care when driving the clock input.

Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should

ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as

possible in which to operate.

The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at

the CLK input, any clock buffers external to the THS1030 should have fast rising edges. Use a fast logic family

such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other

logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.

The CLK input threshold is nominally around AV /2—ensure that any clock buffers have an appropriate supply

voltage to drive above and below this level.

digital output loading and circuit board layout

The THS1030 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30-MHz clock and 3-V

digital supply. Minimizing the load on the outputs will improve THS1030 signal-to-noise performance by

reducing the switching noise coupling from the THS1030 output buffers to the internal analog circuits. The

output load capacitance can be minimized by buffering the THS1030 digital outputs with a low input capacitance

buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks

between the THS1030 and this buffer.

Noise levels at the output buffers, and hence coupling to the analog circuits within THS1030, becomes worse

as the THS1030 digital supply voltage is increased. Where possible, consider using the lowest DV

application can tolerate.

that the

Use good layout practices when designing the application PCB to ensure that any off-chip return currents from

the THS1030 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any

sensitive analog circuits. The THS1030 should be soldered directly to the PCB for best performance. Socketing

the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢄ ꢅꢄ

ꢅ ꢆꢇ ꢀ ꢈ ꢉ ꢊꢉ ꢆꢇꢋ ꢃ ꢄ ꢆꢌꢍ ꢀꢋ ꢅꢄ ꢎ ꢂꢏ ꢂ

ꢐꢎ ꢈ ꢂ ꢑꢒꢑ ꢓꢈ ꢔ ꢆꢀꢈ ꢆꢕꢍꢔ ꢍ ꢀꢑꢓ ꢐꢈ ꢒ ꢇꢖ ꢗꢀ ꢖ ꢗ

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

user tips for obtaining best performance from the THS1030

Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails.

ORG modes offer the simplest configurations for ADC reference generation.

Choose differential input mode for best distortion performance.

Choose a 2-V ADC input span for best noise performance.

Choose a 1-V ADC input span for best distortion performance.

If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the

system. Care should be taken to ensure noise is not injected into the THS1030.

Use external voltage sources for ADC reference generation where there are stringent requirements on

accuracy and drift.

Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB

traces.

TLC876 mode

The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher

speed by dropping the THS1030 into their sockets. Grounding the 1876M pin effectively puts the THS1030 into

876 mode using the external ADC reference. The MODE pin should either be grounded or left floating.

The REFSENSE pin is connected to DV

when the THS1030 is dropped into a TLC876 socket. For

= 5-V applications, this will disable the ORG. For TLC876 applications using DV = 3.3 V, the VREF pin

will be driven to AV . In TLC876/AD876 mode, the pipeline latency is increased to 3.5 clock cycles to match

the TLC876 latency.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

THS1030CDW

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TH1030

THS1030CDWG4

THS1030CDWR

THS1030CDWRG4

THS1030CPW

ACTIVE

1000

Green (RoHS

& no Sb/Br)

0 to 70

TH1030

TJ1030

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

THS1030CPWG4

THS1030CPWR

THS1030CPWRG4

THS1030IDW

Green (RoHS

& no Sb/Br)

0 to 70

2000

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

-40 to 85

THS1030IDWG4

THS1030IPW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

THS1030IPWG4

THS1030IPWR

THS1030IPWRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

THS1030CDWR

THS1030CPWR

THS1030IPWR

SOIC

1000

2000

330.0

32.4

16.4

11.35 18.67

3.1

1.8

16.0

12.0

32.0

16.0

TSSOP

6.9

10.2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

THS1030CDWR

THS1030CPWR

THS1030IPWR

SOIC

1000

2000

367.0

55.0

38.0

TSSOP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

THS1030_13 [TI]

相关型号：

THS1031

THS1031CDW

THS1031CDWG4

THS1031CDWR

THS1031CDWRG4

THS1031CPW

THS1031CPWG4

THS1031CPWLE

THS1031CPWR

THS1031CPWRG4

THS1031IDW

THS1031IDWG4