THS1030_技术文档

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

28-PIN TSSOP/SOIC PACKAGE

(TOP VIEW)

10-Bit Resolution 30 MSPS

Analog-to-Digital Converter:

Configurable Input: Single-Ended or

Differential

AGND

AV

DD

1

28

27

26

25

24

23

22

21

20

19

18

DV

AIN

V

2

DD

Differential Nonlinearity: ±0.3 LSB

Signal-to-Noise: 57 dB

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

3

REF

REFBS

REFBF

MODE

4

5

Spurious Free Dynamic Range: 60 dB

Adjustable Internal Voltage Reference

Out-of-Range Indicator

6

REFTF

REFTS

876M

7

8

Power-Down Mode

9

AGND

10

11

Pin Compatible with TLC876

REFSENSE

description

I/O9 12

OVR 13

17 STBY

16 OE

The THS1030 is a CMOS, low power, 10-bit, 30

MSPS analog-to-digital converter (ADC) that can

operate with a supply range from 2.7 V to 3.3 V.

The THS1030 has been designed to give circuit

developers more flexibility. The analog input to the

DGND 14

15 CLK

THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage

references to match the user’s design requirements. For more design flexibility, the internal reference can be

bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the

application. The out-of-range output is used to monitor any out-of-range condition in THS1030s input range.

The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video,

multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit

charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and

camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both

imaging and communications systems.

The THS1030I is characterized for operation from –40°C to 85°C

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

28-TSSOP (PW)

THS1030CPW

THS1030IPW

28-SOIC (DW)

THS1030CDW

THS1030IDW

0°C to 70°C

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

functional block diagram

AIN

Output

Buffers

I/O0 –

I/O9

SHA

A/D

REFTS

REFBS

MODE

OVR

OE

DC

REF

SW3

Timing

Circuit

REFTF

REFBF

VBG

SW4

REFSENSE

VREF

STBY

CLK

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

Terminal Functions

TERMINAL

NAME

AGND

AIN

AV

I/O

DESCRIPTION

NO.

1, 19

27

I

Analog ground

Analog input

28

Analog supply

Clock input

DD

CLK

15

DGND

14

Digital ground

Digital driver supply

DV

2

DD

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

3

4

5

6

7

8

9

10

11

12

Digital I/O bit 0 (LSB)

Digital I/O bit 1

Digital I/O bit 2

Digital I/O bit 3

Digital I/O bit 4

Digital I/O bit 5

Digital I/O bit 6

Digital I/O bit 7

Digital I/O bit 8

Digital I/O bit 9 (MSB)

I/O

MODE

OE

23

16

13

25

24

18

22

21

17

26

20

I

Mode input

I

HI to the 3-state data bus, LO to enable the data bus

Out-of-range indicator

OVR

O

REFBS

REFBF

I

Reference bottom sense

I

Reference bottom decoupling

REFSENSE

REFTF

I

Reference sense

I

Reference top decoupling

REFTS

I

Reference top sense

STBY

I

I/O

I

HI = power down mode, LO = normal operation mode

Internal and external reference for ADC

HI = THS1030 mode, LO = TLC876 mode (see section 4 for TLC876 mode)

V

REF

876M

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage: AV

to AGND, DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 6.5 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 0.3 V

AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 to 6.5 V

DD

Mode input MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV

Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . . . –0.3 to AV

Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV

+ 0.3 V

DD

Reference input V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV

REF

Reference output V

REF

Clock input CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV

Digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to DV

Digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to DV

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C

Storage temperature range, T

J

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

STG

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM

MAX

UNIT

V

High-level input voltage, V

IH

2.4

Low-level input voltage, V

0.2 x DV

V

IL

DD

analog inputs

MIN NOM

MAX

REFTS

2

UNIT

Analog input voltage, V

I(AIN)

REFBS

V

Reference input voltage, V

1

0

I(VREF)

AV

DD

I(REFTS)

I(REFBS)

AV –1

DD

power supply

MIN NOM

MAX

UNIT

AV

DD

2.7

3

5.5

Supply voltage

Maximum sampling rate = 30 MSPS

V

DV

3

DD

REFTS, REFBS reference voltages (MODE = AV

)

DD

PARAMETER

MIN NOM

MAX

AV

UNIT

V

REFTS

REFBS

Reference input voltage (top)

1

DD

Reference input voltage (bottom)

Differential input (REFTS – REFBS)

Switched input capacitance on REFTS

0

AV –1

DD

V

1

2

V

0.5

pF

sampling rate and resolution

PARAMETER

MIN NOM

MAX

UNIT

Fs

5

30 MSPS

Bits

Resolution

10

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics over recommended operating conditions, AV = 3 V, DV

= 3 V, Fs = 30

DD

MSPS/50% duty cycle, MODE = AV , 2 V input span from 0.5 V to 2.5 V, external reference, T =

DD

A

–40°C to 85°C (unless otherwise noted)

analog inputs

PARAMETER

MIN

TYP

MAX

UNIT

V

I(AIN)

Analog input voltage

REFBS

REFTS

C

Switched input capacitance

Full power BW (–3 dB)

1.2

150

60

pF

I

FPBW

MHz

µA

DC leakage current (input = ±FS)

VREF reference voltages

PARAMETER

MIN

TYP

MAX

1.05

2.10

2

UNIT

V

Internal 1 V reference (REFSENSE = V

)

0.95

1.90

1

2

REF

Internal 2 V reference (REFSENSE = AV

V

SS

)

External reference (REFSENSE = AV

Reference input resistance

V

DD

18

kΩ

REFTF, REFBF reference voltages

PARAMETER

TEST CONDITIONS

MIN

1

TYP

MAX

2

UNIT

Differential input (REFTF – REFBF)

V

AV

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

1.3

2

1.5

2.5

2

1.7

3

DD

Input common mode (REFTF + REFBF)/2

V

REF

V

REF

V

REF

V

REF

= 1 V

= 2 V

= 1 V

= 2 V

3

REFTF (MODE = AV

)

DD

2.5

3.5

1

0.5

2

REFBF (MODE = AV

)

DD

V

1.5

600

Input resistance between REFTF and REFBF

Ω

dc accuracy

PARAMETER

MIN

TYP

±1

MAX

±2

UNIT

LSB

INL

Integral nonlinearity

Differential nonlinearity

Offset error

DNL

±0.3

0.4

±1

1.4 %FSR

3.5 %FSR

Gain error

1.4

Missing code

No missing code assured

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics over recommended operating conditions, AV = 3 V, DV

= 3 V, Fs = 30

DD

MSPS/50% duty cycle, MODE = AV , 2 V input span from 0.5 V to 2.5 V, external reference, T =

DD

A

–40°C to 85°C (unless otherwise noted) (continued)

dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

9

MAX

UNIT

f = 3.5 MHz

8.4

f = 3.5 MHz, AV

f = 15 MHz, 3 V

= 5 V

9

DD

ENOB

SFDR

THD

Effective number of bits

Spurious free dynamic range

Total harmonic distortion

Signal-to-noise

Bits

7.8

f = 15 MHz, AV

f = 3.5 MHz

7.7

DD

56

60.6

64.6

48.5

53

f = 3.5 MHz, AV

f = 15 MHz

DD

dB

f = 15 MHz, AV

f = 3.5 MHz

DD

–60

–66.9

–47.5

–53.1

57

–56

f = 3.5 MHz, AV

f = 15 MHz

DD

f = 15 MHz, AV

f = 3.5 MHz

DD

53

f = 3.5 MHz, AV

f = 15 MHz

56

DD

SNR

53.1

49.4

56

f = 15 MHz, AV

f = 3.5 MHz

DD

52.5

f = 3.5 MHz, AV

f = 15 MHz

56

DD

SINAD Signal-to-noise and distortion

dB

48.6

48.1

f = 15 MHz, AV

DD

clock

PARAMETER

MIN

33

TYP

MAX

UNIT

ns

t

Clock period

(CK)

(CKH)

(CKL)

d

Pulse duration, clock high

Pulse duration, clock low

Clock to data valid

Pipeline latency

15

16.5

ns

15

ns

20

ns

3

4

2

Cycles

ns

t

Aperture delay

(ap)

Aperture uncertainty (jitter)

ps

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

29

MAX

40

UNIT

I

Operating supply current

AV

=DV

DD

= 3 V, MODE = AGND

= 3 V

mA

CC

DD

= DV

87

120

DD

P

Power dissipation

mW

D

= DV

= 5 V

150

3

P (STBY) Standby power

=DV

= 3 V, MODE = AGND

5

D

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PARAMETER MEASUREMENT INFORMATION

Sample 2

Sample 3

Sample 1

Sample 5

Sample 4

Analog Input

t

(CK)

t

(CKL)

t

(CKH)

Input Clock

(See

Note A)

t

d

Pipeline Latency

Digital Output

Sample 1

Sample 2

NOTE A: All timing measurements are based on 50% of edge transition.

Figure 1. Digital Output Timing Diagram

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

TYPICAL CHARACTERISTICS

POWER

vs

SAMPLING FREQUENCY

90

88

86

84

82

80

78

76

AV

DD

= DV

= 3.5 MHz

= 3 V

DD

F

in

T

= 25°C

A

5

10

15

20

25

30

f

– Sampling Frequency – MHz

s

Figure 2

EFFECTIVE NUMBER OF BITS

vs

TEMPERATURE

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

= DV

= 3 V

DD

= 3.5 MHz

F

in

= 30 MSPS

s

–40

–15

10

35

60

85

Temperature – °C

Figure 3

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

DD

= DV

= 3.5 MHz

= 3 V

DD

F

in

T

= 25°C

A

5

10

15

20

25

30

f

– Sampling Clock – MSPS

s

Figure 4

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

DV

= 5 V

= 3 V

= 3.5 MHz

DD

F

T

A

in

= 25°C

5

10

15

20

25

30

f

– Sampling Clock – MSPS

s

Figure 5

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10.0

9.5

9.0

8.5

8.0

7.5

7

AV

DD

= DV

= 3.5 MHz

= 5 V

DD

F

in

A

T

= 25°C

5

10

15

20

25

30

f

– Sampling Clock – MSPS

s

Figure 6

DIFFERENTIAL NONLINEARITY

vs

INPUT CODE

1.00

0.80

AV

DD

= 3 V

DV

DD

0.60

F

= 30 MSPS

s

0.40

0.20

–0.00

–0.20

–0.40

–0.60

–0.80

–1.00

0

128

256

384

512

640

768

896

1024

Input Code

Figure 7

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

vs

INPUT CODE

2.0

1.5

AV

DD

= 3 V

DV

DD

Fs = 30 MSPS

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2

0

128

256

384

512

640

768

896

1024

Input Code

Figure 8

FFT

vs

FREQUENCY

0

–20

AV

DD

= 3 V

DV

DD

= 3.5 MHz

F

in

–40

–60

–80

–100

–120

–140

0

2

4

6

8

10

12

14

f – Frequency – MHz

Figure 9

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

Table 1. Mode Selection

ANALOG

INPUT

SPAN

MODE

REFSENSE

VREF

REFTS

REFBS

MODES

FIGURE

AIN

1 V

2 V

AV

Short together

AGND

7, 14

8, 15

DD

AV

AGND

Short together

Short together to R

a

Top/bottom

1+R /R

Mid R & R

9, 14, 15

a

b

a

b

External

AIN

AV

DD

NC

AGND

10, 14, 15

DD

V

REF

AIN

1 V

2 V

AV /2

DD

Short together

AGND

Mid R & R

7, 13

8, 13

9, 13

10, 13

AV /2

DD

NC

Short together to the common

mode voltage

Center span

1+R /R

AV /2

DD

R

a

b

a

b

a

V

REF

AV /2

DD

AV

DD

External

reference

Voltage within supply

(REFTS–REBS) = 2 V max

AIN

2 V max

AGND

See Note 1

AGND

See Note 1

11, 12

AIN is input 1

REFTS &

REFBS are

shorted

together for

input 2

1 V

2 V

AV

Short together

DD

Differential

input

NC

Short together AV /2

DD

16

V

REF

AV

DD

External

NOTE 1: In external reference mode, V

can be available for external use with CENTER SPAN set-up.

REF

reference operations

V

-pin reference

REF

The voltage reference sources on the V

pin are controlled by the REFSENSE pin as shown in Table 2.

REF

Table 2. V

Reference Selection

REF

REFSENSE

V

REF

AGND

2 V

AV

DD

The internal reference is disabled and an external reference should be connected to V

pin.

REF

Short to V

REF

1 V

Connect to R /R

1+R /R

a b

a

b

1-V reference: The internal reference may be set to 1 V by connecting REFSENSE to V

.

REF

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

V

-pin reference (continued)

REF

THS1030

ADC/DAC

REF

+

_

V

REF

= 1 V

+

–

VBG

REFSENSE

AGND

Figure 10. V

1-V Reference Mode

REF

2-V reference: The internal reference may be set to 2 V by connecting REFSENSE to AGND.

THS1030

ADC/DAC

REF

+

_

V

REF

= 2 V

+

–

VBG

REFSENSE

AGND

Figure 11. V

2-V Reference Mode

REF

External divider: The internal reference can be set to a voltage between 1 V and 2 V by adding external

resistors.

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

V

-pin reference (continued)

REF

THS1030

ADC/DAC

REF

+

_

V

REF

= 1 + (Ra/Rb)

+

–

VBG

Ra

REFSENSE

Rb

AGND

Figure 12. V

External-Divider Reference Mode

REF

External reference: The internal reference may be overridden by using an external reference. This

condition is met by connecting REFSENSE to AV

and an external reference circuit to the V

pin.

DD

REF

THS1030

ADC/DAC

REF

+

V

REF

= External

_

+

VBG

–

REFSENSE

AV

DD

AGND

Figure 13. V

External Reference Mode

REF

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

ADC reference

The MODE pin is used to select the reference source for the ADC.

Internal ADC Reference: Connect the MODE pin to AV to use the reference source for ADC generated

DD

on the V

pin. (See V

REFERENCE described in Table 2) such that (REFTF–REFBF) = V

and

REF

(REFTF+REFBF)/2 is set to a voltage for optimum operation of the ADC (near AV /2).

DD

External ADC Reference: To supply an external reference source to the ADC, connect the MODE pin to

AGND. An external reference source should be connected to REFTF/REFTS and REFBF/REFBS.

MODE =AGNDclosesinternalswitchestoallowaKelvinconnectionthroughREFTS/REFBS, anddisables

the on-chip amplifiers which drive on to the ADC references. Differential input is not supported

analog input mode

single-ended input

The single-ended input can be configured to work with either an external ADC reference or internal ADC

reference.

External ADC Reference Mode: A single-ended analog input is accepted at the AIN pin where the input

signal is bounded by the voltages on the REFTS and REFBS pins. Figure 14 shows an example of applying

external reference to REFTS and REFBS pins in which REFTS is connected to the low-impedance 2-V

source and REFBS is connected to the low-impedance 2-V source. REFTS and REFBS may be driven to

any voltage within the supply as long as the difference (REFTS – REFBS) is between 1 V and 2 V as

specified in Table 2. Figure 15 shows an example of an external reference using a Kelvin connection to

eliminate line voltage drop errors.

2 V

1 V

THS1030

SHA

AIN

A/D

REFTS

2 V

1 V

REFBS

MODE

SW3

REFTF

0.1 µF

10 µF

REFBF

Figure 14. External ADC Reference Mode

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

single-ended input (continued)

REFTF

REFBF

THS1030

SHA

AIN

A/D

REFTS

REFBS

MODE

0.1 µF

SW3

REFTF

REFT

0.1 µF

10 µF

REFBF

REFB

Figure 15. Kelvin Connection With External ADC Reference Mode

InternalADCReferenceModeWithExternalInputCommonMode:Theinputcommonmodeissupplied

to pins REFTS and REFBS while connected together. The input signal should be centered around this

common mode with peak-to-peak input equal to the voltage on the V

pin. Input can be either dc-coupled

REF

or ac-coupled to the same common mode voltage (see Figure 16) or any other voltage within the input

voltage range.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

single-ended input (continued)

2 V

THS1030

SHA

AIN

1 V

A/D

REFTS

1.5 V

REFBS

MODE

AV

DD

REFTF

ADC

REF

0.1 µF

10 µF

V

REF

0.1 µF

+

_

– +

1 V

REFBF

0.1 µF

REFSENSE

Figure 16. External Input Common Mode

Internal ADC Reference Mode With Common Mode Input V : The input common mode is set to

REF/2

V

/2byconnectingREFTStoV

andREFBStoAV .TheinputsignalatAINwillswingbetweenV

REF

SS REF

and AV

.

SS

2 V

1 V

THS1030

AIN

SHA

A/D

REFTS

1.5 V

REFBS

MODE

AV

DD

REFTF

ADC

REF

0.1 µF

10 µF

+

_

– +

1 V

V

REF

REFBF

0.1 µF

REFSENSE

Figure 17. Common Mode Input V

/2 With 1-V Internal Reference

REF

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

single-ended input (continued)

2 V

THS1030

SHA

AIN

1 V

A/D

REFTS

1.5 V

REFBS

MODE

AV

DD

REFTF

ADC

REF

0.1 µF

10 µF

0.1 µF

+

_

– +

1 V

V

REF

REFBF

0.1 µF

REFSENSE

Figure 18. Common Mode Input V

/2 With 2-V Internal Reference

REF

differential input

In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the

common point where REFTS and REFBS are tied together. The common mode of the input should be set to

AV /2 as shown in Figure 19. The maximum magnitude of the differential input signal should be equal to V

.

DD

REF

V

REF

THS1030

SHA

AIN

AV /2

DD

A/D

REFTS

REFBS

MODE

AV

DD

REFTF

ADC

REF

V

REF

V

REF

is either internal or external

0.1 µF

10 µF

0.1 µF

REFBF

0.1 µF

Figure 19. Differential Input

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PRINCIPLES OF OPERATION

digital input mode

3-State Output: The digital outputs can be set to high-impedance state by applying a LO logic to the OE

pin.

Power Down: The whole device will power down by applying a HI logic to the STBY pin. The ADC will wake

up in 400 ns after the pin STBY is reset.

TLC876 mode

The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher

speed by dropping the THS1030 into their sockets. Floating the MODE pin effectively puts the THS1030 into

876 mode using the external ADC reference. The REFSENSE pin will be connected to DV

by the TLC876

DD

socket. In the TLC876/AD876 mode, the pipeline latency will be switched to 3.5 cycles to match TLC876/AD876

specifications.

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

16 PINS SHOWN

0.050 (1,27)

16

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

9

0.419 (10,65)

0.400 (10,15)

0.010 (0,25) NOM

0.299 (7,59)

0.293 (7,45)

Gage Plane

0.010 (0,25)

1

8

0°–8°

0.050 (1,27)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.012 (0,30)

0.004 (0,10)

0.104 (2,65) MAX

PINS **

16

20

24

28

DIM

0.410

0.510

0.610

0.710

A MAX

A MIN

(10,41) (12,95) (15,49) (18,03)

0.400

0.500

0.600

0.700

(10,16) (12,70) (15,24) (17,78)

4040000/C 07/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	THS1030
厂家：	TEXAS INSTRUMENTS
描述：	2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER 2.7 V 。 5.5 V ， 10位， 30 MSPS CMOS模拟数字转换器转换器
文件：	总22页 (文件大小：303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS1030 [TI]

相关型号：

THS1030CDW

THS1030CDWG4

THS1030CDWR

THS1030CDWRG4

THS1030CPW

THS1030CPWG4

THS1030CPWLE

THS1030CPWR

THS1030CPWRG4

THS1030IDW

THS1030IDWG4

THS1030IDWR