THS2630 [TI]
35V、180MHz 高速、低噪声、全差分放大器;
| 型号： | THS2630 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 35V、180MHz 高速、低噪声、全差分放大器 放大器 |
| 文件： | 总37页 (文件大小：2070K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS2630
ZHCSQB3 –JANUARY 2023
THS2630 高速、低噪声、全差分I/O 放大器
1 特性
3 说明
• 高性能
THS2630 器件属于全差分输入/差分输出器件系列，该
系列器件使用德州仪器 (TI) 先进的高压互补双极工艺
制造。
– 带宽：187MHz（VCC = ±15V，G = 1V/V）
– 压摆率：75V/µs
– 增益带宽积：245MHz
– 失真：-108dBc THD（2VPP、250kHz 时）
THS2630 具有从输入到输出的真正全差分信号路径和
高达 ±17.5V 的高电源电压。这种设计带来了出色的共
模噪声抑制性能（800kHz 时为 95dB）和总谐波失真
（2VPP、250kHz 时为 −108dBc）。高电压差分信号
链可通过宽电源电压范围提高裕量和动态范围，而无需
为差分信号的每个极性添加单独的放大器。
• 电压噪声
– 1/f 电压噪声拐角频率：85Hz
– 输入基准噪声1.1nV/√Hz
• 单电源电压范围：5V 至35V
• 静态电流（关断）：770µA (THS2630S)
THS2630 在–40°C 至+85°C 的宽温度范围内运行。
2 应用
封装信息(1)
• 单端至差分转换
• 差分ADC 驱动器
• 差分抗混叠
• 差分发送器和接收器
• 输出电平转换器
• 医疗超声波
封装尺寸（标称值）
器件型号
封装
D（SOIC，8）
4.90mm × 3.91mm
THS2630
DGN（HVSSOP，8） 3.00mm × 3.00mm
DGK（VSSOP，8） 3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
-50
± 15 V
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-60
THS4032
-70
+5 V
± 15 V
-80
-90
CH_A
To TGC VCNTL
DAC8802
THS2630
-100
-110
-120
AFE58JD18
CH_B
100k
1M
10M
Frequency (Hz)
VOUT = 2VPP
Filtering and
Attenuation
Low-Noise Current to
Voltage Converter
总谐波失真与频率间的关系
适用于超声波的时间增益控制DAC
参考设计
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOSE96
THS2630
ZHCSQB3 –JANUARY 2023
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Table of Contents
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 18
8.3 Power Supply Recommendations.............................20
8.4 Layout....................................................................... 20
9 Device and Documentation Support............................23
9.1 Documentation Support............................................ 23
9.2 接收文档更新通知..................................................... 23
9.3 支持资源....................................................................23
9.4 Trademarks...............................................................23
9.5 静电放电警告............................................................ 23
9.6 术语表....................................................................... 23
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics: THS2630D............................ 8
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................14
Information.................................................................... 23
10.1 Mechanical Data..................................................... 24
10.2 Tape and Reel Information......................................28
4 Revision History
DATE
REVISION
NOTES
January 2023
*
Initial Release
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5 Pin Configuration and Functions
VIN-
VOCM
VCC+
1
2
3
4
8
7
6
5
VIN+
PD
VIN-
VOCM
VCC+
1
2
3
4
8
7
6
5
VIN+
NC
VCC -
VOUT-
VCC -
VOUT-
VOUT+
VOUT+
图5-1. THS2630S D, DGN, or DGK Package
8-Pin SOIC, HVSSOP, or VSSOP
(Top View)
图5-2. THS2630 D, DGN, or DGK Package
8-Pin SOIC, HVSSOP, or VSSOP
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NC
THS2630S THS2630
7
No connect
—
7
3
6
1
2
4
5
8
—
I
PD
Active low power-down pin
Positive supply voltage pin
Negative supply voltage pin
Negative input pin
—
3
6
1
2
4
5
8
VCC+
VCC–
VIN–
VOCM
VOUT+
VOUT–
VIN+
I/O
I/O
I
I
Common mode input pin
Positive output pin
O
O
I
Negative output pin
Positive input pin
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VI
Input voltage
+VCC
37
V
V
–VCC
VCC– to VCC+
Supply voltage
Supply turn-on/off dV/dT(2)
1.7
150
1.5
10
V/µs
mA
V
(3)
IO
Output current
VID
IIN
Differential input voltage
-1.5
Continuous Input Current
Maximum junction temperature
Maximum junction temperature, continuous operation, long-term reliability
Operating free-air temperature
Storage temperature
mA
°C
°C
°C
°C
(4)
TJ
150
125
85
(5)
TJ
TA
0
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remain off.
(3) The THS2630 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the
PowerPAD thermally-enhanced package.
(4) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(5) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
6.2 ESD Ratings
VALUE
UNIT
THS2630: D, DGK, OR DGN PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±3500
±1500
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.5
5
NOM
MAX
±17.5
35
UNIT
V
Dual supply
Vcc+ to
Vcc–
Single supply
TA
Operating free-air temperature
85
°C
–40
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6.4 Thermal Information
THS2630
DGN (HVSSOP)
8 PINS
57.3
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.3
67.3
DGK (VSSOP)
UNIT
8 PINS
147.3
37.9
83.2
0.9
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
82.9
RθJB
ψJT
Junction-to-board thermal resistance
69.8
29.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
19.5
6.3
69.0
29.7
81.6
n/a
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
13.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DYNAMIC PERFORMANCE
VCC = 5 V
181
183
187
108
108
111
245
100
75
VCC = ±5 V
VCC = ±15 V
VCC = 5 V
Gain = 1, RF = 390 Ω
Small-signal bandwidth (–3 dB),
BW
MHz
single-ended input, differential
output, VI = 63 mVPP
VCC = ±5 V
VCC = ±15 V
Gain = 2, RF = 750 Ω
Gain-bandwidth product
VOCM small-signal bandwidth
Slew rate(1)
VO = 200 mVPP, Gain = 20, RF = 750Ω
MHz
V/µs
ns
VI = 63 mVPP
SR
ts
Settling time to 0.1%
Settling time to 0.01%
31
Step voltage = 2 V, gain = 1
52
DISTORTION PERFORMANCE
f = 250 kHz
–106
–93
–106
–93
–108
–94
–99
–84
–100
–86
109
VCC = 5 V
f = 1 MHz
f = 250 kHz
VCC = ±5 V
f = 1 MHz
Total harmonic distortion, differential
input, differential output, VO = 2 VPP
f = 250 kHz
VCC = ±15 V
THD
dBc
f = 1 MHz
f = 250 kHz
VCC = ±5 V
f = 1 MHz
VO = 4 VPP
f = 250 kHz
VCC = ±15 V
f = 1 MHz
VCC = ±2.5
VO= 2 VPP
VO = 4 VPP
VCC = ±5
VCC = ±15
VCC = ±5
VCC = ±15
112
Spurious-free dynamic range,
differential input, differential output, f
= 250 kHz
SFDR
116
dBc
104
106
IMD3
OIP3
Third intermodulation distortion
Third-order intercept
dBc
dB
–53
41.5
VI(PP) = 4 V, F1 = 3 MHz, F2 = 3.5 MHz
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MAX UNIT
6.5 Electrical Characteristics (continued)
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
NOISE PERFORMANCE
Vn
In
Input voltage noise
Input current noise
f = 10 kHz
f = 10 kHz
1.1
1.3
nV/√Hz
pA/√Hz
DC PERFORMANCE
TA = +25°C
91
87
95
Open-loop gain
dB
TA = full range
TA = +25°C
VOS
VOS
Input offset voltage
Input offset voltage
Input offset voltage drift
Input bias current
-1.3
±0.1
1.3
mV
1.5
TA = full range
TA = full range
TA = 25℃
0.8
4.8
4.8
22
3.2 µV/°C
9.8
IIB
TA = 25℃
IIB
Input bias current
TA = full range
TA = 25℃
TA = full range
TA = 25℃
15.1
350
400
µA
nA
IOS
IOS
Input offset current
Input offset current
Input offset current drift
-250
81
TA = full range
TA = full range
nA
0.13
95
nA/°C
INPUT CHARACTERISTICS
CMRR
VICR
Common-mode rejection ratio
dB
V
TA = 25℃
TA = 25℃
–3.77 to
–4 to
Common-mode input voltage range
4.3
4.5
RI
RI
Common-mode input resistance
Differential input resistance
320
12
MΩ
kΩ
Measured into each input terminal
Measured into each input terminal
Common- mode input capacitance,
closed loop
CI_CM
1.3
pF
Differential input capacitance, closed
loop
CI_DIFF
ro
2.3
26
pF
Output resistance
Open loop
Open loop
Ω
OUTPUT CHARACTERISTICS
TA = +25°C
±13.1
±12.9
25
±13.4
45
V
V
Output voltage swing
VCC = ±15 V, RL = 1kΩ
VCC = 5 V, RL = 7 Ω
VCC = ±5 V, RL = 7 Ω
VCC = ±15 V, RL = 7 Ω
TA = full range
TA = +25°C
TA = full range
TA = +25°C
20
30
55
IO
Output current
mA
TA = full range
TA = +25°C
28
65
85
TA = full range
60
POWER SUPPLY
Quiescent current
VCC = ±5 V
VCC = ±5 V
VCC = ±15 V
VCC = ±17.5 V
TA = +25°C
TA = full range
TA = +25°C
TA = +25°C
8.9
10.5
12.4
13.2
13.2
mA
mA
mA
mA
Quiescent current
Quiescent current
Quiescent current
ICC
11
11
Quiescent current (shutdown)
(THS2630S only)(2)
ICC(SD)
PSRR
TA = +25°C
TA = +25°C
0.77
98
0.92
mA
dB
PD = –5 V
Power-supply rejection ratio (dc)
76
OUTPUT COMMON-MODE (VOCM) CONTROL
VOCM
VOCM offset voltage
specs
VOCM driven to midsupply
-2.7
0.2
2.7
mV
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6.5 Electrical Characteristics (continued)
VCC= ±5 V, Gain = 1 V/V, RF = 390 Ω, RL = 800 Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
Default VOCM offset
VOCM input range low
VOCM input range high
VOCM input range low
VOCM input range high
VOCM input noise
TEST CONDITIONS
MIN
TYP
0.65
–14
13.7
–4.1
3.8
MAX UNIT
Relative to midsupply, VOCM pin floating
-10
10
mV
V
–13.8
VS = ±15 V
13.3
3.5
V
VOCM
specs
V
V
–4
Flat-band, Vocm driven
13
nV/√Hz
kΩ
VOCM input resistance
15
(1) Slew rate is measured from an output level range of 25% to 75%.
(2) For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section.
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6.6 Typical Characteristics: THS2630D
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω(unless otherwise
noted)
25
20
15
10
5
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
0
G = 1, RF = 390
G = 2, RF = 750
G = 5, RF = 2 k
G = 10, RF = 4 k
-5
RF = 390
RF = 620
-10
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
VI = 63 mVPP
VI = 63 mVPP
图6-1. Small-Signal Frequency Response
图6-2. Small-Signal Frequency Response
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
VCC = 5 V
VCC = 15 V
100k
1M
10M
100M
1G
Frequency (Hz)
VI = 63 mVPP
VI = 63 mVPP
图6-4. Small-Signal Frequency Response
图6-3. Small-Signal Frequency Response
1
0.5
0
VoutP
VoutN
VI (Diff)
-0.5
0.5
0
-0.5
-1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (s)
.
VI = 63 mVPP
图6-6. Large-Signal Transient Response (Differential In/Single
图6-5. Small-Signal Frequency Response
Out)
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6.6 Typical Characteristics: THS2630D (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω(unless otherwise
noted)
5
0
-20
-40
-5
-60
-10
-15
-20
-25
-80
-100
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-120
100k
1M
10M
100M
100k
1M
10M
Frequency (Hz)
100M
1G
Frequency (Hz)
RF = 1 kΩ
VI = 0.2 VRMS
图6-8. Common-Mode Rejection Ratio vs Frequency
图6-7. Large-Signal Frequency Response
13
12
11
10
9
900
VCC = 15 V
VCC = 5 V
850
800
750
700
650
8
7
-40
-40
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
TA - Free-Air Temperature (C)
TA - Free-Air Temperature (C)
.
.
图6-10. Supply Current vs Free-Air Temperature (Shutdown
图6-9. Supply Current vs Free-Air Temperature
State)
-2
-3
-4
-5
-6
-7
-8
2.04
2.02
2
IB-
IB+
1.98
1.96
1.94
1.92
1.9
0
25
50
75
Time (ns)
100
125
150
-50
-25
0
25
50
75
100
TA - Free-Air Temperature - C
RF = 510 Ω, CF= 1 pF, VCC= 5 V, VO = 4 VPP
图6-12. Settling Time
.
图6-11. Input Bias Current vs Free-Air Temperature
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6.6 Typical Characteristics: THS2630D (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω(unless otherwise
noted)
-30
-40
-50
-60
-70
-80
-90
-100
2.5
2
VCC = +5 V
VEE = -5 V
1.5
1
0.5
0
+
VO-
VO
-0.5
-1
-1.5
-2
-2.5
10k
100k
1M
10M
100M
0
40
80
120
Time (ns)
160
200
Frequency (Hz)
RF = 330 Ω, RL = 400 Ω
VI_Peak = 2 V, CL = 10 pF, VCC = ±15 V
图6-13. Power-Supply Rejection Ratio vs Frequency
图6-14. Large-Signal Transient Response
(Differential Out)
-50
-50
-60
VCC = 2.5 V
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
VCC = 5 V
-60
VCC = 15 V
-70
-70
-80
-90
-80
-90
-100
-110
-120
-100
-110
-120
100k
1M
10M
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
VOUT = 2 VPP
VOUT = 2 VPP, Single-ended Input, Differential Output
图6-16. Second-Harmonic Distortion vs Frequency
-104
图6-15. Total Harmonic Distortion vs Frequency
-30
VCC = 5 V
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-40
-50
-106
-108
-110
-112
-114
-116
-118
-120
-122
VCC = 15 V
-60
-70
-80
-90
-100
-110
-120
100k
1M
10M
0
1
2
3
4
5
6
7
Frequency (Hz)
VO - Output Voltage (V)
f = 250 kHz, Single-ended Input, Differential Output
图6-18. Second-Harmonic Distortion vs Output Voltage
VOUT = 4 VPP, Single-ended Input, Differential Output
图6-17. Second-Harmonic Distortion vs Frequency
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6.6 Typical Characteristics: THS2630D (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω(unless otherwise
noted)
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-30
-40
VCC = 2.5 V
VCC = 5 V
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-50
-60
-70
-80
-90
-100
-110
-120
100k
1M
10M
0
1
2
3
4
5
6
7
Frequency (Hz)
VOUT - Output Voltage (V)
VOUT = 4 VPP, Single-ended Input, Differential Output
图6-20. Third-Harmonic Distortion vs Frequency
f = 500 kHz, Single-ended Input, Differential Output
图6-19. Second-Harmonic Distortion vs Output Voltage
-40
-90
VCC = 2.5 V
-94
-98
-50
-60
VCC = 5 V
VCC = 15 V
-102
-106
-110
-114
-118
-122
-126
-130
-134
-70
-80
-90
-100
-110
-120
-130
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
100k
1M
10M
0
1
2
3
4
5
6
7
Frequency (Hz)
VO - Output Voltage (V)
VOUT = 2 VPP, Single-ended Input, Differential Output
图6-21. Third-Harmonic Distortion vs Frequency
f = 500 kHz, Single-ended Input, Differential Output
图6-22. Third-Harmonic Distortion vs Output Voltage
-100
10
-105
-110
-115
-120
-125
-130
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
1
0
1
2
3
4
5
6
7
10
100
1k
10k
100k
VOUT - Output Voltage (V)
Frequency (Hz)
f = 250 kHz, Single-ended Input, Differential Output
.
图6-23. Third-Harmonic Distortion vs Output Voltage
图6-24. Voltage Noise vs Frequency
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6.6 Typical Characteristics: THS2630D (continued)
at TA = 25°C, VCC = ±5 V, RF = 390 Ω, G = +1 V/V, differential input, differential output and RL = 800 Ω(unless otherwise
noted)
10
1
10
100
1k
10k
100k
Frequency (Hz)
.
RF = 1 kΩ
图6-25. Current Noise vs Frequency
图6-26. Input Offset Voltage vs Common-Mode Output Voltage
15
100
10
5
Vcc = 5 V
Vcc = 15 V
10
1
0
-5
-10
-15
0.1
100k
100
1k
10k
100k
1M
10M
100M
1G
RL ()
Frequency (Hz)
.
RF = 1 kΩ, G = 2 V/V
图6-28. Output Impedance vs Frequency
图6-27. Output Voltage vs Differential Load Resistance
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7 Detailed Description
7.1 Overview
7.1.1 Fully-Differential Amplifiers
The THS2630 is a fully differential amplifier (FDA). Differential signal processing offers a number of performance
advantages in high-speed analog signal processing systems, including immunity to external common-mode
noise, suppression of even-order non-linearities, and increased dynamic range. FDAs not only serve as the
primary means of providing gain to a differential signal chain, but also provide a monolithic solution for
converting single-ended signals into differential signals allowing for easy, high-performance processing. For
more information on the basic theory of operation for FDAs, refer to the Fully Differential Amplifiers application
note.
7.2 Functional Block Diagram
V
CC+
Output Buffer
V
IN−
x1
V
OUT+
C
R
R
V
IN+
Vcm Error
Amplifier
+
_
C
x1
V
OUT−
Output Buffer
V
CC+
30 kW
V
CC−
30 kW
V
CC−
V
OCM
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7.3 Feature Description
图 7-1 and 图 7-2 shows the differences between the operation of the THS2630 in two different modes. FDAs
can work with either differential or single-ended inputs.
RG
RG
RF
RF
VCC+
VCC+
VSource
–
+
–
+
VOUT+
VOUT-
VOUT+
VOUT-
+
–
+
–
VOCM
VSource
VOCM
VCC-
VCC-
RG
RF
RG
RF
图7-2. Amplifying Single-ended Input Signals
图7-1. Amplifying Differential Input Signals
7.4 Device Functional Modes
7.4.1 Power-Down Mode
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS2630S is an active low input. If left unconnected, an internal 250 kΩ resistor to VCC+ keeps the device
turned on. The threshold voltage for the power-down function is approximately 1.4 V above VCC–. This means
that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V above
VCC–, the device is off. It is recommended to pull the terminal to VCC– to turn the device off. 图 7-3 shows the
simplified version of the power-down circuit. While in the power-down state, the amplifier goes into a high-
impedance state. The amplifier's output impedance is typically greater than 1 MΩ in the power-down state.
V
CC
250 kΩ
To Internal Bias
Circuitry Control
PD
V
CC
图7-3. Simplified Power-Down Circuit
Similar to an opamp in an inverting configuration, the output impedance of an FDA is determined by its feedback
network configuration. In addition, the THS2630S has an internal 10 kΩresistor at each output that is tied to the
VCM error amplifier (see 节 7.2). The differential output impedance is equal to [(2*RF + 2*RG) || 20 kΩ]. 图 7-4
shows the closed loop output impedance of the THS2630S when in power-down.
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3500
3000
2500
2000
1500
1000
500
0
100k
1M
10M
100M
1G
Frequency (Hz)
VCC = ±5 V, G = 1 V/V, RF = 1kΩ, PD = VCC-
图7-4. Output Impedance (in Power-Down) vs Frequency
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Output Common-Mode Voltage
The output common-mode voltage pin sets the dc output voltage of the THS2630. A voltage applied to the VOCM
pin from a low-impedance source can be used to directly set the output common-mode voltage. If the VOCM pin
is left floating it defaults to the mid-rail voltage, defined as:
V
+ V
CC +
CC −
(1)
2
To minimize common-mode noise, connect a 0.1-µF bypass capacitor to the VOCM pin. Output common-mode
voltage causes additional current to flow in the feedback resistor network. Since this current is supplied by the
output stage of the amplifier, this creates additional power dissipation. For commonly-used feedback resistance
values, this current is easily supplied by the amplifier. The additional internal power dissipation created by this
current may be significant in some applications and may dictate use of the MSOP PowerPAD package to
effectively control self-heating.
8.1.1.1 Resistor Matching
Resistor matching is important in FDAs to maintain good output balance. An ideal differential output signal
implies the two outputs of the FDA should be exactly equal in amplitude and shifted 180° in phase. Any
imbalance in amplitude or phase between the two output signals results in an undesirable common-mode signal
at the output. The output balance error is a measure of how well the outputs are balanced and is defined as the
ratio of the output common-mode voltage to the output differential signal.
V
− V
2
OUT +
OUT +
OUT −
Output Balance Error =
(2)
V
− V
OUT −
At low frequencies, resistor mismatch is the primary contributor to output balance errors. Additionally CMRR,
PSRR, and HD2 performance diminish if resistor mismatch occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to optimize performance. See 表8-1 for recommended resistor values to use for a
particular gain.
表8-1. Recommended Resistor Values
Gain (V/V)
RG (Ω)
RF (Ω)
390
1
2
390
374
750
5
402
2010
4020
10
402
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8.1.2 Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The THS2630 has been internally compensated to maximize its bandwidth and slew rate performance.
When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the
device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in 图
8-1. A minimum value of 20 Ω should work well for most applications. For example, in 50-Ω transmission
systems, setting the series resistor value to 50 Ω both isolates any capacitance loading and provides the proper
line impedance matching at the source end.
RG
RF
VCC+
20 Ω
VOUT+
–
+
+
–
VOCM
VOUT-
20 Ω
VCC-
RG
RF
图8-1. Driving a Capacitive Load
8.1.3 Data Converters
Driving data converters are one of the most popular applications for fully-differential amplifiers. 图 8-2 shows a
typical configuration of an FDA attached to a differential analog-to-digital converter (ADC).
RG
RF
VDD
VIN
VCC+ = 5 V
RCB
AVDD DVDD
AIN1
–
VOCM
+
–
CCB
THS1206
+
AIN2
VREF
AVSS
0.1 μF
RCB
VCC- = -5 V
RG
RF
图8-2. Fully-Differential Amplifier Attached to a Differential ADC
FDAs can operate with a single supply. VOCM defaults to the mid-rail voltage, VCC/2. The differential output may
be fed into a data converter. This method eliminates the use of a transformer in the circuit. If the ADC has a
reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the amplifier using a
bypass capacitor to reduce broadband common-mode noise.
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RG
RF
VDD
VIN
VCC = 5 V
RCB
AVDD DVDD
AIN1
–
VOCM
+
–
CCB
THS1206
+
0.1 μF
AIN2
VREF
AVSS
RCB
RG
RF
图8-3. Fully-Differential Amplifier Using a Single Supply
8.1.4 Single-Supply Applications
For proper operation, the input common-mode voltage to the input terminal of the amplifier should not exceed
the common-mode input voltage range. However, some single-supply applications may require the input voltage
to exceed the common-mode input voltage range. In such cases, the circuit configuration of 图 8-4 is suggested
to bring the common-mode input voltage within the specifications of the amplifier.
VCC
RPU
RG
RF
VDD
VIN
VP
VCC = 5 V
RCB
VOUT
AVDD DVDD
AIN1
–
VOCM
+
–
CCB
THS1206
VCC
+
0.1 μF
AIN2
VREF
AVSS
RPU
VOUT
RCB
RG
RF
图8-4. Circuit With Improved Common-Mode Input Voltage
方程式3 is used to calculate RPU
:
V
− V
CC
P
R
=
(3)
PU
1
1
V
− V
+
V
− V
IN
P
OUT P
R
R
G
F
8.2 Typical Application
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. 图 8-5 shows a
method by which the noise may be filtered in the THS2630.
图 8-5 shows a typical application design example for the THS2630 device in active low-pass filter topology
driving and ADC.
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C1
R2
V
CC
R4
+
C3
R1
R3
−
+
V
−
V
V
+
IN
IN
R
(t)
THS2630
C2
Vs
THS1050
−
+
−
IN
V
+
IN
V
OCM
V
OCM
C3
R1
R3
V
R4
IC
V
−
CC
+
C1
R2
图8-5. Antialias Filtering
8.2.1 Design Requirements
表8-2 provides example design parameters and values for the typical application design example in 图8-5.
表8-2. Design Parameters
DESIGN PARAMETERS
Supply voltage
VALUE
±2.5 V to ±17.5 V
Voltage feedback
Amplifier topology
DC coupled with output common
mode control capability
Output control
500 kHz, Multiple feedback low
pass filter
Filter requirement
8.2.2 Detailed Design Procedure
8.2.2.1 Active Antialias Filtering
图8-5 shows a multiple-feedback (MFB) lowpass filter. The transfer function for this filter circuit is:
Rt
K
2R4 + Rt
j2πfR4RtC3
2R4 + Rt
R2
R1
H
f =
×
Wℎere K =
(4)
(5)
d
2
f
jf
1
1 +
−
+
+ 1
Q
FSF × fc
FSF × fc
2 × R2R3C1C2
1
FSF × fc =
and Q =
R3C1 + R2C1 + KR3C1
2π 2 × R2R3C1C2
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
2
2
Re + Im
2
2
FSF = Re + Im and Q =
(6)
2Re
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
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2 × mn
1 + m 1 + K
1
FSF × fc =
and Q =
(7)
2πRc 2 × mn
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
8.2.3 Application Curve
5
0
-5
-10
-15
VCC = 2.5 V
VCC = 5 V
VCC = 15 V
-20
-25
100k
1M
10M
100M
1G
Frequency (Hz)
图8-6. Large-Signal Frequency Response
8.3 Power Supply Recommendations
The THS2630 device was designed to be operated on power supplies ranging from ±2.5 V to ±17.5 V (single-
ended supplies of 5 V to 35 V). TI recommends using a power-supply accuracy of 5% or better. When operated
on a board with high-speed digital signals, it is important to provide isolation between digital signal noise and the
analog input pins. The THS2630 is connected to power supplies through pin 3 (VCC+) and pin 6 (VCC-). Each
supply pin should be decoupled to GND as close to the device as possible with a low-inductance, surface-mount
ceramic capacitor of approximately 10 nF. When vias are used to connect the bypass capacitors to a ground
plane the vias should be configured for minimal parasitic inductance. One method of reducing via inductance is
to use multiple vias. For broadband systems, two capacitors per supply pin are advised.
To avoid undesirable signal transients, the THS2630 device should not be powered on with large inputs signals
present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs
when an ADC is used in the application.
8.4 Layout
8.4.1 Layout Guidelines
To achieve the levels of high-frequency performance of the THS2630 device, follow proper printed-circuit board
(PCB) high-frequency design techniques. A general set of guidelines is given below. In addition, a THS2630
device evaluation board is available to use as a guide for layout or for evaluating the device performance.
• Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
• Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this
distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer
should strive for distances of less than 0.1 inches between the device power terminals and the ceramic
capacitors.
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• Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inputs of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
8.4.2 Layout Example
RG–
RF+
VIN
RT–
VCC+
CBYP
RO+
–
+
+
–
FDA
VOCM
CL
RO–
PD
VCC+
CBYP
VCC-
RG+
RF–
RS+
RT+
图8-7. Representative Schematic for Layout
RS+
VIN
RT+
RT–
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
1
2
3
4
8
7
6
5
IN–
IN+
Place the feedback resistors, RF±, gain
resistors, RG±, and the isolation
resistors, RO±, as close to the device
pins as possible to minimize parasitics
VOCM
VCC+
PD
VCC–
OUT+
OUT–
Vias to connect supply pins to
CBYP. Place CBYP capacitors on
the other side of the PCB as
close to the vias as possible.
Ground and power plane exist on
inner layers.
CL
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
图8-8. Layout Recommendations
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8.4.3 General PowerPAD Design Considerations
The THS2630 is available in a thermally-enhanced DGN package, which is a member of the PowerPAD family of
packages. This package is constructed using a downset leadframe upon which the die is mounted (see 图 8-9 a
and 图 8-9 b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of
the package (see 图 8-9 c). Because this thermal pad has direct thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the previously awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in PowerPAD Thermally-Enhanced Package technical brief. This document can be found on the TI website
(www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI
sales office. Refer to SLMA002 when ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A. The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from VCC– to VCC+
.
Typically, the thermal pad is connected to the ground plane because this plane tends to physically be the largest and is able to dissipate
the most amount of heat.
图8-9. Views of Thermally-Enhanced DGN Package
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Design Guide for 2.3 nV/√Hz, Differential, Time Gain Control (TGC) DAC Reference
Design for Ultrasound design guide
• Texas Instruments, EVM User's Guide for High-Speed Fully-Differential Amplifier user's guide
• Texas Instruments, Fully Differential Amplifiers application note
• Texas Instruments, Maximizing Signal Chain Distortion Performance Using High Speed Amplifiers application
note
• Texas Instruments, PowerPAD Thermally-Enhanced Package technical brief
• Texas Instruments, TI Precision Labs - Fully Differential Amplifiers video series
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10.1 Mechanical Data
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
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THS2630
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
26
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Product Folder Links: THS2630
THS2630
ZHCSQB3 –JANUARY 2023
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10.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PTHS2630SDR
SOIC
D
8
8
2500
2500
330
330
12.4
12.4
6.40
6.40
5.20
5.20
2.10
2.10
8
8
12
12
Q1
Q1
PTHS2630SDGKR
VSSOP
DGK
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
2500
2500
Length (mm) Width (mm)
Height (mm)
PTHS2630SDR
PTHS2630SDGKR
SOIC
D
8
8
367
366
367
364
35
50
VSSOP
DGK
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTHS2630SDGKR
PTHS2630SDR
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
2500
2500
TBD
TBD
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2023
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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