THS3092DDAG3 [TI]
双路高电压、低失真电流反馈运算放大器 | DDA | 8 | -40 to 85;
| 型号： | THS3092DDAG3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路高电压、低失真电流反馈运算放大器 | DDA | 8 | -40 to 85 放大器 光电二极管 运算放大器 放大器电路 |
| 文件： | 总34页 (文件大小：1582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK
OPERATIONAL AMPLIFIERS
FEATURES
DESCRIPTION
•
Low Distortion
The THS3092 and THS3096 are dual high-voltage,
low-distortion, high speed, current-feedback
amplifiers designed to operate over a wide supply
range of ±5 V to ±15 V for applications requiring
large, linear output signals such as Pin, Power FET,
and VDSL line drivers.
– 66 dBc HD2 at 10 MHz, RL = 100 Ω
– 76 dBc HD3 at 10 MHz, RL = 100 Ω
Low Noise
•
– 13 pA/√Hz Noninverting Current Noise
– 13 pA/√Hz Inverting Current Noise
– 2 nV/√Hz Voltage Noise
The THS3096 features a power-down pin (PD) that
puts the amplifier in low power standby mode, and
lowers the quiescent current from 9.5 mA to 500 µA.
•
•
•
•
•
High Slew Rate: 5700 V/µs (G = 5, VO = 20 VPP
Wide Bandwidth: 160 MHz (G = 5, RL = 100 Ω)
High Output Current Drive: ±250 mA
Wide Supply Range: ±5 V to ±15 V
Power-Down Feature: (THS3096 Only)
)
The wide supply range combined with total harmonic
distortion as low as -66 dBc at 10 MHz, in addition, to
the high slew rate of 5700 V/µs makes the
THS3092/6 ideally suited for high-voltage arbitrary
waveform driver applications. Moreover, having the
ability to handle large voltage swings driving into
high-resistance and high-capacitance loads while
maintaining good settling time performance makes
the THS3092/6 ideal for Pin driver and PowerFET
driver applications.
APPLICATIONS
•
•
•
•
High-Voltage Arbitrary Waveform
Power FET Driver
Pin Driver
VDSL Line Driver
The THS3092 is offered in an 8-pin SOIC (D), and
the 8-pin SOIC (DDA) packages with PowerPAD™.
The THS3096 is offered in the 8-pin SOIC (D) and
the 14-pin TSSOP (PWP) packages with PowerPAD.
TYPICAL ARBITARY WAVEFORM
GENERATOR OUTPUT DRIVE CIRCUIT
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−20
G = 5,
V
= 20 V
PP
O
R
R
V
= 715 Ω,
= 100 Ω,
= ±15 V
F
L
−30
−40
V
OUT
S
−
+
IOUT1
DAC5686
IOUT2
−
+
THS3092
−50
−60
−70
V
= 10 V
PP
O
THS4271
V
= 5 V
PP
O
−
+
−80
−90
V
= 2 V
10 M
THS3092
O
PP
100 k
1 M
100 M
f − Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRO-
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TOP VIEW
D, DDA
TOP VIEW
D, PWP
THS3096
THS3092
1V
V
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT
S+
1V
V
1
2
3
4
8
1V
1V
2V
2V
2V
OUT
S+
IN−
OUT
1V
1V
7
6
5
2V
2V
2V
IN−
OUT
IN−
IN+
IN−
IN+
V
S−
IN+
V
S−
NC
REF
NC
IN+
NC
PD
NC
8
NC = No Internal Connection
NC = No Internal Connection
See Note A.
Note A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin
functional range is from V to (V − 4 V).
S−
S+
ORDERING INFORMATION
PART NUMBER
THS3092D
PACKAGE TYPE
TRANSPORT MEDIA, QUANTITY
Rails, 75
SOIC-8
THS3092DR
THS3092DDA
THS3092DDAR
Power-down
Tape and Reel, 2500
Rails, 75
SOIC-8-PP(1)
Tape and Reel, 2500
THS3096D
Rails, 75
SOIC-8
THS3096DR
THS3096PWP
THS3096PWPR
Tape and Reel, 2500
Rails, 90
TSSOP-14-PP(1)
Tape and Reel, 2000
(1) The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATING TABLE
POWER RATING(2)
PACKAGE
ΘJC (°C/W)
ΘJA (°C/W)(1)
TA≤ 25°C
1.02 W
2.18 W
2.67 W
TA = 85°C
410 mW
873 mW
1.07 W
D-8
38.3
9.2
97.5
45.8
37.5
DDA-8(3)
PWP-14(3)
2.07
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
(3) The THS3092 and THS3096 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
2
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
RECOMMENDED OPERATING CONDITIONS
MIN
±5
MAX
±15
30
UNIT
V
Dual supply
Supply voltage
Single supply
10
Operating free-air temperature, TA
-40
85
°C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)(1)
UNIT
33 V
Supply voltage, VS- to VS+
Input voltage, VI
± VS
Differential input voltage, VID
± 4 V
350 mA
Output current, IO
Continuous power dissipation
See Dissipation Ratings Table
Maximum junction temperature, TJ
150°C
125°C
(2)
Maximum junction temperature, continuous operation, long term reliability, TJ
Storage temperature, Tstg
-65°C to 150°C
300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings:
HBM
2000
1500
150
CDM
MM
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
3
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
AC PERFORMANCE
G = 1, RF = 1.1 kΩ, VO = 200 mVPP
G = 2, RF = 909 Ω, VO = 200 mVPP
G = 5, RF = 715 Ω, VO = 200 mVPP
G = 10, RF = 604 Ω, VO = 200 mVPP
G = 2, RF = 909 Ω, VO = 200 mVPP
G = 5, RF = 715 Ω , VO = 5 VPP
G = 2, VO = 10-V step, RF = 909 Ω
G = 5, VO = 20-V step, RF = 715 Ω
G = 2, VO = 5-VPP, RF = 909 Ω
G = -2, VO = 2 VPP step
135
145
160
145
50
Small-signal bandwidth, -3 dB
MHz
TYP
0.1 dB bandwidth flatness
Large-signal bandwidth
150
4000
5700
5
Slew rate (25% to 75% level)
V/µs
ns
TYP
TYP
TYP
Rise and fall time
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
42
ns
G = -2, VO = 2 VPP step
72
RL = 100Ω
RL = 1 kΩ
RL = 100Ω
RL = 1 kΩ
66
66
2nd Harmonic distortion
3rd Harmonic distortion
G = 2,
RF = 909 Ω ,
VO = 2 VPP
f = 10 MHz
dBc
TYP
,
76
78
Input voltage noise
f > 10 kHz
f > 10 kHz
f > 10 kHz
2
nV / √Hz
pA / √Hz
pA / √Hz
TYP
TYP
TYP
Noninverting input current noise
Inverting input current noise
13
13
NTSC
PAL
0.013%
0.011%
0.020°
0.026°
60
Differential gain
G = 2,
RL = 150 Ω,
RF = 909 Ω
TYP
dB
NTSC
PAL
Differential phase
G = 2,
RL = 100 Ω,
f = 10 MHz
Ch 1 to 2
Crosstalk
Ch 2 to 1
56
DC PERFORMANCE
Transimpedance
VO = ±7.5 V, Gain = 1
850
0.9
350
3
300
4
300
4
kΩ
mV
MIN
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
Input offset voltage
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
±10
20
±10
20
µV/°C
µA
4
15
15
10
±20
20
±20
20
µA/°C
µA
VCM = 0 V
3.5
1.7
±20
15
±20
15
µA/°C
µA
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Noninverting input resistance
Noninverting input capacitance
Inverting input resistance
Inverting input capacitance
±20
±20
µA/°C
±13.6
78
±13.3
±13
±13
V
dB
MΩ
pF
Ω
MIN
MIN
TYP
TYP
TYP
TYP
VCM = ±10 V
68
65
65
1.3
0.1
30
1.4
pF
4
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
VS = ±15 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
OUTPUT CHARACTERISTICS
RL = 1 kΩ
RL = 100 Ω
RL = 40 Ω
RL = 40 Ω
±13.2
±12.5
280
±12.8
±12.1
225
±12.5
±11.8
200
±12.5
±11.8
200
Output voltage swing
V
MIN
Output current (sourcing)
Output current (sinking)
Output impedance
mA
mA
Ω
MIN
MIN
TYP
250
200
175
175
f = 1 MHz, Closed loop
0.06
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
±15
9.5
9.5
75
±16
10.5
8.5
70
±16
11
8
±16
11
8
V
MAX
MAX
MIN
MIN
MIN
mA
mA
dB
dB
Per channel
VS+ = 15.5 V to 14.5 V, VS- = 15 V
VS+ = 15 V, VS- = -15.5 V to -14.5 V
65
65
65
65
73
68
POWER-DOWN CHARACTERISTICS (THS3096 ONLY)
Enable, REF = 0 V
Power-down voltage level
≤ 0.8
≥ 2
500
11
V
MAX
MAX
MAX
Power-down , REF = 0 V
Power-down quiescent current
VPD quiescent current
PD = 0V
700
15
800
20
800
20
µA
µA
VPD = 0 V, REF = 0 V,
VPD = 3.3 V, REF = 0 V
90% of final value
10% of final value
11
15
20
20
Turnon time delay
Turnoff time delay
60
µs
TYP
150
5
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C to
85°C
MIN/TYP/
MAX
25°C
25°C
UNIT
AC PERFORMANCE
G = 1, RF = 1.1 kΩ, VO = 200 mVPP
G = 2, RF = 909 Ω, VO = 200 mVPP
G = 5, RF = 715 Ω, VO = 200 mVPP
G = 10, RF = 604 Ω, VO = 200 mVPP
G = 2, RF = 909 Ω, VO = 200 mVPP
G = 2, RF = 909 Ω , VO = 5 VPP
G = 2, VO= 5-V step, RF = 909 Ω
G = 5, VO= 5-V step, RF = 715 Ω
G = 2, VO = 5-V step, RF = 909 Ω
G = -2, VO = 2 VPP step
125
140
145
135
42
Small-signal bandwidth, -3 dB
MHz
TYP
0.1 dB bandwidth flatness
Large-signal bandwidth
125
1050
1350
5
Slew rate (25% to 75% level)
V/µs
ns
TYP
TYP
TYP
Rise and fall time
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
35
ns
G = -2, VO = 2 VPP step
73
RL = 100Ω
64
67
2nd Harmonic distortion
3rd Harmonic distortion
G = 2,
RF = 909 Ω ,
VO = 2 VPP
f = 10 MHz
RL = 1 kΩ
RL = 100Ω
RL = 1 kΩ
dBc
TYP
,
75
75
Input voltage noise
f > 10 kHz
f > 10 kHz
f > 10 kHz
2
nV / √Hz
pA / √Hz
pA / √Hz
TYP
TYP
TYP
Noninverting input current noise
Inverting input current noise
13
13
NTSC
PAL
0.027%
0.025%
0.04°
0.05°
60
Differential gain
G = 2,
RL = 150 Ω,
RF = 909 Ω
TYP
dB
NTSC
PAL
Differential phase
G = 2,
RL = 100 Ω,
f = 10 kHz
Ch 1 to 2
Crosstalk
Ch 2 to 1
56
DC PERFORMANCE
Transimpedance
VO = ±2.5 V, Gain = 1
700
0.3
250
2
200
3
200
3
kΩ
mV
MIN
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
Input offset voltage
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
±10
20
±10
20
µV/°C
µA
2
5
1
15
15
10
±20
20
±20
20
µA/°C
µA
VCM = 0 V
±20
15
±20
15
µA/°C
µA
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Noninverting input resistance
Noninverting input capacitance
Inverting input resistance
Inverting input capacitance
±20
±20
µA/°C
±3.6
66
±3.3
±3
±3
V
dB
MΩ
pF
Ω
MIN
MIN
TYP
TYP
TYP
TYP
VCM = ±2.0 V, VO = 0 V
60
57
57
1.1
1.2
32
1.5
pF
6
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
VS = ±5 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
OUTPUT CHARACTERISTICS
RL = 1 kΩ
RL = 100 Ω
RL = 10 Ω
RL = 10 Ω
±3.4
±3.1
200
180
0.09
±3.1
±2.7
160
150
±2.8
±2.5
140
125
±2.8
±2.5
140
125
Output voltage swing
V
MIN
Output current (sourcing)
Output current (sinking)
Output impedance
mA
mA
Ω
MIN
MIN
TYP
f = 1 MHz, Closed loop
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
±5
8.2
8.2
73
±4.5
9
±4.5
9.5
6.5
63
±4.5
9.5
6.5
63
V
MAX
MAX
MIN
MIN
MIN
mA
mA
dB
dB
Per channel
7
VS+ = 5.5 V to 4.5 V, VS- = -5 V
VS+ = 5 V, VS- = -4.5 V to 5.5 V
68
65
71
60
60
POWER-DOWN CHARACTERISTICS (THS3096 ONLY)
Enable, REF = 0 V
Power-down voltage level
≤ 0.8
≥ 2
300
11
V
MAX
MAX
MAX
Power-down , REF = 0 V
Power-down quiescent current
VPD quiescent current
PD = 0V
500
15
600
20
600
20
µA
µA
VPD = 0 V, REF = 0 V,
VPD = 3.3 V, REF = 0 V
90% of final value
10% of final value
11
15
20
20
Turnon time delay
Turnoff time delay
60
µs
TYP
150
7
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
±15-V graphs
Noninverting frequency response
Inverting frequency response
0.1 dB flatness
1, 2
3
4
Noninverting frequency response
Inverting frequency response
Frequency response capacitive load
Recommended RISO
5
6
7
vs Capacitive load
vs Frequency
8
2nd Harmonic distortion
3rd Harmonic distortion
Slew rate
9, 11
10, 12
13, 14, 15
16
vs Frequency
vs Output voltage step
vs Frequency
Noise
Settling time
17, 18
19
Quiescent current
vs Supply voltage
vs Load resistance
vs Case temperature
vs Case temperature
vs Frequency
Output voltage
20
Input bias and offset current
Input offset voltage
21
22
Transimpedance
23
Rejection ratio
vs Frequency
24
Noninverting small signal transient response
Inverting large signal transient response
Overdrive recovery time
Differential gain
25
26, 27
28
vs Number of loads
vs Number of loads
vs Frequency
29
Differential phase
30
Closed loop output impedance
Crosstalk
31
vs Frequency
32
Power-down quiescent current
Turnon and turnoff time delay
vs Supply voltage
33
34
8
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (continued)
TABLE OF GRAPHS
FIGURE
±5-V graphs
Noninverting frequency response
Inverting frequency response
0.1 dB flatness
35
36
37
Noninverting frequency response
Inverting frequency response
Settling time
38
39
40
2nd Harmonic distortion
3rd Harmonic distortion
Slew rate
vs Frequency
41
vs Frequency
42
vs Output voltage step
43, 44, 45
46
Noninverting small signal transient response
Output voltage load resistance
Input bias and offset current
Overdrive recovery time
Rejection ratio
47
vs Case temperature
48
49
vs Frequency
vs Frequency
50
Crosstalk
51
9
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (±15 V)
NONINVERTING
FREQUENCY RESPONSE
NONINVERTING
FREQUENCY RESPONSE
INVERTING
FREQUENCY RESPONSE
24
22
20
18
16
14
12
10
8
9
8
7
6
5
4
3
2
1
0
24
22
20
18
16
14
R
O
= 100 Ω,
L
R
O
= 100 Ω,
R
= 499 Ω
L
F
V
= 200 mV , V = ±15 V
PP
S
V
= 200 mV , V = ±15 V
S
PP
R
= 909 Ω
F
G = 10, R = 604 Ω
F
G = −10, R = 604 Ω
F
G = 5, R = 715 Ω
G = −5, R = 715 Ω
F
F
12
10
R
= 1.2 k Ω
F
8
6
4
2
G =2, R = 909 Ω
F
6
4
G = −2, R = 806 Ω
F
Gain = 2,
2
G =1, R = 1.1 kΩ
F
R
= 100 Ω,
= 200 mV
= ±15 V
L
0
−2
−4
0
−2
V
V
,
PP
O
S
G = −1, R = 909 Ω
F
−4
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
10 M
100 M
1 G
1 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
NONINVERTING
FREQUENCY RESPONSE
INVERTING
FREQUENCY RESPONSE
0.1 dB FLATNESS
16
6.3
6.2
6.1
16
Gain = 2,
V
= 2V
O PP
14
12
10
8
V
= 1 V
PP
O
R
F
R
L
= 909 Ω,
= 200 Ω,
= 200 mV
= ±15 V
14
12
V
V
,
PP
O
S
V
= 20V
PP
O
10
V
= 10V
PP
O
V
= 20 V
PP
O
6
8
6
V
= 5V
PP
O
6
V
= 10 V
PP
V
= 1V
PP
O
O
5.9
Gain = 5,
4
Gain = −5,
4
2
0
R
F
R
L
= 715 Ω,
= 100 Ω,
= ±15 V
R
R
V
= 715 Ω,
= 100 Ω,
= ±15 V
F
L
5.8
5.7
V
V
= 5 V
= 2 V
O
O
PP
2
V
S
S
PP
100 M
0
1 M
10 M
100 M
1 G
1 M
10 M
1 G
100 k
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
RECOMMENDED RISO
vs
CAPTIVATE LOAD
2ND HARMONIC DISTORTION
FREQUENCY RESPONSE
CAPACITIVE LOAD
vs
FREQUENCY
45
16
14
−40
−50
−60
−70
−80
−90
G = 1
= 1.1 kΩ,
= 100 Ω
V
V
= ±15 V,
= 2 V
PP
S
Gain = 5,
= ±15 V
R
C
= 39.2 Ω
(ISO)
= 10 pF
R
F
40
35
30
25
20
15
10
5
O
L
V
R
S
L
12
10
8
R
= 30.9 Ω
L
(ISO)
C
= 22 pF
R
= 20 Ω
(ISO)
L
C
= 47 pF
G = 1
6
R
= 1.1 kΩ,
L
F
G = 2
R
= 15 Ω
(ISO)
R
= 1 kΩ
R
L
= 909 Ω,
= 1 kΩ
F
C
L
= 100 pF
4
715 Ω
R
178 Ω
R
ISO
2
−
+
Gain = 5
R
V
G = 2
C
L
= 100 Ω
=±15 V
R
L
= 909 Ω,
= 100 Ω
L
F
0
R
S
0
−2
100 k
1 M
10 M
100 M
10 M
100 M
1 G
10
100
f − Frequency − Hz
C
L
− Capacitive Load − pF
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
10
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (±15 V) (continued)
3RD HARMONIC DISTORTION
vs
2ND HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
FREQUENCY
−40
−50
−60
−70
−30
−40
−50
−60
−70
−80
−90
−30
−40
V
= 20 V
PP
O
V
V
= ±15 V,
V
= 20 V
PP
S
O
G = 1
= 2 V
R
= 1.1 kΩ,
L
O
PP
F
V
= 10 V
PP
O
R
= 1 kΩ
V
= 10 V
PP
O
−50
−60
G = 5
= 715 Ω,
= 100 Ω,
= ±15 V
G = 1
= 1.1 kΩ,
= 100 Ω
G = 5
= 715 Ω,
= 100 Ω,
= ±15 V
R
F
L
s
R
R
F
F
L
s
R
R
R
L
V
V
−70
G = 2
V
= 5 V
PP
O
R
= 909 Ω,
= 100 Ω
F
L
−80
R
V
= 5 V
PP
O
−80
−90
−90
G = 2
V
= 2 V
10 M
O
PP
R
L
= 909 Ω,
V
= 2 V
PP
F
O
R
= 1 kΩ
−100
−100
100 k
1 M
10 M
100 M
100 k
100 k
1 M
10 M
100 M
100 M
1 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 10.
Figure 11.
Figure 12.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
4000
3500
3000
2500
2000
1500
1000
500
800
700
600
500
400
300
200
100
0
6000
5000
4000
3000
2000
1000
0
Rise
Gain = 5
Gain = 2
R
R
V
= 100 Ω
= 715 Ω
= ±15 V
R
R
V
= 100 Ω
= 909 Ω
= ±15 V
L
F
Rise
L
F
S
Fall
S
Rise
Gain = 1
R
R
Fall
Fall
7
= 100 Ω
= 1.1 kΩ
= ±15 V
L
F
S
V
0
0
1
2
3
4
5
6
8
9
10
0
2
4
6
8
10 12 14 16 18 20
0
0.5
1
1.5
2
2.5
3
3.5
4
V
− Output Voltage −V
V
− Output Voltage −V
PP
O
PP
V
− Output Voltage − V
O
O
PP
Figure 13.
Figure 14.
Figure 15.
NOISE
vs
FREQUENCY
SETTLING TIME
SETTLING TIME
1000
100
10
1.25
1
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
Rising Edge
Rising Edge
0.75
0.5
0.25
0
Gain = −2
Gain = −2
I
n−
R
R
V
= 100 Ω
= 806 Ω
= ±15 V
L
F
S
R
R
V
= 100 Ω
=806 Ω
= ±15 V
L
F
−0.25
−0.5
S
I
n+
−2.5
−3
−3.5
−4
−0.75
V
n
Falling Edge
Falling Edge
−1
1
−1.25
−4.5
10
100
1 k
10 k
100 k
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
f − Frequency − Hz
t − Time − ns
t − Time − ns
Figure 16.
Figure 17.
Figure 18.
11
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (±15 V) (continued)
INPUT BIAS AND
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
OFFSET CURRENT
vs
vs
LOAD RESISTANCE
CASE TEMPERATURE
7
16
12
8
11
V
= ±15 V
I
-
S
6.5
6
IB
T
= 85 °C
10.5
A
5.5
5
10
T
A
= 25 °C
4.5
4
9.5
4
I
+
IB
V
= ±15 V
S
9
8.5
8
3.5
3
0
T
= -40 to 85°C
A
T
= −40 °C
A
-4
2.5
2
-8
1.5
1
7.5
7
I
-12
-16
OS
Per Channel
9 10 11 12 13 14 15
0.5
0
3
4
5
6
7
8
10
100
1000
-40-30-20 -10
0 10 20 30 40 50 60 70 80 90
R
L
- Load Resistance - Ω
V
− Supply Voltage − ±V
S
T
C
- Case Temperature - °C
Figure 19.
Figure 20.
Figure 21.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
TRANSIMPEDANCE
vs
REJECTION RATIO
vs
FREQUENCY
FREQUENCY
3
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
V
= ±15 V
S
V
= ±15 V and ±5 V
S
2.5
PSRR−
2
CMRR
V
= ±15 V
S
1.5
1
PSRR+
V
= ±5 V
S
0.5
10
0
10
0
0
100 k
1 M
10 M
100 M
1 G
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
T
C
- Case Temperature - °C
Figure 22.
Figure 23.
Figure 24.
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
6
5
4
3
2
1
12
0.3
0.25
0.2
Gain = −5,
10
Output
R
R
V
= 100 Ω,
= 715 Ω,
= ±15 V
L
F
S
Output
8
6
4
2
0.15
0.1
Input
0.05
Input
Input
0
0
0
−0.05
−0.1
−2
−1
−4
−6
−2
−3
−4
−5
−6
Gain = 2,
Gain = 2,
−0.15
−0.2
R
R
V
= 100 Ω,
= 715 Ω,
= ±15 V
L
F
R
R
V
= 100 Ω,
= 909 Ω,
= ±15 V
L
F
S
Output
−8
−10
−12
S
−0.25
−0.3
−5
0
5
10 15 20 25 30 35 40 45 50 55 60
−10
0
10 20 30 40 50 60 70
−10
0
10 20 30 40 50 60 70
t − Time − ns
t − Time − ns
t − Time − ns
Figure 25.
Figure 26.
Figure 27.
12
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (±15 V) (continued)
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
vs
OVERDRIVE RECOVERY TIME
NUMBER OF LOADS
20
15
10
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.05
4
Gain = 2
G = 5,
Gain = 2
R
V
= 909 Ω
= ±15 V
F
S
3
2
1
R
R
V
= 100 Ω,
= 715 Ω,
= ±15 V
L
F
S
R
V
= 909 Ω
= ±15 V
F
S
0.04
0.03
0.02
0.01
0
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
°
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
5
PAL
0
0
PAL
−5
−1
−10
−15
−20
−2
−3
−4
NTSC
NTSC
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
t − Time − µs
Number of Loads − 150 Ω
Number of Loads − 150 Ω
Figure 28.
Figure 29.
Figure 30.
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
POWER-DOWN QUIESCENT
CURRENT
CROSSTALK
vs
FREQUENCY
vs
FREQUENCY
SUPPLY VOLTAGE
600
500
400
300
200
0
−10
−20
−30
−40
−50
−60
−70
100
10
1
V
R
= ±15 V,
= 100 Ω
S
Gain = 2,
L
R
R
= 5.11 Ω,
= 909 Ω,
= ±15 V
ISO
F
S
T
= 85°C
= 25°C
G= 5, CH1 to 2
A
V
G= 5, CH2 to 1
T
A
= -40°C
T
A
G= 2, CH2 to 1
909 Ω
909 Ω
0.1
V
−80
−90
O
5.11 Ω
−
+
100
0
G= 2, CH1 to 2
0.01
−100
3
4
5
6
7
8
9
10 11 12 13 14 15
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
V
- Supply Voltage - ±V
S
f − Frequency − Hz
Figure 31.
Figure 32.
Figure 33.
TURNON AND TURNOFF
TIME DELAY
6
5
Powerdown Pulse
4
3
2
1
0
Gain = 2,
V
= 0.1 Vdc
I
R
L
= 100 Ω
V
= ±15 V and ±5 V
S
0.3
0.2
0.1
0
Output Voltage
−0.1
0
1
2
3
4
5
6
7
t − Time − ms
Figure 34.
13
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (±5 V)
NONINVERTING
FREQUENCY RESPONSE
INVERTING
FREQUENCY RESPONSE
0.1 dB FLATNESS
24
22
20
18
16
14
12
10
8
6.3
6.2
6.1
24
22
20
18
16
14
12
10
8
Gain = 2,
G = −10, R = 604 Ω
G = 10, R = 604 Ω
F
F
R
F
R
L
= 909 Ω,
= 100 Ω,
= 200 mV
= ±5 V
V
V
,
PP
O
S
G = 5, R = 715 Ω
G = −5, R = 715 Ω
F
F
R
O
S
= 100 Ω,
= 200 mV
= ±5 V
L
R
V
= 100 Ω,
= 200 mV
= ±5 V
L
O
S
V
V
,
PP
,
PP
6
5.9
5.8
5.7
V
6
6
G = 2, R = 909 Ω
G = −2, R = 806 Ω
F
F
4
4
2
2
0
−2
0
−2
G = −1, R = 906 Ω
F
G = 1, R = 1.1 kΩ
F
−4
−4
1
10
100
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − MHz
f − Frequency − Hz
Figure 35.
Figure 36.
Figure 37.
NONINVERTING
FREQUENCY RESPONSE
INVERTING
FREQUENCY RESPONSE
SETTLING TIME
16
14
12
10
8
16
14
12
10
8
1.25
1
V
= 2 V
PP
O
V
= 1 V
PP
O
Rising Edge
0.75
0.5
V
= 1 V
PP
O
0.25
0
Gain = −2
R
R
V
= 100 Ω
= 806 Ω
= ±5 V
L
F
V
= 5 V
PP
O
−0.25
−0.5
−0.75
−1
S
6
6
V
= 2 V
PP
O
4
4
G = 5,
G = 5,
R
R
V
= 715 Ω,
= 100 Ω,
= ±5V
F
L
S
Falling Edge
R
R
= 715 Ω,
= 100 Ω,
= ±5V
F
L
S
V
= 5 V
PP
2
2
O
V
0
0
−1.25
100 M
1 M
10 M
1 G
0
1
2
3
4
5
6
7
8
9
10
10 M
100 M
1 G
1 M
f − Frequency − Hz
f − Frequency − Hz
t − Time − ns
Figure 38.
Figure 39.
Figure 40.
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
SLEW RATE
vs
OUTPUT VOLTAGE STEP
vs
vs
FREQUENCY
FREQUENCY
−40
−50
−60
−70
−80
−90
−40
−50
−60
−70
−80
−90
900
800
700
600
500
400
300
200
100
0
V
V
= ±5 V,
S
O
G = 2, R = 909Ω,
F
G = 2, R = 909 Ω,
Gain =1
F
= 2 V
PP
R = 100 Ω
L
R
R
V
= 100 Ω
= 1.1 kΩ
= ±5 V
L
F
S
R
L
= 100 Ω
Rise
G = 1, R = 1.1 kΩ,
F
R
= 100 Ω
L
G =1, R = 1.1 kΩ,
F
R
G = 2, R = 909Ω,
F
R
Fall
= 100 Ω
= 1 kΩ
L
L
G = 1, R = 1.1 kΩ,
F
R
= 1 kΩ
L
G =1, R = 1.1 kΩ,
F
R
L
= 1 kΩ
V
V
= 2 V ,
PP
= ±5 V
O
S
G = 2, R = 909 Ω,
F
R
L
= 1 kΩ
100 k
1 M
10 M
100 k
1 M
10 M
100 M
100 M
0
0.5
1
1.5
2
2.5
3
3.5
4
f − Frequency − Hz
f − Frequency − Hz
V
− Output Voltage −V
O
PP
Figure 41.
Figure 42.
Figure 43.
14
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS (±5 V) (continued)
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
OUTPUT VOLTAGE STEP
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1400
1200
1000
800
600
400
200
0
0.3
Gain = 2
Gain = 5
0.25
R
R
= 100 Ω
= 909Ω
= ±5 V
R
R
V
= 100 Ω
= 715 Ω
= ±5 V
Output
L
F
S
Rise
L
F
S
0.2
0.15
0.1
Rise
V
Fall
Fall
Input
0.05
0
−0.05
−0.1
Gain = 2
−0.15
R
R
V
= 100 Ω
= 909 Ω
= ±5 V
L
F
S
−0.2
−0.25
−0.3
0
1
2
3
4
5
0
1
2
3
4
5
−10
0
10 20 30 40 50 60 70
V
− Output Voltage −V
O
PP
V
− Output Voltage −V
t − Time − ns
O
PP
Figure 44.
Figure 45.
Figure 46.
INPUT BIAS AND
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
OFFSET CURRENT
vs
CASE TEMPERATURE
OVERDRIVE RECOVERY TIME
8
5
4
3
2
1
0
3.5
1
V
= ±5 V
Gain = 5,
S
3
2.5
0.8
7
6
5
4
3
2
R
R
V
= 100 Ω,
= 715 Ω,
= ±5 V
L
F
S
0.6
0.4
0.2
2
1.5
1
I
IB-
I
OS
0.5
V
T
A
= ±5 V
= -40 to 85°C
S
0
0
-0.5
−0.2
−1
-1
-1.5
−0.4
−0.6
−2
−3
−4
−5
I
IB+
-2
−0.8
−1
-2.5
-3
1
0
0
0.2
0.4
0.6
0.8
1
-3.5
-40 -30 -20-10
0
10 20 30 40 50 60 70 80 90
10
100
1000
t − Time − µs
T - Case Temperature - °C
C
R
L
- Load Resistance - Ω
Figure 47.
Figure 48.
Figure 49.
REJECTION RATIO
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
70
60
50
40
30
20
10
0
V
R
= ±5 V,
= 100 Ω
S
V
= ±5 V
S
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
L
PSRR-
G= 5, CH1 to 2
G= 5, CH2 to 1
CMRR
G= 2, CH2 to 1
PSRR+
G= 2, CH1 to 2
0
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
f − Frequency − Hz
f - Frequency - Hz
Figure 50.
Figure 51.
15
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
APPLICATION INFORMATION
WIDEBAND, NONINVERTING OPERATION
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain setting
resistors RF and RG at different gains to give
maximum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
The THS3092/6 are unity gain stable 135-MHz
current-feedback operational amplifiers, designed to
operate from a ±5-V to ±15-V power supply.
Figure 52 shows the THS3092 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
15 V
+V
S
THS3092 and THS3096 RF and RG values for minimal peaking
+
with RL = 100 Ω
0.1 µF
49.9 Ω
6.8 µF
50 Ω Source
49.9 Ω
SUPPLY VOLTAGE
GAIN (V/V)
RG (Ω)
RF (Ω)
(V)
+
_
V
I
±15
--
1.1 k
1.1 k
909
909
715
715
604
604
909
806
715
604
1
±5
--
50 Ω LOAD
R
F
±15
909
909
178
178
66.5
66.5
909
402
143
60.4
2
5
909 Ω
±5
909 Ω
R
G
0.1 µF
6.8 µF
±15
+
±5
±15
−V
S
10
±5
−15 V
-1
-2
±15 and ±5
±15 and ±5
±15 and ±5
±15 and ±5
Figure 52. Wideband, Noninverting Gain
Configuration
-5
-10
16
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
WIDEBAND, INVERTING OPERATION
Figure 53 shows the THS3092 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 52 are
retained in an inverting circuit configuration.
+V
S
50 Ω Source
+
49.9 Ω
50 Ω LOAD
V
I
49.9 Ω
15 V
+V
S
R
T
_
+
+V
2
S
R
F
0.1 µF
49.9 Ω
6.8 µF
909 Ω
R
G
+
909 Ω
_
+V
2
S
50 Ω LOAD
R
F
50 Ω Source
R
G
R
F
806 Ω
V
V
I
402 Ω
806 Ω
S
50 Ω Source
R
M
R
G
0.1 µF
6.8 µF
_
57.6 Ω
49.9 Ω
50 Ω LOAD
V
I
+
402 Ω
R
T
57.6 Ω
+
−V
S
−15 V
+V
2
+V
S
S
2
Figure 53. Wideband, Inverting Gain
Configuration
Figure 54. DC-Coupled, Single-Supply Operation
SINGLE SUPPLY OPERATION
VDSL Driver Circuit
The THS3092/6 have the capability to operate from a
The THS3092 and THS3096 have the ability to drive
over 200 mA of current with very high voltage swings.
Using these amplifiers coupled with the very high
slew rate, low distortion, and low noise required in
VDSL applications, makes for a perfect match. In
VDSL systems where the receive signal is critical, the
use of a low transformer ratio is necessary. With this
low ratio, the output swing required from the line
driver amplifier must increase, especially when driv-
ing the VDSL’s full 14.5-dBm power onto the line. The
line driver's low distortion and noise is critical for the
VDSL as the receive bands are intertwined with the
transmit frequency bands up to the 12-MHz VDSL
limit.
single
supply
voltage
ranging
from
10 V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits shown in Figure 54 shows inverting and
noninverting amplifiers configured for single supply
operations.
17
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
Figure 55 shows a traditional hybrid connection
approach for achieving the 14.5-dBm line power
utilizing a 1:1 transformer. Looking at the input to the
amplifiers shows a low-pass filter consisting of two
separate capacitors to ground. There is an argument
that since the signal coming out of the DAC is
fully-differential then a single capacitor (10 pF in this
case) is perfectly acceptable. The problem with this
idea is that many DACs have common-mode energy
due to images around the sampling frequency which
must be filtered before reaching the amplifier. An
amplifier simply amplifies its input–including the
DAC’s images at high frequencies–and pass it
through to the transformer and ultimately to the line,
possibly causing the system to fail EMC compliance.
A single capacitor does not remove these com-
mon-mode images, it only removes the differential
signal images. However, two separate filter capaci-
tors filter both the common-mode signals and the
differential-mode signals. Be sure to place the ground
connection point of the capacitors next to each other,
and then tie a single ground point at the middle of this
trace.
One of the concerns about any DSL line driver is the
power dissipation. One of the most common ways to
reduce power is by using active termination, aka
synthesized impedance. Refer to TI Application Note
SLOA100 for more information on active termination.
The drawback to active termination is the received
signal is reduced by the same synthesis factor
utilized in the system. Due to the very high attenu-
ation of the line at up to 12 MHz, the receive signal
can be severely diminished. Thus, the use of active
termination should be kept to modest levels at best.
Figure 56 shows an example of utilizing a simple
active termination scheme with a synthesis factor of 2
to achieve the same line power, but with a reduced
power supply voltage that ultimately saves power in
the system.
20 V
10 V
6.8 m F
24.9 W
0.01 m F
4.99 kW
THS3092
+
200 W
DAC
V
IN+
330 pF
22 pF
−
1:1
604 W
14.5 dBm
Line Power
1.21 kW
1.21 kW
191 W
0.01 m F
100 W
26 V
13 V
22 pF
604 W
0.01 mF 6.8 mF
4.99 kW
−
+
THS3092
200 W
DAC
DAC
49.9 W
+
−
24.9 W
*Hybrid Connection Not
Shown For Simplicity
V
IN+
V
IN−
THS3092
330 pF
22 pF
330 pF
200 W
4.99 kW
1:1
14.5 dBm
Line Power
604 W
10 V
133 W
100 W
Hybrid
To RX
604 W
0.015 mF
Figure 56.
22 pF
−
Video Distribution
DAC
+
49.9 W
V
IN−
THS3092
200 W
330 pF
4.99 kW
The wide bandwidth, high slew rate, and high output
drive current of the THS3092/6 matches the demands
for video distribution for delivering video signals down
multiple cables. To ensure high signal quality with
minimal degradation of performance, a 0.1-dB gain
flatness should be at least 7x the passband fre-
quency to minimize group delay variations from the
amplifier. A high slew rate minimizes distortion of the
video signal, and supports component video and
RGB video signals that require fast transition times
and fast settling times for high signal quality.
13 V
Figure 55.
Additionally, level shifting must be done to center the
common-mode voltage appearing at the amplifier’s
noninverting input to optimally the midpoint of the
power supply. As
a
side benefit of the
ac-coupling/level shifter, a simple high pass filter is
formed. This is generally a good idea for VDSL
systems where the transmit band is typically above 1
MHz, but can be as low as 25 kHz.
18
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
909 Ω
909 Ω
715 Ω
15 V
75-Ω Transmission Line
V
O(1)
V
S
75 Ω
−
+
178 Ω
Ferrite Bead
_
+
V
I
−15 V
75 Ω
n Lines
100 Ω LOAD
75 Ω
1 µF
−V
S
V
O(n)
75 Ω
49.9 Ω
V
S
75 Ω
Figure 60.
Figure 57. Video Distribution Amplifier
Application
Placing a small series resistor, RISO, between the
amplifier’s output and the capacitive load, as shown
in Figure 59, is an easy way of isolating the load
capacitance.
Driving Capacitive Loads
Applications such as FET line drivers can be highly
capacitive and cause stability problems for
high-speed amplifiers.
Using a ferrite chip in place of RISO, as shown in
Figure 60, is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the low fre-
quency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ω - 50 Ω, at 100 MHz and low impedance
at dc.
Figure 58 through Figure 63 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 58 for
recommended resistor values versus capacitive load.
45
Figure 61 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the capaci-
tance at high frequency. At low frequency, feedback
is mainly from the load side of RISO. At high fre-
quency, the feedback is mainly via the 27-pF capaci-
tor. The resistor RIN in series with the negative input
is used to stabilize the amplifier and should be equal
to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 62 gives similar
results with reduced dc offset and low frequency
noise. (See the ADDITIONAL REFERENCE MA-
TERIAL section for Expanding the usability of
current-feedback amplifiers.)
Gain = 5,
= ±15 V
40
V
S
35
30
25
20
15
10
5
715 Ω
178 Ω
R
ISO
−
+
C
L
0
10
100
C
L
− Capacitive Load − pF
Figure 58. Recommended RISO vs Capacitive Load
R
F
715 Ω
715 Ω
V
S
27 pF
178 Ω
100 Ω LOAD
_
+
5.11 Ω
R
IN
V
S
R
ISO
R
G
715 Ω
100 Ω LOAD
_
5.11 Ω
1 µF
−V
S
178 Ω
+
49.9 Ω
V
S
1 µF
−V
S
49.9 Ω
V
S
Figure 59.
Figure 61.
19
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
R
F
V
S
V
S
715 Ω
5.11 Ω
+
27 pF
_
F
IN
−V
V
S
S
FB
R
G
100 Ω LOAD
_
5.11 Ω
604 Ω
178 Ω
+
133 Ω
604 Ω
1 µF
−V
S
49.9 Ω
V
S
V
S
_
5.11 Ω
Figure 62.
+
−V
−V
S
S
Figure 63 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster like when driving large FET transistors.
Figure 64. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
715 Ω
V
S
178 Ω
The THS3096 features a power-down pin (PD) which
lowers the quiescent current from 9.5 mA down to
500 µA, ideal for reducing system power.
_
+
5.11 Ω
24.9 Ω
−V
S
The power-down pin of the amplifier defaults to the
negative supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and are given in the specification tables. Below
the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
715 Ω
V
S
V
S
1 nF
178 Ω
_
+
5.11 Ω
24.9 Ω
−V
S
Figure 63.
Figure 64 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 65 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 2420 Ω. Figure 52 shows this circuit
configuration for reference.
20
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
2500
V
= ±15 V and ±5 V
S
2000
Achieving optimum performance with high frequency
amplifier, like the THS3092/6, requires careful
attention to board layout parasitic and external
component types.
1500
1000
1.21 kΩ 1.21 kΩ
Recommendations that optimize performance include:
V
O
50 Ω
−
+
500
0
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
Figure 65. Power-down Output Impedance vs
Frequency
•
Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
Careful selection and placement of external
components preserve the high frequency per-
formance of the THS3092/6. Resistors should be
a very low reactance type. Surface-mount re-
sistors work best and allow a tighter overall
layout. Again, keep their leads and PC board
trace length as short as possible. Never use
wirebound type resistors in a high frequency
application. Since the output pin and inverting
input pins are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistors, if any, as close as poss-
ible to the inverting input pins and output pins.
Other network components, such as input termin-
ation resistors, should be placed close to the
gain-setting resistors. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create sig-
nificant time constants that can degrade perform-
ance. Good axial metal-film or surface-mount
resistors have approximately 0.2 pF in shunt with
the resistor. For resistor values > 2.0 kΩ, this
parasitic capacitance can add a pole and/or a
zero that can effect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V-) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage
equal
to
approximately
[(V+ - V-) -0.7 V]×Gain. This also implies that if a
voltage is applied to the output while in power-down
mode, the V- node voltage is equal to
V
O(applied)× RG/(RF + RG). For low gain configurations
and a large applied voltage at the output, the ampli-
fier may actually turn ON due to the aforementioned
behavior.
•
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3096 and
THS3096 feature a reference pin (REF) which allows
the user to control the enable or disable power-down
voltage levels applied to the PD pin. In most
split-supply applications, the reference pin is connec-
ted to ground. In either case, the user needs to be
aware of voltage-level thresholds that apply to the
power-down pin. The usable range at the REF pin is
from VS- to (VS+ - 4 V).
21
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS3092/6 are nominally com-
pensated to operate with a 2-pF parasitic load.
Higher parasitic capacitive loads without an RS
are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrin-
sic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is not necessary onboard, and
in fact, a higher impedance environment im-
proves distortion as shown in the distortion ver-
sus load plots. With a characteristic board trace
impedance based on board material and trace
dimensions, a matching series resistor into the
trace from the output of the THS3092/6 is used
as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective im-
pedance should be set to match the trace im-
pedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case. This does not preserve signal integrity
as well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation due to the voltage
divider formed by the series output into the
terminating impedance.
leadframe upon which the die is mounted [see
Figure 66(a) and Figure 66(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see Fig-
ure 66(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal per-
formance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS3092/6 have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing oper-
ation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 66. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.300
0.100
0.035
0.026
0.010
Pin 1
0.030
•
Socketing a high speed part like the THS3092/6
are not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost im-
possible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS3092/6 parts directly onto the board.
0.060
0.060
0.140
0.050
0.176
0.035
0.080
0.010
vias
PowerPAD™ DESIGN CONSIDERATIONS
Top View
The
THS3092/6
are
available
in
a
Figure 67. DDA PowerPAD PCB Etch and Via
Pattern
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
22
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
PowerPAD™ LAYOUT CONSIDERATIONS
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
1. PCB with a top side etch pattern as shown in
Figure 67. There should be etch for the leads as
well as etch for the thermal pad.
The THS3092/6 incorporates automatic thermal
shutoff protection. This protection circuitry shuts down
the amplifier if the junction temperature exceeds
approximately 160°C. When the junction temperature
reduces to approximately 140°C, the amplifier turns
on again. But, for maximum performance and re-
liability, the designer must take care to ensure that
the design does not exeed a junction temperature of
125°C. Between 125°C and 150°C, damage does not
occur, but the performance of the amplifier begins to
degrade and long term reliability suffers. The thermal
characteristics of the device are dictated by the
package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
2. Place 13 holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3092/6 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal pad. They can be larger because
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS-,
is acceptable as there is no electrical connection
to the silicon.
Tmax TA
qJA
PDmax
+
where:
P
Dmax
is the maximum power dissipation in the amplifier (W).
T
T
θ
is the absolute maximum junction temperature (°C).
max
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. There-
fore, the holes under the THS3092/6 PowerPAD
package should make their connection to the
internal ground plane with a complete connection
around the entire circumference of the
plated-through hole.
is the ambient temperature (°C).
= θ + θ
A
JA
JC
CA
θ
is the thermal coeffiecient from the silicon junctions to
JC
the case (°C/W).
θ
is the thermal coeffiecient from the case to ambient
CA
air (°C/W).
For systems where heat dissipation is more critical,
the THS3092 is offered in an 8-pin SOIC (DDA) with
PowerPAD package, and the THS3096 is offered in a
14-pin TSSOP (PWP) with PowerPAD package for
even better thermal performance. The thermal coef-
ficient for the PowerPAD packages are substantially
improved over the traditional SOIC. Maximum power
dissipation levels are depicted in the graph for the
available packages. The data for the PowerPAD
packages assume a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note (literature
number SLMA002). The following graph also illus-
trates the effect of not soldering the PowerPAD to a
PCB. The thermal impedance increases substantially
which may cause serious heat and performance
issues. Be sure to always solder the PowerPAD to
the PCB for optimum performance.
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its 13 holes exposed. The bottom-side solder
mask should cover the 13 holes of the thermal
pad area. This prevents solder from being pulled
away from the thermal pad area during the reflow
process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
23
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
DESIGN TOOLS
4
Τ
J
= 125°C
3.5
3
Evaluation
Fixtures,
Spice
Models,
and
θ
= 45.8°C/W
Application Support
JA
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal an evaluation board has
been developed for the THS3092/6 operational ampli-
fier. The board is easy to use, allowing for straightfor-
ward evaluation of the device. The evaluation board
can be ordered through the Texas Instruments web
site, www.ti.com, or through your local Texas
Instruments sales representative.
2.5
2
θ
= 58.4°C/W
JA
θ
= 95°C/W
JA
1.5
1
0.5
0
θ
= 158°C/W
JA
−40
−20
0
20
40
60
80
100
T
− Free-Air Temperature − °C
A
Computer simulation of circuit performance using
SPICE is often useful when analyzing the perform-
ance of analog circuits and systems. This is particu-
larly true for video and RF-amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS3092/6 is available through either the
Texas Instruments web site (www.ti.com) or as one
model on a disk from the Texas Instruments Product
Information Center (1–800–548–6132). The PIC is
also available for design assistance and detailed
product information at this number. These models do
a good job of predicting small-signal ac and transient
performance under a wide variety of operating con-
ditions. They are not intended to model the distortion
characteristics of the amplifier, nor do they attempt to
distinguish between the package types in their
small-signal ac performance. Detailed information
about what is and is not modeled is contained in the
model file itself.
Results are With No Air Flow and PCB Size = 3”x 3”
θJ = 45.8°C/W for 8-Pin SOIC w/PowerPad (DDA)
θJ = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJ = 95°C/W for 8-Pin SOIC High−K Test PCB (D)
θJ = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
A
A
A
A
Figure 68. Maximum Power Distribution vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
24
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
THS3092 EVM
GND
J8
- 5 V
J7
5 V
J9
FB1
FB2
C2
5 V
-5 V
+
C1
C4
C3
+
TP1 TP2
R6
J2
R1
5 V
U1:A
8
R2
2
3
J1
Figure 70. THS3092 EVM Board Layout
(Top Layer)
R5
1
J3
R4
4
R3
-5 V
R7
J4
R8
6
5
R9
J6
R11
7
U1:B
J5
R12
R10
Figure 69. THS3092 EVM Schematic
Figure 71. THS3092 EVM Board Layout
(Ground Plane)
25
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
Figure 72. THS3092 EVM Board Layout
(Power Plane)
Figure 73. THS3092 EVM Board Layout
(Bottom Layer)
Table 2. THS3092 EVM Bill of Materials
THS3092DGN EVM
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
ITEM
DESCRIPTION
SMD SIZE
1206
PART NUMBER(1)
1
2
Bead, Ferrite, 3 A, 80 Ω
FB1, FB2
2
2
(Steward) HI1206N800R-00
Cap. 22 µF, Tanatalum,
35 V, 10%
D
C1, C2
(AVX) TAJD685K035R
3
4
Cap. 0.1 µF, Ceramic, X7R, 16 V
Resistor, 178 Ω, 1/8 W, 1%
Resistor, 715 Ω, 1/8 W, 1%
Open
0805
0805
0805
1206
1206
1206
C3, C4
R1, R8
2
2
2
2
2
4
6
3
2
1
1
(AVX) 08055C104KAT2A
(KOA) RK73H2ALTD1780F
(KOA) RK73H2ALTD7150F
5
R6, R7
6
R4, R12
7
Resistor, 0 Ω, 1/4 W, 1%
Resistor, 49.9 Ω, 1/4 W, 1%
Connector, edge, SMA PCB jack
Jack, banana, 0.25" dia. hole
Test point, black
R2, R9
(KOA) RK73Z2BLTD
(KOA) RK73H2BLTD49R9F
(Johnson) 142-0701-801
(SPC) 813
8
R1, R5, R10, R11
J1, J2, J3, J4, J5, J6
J7, J8, J9
TP1, TP2
U1
9
10
11
12
13
(Keystone) 5001
IC, THS3092
(TI) THS3092DDA
Board, printed-circuit
(TI) EDGE # 6446250 Rev. A
(1) The manufacturer's part numbers were used for test purposes only.
26
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
THS3096 EVM
GND
J8
5 V
J7
-5 V
J9
FB1
FB2
5 V
-5 V
C5
+
C1
C4
C3
C2
+
TP1 TP2
R4
J1
R3
5 V
14
U1:A
R1
2
3
J3
R5
1
15
Figure 75. THS3096 EVM Board Layout
(Top Layer)
J2
R6
4
R2
-5 V
R9
J4
R8
U1:B
R7
J6
12
11
R11
13
9
J5
6
R10
R12
R13
J10
R14
JP1
R15
5 V
Figure 74. THS3096 EVM Schematic
Figure 76. THS3096 EVM Board Layout
(Ground Plane)
27
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
Figure 77. THS3096 EVM Board Layout
(Power Plane)
Figure 78. THS3096 EVM Board Layout
(Bottom Layer)
Table 3. THS3096 EVM Bill of Materials
THS3096PWP EVM
REFERENCE
PCB
QTY
MANUFACTURER'S
PART NUMBER
ITEM
DESCRIPTION
SMD SIZE
DESIGNATOR
FB1, FB2
C1, C2
1
2
Bead, Ferrite, 3 A, 80 Ω
Cap. 22 µF, Tanatalum, 25 V, 10%
Cap. 0.1 µF, Ceramic, X7R, 50 V
Cap. 0.1 µF, Ceramic, X7R, 50 V
Resistor, 100 Ω, 1/8W, 1%
Resistor, 178 Ω, 1/8 W, 1%
Resistor, 715 Ω, 1/8 W, 1%
Resistor, 20 kΩ, 1/8 W, 1%
Open
1206
D
2
2
2
1
1
2
2
2
2
2
4
1
1
6
3
1
2
1
1
(Steward) HI1206N800R-00
(AVX) TAJD226K025R
3
0805
1206
0805
0805
0805
0805
1206
1206
1206
2 pos.
C3, C4
(AVX) 08055C104KAT2A
(AVX) 12065C104KAT2A
(KOA) RK73H2ALTD1000F
(KOA) RK73H2ALTD1780F
(KOA) RK73H2ALTD7150F
(KOA) RK73H2ALTD2002F
4
C5
5
R13
6
R3, R8
7
R4, R9
8
R14, R15
R6, R10
R1, R7
9
10
11
12
13
14
15
16
17
18
19
Resistor, 0 Ω, 1/4 W, 1%
Resistor, 49.9 Ω, 1/4 W, 1%
Header, 0.1" ctrs, 0.025" sq. pins
Shunts
(KOA) RK73Z2BLTD
(KOA) RK73H2BLTD49R9F
(Sullins) PZC36SAAN
(Sullins) SSC02SYAN
(Amphenol) 901-144-8RFX
(SPC) 813
R2, R5, R11, R12
JP1
JP1
Connector, SMA PCB jack
Jack, banana, 0.25" dia. hole
Test point, red
J1, J2, J3, J4, J5, J6
J7, J8, J9
J10
(Keystone) 5000
Test point, black
TP1, TP2
U1
(Keystone) 5001
IC, THS3096
(TI) THS3096PWP
Board, printed-circuit
(TI) EDGE # 6454586 Rev. A
28
THS3092
THS3096
www.ti.com
SLOS428A–DECEMBER 2003–REVISED FEBRUARY 2004
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
Current Feedback Analysis and Compensation (SLOA021)
Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
•
Active Output Impedance for ADSL Line Drivers (SLOA100)
29
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相关型号：
THS3092DG4
Dual- High-Voltage, Low Distortion, Current-Feedback Operational Amplifier 8-SOIC -40 to 85
TI
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