THS3110_14 [TI]
LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS;
| 型号： | THS3110_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS 放大器 |
| 文件： | 总28页 (文件大小：913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK,
OPERATIONAL AMPLIFIERS
FEATURES
DESCRIPTION
•
Low Noise
The THS3110 and THS3111 are low-noise,
high-voltage, current-feedback amplifiers designed to
operate over a wide supply range of ±5 V to ±15 V for
today's high performance applications.
– 2 pA/√Hz Noninverting Current Noise
– 10 pA/√Hz Inverting Current Noise
– 3 nV/√Hz Voltage Noise
The THS3110 features a power-down pin (PD) that
puts the amplifier in low power standby mode, and
lowers the quiescent current from 4.8 mA to 270 µA.
•
•
High Output Current Drive: 260 mA
High Slew Rate: 1300 V/µs (RL = 100 Ω,
VO = 8 VPP
)
These
amplifiers
provide
well-regulated
The unity
ac
gain
•
•
•
Wide Bandwidth: 90 MHz (G = 2, RL = 100 Ω)
Wide Supply Range: ±5 V to ±15 V
performance characteristics.
bandwidth of 100 MHz allows for good distortion
characteristics below 10 MHz. Coupled with high
1300-V/µs slew rate, the THS3110 and THS3111
amplifiers allow for high output voltage swings at high
frequencies.
Power-Down Feature: (THS3110 Only)
APPLICATIONS
•
•
•
•
Video Distribution
Power FET Driver
Pin Driver
The THS3110 and THS3111 are offered in a 8-pin
SOIC (D), and the 8-pin MSOP (DGN) packages with
PowerPAD™.
Capacitive Load Driver
DIFFERENTIAL PHASE
DIFFERENTIAL GAIN
vs
vs
NUMBER OF LOADS
NUMBER OF LOADS
0.3
0.4
0.35
0.3
VIDEO DISTRIBUTION AMPLIFIER APPLICATION
Gain = 2,
= 1 kΩ,
= ±15 V,
40 IRE − NTSC and PAL,
Gain = 2,
R
V
= 1 kΩ,
R
F
S
F
= ±15 V,
1 kΩ
1 kΩ
0.25
0.2
0.15
0.1
0.05
0
V
S
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
Worst Case ±100 IRE Ramp
15 V
75-Ω Transmission Line
75 Ω
V
O(1)
0.25
0.2
−
+
PAL
PAL
V
I
NTSC
−15 V
75 Ω
0.15
0.1
NTSC
n Lines
75 Ω
V
O(n)
75 Ω
0.05
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
75 Ω
Number of 150 Ω Loads
Number of 150 Ω Loads
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling procedures and installation procedures can cause damage.
TOP VIEW
D, DGN
TOP VIEW
D, DGN
THS3110
THS3111
REF
PD
NC
NC
1
2
3
4
8
7
6
5
1
2
3
4
8
V
IN−
V
IN+
V
V
V
IN−
V
IN+
7
6
5
V
V
S+
S+
OUT
OUT
V
S−
NC
V
S−
NC
NC = No Internal Connection
NC = No Internal Connection
Note: The device with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin
functional range is from V to (V − 4 V).
S−
S+
AVAILABLE OPTIONS
PACKAGED DEVICE
PLASTIC MSOP (DGN)(1)(2)
TA
PLASTIC SMALL OUTLINE SOIC (D)
THS3110CD
SYMBOL
THS3110CDGN
THS3110CDGNR
THS3110IDGN
THS3110IDGNR
THS3111CDGN
THS3111CDGNR
THS3111IDGN
THS3111IDGNR
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
BJB
THS3110CDR
THS3110ID
BIR
BJA
BIS
THS3110IDR
THS3111CD
THS3111CDR
THS3111ID
THS3111IDR
(1) Available in tape and reel. The R suffix standard quantity is 2500 (e.g. THS3110CDGNR).
(2) The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATING TABLE
POWER RATING
TJ = 125°C
PACKAGE
ΘJC (°C/W)
ΘJA (°C/W)
TA = 25°C
1.05 W
TA = 85°C
D-8(1)
DGN-8(2)
38.3
4.7
95
421 mW
685 mW
58.4
1.71 W
(1) This data was taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the ΘJA is 95°C/W with
power rating at TA = 25°C of 1.05 W.
(2) This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch x 3 inch PCB. For further information, refer to
the Application Informationsection of this data sheet.
2
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
RECOMMENDED OPERATING CONDITIONS
MIN
±5
NOM
MAX
±15
30
UNIT
Dual supply
Supply voltage
Single supply
V
10
Commercial
Operating free-air temperature, TA
Industrial
0
70
-40
-40
-40
85
°C
Operating junction temperature, continuous operating temperature, TJ
Normal storage temperature, Tstg
125
85
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)(1)
UNIT
Supply voltage, VS- to VS+
Input voltage, VI
33 V
± VS
Differential input voltage, VID
± 4 V
(2)
Output current, IO
300 mA
Continuous power dissipation
See Dissipation Ratings Table
150°C
(3)
Maximum junction temperature, TJ
(4)
Maximum junction temperature, continuous operation, long term reliability, TJ
125°C
Commercial
Industrial
0°C to 70°C
-40°C to 85°C
-65°C to 125°C
300°C
Operating free-air temperature, TA
Storage temperature, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings:
HBM
900
1500
200
CDM
MM
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3110 and THS3111 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
3
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 1 k Ω,RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
AC PERFORMANCE
G = 1, RF = 1.5 kΩ, VO = 200 mVPP
G = 2, RF = 1 kΩ, VO = 200 mVPP
G = 5, RF = 806 Ω, VO = 200 mVPP
G = 10, RF = 604 Ω, VO = 200 mVPP
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
G = 5, RF = 806 Ω , VO = 4 VPP
G = 1, VO = 4-V step, RF = 1.5 kΩ
G = 2, VO = 8-V step, RF = 1 kΩ
100
90
Small-signal bandwidth, -3 dB
87
MHz
V/µs
TYP
TYP
66
0.1 dB bandwidth flatness
Large-signal bandwidth
45
95
800
1300
Slew rate (25% to 75% level)
Slew rate
Recommended maximum SR for
repetitive signals(1)
900
V/µs
ns
MAX
TYP
Rise and fall time
G = -5, VO = 10-V step, RF = 806 Ω
G = -2, VO = 2 VPP step
8
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
27
ns
TYP
G = -2, VO = 2 VPP step
250
RL = 100 Ω
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
52
53
2nd Harmonic distortion
3rd Harmonic distortion
G = 2,
RF = 1 kΩ ,
VO = 2 VPP
f = 10 MHz
dBc
TYP
,
48
68
Input voltage noise
f > 20 kHz
f > 20 kHz
f > 20 kHz
3
nV / √Hz
pA / √Hz
pA / √Hz
TYP
TYP
TYP
Noninverting input current noise
Inverting input current noise
2
10
NTSC
PAL
0.011%
0.013%
0.029°
0.033°
Differential gain
G = 2,
RL = 150 Ω,
RF = 1 kΩ
TYP
NTSC
PAL
Differential phase
DC PERFORMANCE
Transimpedance
VO = ±3.75 V, Gain = 1
1.6
1.5
1
6
0.7
8
0.7
8
MΩ
mV
MIN
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
Input offset voltage
VCM = 0 V
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
±10
6
±10
6
µV/°C
µA
1
4
VCM = 0 V
VCM = 0 V
VCM = 0 V
±10
20
±10
20
nA/°C
µA
1.5
2.5
15
15
±10
20
±10
20
nA/°C
µA
Average offset current drift
INPUT CHARACTERISTICS
Input common-mode voltage range
Common-mode rejection ratio
Noninverting input resistance
Noninverting input capacitance
OUTPUT CHARACTERISTICS
±30
±30
nA/°C
±13.3
68
±13
±12.5
±12.5
V
MIN
MIN
TYP
TYP
VCM = ±12.5 V
62
60
60
dB
MΩ
pF
41
0.4
RL = 1 kΩ
±13.5
±13.4
260
±13
±12.5
200
±12.5
±12
±12.5
±12
Output voltage swing
V
MIN
RL = 100 Ω
Output current (sourcing)
Output current (sinking)
Output impedance
RL = 25 Ω
175
175
mA
mA
Ω
MIN
MIN
TYP
RL = 25 Ω
260
200
175
175
f = 1 MHz, Closed loop
0.15
(1) For more information, see the Application Information section of this data sheet.
4
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VS = ±15 V, RF = 1 k Ω,RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
POWER-DOWN CHARACTERISTICS
±15
4.8
4.8
83
±16
6.5
3.8
75
±16
7.5
2.5
70
±16
7.5
2.5
70
V
MAX
MAX
MIN
MIN
MIN
mA
mA
dB
dB
VS+ = 15.5 V to 14.5 V, VS- = 15 V
VS+ = 15 V, VS- = -15.5 V to -14.5 V
78
70
66
66
Enable, REF = 0 V
Power-down , REF = 0 V
PD = 0V
≤ 0.8
Power-down voltage level
Power-down quiescent current
VPD quiescent current
V
MAX
MAX
TYP
≥ 2
270
450
500
500
µA
µA
VPD = 0 V, REF = 0 V,
VPD = 3.3 V, REF = 0 V
90% of final value
10% of final value
11
11
Turnon time delay
Turnoff time delay
Input impedance
4
6
µs
TYP
TYP
3.4 || 1.7
kΩ || pF
5
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RF = 1.15 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C to
85°C
MIN/TYP/
MAX
25°C
25°C
UNIT
AC PERFORMANCE
G = 1, RF = 1.5 kΩ, VO = 200 mVPP
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
G = 5, RF = 806 Ω, VO = 200 mVPP
G = 10, RF = 604 Ω, VO = 200 mVPP
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
G = 5, RF = 806 Ω , VO = 4 VPP
85
78
Small-signal bandwidth, -3 dB
80
MHz
V/µs
TYP
TYP
60
0.1 dB bandwidth flatness
Large-signal bandwidth
15
80
G = 1, VO= 4-V step, RF = 1.5 kΩ
G = 2, VO= 4-V step, RF = 1 kΩ
640
700
Slew rate (25% to 75% level)
Slew rate
Recommended maximum SR for
repetitive signals(1)
900
V/µs
ns
MAX
TYP
Rise and fall time
G = -5, VO = 5-V step, RF = 806Ω
G = -2, VO = 2 VPP step
7
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
20
ns
TYP
G = -2, VO = 2 VPP step
200
RL = 100Ω
55
56
2nd Harmonic distortion
3rd Harmonic distortion
G = 2,
RF = 1 kΩ ,
VO = 2 VPP
f = 10 MHz
RL = 1 kΩ
RL = 100Ω
RL = 1 kΩ
dBc
TYP
,
45
62
Input voltage noise
f > 20 kHz
f > 20 kHz
f > 20 kHz
3
nV / √Hz
pA / √Hz
pA / √Hz
TYP
TYP
TYP
Noninverting input current noise
Inverting input current noise
2
10
NTSC
PAL
0.011%
0.015%
0.020°
0.033°
Differential gain
G = 2,
RL = 150 Ω,
RF = 1 kΩ
TYP
NTSC
PAL
Differential phase
DC PERFORMANCE
Transimpedance
VO = ±1.25 V, Gain = 1
1.6
3
1
6
0.7
8
0.7
8
MΩ
mV
MIN
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
Input offset voltage
VCM = 0 V
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
±10
6
±10
6
µV/°C
µA
1
1
1
4
8
6
VCM = 0 V
VCM = 0 V
VCM = 0 V
±10
10
±10
8
±10
10
±10
8
nA/°C
µA
nA/°C
µA
Average offset current drift
INPUT CHARACTERISTICS
Input common-mode voltage range
Common-mode rejection ratio
Noninverting input resistance
Noninverting input capacitance
OUTPUT CHARACTERISTICS
±20
±20
nA/°C
±3.2
65
±2.9
±2.8
±2.8
V
MIN
MIN
TYP
TYP
VCM = ±2.5 V
62
58
58
dB
MΩ
pF
35
0.5
RL = 1 kΩ
±4
±3.8
±3.7
150
150
±3.6
±3.5
125
125
±3.6
±3.5
125
125
Output voltage swing
V
MIN
RL = 100 Ω
±3.8
220
220
0.15
Output current (sourcing)
Output current (sinking)
Output impedance
RL = 10 Ω
mA
mA
Ω
MIN
MIN
TYP
RL = 10 Ω
f = 1 MHz, Closed loop
(1) For more information, see the Application Information section of this data sheet.
6
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, RF = 1.15 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C to
85°C
MIN/TYP/
MAX
25°C
25°C
UNIT
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
POWER-DOWN CHARACTERISTICS
±5
4
±4.5
6
±4.5
7
±4.5
7
V
MIN
MAX
MIN
MIN
MIN
mA
mA
dB
dB
4
3.2
72
67
2
2
VS+ = 5.5 V to 4.5 V, VS- = 5 V
VS+ = 5 V, VS- = -5.5 V to -4.5 V
80
75
67
62
67
62
Enable, REF = 0 V
Power-down , REF = 0 V
PD = 0 V
≤ 0.8
Power-down voltage level
Power-down quiescent current
VPD quiescent current
V
MAX
MAX
TYP
≥ 2
200
450
500
500
µA
µA
VPD = 0 V, REF = 0 V,
VPD = 3.3 V, REF = 0 V
90% of final value
10% of final value
11
11
Turnon time delay
Turnoff time delay
Input impedance
4
6
µs
TYP
TYP
3.4 || 1.7
kΩ || pF
7
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
±15-V graphs
Noninverting small signal gain frequency response
Inverting small signal gain frequency response
0.1 dB flatness
1, 2
3
4
Noninverting large signal gain frequency response
Inverting large signal gain frequency response
Frequency response capacitive load
Recommended RISO
5
6
7
vs Capacitive load
vs Frequency
8
2nd Harmonic distortion
9
3rd Harmonic distortion
vs Frequency
10
Harmonic distortion
vs Output voltage swing
vs Output voltage step
vs Frequency
11, 12
Slew rate
13, 14, 15, 16
Noise
17
18, 19
20
Settling time
Quiescent current
vs Supply voltage
vs Load resistance
vs Case temperature
vs Case temperature
vs Frequency
Output voltage
21
Input bias and offset current
Input offset voltage
22
23
Transimpedance
24
Rejection ratio
vs Frequency
25
Noninverting small signal transient response
Inverting large signal transient response
Overdrive recovery time
26
27
28
Differential gain
vs Number of loads
vs Number of loads
vs Frequency
29
Differential phase
30
Closed loop output impedance
Power-down quiescent current
Turnon and turnoff time delay
±5-V graphs
31
vs Supply voltage
32
33
Noninverting small signal gain frequency response
Inverting small signal gain frequency response
0.1 dB flatness
34
35
36
Noninverting large signal gain frequency response
Inverting large signal gain frequency response
Slew rate
37
38
vs Output voltage step
vs Frequency
39, 40, 41, 42
2nd Harmonic distortion
43
44
3rd Harmonic distortion
vs Frequency
Harmonic distortion
vs Output voltage swing
45, 46
47
Noninverting small signal transient response
Inverting small signal transient response
Overdrive recovery time
48
49
Rejection ratio
vs Frequency
50
8
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V)
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL SIGNAL
FREQUENCY RESPONSE
9
24
22
20
18
16
14
12
24
22
20
18
16
14
12
10
R
V
V
= 100 Ω,
L
G = -10, R = 649 Ω
R
= 649 Ω
F
F
G = 10, R = 604 Ω
8
7
= 0.2 V ,
F
O
S
PP
= ±15 V
G = -5, R = 909 Ω
F
G = 5, R = 806 Ω
F
6
5
4
R
O
S
= 100 Ω,
L
R
= 1.15 kΩ
F
V
V
= 0.2 V ,
PP
10
8
= ±15 V
G = -2, R = 1.1 kΩ
F
R
= 1.5 kΩ
G = 2, R = 1.15 kΩ
8
6
4
2
F
F
6
3
2
Gain = 2,
= 100 Ω,
= 0.2 V ,
PP
= ±15 V
4
R
V
V
L
2
G = -1, R = 1 kΩ
G = 1, R = 1.5 kΩ
F
F
O
S
0
0
-2
-4
1
0
-2
-4
100 k
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 1.
Figure 2.
Figure 3.
NONINVERTING LARGE SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE SIGNAL
FREQUENCY RESPONSE
0.1 dB FLATNESS
16
6.4
16
14
12
10
8
R
= 100 Ω,
L
G = 5, R = 806 Ω
F
14
12
Gain = 2,
V
V
= 2 V ,
O
S
PP
6.3
6.2
R
R
= 1.15 kΩ,
= 100 Ω,
= 0.2 V
= ±15 V
G = -5, R = 806 Ω
F
L
F
10
8
V
V
,
O
S
PP
= ±15 V
6.1
6
6
G = 2, R = 1 kΩ
F
4
5.9
5.8
6
2
G =-1, R = 1 kΩ
F
4
0
R
V
V
= 100 Ω,
L
5.7
5.6
2
-2
-4
= 4 V ,
= ±15 V
O
S
PP
0
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 M
10 M
100 M
1 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 4.
Figure 5.
Figure 6.
RECOMMENDED RISO
vs
Capacitive LOAD
2nd HARMONIC DISTORTION
FREQUENCY RESPONSE
CAPACITIVE LOAD
vs
FREQUENCY
60
50
40
30
20
16
14
12
10
-30
-40
R
= 54.9 Ω, C = 22 pF
L
Gain = 5,
(ISO)
G = 5, R = 806 Ω
F
R
L
= 100 Ω,
= ±15 V
V
S
Gain = 5,
-50
-60
R
V
= 100 Ω
= ±15 V
L
G = 2, R = 1 kΩ
F
S
8
6
4
2
R
C
= 54.9 Ω
= 39.2 Ω
(ISO)
= 10 pF
‘
-70
-80
L
G = -2, R = 1 kΩ
F
R
(ISO)
R
L
= 1 kΩ,
C
= 47 pF
L
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±15 V
O
10
0
-90
R
C
= 28 Ω
(ISO)
= 100 pF
L
0
L
S
-100
-2
10
100
100 k
1 M
10 M
100 M
10 M
100 M 200 M
C
L
- Capacitive Load - pF
f - Frequency - Hz
Capacitive Load - MHz
Figure 7.
Figure 8.
Figure 9.
9
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V) (continued)
3rd HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
vs
FREQUENCY
OUTPUT VOLTAGE SWING
-40
-45
-50
-55
-60
-70
-75
-80
-30
-40
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±15 V
O
HD3
L
HD3
S
-50
-60
G = 5, R = 806 Ω
F
HD2
G = 2,
= 1 kΩ
HD2
-85
-90
R
F
-70
-80
Gain = 2,
Gain = 2,
R
F
R
L
= 1 kΩ,
= 100 Ω,
R
R
= 1 kΩ,
= 100Ω,
F
G = -2,
L
-65
-70
R
F
R
L
= 1 kΩ
= 1 kΩ,
-95
f= 1 MHz
= ±15 V
-90
f = 8 MHz
= ±15 V
V
S
V
S
-100
-100
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
100 k
1 M
10 M
100 M
V
- Output Voltage Swing - V
V
- Output Voltage Swing - V
O
PP
f - Frequency - Hz
O
PP
Figure 10.
Figure 11.
Figure 12.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
1400
1200
1000
800
600
400
200
0
1000
800
600
400
1400
Gain = 1
Gain = 2
Fall
Gain = 1
R
R
V
= 100 Ω
= 1.5 kΩ
= ±15 V
R
L
R
F
V
=100 Ω
=1 kΩ
L
F
Fall
1200
1000
800
R
R
V
= 1 kΩ
= 1.5 kΩ
= ±15 V
L
F
S
Fall
= ±15 V
S
S
Rise
Rise
Rise
600
400
200
0
200
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
6
7
8
9
10
V
- Output Voltage -V
V
- Output Voltage -V
PP
V
- Output Voltage -V
O
PP
O
O
PP
Figure 13.
Figure 14.
#IMPLIED #IMPLIED.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
NOISE
vs
FREQUENCY
SETTLING TIME
1600
1400
1200
1000
800
1.5
100
Rising Edge
Gain = 2
Fall
R
L
R
F
S
=1 kΩ
=1 kΩ
1
V
= ±15 V
Rise
0.5
I
n-
Gain = -2
R
R
V
= 100 Ω
= 1.1 kΩ
= ±15 V
L
F
S
0
10
V
n
600
-0.5
400
Falling Edge
I
-1
n+
200
0
-1.5
1
0
2
4
6
8
10 12 14 16 18
10
10
100
1 k
10 k
100 k
0
1
2
3
4
5
6
7
8
9
t - Time - ns
f - Frequency - Hz
V
- Output Voltage -V
O
PP
#IMPLIED #IMPLIED.
Figure 15.
Figure 16.
10
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V) (continued)
QUIESCENT CURRENT
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
vs
SETTLING TIME
SUPPLY VOLTAGE
3
6
5
16
14
12
10
8
6
4
2.5
T
= 85 °C
A
Rising Edge
2
T
= 25 °C
= -40 °C
A
1.5
4
3
2
1
0
1
T
A
0.5
Gain = -2
2
V
T
= ±15 V
= -40° to 85°C
S
R
R
V
= 100 Ω
= 1.1 kΩ
= ±15 V
L
F
0
-2
-4
-6
-8
-10
-12
-14
-16
0
A
-0.5
S
-1
-1.5
-2
Falling Edge
-2.5
-3
10
100
1000
0
2
4
6
8
10 12 14 16 18 20
2
3
4
5
6
7
8
9
10 11 12 13 14 15
t - Time - ns
R
L
- Load Resistance - Ω
V
- Supply Voltage - ±V
S
Figure 17.
#IMPLIED #IMPLIED.
Figure 18.
INPUT BIAS AND
OFFSET CURRENT
vs
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
TRANSIMPEDANCE
vs
CASE TEMPERATURE
FREQUENCY
120
100
3.5
3
4
V
= ±15 V
S
3.5
V
= ±15 V
S
3
I
I
2.5
2
IB-
80
60
40
V
= ±5 V
2.5
S
V
= ±5 V
S
2
1.5
1
OS
1.5
1
V
= ±15 V
S
I
IB+
20
0
0.5
0
0.5
0
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90
100 k
1 M
10 M
100 M
1 G
T
C
- Case Temperature - °C
f - Frequency - Hz
T
C
- Case Temperature - °C
Figure 19.
Figure 20.
Figure 21.
REJECTION RATIO
vs
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
FREQUENCY
6
0.2
0.15
0.1
70
60
Gain = -5,
V
= ±15 V
S
5
4
R
R
V
= 100 Ω,
= 909 Ω,
= ±15 V
L
F
S
CMRR
Output
Input
3
2
1
0
50
40
30
20
0.05
PSRR+
Input
0
-0.05
-0.1
-1
-2
-3
-4
PSRR-
Gain = 2,
R
R
V
= 100 Ω,
= 1 kΩ,
= ±15 V
L
F
S
Output
10
0
-0.15
-0.2
-5
-6
0
10 20 30 40 50 60 70 80
10 M
100 M
0
10 20 30 40 50 60 70 80
100 k
1 M
t - Time - ns
f - Frequency - Hz
t - Time - ns
Figure 22.
Figure 23.
Figure 24.
11
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±15 V) (continued)
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
vs
vs
OVERDRIVE RECOVERY TIME
NUMBER OF LOADS
NUMBER OF LOADS
20
15
0.3
0.25
0.2
0.4
0.35
0.3
5
Gain = 2,
Gain = 4,
Gain = 2,
R
= 1 kΩ,
F
S
R
V
= 1 kΩ,
= ±15 V,
R
R
V
= 100 Ω,
= 681 Ω,
= ±15 V
F
L
F
V
= ±15 V,
S
40 IRE - NTSC and PAL,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
10
2.5
0
Worst Case ±100 IRE Ramp
S
5
0
0.25
0.2
PAL
PAL
0.15
0.1
NTSC
-5
0.15
0.1
NTSC
-2.5
-5
-10
-15
-20
0.05
0
0.05
0
0
0.2
0.4
0.6
0.8
1
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
t - Time - µs
Number of 150 Ω Loads
Number of 150 Ω Loads
Figure 25.
Figure 26.
Figure 27.
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
POWER-DOWN QUIESCENT
CURRENT
vs
TURNON AND TURNOFF
TIME DELAY
FREQUENCY
SUPPLY VOLTAGE
350
300
250
200
150
100
100
10
1
1.5
Gain = 2,
1
0.5
0
R
R
V
= 1 kΩ,
= 100 Ω,
= ±15 V
F
F
Output Voltage
T
= 85°C
A
S
6
−0.5
Powerdown Pulse
5
4
3
2
T
= -40°C
A
T
A
= 25°C
Gain = 5,
0.1
V
= 0.1 Vdc
I
1
0
R
L
= 100 Ω
50
0
V
= ±15 V and ±5 V
S
−1
0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
3
5
7
9
11
13
15
100 k
1 M
10 M
100 M
1 G
t − Time − ms
V
- Supply Voltage - ±V
f - Frequency - Hz
S
#IMPLIED #IMPLIED.
Figure 28.
Figure 29.
12
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±5 V)
NONINVERTING SMALL SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL SIGNAL
FREQUENCY RESPONSE
0.1 dB FLATNESS
24
22
20
18
16
14
12
6.4
24
22
20
18
16
14
12
R
V
= 100 Ω,
R
= 100 Ω,
L
O
S
Gain = 2,
L
G = -10, R = 649 Ω
F
G = 10, R = 604 Ω
= 0.2 V
,
F
PP
V
V
= 0.2 V ,
O
S
PP
R
F
R
L
= 1.15 kΩ,
= 100 Ω,
6.3
6.2
6.1
V
= ±5 V
= ±5 V
V
V
= 0.2 V ,
PP
= ±5 V
O
S
G = 5, R = 806 Ω
F
G = -5, R = 909 Ω
F
10
8
10
8
6
G = 2, R = 1.15 kΩ
F
G = -2, R = 1.1 kΩ
F
5.9
6
4
2
6
4
5.8
2
0
G = -1, R = 1 kΩ
F
G = 1, R = 1.5 kΩ
F
0
-2
-4
5.7
5.6
−2
−4
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
100 k
10 M
100 M
1 M
f - Frequency - Hz
f − Frequency − Hz
f - Frequency - Hz
Figure 30.
Figure 31.
Figure 32.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
NONINVERTING LARGE SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE SIGNAL
FREQUENCY RESPONSE
16
14
12
10
8
16
14
12
10
8
800
700
600
500
400
300
200
100
0
G = -5, R = 909 Ω
F
G = 5, R = 806 Ω
Gain = 1
F
Fall
R
R
V
= 100 Ω
= 1.5 kΩ
= ±5 V
L
F
S
Rise
V
= 2 V ,
PP
O
R
V
= 100 Ω,
= ±5 V
L
6
S
G = 2, R = 1.15 kΩ
F
4
6
2
G =-12, R = 1 kΩ
F
4
V
= 4 V ,
PP
O
0
R
= 100 Ω,
= ±5 V
L
2
0
-2
V
S
-4
10 M
100 M
1 G
1 M
10 M
100 M
1 G
1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
f - Frequency - Hz
f - Frequency - Hz
V
- Output Voltage -V
O
PP
#IMPLIED #IMPLIED.
#IMPLIED #IMPLIED.
Figure 33.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
800
700
600
500
400
300
200
800
700
600
500
400
300
800
700
600
500
400
300
Rise
Gain = 2
Gain = 2
Fall
Gain = 1
Rise
R
R
V
= 1 kΩ
= 1 kΩ
= ±5 V
R
R
V
= 100 Ω
= 1 kΩ
= ±5 V
L
F
L
F
R
L
R
F
V
= 1 kΩ
= 1.5 kΩ
= ±5 V
Rise
S
S
Fall
S
Fall
200
100
200
100
0
100
0
0
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
0
1
2
3
4
5
6
V
- Output Voltage -V
V
O
- Output Voltage -V
PP
O
PP
V
- Output Voltage -V
PP
O
Figure 34.
#IMPLIED #IMPLIED.
#IMPLIED #IMPLIED.
13
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS (±5 V) (continued)
2nd HARMONIC DISTORTION
3rd HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
vs
FREQUENCY
FREQUENCY
-65
-70
-75
-80
-85
-90
-30
-40
-30
-40
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±5 V
O
G = 5, R = 681 Ω
F
L
S
HD3
G = 2, R = 681 Ω
F
-50
-60
-50
-60
G = 5,
= 681 Ω
R
F
HD2
-70
-80
-70
-80
G = 2,
= 681 Ω
G = -2, R = 1 kΩ
F
Gain = 2,
R
F
R
L
= 1 kΩ,
R
R
= 1.15 kΩ
= 100 Ω,
F
L
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±5 V
O
f= 1 MHz
G = -2, R = 1 kΩ
-90
-90
-95
F
L
V
= ±5 V
S
R
L
= 1 kΩ,
S
-100
-100
-100
0
1
2
3
4
5
6
7
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
V
- Output Voltage Swing - V
f - Frequency - Hz
f - Frequency - Hz
O
PP
Figure 35.
Figure 36.
Figure 37.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
3
-40
-50
-60
-70
0.2
Gain = -5,
2.5
2
0.15
0.1
R
R
V
= 100 Ω,
= 909 Ω,
= ±5 V
Output
Input
L
F
S
HD3
1.5
1
HD2
0.05
0
0.5
Input
0
-0.5
-1
-0.05
-0.1
Gain = 2,
Gain = 2
R
R
= 1 kΩ
= 100 Ω,
F
R
R
V
= 100 Ω
= 1.15 kΩ
= ±5 V
-1.5
-2
L
F
S
-80
-90
L
Output
f= 8 MHz
-0.15
-0.2
V
= ±5 V
S
-2.5
-3
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
t - Time - ns
t - Time - ns
V
- Output Voltage Swing - V
O
PP
Figure 38.
Figure 39.
Figure 40.
REJECTION RATIO
vs
OVERDRIVE RECOVERY TIME
FREQUENCY
5
70
1.25
V
S
= ±5 V
Gain = 4,
4
3
1
R
R
V
= 100 Ω,
= 909 Ω,
= ±5 V
L
F
S
60
50
40
30
20
10
0
0.75
CMRR
0.5
2
1
0
0.25
PSRR+
0
-1
-0.25
-0.5
-2
-3
-4
-0.75
-1
PSRR-
-1.25
-5
0
0.2
0.4
0.6
0.8
1
100 k
1 M
10 M
100 M
t - Time - µs
f - Frequency - Hz
Figure 41.
Figure 42.
14
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
APPLICATION INFORMATION
MAXIMUM SLEW RATE FOR REPETITIVE
SIGNALS
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain setting
resistors RF and RG at different gains to give maxi-
mum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
The THS3110 and THS3111 are recommended for
high slew rate pulsed applications where the internal
nodes of the amplifier have time to stabilize between
pulses. It is recommended to have at least 20-ns
delay between pulses.
The THS3110 and THS3111 are not recommended
for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/µs. Using the
part in these applications results in excessive current
draw from the power supply and possible device
damage.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3110 and THS3111 RF and RG values for minimal peaking
with RL = 100 Ω
For applications with high slew rate, repetitive signals,
the THS3091 and THS3095 (single), or THS3092 and
THS3096 (dual) are recommended.
SUPPLY VOLTAGE
GAIN (V/V)
RG (Ω)
RF (Ω)
(V)
±15
--
--
1.5 k
1.5 k
1 k
1
WIDEBAND, NONINVERTING OPERATION
±5
±15
1 k
The THS3110 and THS3111 are unity gain stable
100-MHz current-feedback operational amplifiers, de-
signed to operate from a ±5-V to ±15-V power supply.
2
5
±5
±15
1.15 k
200
200
66.5
66.5
1 k
1.15 k
806
806
604
604
1 k
±5
Figure 43 shows the THS3111 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment pres-
enting a 50-Ω load impedance.
±15
10
-1
±5
±15
±5
1 k
1 k
-2
-5
±15 and ±5
±15 and ±5
±15 and ±5
549
182
64.9
1.1 k
909
649
15 V
+V
S
-10
+
0.1 µF
49.9 Ω
6.8 µF
50 Ω Source
49.9 Ω
+
V
I
THS3110
_
50 Ω LOAD
R
F
1 kΩ
1 kΩ
R
G
0.1 µF
6.8 µF
+
-V
S
-15 V
Figure 43. Wideband, Noninverting Gain
Configuration
15
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
WIDEBAND, INVERTING OPERATION
+V
S
Figure 44 shows the THS3111 in a typical inverting
gain configuration where the input and output im-
pedances and signal gain from Figure 43 are retained
in an inverting circuit configuration.
50 Ω Source
+
49.9 Ω
50 Ω LOAD
V
I
THS3110
49.9 Ω
R
T
_
15 V
+V
S
+V
2
S
R
F
+
1 kΩ
R
G
0.1 µF
49.9 Ω
6.8 µF
1 kΩ
+
THS3110
+V
2
S
_
R
F
50 Ω LOAD
1.1 kΩ
50 Ω Source
R
G
V
R
F
S
50 Ω Source
R
G
_
V
I
549 Ω
1.1 kΩ
49.9 Ω
50 Ω LOAD
V
I
R
M
549 Ω
R
T
THS3110
+
0.1 µF
6.8 µF
56.2 Ω
56.2 Ω
+
+V
2
+V
2
S
S
-V
S
-15 V
Figure 45. DC-Coupled, Single-Supply Operation
Figure 44. Wideband, Inverting Gain
Configuration
Video Distribution
SINGLE SUPPLY OPERATION
The wide bandwidth, high slew rate, and high output
drive current of the THS3110 and THS3111 matches
the demands for video distribution for delivering video
signals down multiple cables. To ensure high signal
quality with minimal degradation of performance, a
0.1-dB gain flatness should be at least 7x the
passband frequency to minimize group delay vari-
ations from the amplifier. A high slew rate minimizes
distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality.
The THS3110 and THS3111 have the capability to
operate from a single supply voltage ranging from
10 V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits shown in Figure 45 shows inverting and
noninverting amplifiers configured for single supply
operations.
1 kΩ
1 kΩ
15 V
75-Ω Transmission Line
V
O(1)
75 Ω
-
+
V
I
-15 V
75 Ω
n Lines
75 Ω
V
O(n)
75 Ω
75 Ω
Figure 46. Video Distribution Amplifier
Application
16
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
Driving Capacitive Loads
Placing a small series resistor, RISO, between the
amplifier’s output and the capacitive load, as shown
in Figure 48, is an easy way of isolating the load
capacitance.
Applications, such as FET drivers and line drivers can
be highly capacitive and cause stability problems for
high-speed amplifiers.
Using a ferrite chip in place of RISO, as shown in
Figure 49, is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the low fre-
quency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ω - 50 Ω, at 100 MHz and low impedance
at dc.
Figure 47 through Figure 53 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 47 for
recommended resistor values versus capacitive load.
60
Gain = 5,
R
= 100 Ω,
= ±15 V
L
50
40
30
20
V
S
Figure 50 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the capaci-
tance at high frequency. At low frequency, feedback
is mainly from the load side of RISO. At high fre-
quency, the feedback is mainly via the 27-pF capaci-
tor. The resistor RIN in series with the negative input
is used to stabilize the amplifier and should be equal
to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 51 gives similar
results with reduced dc offset and low frequency
noise. (See the ADDITIONAL REFERENCE MA-
TERIAL section for expanding the usability of cur-
rent-feedback amplifiers.)
10
0
10
100
C
L
- Capacitive Load - pF
Figure 47. Recommended RISO vs Capacitive Load
806 Ω
R
F
V
S
200 Ω
100 Ω LOAD
806 Ω
_
+
5.11 Ω
27 pF
V
R
ISO
R
IN
1 µF
-V
49.9 Ω
S
S
R
750 Ω
G
100 Ω LOAD
_
5.11 Ω
V
S
200 Ω
+
1 µF
-V
S
Figure 48.
49.9 Ω
V
S
806 Ω
Figure 50.
V
S
200 Ω
Ferrite Bead
_
+
100 Ω LOAD
1 µF
-V
49.9 Ω
S
V
S
Figure 49.
17
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
R
F
V
S
V
S
806 Ω
5.11 Ω
+
27 pF
_
F
IN
-V
V
S
S
R
FB
G
100 Ω LOAD
_
5.11 Ω
301 Ω
200 Ω
+
66.5 Ω
301 Ω
1 µF
-V
49.9 Ω
S
V
S
V
S
_
5.11 Ω
Figure 51.
+
-V
-V
S
S
Figure 52 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster like when driving large FET transistors.
Figure 53. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
806 Ω
V
S
200 Ω
The THS3110 features a power-down pin (PD) which
lowers the quiescent current from 4.8 mA down to
270 µA, ideal for reducing system power.
_
+
5.11 Ω
24.9 Ω
-V
S
The power-down pin of the amplifier defaults to the
negative supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and are given in the specification tables. Below
the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
806 Ω
V
S
V
S
1 nF
200 Ω
_
+
5.11 Ω
24.9 Ω
-V
S
Figure 52.
Figure 53 shows a push-pull FET driver circuit typical
of ultrsound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 54 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 1870 Ω. Figure 43 shows this circuit
configuration for reference.
18
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
2000
1800
1600
1400
1200
1000
800
Achieving optimum performance with high frequency
amplifier, like the THS3110 and THS3111, requires
careful attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
600
Gain = 2
400
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
R
V
= 1 kΩ
= ±15 V and ±5 V
F
S
200
0
100 k
1 M
10 M
100 M
1 G
f - Frequency - Hz
Figure 54. Power-down Output Impedance vs
Frequency
•
Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
Careful selection and placement of external
components preserve the high frequency per-
formance of the THS3110 and THS3111. Re-
sistors should be a very low reactance type.
Surface-mount resistors work best and allow a
tighter overall layout. Again, keep their leads and
PC board trace length as short as possible.
Never use wirebound type resistors in a high
frequency application. Since the output pin and
inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed
close to the gain-setting resistors. Even with a
low parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or sur-
face-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible, consist-
ent with load driving considerations.
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V-) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage
equal
to
approximately
[(V+ - V-) -0.7 V] × Gain. This also implies that if a
voltage is applied to the output while in power-down
mode, the V- node voltage is equal to
V
O(applied)× RG/(RF + RG). For low gain configurations
and a large applied voltage at the output, the ampli-
fier may actually turn ON due to the aforementioned
behavior.
•
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3110 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage level thresholds that apply to the power-down
pin. The usable range at the REF pin is from VS- to
(VS+ - 4 V)
19
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS3110 and THS3111 are
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase mar-
gin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated trans-
mission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design hand-
book for microstrip and stripline layout tech-
niques). A 50-Ω environment is not necessary
onboard, and in fact, a higher impedance en-
vironment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance based on board material
and trace dimensions, a matching series resistor
into the trace from the output of the THS3110 /
THS3111 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB attenu-
ation of a doubly terminated transmission line is
almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the THS3110 / THS3111 parts directly
onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS3110 and THS3111 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 55(a) and Figure 55(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see Fig-
ure 55(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal per-
formance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS311x have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing oper-
ation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechan-
ical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high speed part like the THS3110
and THS3111 is not recommended. The ad-
ditional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it
DIE
End View (b)
Bottom View (c)
Figure 55. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
•
20
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. There-
fore, the holes under the THS3110 / THS3111
PowerPAD package should make their connec-
tion to the internal ground plane with a complete
connection around the entire circumference of the
plated-through hole.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
0.035
0.040
0.010
vias
Top View
Figure 56. DGN PowerPAD PCB Etch and Via
Pattern
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard sur-
face-mount component. This results in a part that
is properly installed.
PowerPAD™ LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern as shown in
Figure 56. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3110 and THS3111 incorporates automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately 160°C. When the junction
temperature reduces to approximately 140°C, the
amplifier turns on again. But, for maximum perform-
ance and reliability, the designer must take care to
ensure that the design does not exeed a junction
temperature of 125°C. Between 125°C and 150°C,
damage does not occur, but the performance of the
amplifier begins to degrade and long term reliability
suffers. The thermal characteristics of the device are
dictated by the package and the PC board. Maximum
power dissipation for a given package can be calcu-
lated using the following formula.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3110 / THS3111 IC. These additional
vias may be larger than the 10-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS-,
is acceptable as there is no electrical connection
to the silicon.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
21
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
Tmax TA
qJA
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power dissi-
pation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
PDmax
+
where:
P
Dmax
is the maximum power dissipation in the amplifier (W).
T
max
is the absolute maximum junction temperature (°C).
is the ambient temperature (°C).
T
A
θ
= θ + θ
JC CA
JA
θ
is the thermal coeffiecient from the silicon junctions to
DESIGN TOOLS
JC
the case (°C/W).
Evaluation
Fixtures,
Spice
Models,
and
θ
is the thermal coeffiecient from the case to ambient
CA
Application Support
air (°C/W).
Texas Instruments is committed to providing its cus-
tomers with the highest quality of applications sup-
port. To support this goal an evaluation board has
been developed for the THS3110 and THS3111
operational amplifier. The board is easy to use,
allowing for straightforward evaluation of the device.
The evaluation board can be ordered through the
Texas Instruments web site, www.ti.com, or through
your local Texas Instruments sales representative.
For systems where heat dissipation is more critical,
the THS3110 and THS3111 are offered in an 8-pin
MSOP with PowerPAD package offering even better
thermal performance. The thermal coefficient for the
PowerPAD packages are substantially improved over
the traditional SOIC. Maximum power dissipation
levels are depicted in the graph for the available
packages. The data for the PowerPAD packages
assume a board layout that follows the PowerPAD
layout guidelines referenced above and detailed in
the PowerPAD application note (literature number
SLMA002). The following graph also illustrates the
effect of not soldering the PowerPAD to a PCB. The
thermal impedance increases substantially which may
cause serious heat and performance issues. Be sure
to always solder the PowerPAD to the PCB for
optimum performance.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the perform-
ance of analog circuits and systems. This is particu-
larly true for video and RF-amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS3111 is available through the Texas
Instruments web site (www.ti.com). The PIC is also
available for design assistance and detailed product
information. These models do a good job of pre-
dicting small-signal ac and transient performance
under a wide variety of operating conditions. They are
not intended to model the distortion characteristics of
the amplifier, nor do they attempt to distinguish
between the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
4
Τ
J
= 125°C
3.5
3
θ
= 58.4°C/W
JA
2.5
2
θ
= 95°C/W
JA
1.5
1
0.5
0
θ
= 158°C/W
JA
−40
−20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x 3”
θJ = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
A
θJ = 95°C/W for 8-Pin SOIC High−K Test PCB (D)
A
θJ = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
A
Figure 57. Maximum Power Distribution vs
Ambient Temperature
22
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
NOTE: The Edge number for the THS3111 is
6445587.
J2
GND TP2
J1
V +
J7
V −
S
S
FB2
FB1
V +
S
V −
S
+
C4
C2
C3
C5
C1
C6
+
PD
J7
R5
Z1
R4
R6
0 W
TP1
Vs+
R8B
R8A
7
R3
J5
Vin
2
3
8
_
6
−
J6
Vout
+
4
1
R1
R7A
R7B
Z2
Vs −
J4
Vin+
REF
J8
R2
1
Figure 60. THS3110 EVM Board Layout (Bottom
Layer)
Figure 58. THS3110 EVM Circuit Configuration
Figure 59. THS3110 EVM Board Layout (Top
Layer)
23
THS3110, THS3111
www.ti.com
SLOS422A–SEPTEMBER 2003–REVISED NOVEMBER 2003
Table 2. Bill of Materials
THS3110DGN and THS3111DGN EVM
REFERENCE
SMD SIZE
PCB
QTY
MANUFACTURER'S
PART NUMBER(1)
ITEM
DESCRIPTION
DESIGNATOR
1
2
BeadD, Ferrite, 3 A, 80 Ω
1206
D
FB1, FB2
C1, C2
2
2
(Steward) HI1206N800R-00
Cap. 6.8 µF, Tanatalum,
35 V, 10%
(AVX) TAJD685K035R
3
4
Open
0805
0805
0805
0805
0805
1206
1206
1206
2512
3 Pos.
R5, Z1
C3, C4
C5, C6
R6(2)
2
2
2
1
2
2
2
1
2
1
1
Cap. 0.1 µF, Ceramic, X7R, 50 V
Cap. 100 pF, Ceramic, NPO, 100 V
Resistor, 0 Ω, 1/8 W, 1%
Resistor, 750 Ω, 1/8 W, 1%
Open
(AVX) 08055C104KAT2A
(AVX) 08051A101JAT2A
5
6
(Phycomp) 9C08052A0R00JLHFT
(Phycomp) 9C08052A7500FKHFT
7
R3, R4
R7A, Z2
R2, R8A
R1
8
9
Resistor, 49.9 Ω, 1/4 W, 1%
Resistor, 53.6 Ω, 1/4 W, 1%
Open
(Phycomp) 9C12063A49R9FKRFT
(Phycomp) 9C12063A53R6FKRFT
10
11
12
13
R7B, R8B
JP1(2)
Header, 0.1" CTRS, 0.025" SQ pins
Shunts
(Sullins) PZC36SAAN
(Sullins) SSC02SYAN
JP1(2)
Jack, banana receptance, 0.25" dia.
hole
14
J1, J2, J3
3
(SPC) 813
15
16
17
18
19
20
21
22
23
Test point, red
Test point, black
J7(2), J8(2), TP1
TP2
3
1
3
4
4
1
1
1
1
(Keystone) 5000
(Keystone) 5001
Connector, SMA PCB jack
Standoff, 4-40 hex, 0.625" length
Screw, Phillips, 4-40, 0.250"
IC, THS3110
J4, J5, J6
(Amphenol) 901-144-8RFX
(Keystone) 1808
SHR-0440-016-SN
(TI) THS3110DGN
(TI) EDGE # 6445586
(TI) THS3111DGN
(TI) EDGE # 6445587
U1
U1
Board, printed-circuit (THS3110)
IC, THS3111
Board, printed-circuit (THS3111)
(1) The manufacturer's part numbers were used for test purposes only.
(2) Applies to the THS3110DGN EVM only.
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
Current Feedback Analysis and Compensation (SLOA021)
Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
24
THERMAL PAD MECHANICAL DATA
www.ti.com
DGN (S-PDSO-G8)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
5
Exposed Thermal Pad
1,73
MAX
1
4
1,78
MAX
Top View
NOTE: All linear dimensions are in millimeters
PPTD041
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明