THS3115CPWP [TI]
具有关断状态的双路低噪声高输出电流的 110MHz 放大器 | PWP | 14 | 0 to 70;
| 型号： | THS3115CPWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断状态的双路低噪声高输出电流的 110MHz 放大器 | PWP | 14 | 0 to 70 放大器 光电二极管 |
| 文件： | 总37页 (文件大小：2210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS3112
THS3115
www.ti.com
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
LOW-NOISE, HIGH-SPEED, CURRENT FEEDBACK AMPLIFIERS
Check for Samples: THS3112, THS3115
1
FEATURES
APPLICATIONS
•
•
•
•
Communication Equipment
Video Distribution
Motor Drivers
23
•
Low Noise:
–
–
–
2.9-pA/√Hz Noninverting Current Noise
10.8-pA/√Hz Inverting Current Noise
2.2-nV/√Hz Voltage Noise
Piezo Drivers
•
Wide Supply Voltage Range: ±5 V to ± 15 V
Wide Output Swing:
DESCRIPTION
•
The THS3112/5 are low-noise, high-speed current
feedback amplifiers, ideal for any application requiring
high output current. The low noninverting current
noise of 2.9 pA/√Hz and the low inverting current
noise of 10.8 pA/√Hz increase signal-to-noise ratios
for enhanced signal resolution. The THS3112/5 can
operate from ±5-V to ±15-V supply voltages, while
drawing as little as 4.5 mA of supply current per
channel. It offers low –78-dBc total harmonic
distortion driving 2 VPP into a 100-Ω load. The
THS3115 features a low-power shutdown mode,
consuming only 300-mA shutdown quiescent current
per channel. The THS3112/5 are packaged in
standard SOIC, SOIC PowerPAD™, and TSSOP
PowerPAD packages.
–
25-VPP Output Voltage, RL = 100 Ω, ±15-V
Supply
•
•
High Output Current: 150 mA (Min)
High Speed:
–
–
110-MHz (–3-dB BW, G = 1, ±15 V)
1550-V/µs Slew Rate (G = 2, ±15 V)
•
•
Low Distortion (G = 2):
–78 dBc (1 MHz, 2 VPP, 100-Ω Load)
Low-Power Shutdown (THS3115)
–
–
300-µA Shutdown Quiescent Current per
Channel
•
•
Standard SOIC, SOIC PowerPAD™, and
TSSOP PowerPAD Packages
Evaluation Module Available
space
VOLTAGE NOISE AND CURRENT NOISE
vs
FREQUENCY
THS3112
SOIC (D) AND
THS3115
SOIC (D) AND
100
VCC = ±5 V to ±15 V
SOIC PowerPAD™ (DDA) PACKAGE
(TOP VIEW)
TSSOP PowerPAD™ (PWP) PACKAGE
(TOP VIEW)
TA = +25°C
In-
VCC+
1 OUT
1
2
3
4
8
7
6
5
VCC+
1 OUT
1
2
3
4
5
6
7
14
13
1 IN-
2 OUT
2 IN-
2 IN+
1 IN-
2 OUT
In+
10
1 IN+
VCC-
12 2 IN-
11 2 IN+
10 N/C
1 IN+
VCC-
Vn
N/C
REF
N/C
9
8
SHUTDOWN
N/C
1
10
100
1 k
10 k
100 k
f - Frequency - Hz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2010, Texas Instruments Incorporated
THS3112
THS3115
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICE
EVALUATION
TA
SOIC-8
(D)
SOIC-8 PowerPAD
(DDA)
SOIC-14
(D)
TSSOP-14
(PWP)
MODULES
0°C to +70°C
40°C to +85°C
THS3112CD
THS3112ID
THS3112CDDA
THS3112IDDA
THS3115CD
THS3115ID
THS3115CPWP
THS3115IPWP
THS3112EVM
THS3115EVM
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this data sheet
or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature (unless otherwise noted).
UNIT
Supply voltage, VCC+ to VCC–
33 V
±VCC
Input voltage
(2)
Output current (see
)
275 mA
Differential input voltage
±4 V
Maximum junction temperature
+150°C
Total power dissipation at (or below) +25°C free-air temperature
See Dissipation Ratings Table
0°C to +70°C
–40°C to +85°C
–65°C to +125°C
–65°C to +125°C
Commercial
Operating free-air temperature, TA
Industrial
Commercial
Storage temperature, Tstg
Industrial
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3122 and THS3125 may incorporate a PowerPAD™ on the underside of the chip. This pad acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally-enhanced package.
DISSIPATION RATINGS TABLE
TA = +25°C
POWER RATING
PACKAGE
qJA
D-8
DDA
D-14
PWP
95°C/W(1)
67°C/W
66.6°C/W(1)
1.32 W
1.87 W
1.88 W
37.5°C/W
3.3 W
(1) These data were taken using the JEDEC proposed high-K test PCB.
For the JEDEC low-K test PCB, the qJA is 168°C/W for the D-8
package and 122.3°C/W for the D-14 package.
2
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Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): THS3112 THS3115
THS3112
THS3115
www.ti.com
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Dual supply
±5
10
±15
V
Supply voltage, VCC+ to VCC–
Single supply
C-suffix
30
0
+70
°C
Operating free-air temperature, TA
I-suffix
–40
+85
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC = ±15 V
95
110
103
110
25
RL = 100Ω
RF = 1 kΩ, G = 1
Small-signal bandwidth (–3 dB)
RF = 750 Ω, G =
2
BW
RL = 100 Ω
MHz
Bandwidth (0.1 dB)
Slew rate(1), G = 8
Settling time to 0.1%
RF = 750 Ω, G = 2
48
VO= 10 VPP
VO = 5 VPP
1550
820
1300
50
SR
ts
G = 2, RF = 680Ω
V/µs
ns
VO = 2 VPP
VO= 5 VPP
G = –1
63
(1) Slew rate is defined from the 25% to the 75% output levels.
NOISE/DISTORTION PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
–78
UNIT
VO(PP) = 2 V
VO(PP) = 8 V
VO(PP)= 2 V
VO(PP)= 6 V
f = 10 kHz
G = 2, RF = 680 Ω, VCC= ±15 V,
f = 1 MHz
–75
THD
Total harmonic distortion
Input voltage noise
dBc
–76
G = 2, RF = 680 Ω, VCC= ±5 V,
f = 1 MHz
–74
Vn
In
VCC = ±5 V, ±15 V
VCC = ±5 V, ±15 V
2.2
nV/√Hz
pA/√Hz
Noninverting Input
Inverting Input
2.9
Input current noise
Crosstalk
f = 10 kHz
10.8
–67
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
G = 2, f = 1 MHz, VO = 2 VPP
dBc
%
–67
0.01
0.01
0.011
0.011
G = 2, RL = 150 Ω
40 IRE modulation
±100 IRE Ramp
NTSC and PAL
Differential gain error
Differential phase error
degrees
Copyright © 2001–2010, Texas Instruments Incorporated
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THS3112
THS3115
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
DC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
mV
TA = +25°C
6
10
13
3
Input offset voltage
TA = full range
TA = +25°C
VIO
VCC = ±5 V, VCC = ±15 V
1
Channel offset voltage matching
Offset drift
TA = full range
TA = full range
TA = +25°C
4
10
µV/°C
µA
23
30
2
IN- Input bias current
TA = full range
TA = +25°C
IIB
VCC = ±5 V, VCC = ±15 V
0.33
4
IN+ Input bias current
TA = full range
TA = +25°C
3
22
30
IIO
Input offset current
VCC = ±5 V, VCC = ±15 V
VCC = ±5 V, VCC = ±15 V
µA
TA = full range
RL = 1 kΩ
ZOL
Open-loop transimpedance
1
MΩ
INPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
±2.7
MAX
UNIT
VCC = ±5 V
VCC= ±15 V
±2.5
±12.5
56
TA = full
range
VICR
Input common-mode voltage range
V
±12.7
62
TA = +25°C
VCC = ±5 V,
TA = full
range
VI = –2.5 V to 2.5 V
54
63
60
CMRR Common-mode rejection ratio
dB
TA = +25°C
67
VCC = ±15 V,
VI = –12.5 V to 12.5 V
TA = full
range
IN+
IN–
1.5
15
2
MΩ
Ω
RI
CI
Input resistance
Input capacitance
pF
OUTPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
3.9
MAX UNIT
RL = 1 kΩ
RL = 100Ω
RL = 1 kΩ
RL = 100Ω
TA = +25°C
TA = +25°C
3.6
3.4
3.8
G = 4,
G = 4,
VI = 1 V, VCC = ±5 V,
V
TA = full
range
VO
Output voltage swing
TA = +25°C
TA = +25°C
13.5
13.3
12.2
12
VI = 3.4 V, VCC= ±15 V,
V
TA = full
range
G = 4,
VI = 0.9 V, VCC= ±5 V,
VI = 1.7 V, VCC = ±15 V,
RL = 25 Ω
RL = 25 Ω
TA = +25°C
TA = +25°C
100
175
130
270
14
mA
mA
Ω
IO
ro
Output current drive
Output resistance
G = 4,
Open loop
4
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Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): THS3112 THS3115
THS3112
THS3115
www.ti.com
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
POWER SUPPLY
PARAMETER
TEST CONDITIONS
TA = +25°C
MIN
TYP
MAX
5.5
6
UNIT
4.4
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
TA = full range
TA = +25°C
ICC
Quiescent current (per channel)
mA
4.9
60
69
6.5
7.5
TA = full range
TA = +25°C
53
50
60
55
TA = full range
TA = +25°C
PSRR
Power-supply rejection ratio
dB
TA = full range
SHUTDOWN CHARACTERISTICS (THS3115 Only)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCC+ – 4
UNIT
V
VREF
REF pin voltage level
VCC–
Enable
Disable
REF + 0.8
V
VSHDN
SHUTDOWN pin voltage level
Shutdown quiescent current (per channel)
REF + 2
V
ICC(SHDN)
tDIS
REF = 0 V, VCC= ±5 V to ±15 V
VCC= ±15 V
0.3
200
300
0.45
mA
ns
ns
(1)
Disable time
tEN
Enable time(1)
VCC= ±15 V
VCC= ±5 V to ±15 V, VSHDN = 0 V,
REF = 0 V
IIL(SHDN)
IIH(SHDN)
Shutdown pin low level leakage current
18
25
µA
µA
VCC= ±5 V to ±15 V, VSHDN = 3.3 V,
REF = 0 V
Shutdown pin high level leakage current
110
130
(1) Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has
reached half of its final value.
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Figure 1 to Figure 11,
Figure 13, Figure 14
Small-signal closed-loop gain
vs Frequency
Gain and phase
vs Frequency
Figure 12
Small-signal closed-loop noninverting gain
Small-signal closed-loop inverting gain
Small- and large-signal output
vs Frequency
Figure 15, Figure 16
Figure 17, Figure 18
Figure 19, Figure 20
Figure 20,Figure 21
Figure 23, Figure 24
Figure 25
vs Frequency
vs Frequency
vs Frequency
Harmonic distortion
vs Peak-to-peak output voltage
vs Frequency
Vn, In
Voltage noise and current noise
Common-mode rejection ratio
Power-supply rejection ratio
Crosstalk
CMRR
PSRR
vs Frequency
Figure 26
vs Frequency
Figure 27
vs Frequency
Figure 28
zo
Output impedance
vs Frequency
Figure 29
SR
Slew rate
vs Output voltage step
vs Free-air temperature
vs Common-mode input voltage
vs Free-air temperature
vs Output current
vs Output current
vs Supply voltage
Figure 30
Figure 31
VIO
Input offset voltage
Figure 32
IB
Input bias current
Figure 33
VO
Output voltage
Figure 34, Figure 35
Figure 36
Output voltage headroom
Supply current (per channel)
Shutdown response
ICC
Figure 37
Figure 38
Copyright © 2001–2010, Texas Instruments Incorporated
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THS3112
THS3115
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs FREQUENCY
vs FREQUENCY
vs FREQUENCY
3
0
3
0
15
12
9
RF = 560 W
RF = 560 W
RF = 430 W
RF = 560 W
RF = 750 W
RF = 750 W
RF = 1.2 kW
-3
-3
RF = 750 W
RF = 1.2 kW
-6
-6
6
-9
-9
3
-12
-15
-12
-15
0
G = -1
G = -1
G = -4
VCC = ±5 V
RL = 100 W
VCC = ±15 V
RL = 100 W
VCC = ±15 V
RL = 100 W
-3
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 1.
Figure 2.
Figure 3.
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs FREQUENCY
vs FREQUENCY
vs FREQUENCY
15
12
9
21
18
15
12
9
21
18
15
12
9
RF = 200 W
RF = 430 W
RF = 200 W
RF = 430 W
RF = 430 W
RF = 750 W
RF = 560 W
RF = 750 W
RF = 750 W
6
3
6
6
0
G = -4
3
3
G = -8
G = -8
VCC = ±5 V
RL = 100 W
VCC = ±5 V
RL = 100 W
VCC = ±15 V
RL = 100 W
-3
0
0
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 4.
Figure 5.
Figure 6.
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs FREQUENCY
vs FREQUENCY
vs FREQUENCY
2
1
3
0
8
RF = 750 W
RF = 750 W
7
6
5
4
3
2
1
0
RF = 560 W
RF = 750 W
RF = 910 W
0
RF = 1 kW
RF = 1 kW
RF = 1.1 kW
RF = 1.1 kW
-1
-2
-3
-4
-5
-6
-3
-6
-9
-12
G = 1
G = 1
G = 2
VCC = ±5 V
RL = 100 W
VCC = ±15 V
RL = 100 W
VCC = ±5 V
RL = 100 W
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 7.
Figure 8.
Figure 9.
6
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THS3115
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SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
GAIN
GAIN
GAIN AND PHASE
vs FREQUENCY
vs FREQUENCY
vs FREQUENCY
9
6
15
12
9
15
12
9
RF = 430 W
RF = 430 W
RF = 560 W
RF = 560 W
RF = 750 W
RF = 560 W
RF = 750 W
RF = 1 kW
3
RF = 750 W
RF = 1 kW
RF = 1 kW
0
6
6
-3
-6
-9
3
3
0
0
G = 2
G = 4
G = 4
VCC = ±15 V
VCC = ±15 V
RL = 100 W
VCC = ±15 V
RL = 100 W
RL = 100 W
-3
-3
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 10.
Figure 11.
Figure 12.
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
NONINVERTING GAIN vs
FREQUENCY
vs FREQUENCY
vs FREQUENCY
21
21
20
RF = 250 W
RF = 200 W
RF = 200 W
18
15
12
9
18
15
12
9
15
10
5
RF = 750 W
RF = 560 W
RF = 750 W
RF = 430 W
RF = 750 W
RF = 430 W
RF = 1 kW
0
-5
-10
-15
6
6
3
3
G = 8
G = 8
VCC = ±5 V
RL = 100 W
VCC = ±15 V
RL = 100 W
VCC = ±5 V
RL = 100 W
0
0
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 13.
Figure 14.
Figure 15.
SMALL-SIGNAL CLOSED-LOOP
SMALL-SIGNAL CLOSED-LOOP
INVERTING GAIN vs FREQUENCY
SMALL-SIGNAL CLOSED-LOOP
INVERTING GAIN vs FREQUENCY
NONINVERTING GAIN vs
FREQUENCY
21
18
15
12
9
21
18
15
12
9
21
18
15
12
9
RF = 200 W
RF = 430 W
RF = 430 W
RF = 430 W
RF = 560 W
RF = 750 W
RF = 560 W
6
6
6
3
3
3
RF = 1 kW
0
0
0
RF = 750 W
-3
-6
-9
-12
-15
-3
-6
-9
-12
-15
-3
-6
-9
-12
-15
RF = 750 W
VCC = ±5 V
RL = 100 W
VCC = ±5 V
RL = 100 W
VCC = ±15 V
RL = 100 W
10
100
1000
10
100
1000
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
SMALL- AND LARGE-SIGNAL
OUTPUT
SMALL- AND LARGE-SIGNAL
OUTPUT
HARMONIC DISTORTION
vs FREQUENCY
vs FREQUENCY
vs FREQUENCY
18
12
18
12
-20
-40
G = 2
VCC = ±5 V
G = 2
G = 2
Second
4 VPP
4 VPP
VCC = ±15 V
RF = 680 W
RL = 100 W
RF = 680 W
Harmonic
RF = 680 W
RL = 100 W
RL = 100 W
VCC = ±5 V
VO = 2 VPP
2 VPP
2 VPP
6
6
Third Harmonic
1.125 VPP
1.125 VPP
-60
0
0
0.711 VPP
0.711 VPP
Fourth Harmonic
-6
-6
-80
0.4 VPP
0.4 VPP
-12
-18
-24
-12
-18
-24
0.125 VPP
0.125 VPP
-100
-120
Fifth
Harmonic
0.1
1
10
100
0.1
1
10
100
1000
0.1
1
10
100
1000
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 19.
Figure 20.
Figure 21.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs FREQUENCY
vs PEAK-TO-PEAK OUTPUT
VOLTAGE
vs PEAK-TO-PEAK OUTPUT
VOLTAGE
-20
-40
-10
-30
-70
-80
G = 2
G = 2
Second
RF = 680 W
RL = 100 W
VCC = ±15 V
RF = 680 W
RL = 100 W
VCC = ±5 V
f = 1 MHz
Harmonic
Third Harmonic
Second
Harmonic
VO(PP) = 2 V
Third Harmonic
-60
-50
Fifth Harmonic
-90
-80
-70
Third Harmonic
Fourth Harmonic
-100
-110
G = 2
-100
-120
-90
RF = 680 W
RL = 100 W
VCC = ±15 V
f = 1 MHz
Fifth Harmonic
Second
Fourth Harmonic
Fifth
Harmonic
Harmonic
Fourth Harmonic
-110
0.1
1
10
100
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
f - Frequency - MHz
VPP - Peak-to-Peak Output Voltage - V
V
PP - Peak-to-Peak Output Voltage - V
Figure 22.
Figure 23.
Figure 24.
VOLTAGE NOISE AND CURRENT
NOISE
POWER-SUPPLY REJECTION
RATIO
COMMON-MODE REJECTION RATIO
vs FREQUENCY
vs FREQUENCY
vs FREQUENCY
100
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
VCC = ±5 V to ±15 V
TA = +25°C
G = 2
G = 2
RL = 100 W
RL = 100 W
RF = 680 W
RF = 1 kW
VCC = ±15 V
PSRR- = ±15 V
In-
In+
VCC = ±5 V
10
PSRR- = ±5 V
Vn
1
10
100
1 k
10 k
100 k
f - Frequency - Hz
0.1
1
10
100
0.1
1
10
100
f - Frequency - MHz
f - Frequency - MHz
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT IMPEDANCE
CROSSTALK
vs
SLEW RATE
vs FREQUENCY
FREQUENCY
vs OUTPUT VOLTAGE STEP
0
100
1800
1600
1400
1200
1000
800
600
400
200
0
G = 2
G = 2
VCC = ±5 V to ±15 V
RF = 1 kW
VCC = ±5 V to ±15 V
RF = 680 W
RL = 100 W
TA = +25°C
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
RL = 100 W
RF = 680 W
10
VCC = ±15 V
1
VCC = ±5 V
0.1
0.01
0.1
1
10
100
1000
0
2
4
6
8
10
12
0.1
1
10
100
1000
f - Frequency - MHz
VO - Output Voltage Step - V
f - Frequency - MHz
Figure 28.
Figure 29.
Figure 30.
INPUT OFFSET VOLTAGE
vs COMMON-MODE INPUT
VOLTAGE
INPUT OFFSET VOLTAGE
vs FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs FREE-AIR TEMPERATURE
10
0
-1
-2
-3
-4
-5
-6
9
8
7
6
5
4
3
2
1
VCC = ±15 V
VCC = ±15 V
TA = +25°C
RL = 100 W
VCM = 0 V
RL = 100 W
VCC = ±15 V, IIB-
5
0
-5
-10
-15
VCC = ±5 V, IIB+
VCC = ±5 V, IIB-
VCC = ±15 V, IIB+
0
-15
-10
-5
0
5
10
15
-40
-20
0
20
40
60
80 85
-40
-20
0
20
40
60
80 85
VCM - Common-Mode Input Voltage - V
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 31.
Figure 32.
Figure 33.
OUTPUT VOLTAGE
vs OUTPUT CURRENT
OUTPUT VOLTAGE
vs OUTPUT CURRENT
OUTPUT VOLTAGE HEADROOM
vs OUTPUT CURRENT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
15.0
14.5
14.0
13.5
13.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
|VCC| - |VO
|
VCC = ±15 V and ±5 V
TA = +25°C
G = 4
RF = 750 W
VCC = ±5 V
RF = 750 W
TA = +25°C
VCC = ±15 V
RF = 750 W
TA = +25°C
0
50
100
150
200
250
0
50
100
150
200
250
0
50
100
150
200
250
IO - Output Current - |mA|
IO - Output Current - mA
IO - Output Current - mA
Figure 34.
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT (PER CHANNEL)
vs SUPPLY VOLTAGE
SHUTDOWN RESPONSE
5
4
3
2
1
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
VCC = ±15 V
G = 8
RF = 330 W
TA = +85°C
RL = 100 W
VI = 0.5 VDC
TA = +25°C
TA = -40°C
2.0
1.5
1.0
0.5
0
2
3
4
5
6
7
8
9
10 11 12 13 14 15
4
5
7
0
1
2
3
6
8
9
10
t - Time - ms
VCC - Supply Voltage - ±V
Figure 37.
Figure 38.
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APPLICATION INFORMATION
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain setting
resistors RF and RG at different gains to give
maximum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
Maximum Slew Rate for Repetitive Signals
The THS3115 and THS3112 are recommended for
high slew rate pulsed applications where the internal
nodes of the amplifier have time to stabilize between
pulses. It is recommended to have at least a 20-ns
delay between pulses.
The THS3115 and THS3112 are not recommended
for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/µs. Using the
part in these applications results in excessive current
draw from the power supply and possible device
damage.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3115 and THS3112 RF and RG VALUES FOR MINIMAL
PEAKING WITH RL = 50 Ω, ±5-V to ±15-V POWER SUPPLY
For applications with high slew rate, repetitive signals,
the THS3091 and THS3095 (single versions), or
THS3092 and THS3096 (dual versions) are
recommended.
GAIN (V/V)
RG (Ω)
—
RF (Ω)
1 k
1
2
750
187
28.7
750
140
53.6
750
560
200
750
560
430
4
Wideband, Noninverting Operation
8
The THS3115 and THS3112 are unity gain stable
100-MHz current-feedback operational amplifiers,
designed to operate from a ±5-V to ±15-V power
supply.
–1
–4
–8
Figure 39 shows the THS3115 in a noninverting gain
of 2-V/V configuration used to generate the typical
characteristic curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance and with measurement equipment that
presents a 50-Ω load impedance.
Wideband, Inverting Operation
Figure 40 shows the THS3115 in a typical inverting
gain configuration designed for 50-Ω input/output.
+15 V
+VS
+15 V
+VS
+
6.8 mF
0.1 mF
49.9 W
+
6.8 mF
0.1 mF
49.9 W
50-W Source
THS3115
750 W
VI
RG
50-W Source
50-W Load
750 W
THS3115
750 W
49.9 W
VI
50-W Load
RF
53.6 W
RM
RF
+
-VS
750 W
6.8 mF
0.1 mF
-15 V
RG
+
-VS
6.8 mF
0.1 mF
-15 V
Figure 40. Wideband, Inverting Gain
Configuration
Figure 39. Wideband, Noninverting Gain
Configuration
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Single-Supply Operation
750 W
750 W
The THS3115 and THS3112 have the capability to
operate from a single supply voltage ranging from 10
V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits in Figure 41 show inverting and noninverting
amplifiers configured for single-supply operation.
+15 V
75-W Transmission Line
VO(1)
75 W
VI
75 W
n lines
75 W
75 W
-15 V
VO(n)
75 W
+VS
50-W Source
Figure 42. Video Distribution Amplifier
Application
VI
49.9 W
THS3115
RT
49.9 W
50-W Load
RF
750 W
Driving Capacitive Loads
+VS/2
Applications such as FET drivers and line drivers can
be highly capacitive and cause stability problems for
high-speed amplifiers.
RG
750 W
Figure 43 through Figure 49 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier feedback path. See Figure 43 for
recommended resistor values versus capacitive load.
RF
750 W
+VS/2
+VS
RG
50-W Source
750 W
VI
49.9 W
THS3115
53.6 W
RT
60
50
40
30
20
10
0
50-W Load
+VS/2
+VS/2
Figure 41. DC-Coupled, Single-Supply Operation
Video Distribution
The wide bandwidth, high slew rate, and high output
drive current of the THS3115 and THS3112 match
the demands for video distribution to deliver video
signals down multiple cables. To ensure high signal
quality with minimal degradation of performance, a
0.1-dB gain flatness should be at least 7x the
passband frequency to minimize group delay
variations from the amplifier. A high slew rate
minimizes distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality. Figure 42 illustrates a typical video
distribution amplifier application configuration.
10
100
C
L - Capacitive Load (pF)
Figure 43. Recommended RISO vs Capacitive
Load
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Placing a small series resistor, RISO, between the
amplifier output and the capacitive load, as shown in
Figure 44, is an easy way of isolating the load
capacitance.
Figure 46 shows another method used to maintain
the low-frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 47 gives similar
results with reduced dc offset and low frequency
noise.
RF
+VS
RG
RISO
100-W Load
5.11 W
1 mF
RF
-VS
49.9 W
+VS
27 pF
+VS
RG
750 W
100-W Load
5.11 W
Figure 44. Resistor to Isolate Capacitive Load
RIN
Using a ferrite chip in place of RISO, as Figure 45
shows, is another approach of isolating the output of
the amplifier. The ferrite impedance characteristic
versus frequency is useful to maintain the low
frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ω to 50 Ω, at 100 MHz and low
impedance at dc.
1 mF
-VS
49.9 W
+VS
Figure 46. Feedback Technique with Input
Resistor for Capacitive Load
RF
RF
+VS
27 pF
RG
Ferrite
100-W Load
+VS
Bead
Ferrite
RG
Bead
100-W Load
5.11 W
FIN
1 mF
-VS
1 mF
+VS
49.9 W
-VS
49.9 W
+VS
Figure 45. Ferrite Bead to Isolate Capacitive Load
Figure 47. Feedback Technique with Input Ferrite
Bead for Capacitive Load
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Figure 48 shows a configuration that uses two
amplifiers in parallel to double the output drive current
to larger capacitive loads. This technique is used
when more output current is needed to charge and
discharge the load faster as when driving large FET
transistors.
Saving Power with Shutdown Functionality
and Setting Threshold Levels with the
Reference Pin
The
THS3115
features
a
shutdown
pin
(SHUTDOWN) that lowers the quiescent current from
4.9 mA/amp down to 300 µA/amp, ideal for reducing
system power.
RF
The shutdown pin of the amplifier defaults to the REF
pin voltage in the absence of an applied voltage,
putting the amplifier in the normal on mode of
operation. To turn off the amplifier in an effort to
conserve power, the shutdown pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down (or shutdown) are relative
to the supply rails and are given in the Shutdown
Characteristics table. Below the Enable threshold
voltage, the device is on. Above the Disable threshold
voltage, the device is off. Behavior between these
threshold voltages is not specified.
+VS
RG
5.11 W
24.9 W
-VS
RF
49.9 W
RG
+VS
1 nF
+VS
RG
5.11 W
Note that this shutdown functionality is self-defining:
the amplifier consumes less power in shutdown
mode. The shutdown mode is not intended to provide
24.9 W
-VS
a
high-impedance output. In other words, the
shutdown functionality is not intended to allow use as
a 3-state bus driver. When in shutdown mode, the
impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 48. Parallel Amplifiers for Higher Output
Drive
Figure 49 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in shutdown mode. Most notably is the fact that
the amplifier actually turns on if there is a ±0.7 V or
greater difference between the two input nodes (IN+
and IN–) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage equal to approximately [(IN+ – IN–) – 0.7V] ×
Gain. Also, if a voltage is applied to the output while
in shutdown mode, the IN– node voltage is equal to
VO(applied) × RG/(RF + RG) . For low gain configurations
and a large applied voltage at the output, the
amplifier may actually turn on because of the
behavior described here.
+VS
+VS
5.11 W
-VS
RF
RF
2RG
+VS
5.11 W
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
-VS
-VS
Figure 49. PowerFET Drive Circuit
space
space
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Power-Down Reference Pin Operation
Printed-Circuit Board Layout Techniques for
Optimal Performance
In addition to the shutdown pin, the THS3115
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the SHUTDOWN pin. In most
split-supply applications, the reference pin is
connected to ground. In either case, the user needs
to be aware of voltage-level thresholds that apply to
the shutdown pin. Table 2 shows examples and
illustrate the relationship between the reference
voltage and the shutdown thresholds. In the table, the
threshold levels are derived by the following
equations:
Achieving optimum performance with high-frequency
amplifiers such as the THS3115 and THS3112
requires careful attention to board layout parasitic and
external component types. Recommendations that
optimize performance include:
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance,
a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
SHUTDOWN ≤ REF + 0.8 V for enable
SHUTDOWN ≥ REF + 2V for disable
•
Minimize the distance [0.25 inch, (6,4 mm)] from
the power-supply pins to high-frequency 0.1-µF
and 100-pF decoupling capacitors. At the device
pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to
minimize inductance between the pins and the
Where the usable range at the REF pin is:
VCC– ≤ VREF ≤ (VCC+ – 4V)
The recommended mode of operation is to tie the
REF pin to midrail, therefore setting the
enable/disable thresholds to V(midrail) + 0.8 V and
V(midrail) = 2 V, respectively.
decoupling
capacitors.
The
power-supply
connections should always be decoupled with
these capacitors. Larger (6.8 µF or more)
tantalum decoupling capacitors, effective at lower
frequencies, should also be used on the main
supply pins. These capacitors may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the printed circuit board (PCB).
Table 2. Shutdown Threshold Voltage Levels
REFERENCE
SUPPLY
PIN
ENABLE
DISABLE
VOLTAGE (V) VOLTAGE (V)
LEVEL (V)
LEVEL (V)
±15, ±5
±15
±15
±5
0
0.8
2.8
2.0
4.0
0
2.0
–2.0
1.0
–1.2
1.8
•
Careful selection and placement of external
3.0
1.0
17
components
preserve
the
high-frequency
±5
–1.0
15.0
5.0
–0.2
15.8
5.8
performance of the THS3115 and THS3112.
Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a
tighter overall layout. Again, keep the leads and
PCB trace length as short as possible. Never use
wirebound type resistors in a high-frequency
application. Because the output pin and inverting
input pins are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the
gain-setting resistors. Even with a low parasitic
capacitance that shunts the external resistors,
excessively high resistor values can create
significant time constants that can degrade
+30
+10
7.0
Note that if the REF pin is left unterminated, it floats
to the positive rail and falls outside of the
recommended operating range given above VCC–
≤
VREF ≤ (VCC+ – 4V). As a result, it no longer serves as
a reliable reference for the SHUTDOWN pin, and the
enable/disable thresholds given above no longer
apply. If the SHUTDOWN pin is also left
unterminated, it floats to the positive rail and the
device is disabled. If balanced, split supplies are used
(±VCC) and the REF and SHUTDOWN pins are
grounded, the device is enabled.
space
space
space
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values
greater than 2.0 kΩ, this parasitic capacitance can
add a pole and/or a zero that can affect circuit
operation. Keep resistor values as low as
possible,
consistent
with
load
driving
considerations.
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•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces [0.05 inch (1,3 mm) to 0.1
inch (2,54 mm)] should be used, preferably with
ground and power planes opened up around
them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (less
than 4 pF) may not need an RS because the
•
Socketing a high-speed device such as the
THS3115 and THS3112 is not recommended. The
additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the THS3115/THS3112 amplifiers
directly onto the board.
PowerPAD™ Design Considerations
The THS3115 and THS3112 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 50(a) and Figure 50(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 50(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS311x have no electrical
connection between the PowerPAD and the die.
THS3115
and
THS3112
are
nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (thus
increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrinsic
to
a
doubly-terminated transmission line is
matched-impedance
acceptable, implement
a
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50-Ω
environment is not necessary onboard, and in
fact, a higher impedance environment improves
distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance
based on board material and trace dimensions, a
matching series resistor into the trace from the
output of the THS3115/THS3112 is used as well
as a terminating shunt resistor at the input of the
destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective
impedance should be set to match the trace
DIE
(a) Side View
Thermal
Pad
DIE
(b) End View
(c) Bottom View
Figure 50. Views of Thermally-Enhanced Package
impedance. If the 6-dB attenuation of
a
is
be
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
doubly-terminated
unacceptable,
transmission
long trace
line
can
a
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
configuration does not preserve signal integrity as
well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation as a result of the
voltage divider formed by the series output into
the terminating impedance.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
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PowerPAD™ Layout Considerations
transfer. Therefore, the holes under the
THS3115/THS3112 PowerPAD package should
make the connection to the internal ground plane
with a complete connection around the entire
circumference of the plated-through hole.
0.205
(5,21)
0.060
0.017
(1,52)
(0,432)
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
0.013
(0,33)
Pin 1
0.075
(1,91)
0.094
(2,39)
0.030
(0,76)
0.025
(0,64)
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
0.040
(1,01)
0.010
(0,254)
vias
0.035
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This procedure results
in a part that is properly installed.
(0,89)
Top View
Dimensions are in inches (millimeters).
Figure 51. DGN PowerPAD PCB Etch and Via
Pattern
Power Dissipation and Thermal
Considerations
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
The THS3115 and THS3112 incorporate automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately +160°C. When the junction
temperature reduces to approximately +140°C, the
amplifier turns on again. However, for maximum
performance and reliability, the designer must take
care to ensure that the design does not exceed a
junction temperature of +125°C. Between +125°C
and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade and
1. PCB with a top side etch pattern as shown in
Figure 51.
2. Place five holes in the area of the thermal pad.
These holes should be 0.01 inch (0,254 mm) in
diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These vias help dissipate the heat
generated by the THS3115/THS3112 IC. These
additional vias may be larger than the 0.01-inch
(0,254-mm) diameter vias directly under the
thermal pad. They can be larger because they
are not in the thermal pad area to be soldered so
that wicking is not a problem.
long-term
reliability
suffers.
The
thermal
characteristics of the device are dictated by the
package and the PCB. Maximum power dissipation
for a given package can be calculated using the
following formula.
Tmax - TA
PDMax
=
qJA
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage, such as VS–,
is acceptable as there is no electrical connection
to the silicon.
where:
•
PDMax is the maximum power dissipation in the
amplifier (W)
•
Tmax is the absolute maximum junction
temperature (°C)
•
TA is the ambient temperature (°C)
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application; however, low thermal
resistance is desired for the most efficient heat
qJA = qJC + qCA
where:
•
qJC is the thermal coefficient from the silicon
junctions to the case (°C/W)
•
qCA is the thermal coefficient from the case to
ambient air (°C/W)
Copyright © 2001–2010, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): THS3112 THS3115
THS3112
THS3115
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
www.ti.com
For systems where heat dissipation is more critical,
the THS3115 and THS3112 are also available in an
8-pin MSOP with PowerPAD package that offers
even better thermal performance. The thermal
coefficient for the PowerPAD packages are
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in
Figure 52 for the available packages. The data for the
PowerPAD packages assume a board layout that
follows the PowerPAD layout guidelines discussed
above and detailed in the PowerPAD application note
(literature number SLMA002). Figure 52 also
illustrates the effect of not soldering the PowerPAD to
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TJ = +125°C
q
= 58.4°C/W
JA
q
= 95°C/W
JA
q
= 158°C/W
JA
-40
-20
0
20
40
60
80
100
a
PCB. The thermal impedance increases
T
A - Free-Air Temperature (°C)
substantially, which may cause serious heat and
performance issues. Always solder the PowerPAD to
the PCB for optimum performance.
Results shown are with no air flow and PCB size of 3 in × 3 in
(76,2 mm × 76,2 mm).
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this type of dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
•
qJA = 58.4°C/W for 8-pin MSOP with PowerPAD (DGN
package)
•
•
qJA = 95°C/W for 8-pin SOIC High-K test PCB (D package)
qJA = 158°C/W for 8-pin MSOP with PowerPAD without solder
Figure 52. Maximum Power Dissipation vs
Ambient Temperature
18
Submit Documentation Feedback
Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): THS3112 THS3115
THS3112
THS3115
www.ti.com
SLOS385C –SEPTEMBER 2001–REVISED SEPTEMBER 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October, 2009) to Revision C
Page
•
•
•
•
•
Corrected pin designations for TSSOP pinout drawing ........................................................................................................ 1
Deleted Shutdown pin input levels parameters from Recommended Operating Conditions table ....................................... 3
Added VREF parameter to Shutdown Characteristics table ................................................................................................... 5
Added VSHDN parameter to Shutdown Characteristics table ................................................................................................. 5
Changed reference to GND pin to "REF" in Shutdown quiescent current parameter test conditions in Shutdown
Characteristics table ............................................................................................................................................................. 5
•
•
•
•
Added REF = 0 V to test conditions for IIL(SHDN) parameter in Shutdown Characteristics table ........................................... 5
Added REF = 0 V to test conditions for IIH(SHDN) parameter in Shutdown Characteristics table ........................................... 5
Revised Saving Power with Shutdown Functionality and Setting Threshold Levels with the Reference Pin section ........ 14
Updated Power-Down Reference Pin Operation section; changed references to VS–, VS+ to VCC–, VCC+ .......................... 15
Changes from Revision A (January, 2009) to Revision B
Page
•
•
•
Updated document format to conform to current standards ................................................................................................. 1
Deleted lead temperature specification from Absolute Maximum Ratings table .................................................................. 2
Added Application Information section ............................................................................................................................... 11
Copyright © 2001–2010, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): THS3112 THS3115
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS3112CD
THS3112CDDA
THS3112CDR
THS3112ID
ACTIVE
SOIC
D
8
8
75
75
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
3112C
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
ACTIVE SO PowerPAD
DDA
D
SN
3112C
ACTIVE
ACTIVE
SOIC
SOIC
8
2500 RoHS & Green
NIPDAU
NIPDAU
SN
0 to 70
3112C
D
8
75
75
RoHS & Green
RoHS & Green
-40 to 85
-40 to 85
-40 to 85
0 to 70
3112I
THS3112IDDA
THS3112IDDAR
THS3115CPWP
THS3115CPWPR
THS3115ID
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
PWP
PWP
D
8
3112I
8
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
SN
3112I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
SOIC
14
14
14
14
14
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
HS3115C
HS3115C
THS3115I
HS3115I
HS3115I
0 to 70
50
90
RoHS & Green
RoHS & Green
-40 to 85
-40 to 85
-40 to 85
THS3115IPWP
THS3115IPWPR
HTSSOP
HTSSOP
PWP
PWP
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS3112CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
THS3112IDDAR
SO
DDA
PowerPAD
THS3115CPWPR
THS3115IPWPR
HTSSOP PWP
HTSSOP PWP
14
14
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS3112CDR
THS3112IDDAR
THS3115CPWPR
THS3115IPWPR
SOIC
SO PowerPAD
HTSSOP
D
8
8
2500
2500
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
DDA
PWP
PWP
14
14
HTSSOP
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
THS3112CD
THS3112CDDA
THS3112ID
D
SOIC
HSOIC
SOIC
8
8
75
75
75
75
90
50
90
505.46
505.46
505.46
505.46
530
6.76
6.76
6.76
6.76
10.2
6.76
10.2
3810
3810
3810
3810
3600
3810
3600
4
4
DDA
D
8
4
THS3112IDDA
THS3115CPWP
THS3115ID
DDA
PWP
D
HSOIC
HTSSOP
SOIC
8
4
14
14
14
3.5
4
505.46
530
THS3115IPWP
PWP
HTSSOP
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
PACKAGE OUTLINE
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
12X 0.65
14
1
2X
5.1
4.9
3.9
NOTE 3
7
8
0.30
14X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X (0.6)
NOTE 5
2X (0.4)
NOTE 5
THERMAL
PAD
7
8
0.25
1.2 MAX
GAGE PLANE
2.59
1.89
15
0.15
0.05
0.75
0.50
0 -8
A
20
1
14
DETAIL A
TYPICAL
2.6
1.9
4229706/A 06/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.6)
METAL COVERED
BY SOLDER MASK
SYMM
14X (1.5)
(1.2) TYP
14
14X (0.45)
1
(5)
NOTE 9
(R0.05) TYP
SYMM
(0.6)
15
(2.59)
12X (0.65)
7
8
(
0.2) TYP
VIA
SEE DETAILS
(1.1) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4229706/A 06/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0014K
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.6)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
14X (1.5)
14X (0.45)
14
1
(R0.05) TYP
(2.59)
SYMM
15
BASED ON
0.125 THICK
STENCIL
12X (0.65)
7
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 12X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 2.90
2.60 X 2.59 (SHOWN)
2.37 X 2.36
0.125
0.15
0.175
2.20 X 2.19
4229706/A 06/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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