THS4012DGN [TI]
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS; 290 - MHz的低失真高速放大器
| 型号： | THS4012DGN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS |
| 文件： | 总30页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
THS4011
JG, D AND DGN PACKAGE
(TOP VIEW)
THS4012
Very High Speed
– 290 MHz Bandwidth (G = 1, –3 dB)
– 310 V/µs Slew Rate
†
D AND DGN PACKAGE
(TOP VIEW)
– 37 ns Settling Time (0.1%)
1OUT
1IN–
1IN+
V
CC+
NULL
IN–
NULL
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2OUT
2IN–
2IN+
V
Very Low Distortion
– THD = –80 dBc (f = 1 MHz, R = 150 Ω)
CC+
IN+
OUT
NC
L
–V
CC
V
110 mA Output Current Drive (Typical)
CC–
7.5 nV/√Hz Voltage Noise
NC – No internal connection
Excellent Video Performance
– 70 MHz Bandwidth (0.1 dB, G = 1)
– 0.006% Differential Gain Error
– 0.01° Differential Phase Error
Cross Section View Showing
PowerPAD Option (DGN)
†
This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
±5 V to ±15 V Supply Voltage
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Packages
THS4011
FK PACKAGE
(TOP VIEW)
Evaluation Module Available
description
The THS4011 and THS4012 are very high speed,
single/dual, voltage feedback amplifiers ideal for
a wide range of applications. The devices offer
very good ac performance with 290-MHz
bandwidth, 310-V/µs slew rate, and 37-ns settling
time (0.1%). These amplifiers have a high output
drive capability of 110 mA and draw only 7.8-mA
supply current per channel. For applications
requiring low distortion, the THS4011/12 operate
with a total harmonic distortion (THD) of –80 dBc
at f = 1 MHz. For video applications, the
THS4011/12 offer 0.1 dB gain flatness to 70-MHz,
0.006% differential gain error, and 0.01°
differential phase error.
3
2
1
20 19
NC
V
NC
IN–
NC
IN+
NC
4
5
6
7
8
18
17
16
15
14
CC+
NC
OUT
NC
9
10 11 12 13
RELATED DEVICES
DESCRIPTION
DEVICE
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
CAUTION: THE THS4011 AND THS4012 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
DISTORTION
vs
FREQUENCY
–40
V
R
G = 2
= ± 15 V
= 150 Ω
CC
L
–50
–60
–70
–80
2nd Harmonic
–90
–100
–110
3rd Harmonic
100k
1M
10M
f – Frequency – Hz
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
SMALL
OUTLINE
(D)
NUMBER OF
CHANNELS
MSOP
SYMBOL
EVALUATION
MODULE
PLASTIC
MSOP
(DGN)
CERAMIC
CHIP
CARRIER
(FK)
T
A
†
DIP
(JG)
†
1
2
1
2
THS4011CD
THS4012CD
THS4011ID
THS4012ID
THS4011CDGN
—
—
—
—
—
—
—
—
TIACM
TIABD
TIACN
TIABZ
THS4011EVM
0°C to
70°C
‡
THS4012CDGN
THS4012EVM
THS4011IDGN
—
—
–40°C to
85°C
‡
THS4012IDGN
–55°C to
125°C
1
—
—
THS4011MJG
THS4011MFK
—
—
†
‡
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
functional block diagram
Null
1
2
8
–
IN–
IN+
6
OUT
3
+
Figure 1. THS4011 – Single Channel
V
CC
8
2
3
1IN–
1IN+
–
1
7
1OUT
2OUT
+
6
5
2IN–
2IN+
–
+
4
–V
CC
Figure 2. THS4012 – Dual Channel
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
I
CC
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
O
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
ID
J
A
Operating free-air temperature, T , THS401xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
THS401xI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
THS4011M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds, D, DGN package . . . . . . . . . . . . . . . 300°C
Lead temperature, 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
θ
θ
T = 25°C
A
JA
(°C/W)
JC
PACKAGE
(°C/W)
38.3
4.7
POWER RATING
†
167
D
740 mW
‡
DGN
JG
58.4
119
2.14 W
28
1050 mW
1375 mW
FK
87.7
20
†
‡
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θ is 95°C/W with a power rating at T = 25°C of 1.32 W.
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
JA
A
PC. For further information, refer to Application Information section of this data sheet.
recommended operating conditions
MIN NOM
MAX
±16
32
UNIT
Split supply
Single supply
C suffix
±4.5
9
Supply voltage, V
V
CC
0
70
Operating free-air temperature, T
I suffix
–40
–55
85
°C
A
M suffix
125
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics, V
dynamic performance
= ±15 V, R = 150 Ω, T = 25°C, (unless otherwise noted)
CC
L
A
THS4011C/I,
THS4012C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
290
270
70
MAX
V
= ±15 V
= ±5 V
= ±15 V
= ±5 V
CC
CC
CC
CC
Unity-gain bandwidth (–3 dB)
Gain = 1
MHz
MHz
MHz
V/µs
ns
V
V
V
V
V
V
V
V
V
V
V
BW
SR
Bandwidth for 0.1 dB flatness
Gain = 1
35
V
V
= ±15 V,
= ±5 V,
R
R
= 150 Ω
= 150 Ω,
= 20 V,
= 5 V,
4.9
16
CC
L
L
O(PP)
O(PP)
Full power bandwidth (see Note 2)
Slew rate
CC
= ±15 V
310
260
37
CC
CC
CC
CC
CC
CC
Gain = –1,
R
L
= 150 Ω
= ±5 V
= ±15 V
= ±5 V
= ±15 V
= ±5 V
Settling time to 0.1%
Settling time to 0.01%
V = –2.5 V to 2.5 V, Gain = –1
I
35
t
s
90
V = –2.5 V to 2.5 V, Gain = –1
I
ns
70
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
noise/distortion performance
THS4011C/I,
THS4012C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V
V
= ±15 V,
f = 1 MHz,
c
CC
THD
Total harmonic distortion
–80
dBc
= 2 V
O(PP)
V
Input voltage noise
Input current noise
V
= ±5 V or ±15 V,
= ±5 V or ±15 V,
f = 10 kHz
f = 10 kHz
7.5
1
nV/√Hz
pA/√Hz
n
CC
CC
I
n
V
Gain = 2,
= 150 Ω,
NTSC
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
0.01%
0.01%
0.01°
Differential gain error
R
L
Gain = 2,
Differential phase error
R
NTSC
= 150 Ω,
L
0.001°
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
dc performance
THS4011C/I,
THS4012C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V
= ±15 V,
= ±10 V,
= 1 kΩ
T
= 25°C
10
8
25
CC
A
V/mV
V
R
O
T
A
= full range
= 25°C
L
Open loop gain
V
= ±5 V,
= ±2.5 V,
= 250 Ω
T
A
7
12
1
CC
V/mV
mV
V
O
T
A
= full range
5
R
L
T
A
= 25°C
6
8
V
Input offset voltage
Input offset voltage drift
Input bias current
V
CC
= ±5 V or ±15 V
= ±5 V or ±15 V
IO
T
A
= full range
15 µV/°C
T
A
= 25°C
2
25
6
I
I
V
CC
µA
8
IB
T
A
= full range
= 25°C
T
A
250
Input offset current
Offset current drift
V
V
= ±5 V or ±15 V
= ±5 V or ±15 V
nA
IO
CC
T
A
= full range
400
0.3
nA/°C
CC
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
input characteristics
THS4011C/I,
THS4012C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V
V
= ±15 V
= ±5 V
±13 ±14.1
CC
V
Common-mode input voltage range
V
ICR
±3.8
82
±4.3
CC
T = 25°C
A
110
dB
dB
V
V
= ±15 V,
= ±12 V
CC
IC
T
= full range
T = 25°C
A
77
A
CMRR Common-mode rejection ratio
90
95
V
V
= ±5 V,
= ±2.5 V
CC
IC
dB
T
A
= full range
83
R
C
Input resistance
2
MΩ
I
I
Input capacitance
1.2
pF
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
output characteristics
THS4011C/I,
THS4012C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
±13.5
±3.7
±13
±3.4
110
MAX
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
±13
±3.4
±12
±3
R
= 1 kΩ
L
V
O
Output voltage swing
V
R
R
= 250 Ω
= 150 Ω
L
L
V
V
= ±15 V
= ±5 V
70
CC
I
I
Output current
R
= 20 Ω,
mA
O
L
50
75
CC
Short-circuit output current
Output resistance
V
CC
= ±15 V
150
12
mA
OS
R
Open loop
Ω
O
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
power supply
THS4011C/I,
THS4012C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
±16.5
33
Dual supply
±4.5
V
CC
Supply voltage
V
Single supply
9
T
= 25°C
7.8
6.9
83
9.5
A
V
CC
V
CC
V
CC
= ±15 V
T
A
= full range
= 25°C
11
I
Supply current (each amplifier)
Power supply rejection ratio
mA
dB
CC
T
A
8.5
= ±5 V
T
A
= full range
= 25°C
10
T
A
75
68
PSRR
= ±5 V to ±15 V
T
A
= full range
†
Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics, V
dynamic performance
PARAMETER
= ±15 V, R = 150 Ω, T = 25°C, (unless otherwise noted)
CC
L
A
THS4011M
†
UNIT
TEST CONDITIONS
MIN
*160
TYP
200
70
MAX
Unity-gain bandwidth
Closed loop,
Gain = 1
R
= 1 kΩ
V
= ±15 V
= ±15 V
= ±5 V
MHz
L
CC
V
V
V
V
V
CC
Bandwidth for 0.1 dB flatness
BW
35
MHz
CC
= ±2.5 V
30
CC
V
CC
V
CC
V
CC
= ±15 V,
= ±5 V,
R
R
R
= 150 Ω,
= 150 Ω,
= 1 kΩ
= 20 V
= 20 V
2.5
8
L
L
L
O(PP)
O(PP)
Full power bandwidth (see Note 1)
Slew rate
MHz
V/µs
ns
SR
= ±15 V,
*300
400
37
V
V
V
V
= ±15 V
CC
CC
CC
CC
Settling time to 0.1%
V = –2.5 V to 2.5 V, Gain = –1
I
= ±5 V
35
t
s
= ±15 V
= ±5 V
90
Settling time to 0.01%
V = –2.5 V to 2.5 V, Gain = –1
ns
I
70
†
Full range = –55°C to 125°C for the M suffix.
*This parameter is not tested.
NOTE 1: Full pwer bandwidth = slew rate/2π V
.
(PP)
noise/distortion performance
THS4011M
TYP
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
V
V
= ±15 V,
f = 1 MHz,
c
CC
THD
Total harmonic distortion
–80
dBc
= 1 V
O(PP)
V
Input voltage noise
Input current noise
V
= ±5 V or ±15 V,
= ±5 V or ±15 V,
f = 10 kHz
f = 10 kHz
7.5
1
nV/√Hz
pA/√Hz
n
CC
CC
I
n
V
Gain = 2,
= 150 Ω,
NTSC
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
0.006
0.001
0.01°
Differential gain error
%
R
L
Gain = 2,
R
NTSC
= 150 Ω,
Differential phase error
L
0.002°
†
Full range = –55°C to 125°C for the M suffix.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at T = full range, V
A
= ±15 V, R = 1 kΩ (unless otherwise noted)
CC
L
(continued)
dc performance
THS4011M
†
PARAMETER
UNIT
V/mV
V/mV
TEST CONDITIONS
MIN
TYP
MAX
V
R
= ±15 V,
= 1 kΩ
V
= ±10 V,
= ±2.5 V,
CC
L
O
O
T
= full range
= full range
6
14
A
Open loop gain
V
R
= ±5 V,
= 1 kΩ
V
CC
T
A
5
10
L
T
= 25°C
2
2
6
8
A
V
Input offset voltage
Input offset voltage drift
Input bias current
V
V
V
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
mV
µV/°C
µA
IO
CC
CC
CC
T
A
= full range
15
2
T
A
= 25°C
6
8
I
I
IB
T
A
= full range
4
Input offset current
Offset current drift
V
V
= ±5 V or ±15 V
= ±5 V or ±15 V
25
0.3
250
nA
IO
CC
T
A
= 25°C
nA/°C
CC
†
Full range = –55°C to 125°C for the M suffix.
input characteristics
THS4011M
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
= ±15 V
±13 ±14.1
V
Common-mode input voltage range
ICR
= ±5 V
±3.8
75
±4.3
90
95
2
= ±15 V,
= ±5 V,
V
V
= ±12 V
= ±2.5 V
IC
CMRR Common-mode rejection ratio
dB
84
IC
R
C
Input resistance
MΩ
I
I
Input capacitance
1.2
pF
†
Full range = –55°C to 125°C for the M suffix.
output characteristics
THS4011M
TYP
±13.5
±3.7
±13
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
±13
±3.4
±12
±3
MAX
V
V
V
V
V
V
V
= ±15 V
= ±5 V
CC
CC
CC
CC
CC
CC
CC
R
= 1 kΩ
L
V
Output voltage swing
O
= ±15 V
= ±5 V
R
R
= 250 Ω
= 150 Ω
L
L
±3.4
115
= ±15 V
= ±5 V
70
I
I
Output current
R
= 20 Ω
= 25°C
mA
O
L
50
75
Short-circuit output current
Output resistance
= ±15 V
T
A
150
mA
OS
R
Open loop
12
Ω
O
†
Full range = –55°C to 125°C for the M suffix.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at T = full range, V
A
= ±15 V, R = 1 kΩ (unless otherwise noted)
CC
L
(continued)
power supply
PARAMETER
THS4011M
†
UNIT
TEST CONDITIONS
MIN
±4.5
9
TYP
MAX
±16.5
33
Dual supply
Single supply
V
CC
Supply voltage
V
T
= 25°C
7.8
6.9
9.5
A
V
CC
V
CC
V
CC
= ±15 V
T
A
= full range
= 25°C
11
I
Quiescent current
mA
dB
CC
T
A
8.5
= ±5 V
T
A
= full range
= 25°C
10
T
A
80
78
86
83
PSRR
Power supply rejection ratio
= ±5 V to ±15 V
T
A
= full range
†
Full range = –55°C to 125°C for the M suffix.
PARAMETER MEASUREMENT INFORMATION
1.5 kΩ
1.5 kΩ
1.5 kΩ
1.5 kΩ
_
_
+
V
O1
V
O2
V
I1
V
I2
+
CH1
CH2
150 Ω
150 Ω
50 Ω
50 Ω
Figure 3. THS4012 Crosstalk Test Circuit
10
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TYPICAL CHARACTERISTICS
OUPUT VOLTAGE
vs
SUPPLY VOLTAGE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
14
12
3
1.4
T
= 25° C
A
V
= ±15 V
V
= ±15 V or ±5 V
CC
CC
1.2
1
2.5
R
= 1 kΩ
L
10
8
2
R
= 150 Ω
L
0.8
0.6
1.5
6
1
0.4
0.2
0
4
2
0.5
0
5
7
9
11
13
15
–40 –20
0
20
40
60
80 100
–40 –20
0
20
40
60
80 100
± V – Supply Voltage – V
CC
T
– Free-Air Temperature –
C
A
T
– Free-AIR Temperature – C
A
Figure 4
Figure 5
Figure 6
MAXIMUM OUTPUT VOLTAGE SWING
vs
COMMON-MODE INPUT VOLTAGE
PSRR
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
FREQUENCY
14
100
90
15
13
V
= ±15 V or ±5 V
CC
T
= 25° C
A
13.5
13
V
= ± 15 V
CC
= 1 kΩ
R
80
L
70
60
12.5
12
11
9
V
R
= ± 15 V
= 250 Ω
CC
L
50
40
4.5
4
V
R
= ± 5 V
CC
= 1 kΩ
L
7
30
20
3.5
V
R
= ± 5 V
5
3
CC
3
= 150 Ω
10
0
L
2.5
–40 –20
0
20
40
60
80 100
5
7
9
11
13
15
1k
10k
100k
1M
10M
100M
T
– Free-Air Temperature – C
± V
– Supply Voltage – V
f – Frequency – Hz
A
CC
Figure 7
Figure 8
Figure 9
CMRR
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
OPEN-LOOP GAIN RESPONSE
100
80
0
120
V
± 15V
CC
V
± 5V
V
± 15V
CC
CC
–10
100
–20
–30
V
± 5V
60
40
20
0
CC
80
60
40
V
± 15V
CC
–40
–50
V = CH2
I
V
= CH1
O
–60
–70
V = CH1
I
V
= CH2
O
20
0
–80
–90
–20
1k
1k
10k
100k
1M
10M
100M
100k
1M
10M
100M
1G
10K 100K 1M
10M 100M 1G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 10
Figure 11
Figure 12
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TYPICAL CHARACTERISTICS
DISTORTION
vs
DISTORTION
vs
DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
–40
–50
–40
–50
–40
–50
V
R
G = 2
= ± 15 V
V
R
G = 2
= ± 5 V
V
= ± 15 V
CC
R = 150 Ω
L
CC
= 1 kΩ
CC
= 1 kΩ
L
L
G = 2
–60
–70
–80
–60
–70
–80
–60
–70
–80
2nd Harmonic
2nd Harmonic
2nd Harmonic
–90
–100
–110
–90
–100
–110
–90
–100
–110
3rd Harmonic
3rd Harmonic
3rd Harmonic
100k
1M
10M
100k
1M
10M
100k
1M
10M
f – Frequency – Hz
Figure 13
f – Frequency – Hz
Figure 14
f – Frequency – Hz
Figure 15
DISTORTION
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
5
0
5
–40
–50
R = 270 Ω
f
R = 270 Ω
f
V
R
G = 2
= ± 5 V
CC
= 150 Ω
L
0
R = 100 Ω
f
R = 100 Ω
f
–60
–70
–80
–5
2nd Harmonic
–5
–10
–15
–10
–15
–90
–100
–110
3rd Harmonic
V
R
G = 1
= ± 15 V
= 150 Ω
V
R
G = 1
= ± 5 V
CC
= 150 Ω
L
CC
L
–20
–25
–20
100k
1M
10M
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
f – Frequency – Hz
Figure 16
f – Frequency – Hz
f – Frequency – Hz
Figure 17
Figure 18
NOISE SPECTRAL DENSITY
DIFFERENTIAL PHASE
vs
vs
FREQUENCY
NUMBER OF 150-Ω LOADS
0.35°
0.3°
0.25°
0.2°
0.15°
0.1°
0.05°
0°
100
Gain = 2
V
= ± 15 V
CC
R
= 1 kΩ
F
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
10
V
= ± 5 V
CC
V
= ±15 V or ±5 V
CC
1
10
100
1k
10k
100k
1
2
3
4
f – Frequency – Hz
Number of 150-Ω Loads
Figure 19
Figure 20
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TYPICAL CHARACTERISTICS
DIFFERENTIAL PHASE
vs
DIFFERENTIAL GAIN
vs
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
0.4°
0.35°
0.3°
0.06
0.05
0.05
0.04
0.03
Gain = 2
Gain = 2
Gain = 2
R
= 1 kΩ
R
= 1 kΩ
R = 1 kΩ
F
F
F
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.04
0.03
0.25°
0.2°
V
= ± 15 V
CC
V
= ± 15 V
0.02
0.01
CC
0.15°
0.1°
V = ± 15 V
CC
0.02
0.01
V
= ± 5 V
CC
V
= ± 5 V
CC
0.05°
0°
V
2
= ± 5 V
CC
0
0
1
2
3
4
1
3
4
1
2
3
4
Number of 150-Ω Loads
Number of 150-Ω Loads
Number of 150-Ω Loads
Figure 21
Figure 22
Figure 23
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APPLICATION INFORMATION
theory of operation
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
f s of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
T
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
(7) V
+
CC
(6) OUT
IN– (2)
IN+ (3)
(4) V
–
CC
NULL (1)
NULL (8)
Figure 24. THS4011 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
•
•
•
•
e = Amplifier internal voltage noise (nV/√Hz)
n
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
e
= Thermal voltage noise associated with each resistor (e = 4 kTR )
Rx x
Rx
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
e
Rs
e
n
R
Noiseless
S
+
_
e
ni
e
no
IN+
IN–
e
Rf
R
F
e
Rg
R
G
Figure 25. Noise Model
The total equivalent input noise density (e ) is calculated by using the following equation:
ni
2
2
2
e
e
IN
R
IN–
R
R
4 kTR
4 kT R
R
n
s
ni
S
F
G
F
G
Where:
–23
k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
R || R = Parallel resistance of R and R
F
G
F
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the
ni
overall amplifier gain (A ).
V
R
R
F
e
e
A
e
1
(noninverting case)
no
ni
ni
V
G
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel
G
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares
S
n
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier
Circuits Applications Report (literature number SLVA043).
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
2
e
ni
NF
10log
2
e
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
2
2
e
IN
R
n
S
NF
10log 1
4 kTR
S
Figure 26 shows the noise figure graph for the THS401x.
NOISE FIGURE
vs
SOURCE RESISTANCE
30
f = 10 kHz
T
A
= 25°C
25
20
15
10
5
0
10
100
1 k
10 k
100 k
Source Resistance – Ω
Figure 26. Noise Figure vs Source Resistance
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APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS401x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1.3 kΩ
1.3 kΩ
_
Input
20 Ω
Output
LOAD
THS401x
+
C
Figure 27. Driving a Capacitive Load
offset nulling
The THS401x has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4011. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This
is shown in Figure 28.
V
CC
+
0.1 µF
+
_
THS4011
10 kΩ
0.1 µF
V
CC
–
Figure 28. Offset Nulling Schematic
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APPLICATION INFORMATION
offset voltage
Theoutputoffsetvoltage,(V )isthesumoftheinputoffsetvoltage(V )andbothinputbiascurrents(I )times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB–
R
G
+
–
+
V
I
V
O
R
S
I
IB+
R
R
R
R
F
F
V
V
1
I
R
1
I
R
OO
IO
IB
S
IB–
F
G
G
Figure 29. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS401x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
fortheG=+1configuration. Foroptimumsettlingtimeandminimumringing, afeedback resistorof 100Ω should
be used as shown in Figure 30. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS401x
_
100 Ω
Figure 30. Noninverting, Unity Gain Schematic
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APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer
(see Figure 31).
R
R
F
G
–
V
1
O
+
V
I
R1
V
C1
f
–3dB
2 R1C1
R
O
F
1
1
V
R
1
sR1C1
I
G
Figure 31. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
–3dB
2 RC
C2
R
F
1
R
=
G
R
F
2 –
)
(
R
Q
G
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
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APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS401x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS401x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductancein the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mountcomponents, theproblemwithstrayseriesinductanceisgreatlyreduced. Second, thesmall
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
20
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 33. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 34. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 34. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additionalvias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Webconnectionshaveahighthermalresistanceconnectionthatisusefulforslowingtheheat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS401xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
21
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ , is about 58.4 C/W. For comparison, the non-PowerPAD version of
JA
the THS401x IC (SOIC) is shown. For a given θ , the maximum power dissipation is shown in Figure 35 and
JA
is calculated by the following formula:
T
–T
MAX
A
P
D
JA
Where:
P
= Maximum power dissipation of THS401x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
DGN Package
= 58.4°C/W
T
= 150°C
J
θ
JA
2 oz. Trace And Copper Pad
With Solder
3
DGN Package
= 158°C/W
2 oz. Trace And
Copper Pad
2.5
2
θ
JA
SOIC Package
High-K Test PCB
θ
= 98°C/W
JA
Without Solder
1.5
1
SOIC Package
Low-K Test PCB
0.5
0
θ
= 167°C/W
JA
–40
–20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
22
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially muti-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. When using V
= ±5 V, there is
CC
generally not a heat problem, even with SOIC packages. But, when using V
= ±15 V, the SOIC package is
CC
severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how
the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But,
the device should always be soldered to a copper plane to fully use the heat dissipation properties of the
PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As
more trace and copper area is placed around the device, θ decreases and the heat dissipation capability
JA
increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier
package (THS4012), the sum of the RMS output currents and voltages should be used to choose the proper
package.
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
100
10
200
T
T
A
= 150°C
= 50°C
J
Maximum Output
Current Limit Line
V
= ± 5 V
= 150°C
= 50°C
V
= ± 15 V
CC
CC
T
T
A
180
160
140
120
100
j
Maximum Output
Current Limit Line
DGN Package
= 58.4°C/W
θ
JA
Package With
θ
< = 120°C/W
JA
SO-8 Package
= 167°C/W
80
60
40
θ
SO-8 Package
= 98°C/W
JA
Low-K Test PCB
θ
JA
High-K Test PCB
SO-8 Package
= 167°C/W
Safe Operating
Area
θ
JA
Low-K Test PCB
Safe Operating
Area
20
0
0
3
6
9
12
15
0
1
2
3
4
5
| V | – RMS Output Voltage – V
O
| V | – RMS Output Voltage – V
O
Figure 36
Figure 37
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4012
THS4012
MAXIMUM RMS OUTPUT CURRENT
MAXIMUM RMS OUTPUT CURRENT
vs
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
100
200
Maximum Output
Current Limit Line
Package With
≤ 60°C/W
V
T
= ± 15 V
Maximum Output
Current Limit Line
CC
= 150°C
θ
JA
180
160
140
120
100
J
T
= 50°C
A
Both Channels
SO-8 Package
= 167°C/W
SO-8 Package
= 98°C/W
θ
80
60
40
JA
Low-K Test PCB
θ
10
JA
High-K Test PCB
Safe Operating Area
= ± 5 V
DGN Package
= 58.4°C/W
V
CC
= 150°C
SO-8 Package
SO-8 Package
= 98°C/W
θ
JA
T
J
θ
= 167°C/W
θ
JA
Low-K Test PCB
JA
High-K Test PCB
20
0
T = 50°C
A
Safe Operating Area
Both Channels
4
1
0
3
6
9
12
15
0
1
2
3
5
| V | – RMS Output Voltage – V
O
| V | – RMS Output Voltage – V
O
Figure 38
Figure 39
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
evaluation board
AnevaluationboardisavailablefortheTHS4011(literaturenumberSLOP128)andTHS4012(literaturenumber
SLOP230). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry
has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For
moreinformation, pleaserefertotheTHS4011EVMUser’sGuide(literaturenumberSLOU028)ortheTHS4012
EVM User’s Guide (literature number SLOU041) To order the evaluation board contact your local TI sales office
or distributor.
V
CC
+
+
C1
C2
6.8 µF
0.1 µF
R1
1 kΩ
NULL
R2
49.9 Ω
IN+
+
_
R3
49.9 Ω
OUT
THS4011
NULL
R5
C3
1 kΩ
6.8 µF
+
C4
0.1 µF
IN–
V
CC
–
R4
49.9 Ω
Figure 40. THS4011 Evaluation Board
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
A MIN
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
M
0,25
8
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073271/A 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
18 17 16 15 14 13 12
TERMINALS
MIN
MAX
MIN
MAX
**
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
21
22
23
24
25
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
B SQ
A SQ
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
CERAMIC DUAL-IN-LINE PACKAGE
JG (R-GDIP-T8)
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.063 (1,60)
0.015 (0,38)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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