THS4051MFKB [TI]
70MHz 高速放大器 | FK | 20 | -55 to 125;
| 型号： | THS4051MFKB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 70MHz 高速放大器 | FK | 20 | -55 to 125 放大器 运算放大器 放大器电路 |
| 文件： | 总30页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
THS4051
D, DGN, AND JG PACKAGE
(TOP VIEW)
High Speed
– 70 MHz Bandwidth (G = 1, –3 dB)
– 240 V/µs Slew Rate
– 60-ns Settling Time (0.1%)
NULL
IN–
NULL
1
2
3
4
8
7
6
5
V
High Output Drive, I = 100 mA (typ)
O
CC+
IN+
OUT
NC
Excellent Video Performance
– 0.1 dB Bandwidth of 30 MHz (G = 1)
– 0.01% Differential Gain
V
CC–
NC – No internal connection
– 0.01° Differential Phase
Very Low Distortion
– THD = –82 dBc (f = 1 MHz, R = 150 Ω)
– THD = –89 dBc (f = 1 MHz, R = 1 kΩ)
THS4052
†
D AND DGN PACKAGE
L
L
(TOP VIEW)
Wide Range of Power Supplies
1OUT
1IN–
1IN+
V
CC+
1
2
3
4
8
7
6
5
– V
= ±5 V to ±15 V
CC
2OUT
2IN–
2IN+
Available in Standard SOIC, MSOP
PowerPAD , JG or FK Package
–V
CC
Evaluation Module Available
description
Cross Section View Showing
PowerPAD Option (DGN)
The THS4051 and THS4052 are general-pur-
pose, single/dual, high-speed voltage feedback
amplifiers ideal for a wide range of applications
including video, communication, and imaging.
The devices offer very good ac performance with
70-MHz bandwidth, 240-V/µs slew rate, and
60-ns settling time (0.1%). The THS4051/2 are
stable at all gains for both inverting and non-
inverting configurations. These amplifiers have a
high output drive capability of 100 mA and draw
only 8.5-mA supply current per channel. Excellent
professional video results can be obtained with
the low differential gain/phase errors of 0.01%/
0.01° and wide 0.1 dB flatness to 30 MHz. For
applications requiring low distortion, the
THS4051/2 is ideally suited with total harmonic
distortion of –82 dBc at 1 MHz.
†
This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
THS4051
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
NC
IN–
NC
IN+
NC
NC
V
4
5
6
7
8
18
17
16
15
14
CC+
NC
OUT
NC
9
10 11 12 13
RELATED DEVICES
DEVICE
DESCRIPTION
THS4011/2 290-MHz Low Distortion High-Speed Amplifiers
THS4031/2 100-MHz Low Noise High-Speed Amplifiers
THS4081/2 175-MHz Low Power High-Speed Amplifiers
CAUTION: The THS4051 and THS4052 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
–40
–50
–60
–70
–80
–90
–100
V
= ± 15 V
CC
Gain = 2
= 2 V
V
O(PP)
R
= 150 Ω
L
R
= 1 kΩ
L
100k
1M
10M 20M
f - Frequency - Hz
AVAILABLE OPTIONS
PACKAGED DEVICES
NUMBER
OF
CHANNELS
†
PLASTIC
SMALL
OUTLINE
(D)
PLASTIC MSOP
(DGN)
EVALUATION
MODULE
CHIP
CARRIER
(FK)
T
A
CERAMIC DIP
(JG)
†
SYMBOL
DEVICE
THS4051CDGN
1
2
1
2
THS4051CD
THS4052CD
THS4051ID
THS4052ID
ACQ
ACE
ACR
ACF
—
—
—
—
—
—
—
—
THS4051EVM
0°C to 70°C
‡
THS4052CDGN
THS4052EVM
THS4051IDGN
—
—
–40°C to 85°C
–55°C to 125°C
‡
THS4052IDGN
1
—
—
—
THS4051MJG
THS4051MFK
—
†
‡
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4051CDGN).
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
functional block diagram
V
CC
1IN–
1IN+
1OUT
2OUT
Null
2IN–
2IN+
1
2
8
IN–
6
OUT
3
IN+
–V
CC
Figure 2. THS4052 – Dual Channel
Figure 1. THS4051 – Single Channel
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
I
CC
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
O
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V
IO
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
θ
θ
T = 25°C
A
JA
(°C/W)
JC
PACKAGE
(°C/W)
38.3
4.7
POWER RATING
‡
167
D
740 mW
§
DGN
JG
58.4
119
2.14 W
28
1050 mW
1375 mW
FK
87.7
20
‡
§
ThisdatawastakenusingtheJEDECstandardLow-KtestPCB. FortheJEDECProposedHigh-K
test PCB, the θ is 95°C/W with a power rating at T = 25°C of 1.32 W.
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC.
JA
A
For further information, refer to Application Information section of this data sheet.
recommended operating conditions
MIN NOM
MAX
±16
32
UNIT
Dual supply
Single supply
C-suffix
±4.5
9
Supply voltage, V
and V
CC–
V
CC+
0
70
Operating free-air temperature, T
I-suffix
–40
–55
85
°C
A
M-suffix
125
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at T = 25°C, V
= ±15 V, R = 150 Ω (unless otherwise noted)
A
CC
L
dynamic performance
THS405xC, THS405xI
†
PARAMETER
UNIT
MHz
MHz
MHz
MHz
V/µs
ns
TEST CONDITIONS
MIN
TYP
70
MAX
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= ±15 V
= ±5 V
= ±15 V
= ±5 V
= ±15 V
= ±5 V
CC
Gain = 1
Gain = 2
Gain = 1
70
Dynamic performance small-signal bandwidth
(–3 dB)
CC
38
CC
38
CC
BW
30
CC
Bandwidth for 0.1 dB flatness
30
CC
= 20 V,
= 5 V,
V
V
= ±15 V
= ±5 V
3.8
12.7
240
200
60
O(pp)
O(pp)
CC
§
Full power bandwidth
CC
= ±15 V,
= ±5 V,
= ±15 V,
= ±5 V,
= ±15 V,
= ±5 V,
20-V step,
5-V step
5-V step
2-V step
5-V step
2-V step
Gain = 5
CC
CC
CC
CC
CC
CC
‡
SR
Slew rate
Gain = –1
Settling time to 0.1%
Settling time to 0.01%
Gain = –1
Gain = –1
60
t
s
130
140
ns
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
‡
§
Slew rate is measured from an output level range of 25% to 75%.
Full power bandwidth = slew rate/2 πV
O(Peak)
.
noise/distortion performance
THS405xC, THS405xI
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
–82
MAX
R
R
R
R
= 150 Ω
= 1 kΩ
L
L
L
L
V
= ±15 V
= ±5 V
CC
CC
–89
V
O(pp)
= 2 V,
THD
Total harmonic distortion
dBc
f = 1 MHz, Gain = 2
= 150 Ω
= 1 kΩ
–78
V
–87
V
Input voltage noise
Input current noise
V
V
= ±5 V or ±15 V,
= ±5 V or ±15 V,
f = 10 kHz
f = 10 kHz
14
nV/√Hz
pA/√Hz
n
CC
I
n
0.9
CC
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
0.01%
0.01%
0.01°
0.03°
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp
Differential gain error
Differential phase error
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp
Channel-to-channel crosstalk
(THS4052 only)
V
CC
= ±5 V or ±15 V,
f = 1 MHz
–57
dB
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
dc performance
THS405xC, THS405xI
†
PARAMETER
UNIT
V/mV
V/mV
TEST CONDITIONS
MIN
5
TYP
MAX
T
= 25°C
9
A
V
V
= ±15 V, R = 1 kΩ
V
= ±10 V
CC
L
O
O
T
A
= full range
= 25°C
3
Open loop gain
T
A
2.5
2
6
= ±5 V, R = 250 Ω
V
= ±2.5 V
CC
L
T
A
= full range
= 25°C
T
A
2.5
10
12
V
OS
Input offset voltage
Offset voltage drift
Input bias current
V
CC
V
CC
V
CC
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
mV
µV/°C
µA
T
A
= full range
= full range
= 25°C
T
A
15
T
A
2.5
6
8
I
I
IB
T
A
= full range
= 25°C
T
A
35
250
400
Input offset current
Offset current drift
V
CC
= ±5 V or ±15 V
nA
OS
T
A
= full range
T
A
= full range
0.3
nA/°C
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
input characteristics
THS405xC, THS405xI
MIN TYP MAX
±13.8 ±14.3
†
PARAMETER
UNIT
V
TEST CONDITIONS
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
V
Common-mode input voltage range
ICR
±3.8
70
±4.3
100
100
1
= ±15 V,
= ±5 V,
V
V
= ±12 V
= ±2.5 V
ICR
CMRR Common mode rejection ratio
T
A
= full range
dB
70
ICR
r
Input resistance
MΩ
i
C
Input capacitance
1.5
pF
i
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
output characteristics
THS405xC, THS405xI
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
±11.5
±3.2
TYP
±13
MAX
V
V
V
V
V
V
V
= ±15 V
= ±5 V
R
R
= 250 Ω
= 150 Ω
CC
CC
CC
CC
CC
CC
CC
L
L
±3.5
V
I
Output voltage swing
O
= ±15 V
= ±5 V
±13 ±13.6
R
R
= 1 kΩ
= 20 Ω
V
L
L
±3.5
80
±3.8
100
75
= ±15 V
= ±5 V
‡
mA
Output current
O
50
‡
I
= ±15 V
150
13
mA
Short-circuit current
Output resistance
SC
R
Open loop
Ω
O
†
‡
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
power supply
THS405xC, THS405xI
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
±4.5
9
TYP
MAX
±16.5
33
Dual supply
V
Supply voltage operating range
Supply current (per amplifier)
V
CC
Single supply
T
= 25°C
8.5
7.5
84
10.5
11.5
9.5
A
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
T
A
= full range
= 25°C
I
mA
dB
CC
T
A
T
A
= full range
= 25°C
10.5
T
A
70
68
PSRR Power supply rejection ratio
= ±5 V or ±15 V
T
A
= full range
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
electrical characteristics at T = full range, V
A
= ±15 V, R = 1 kΩ (unless otherwise noted)
CC
L
dynamic performance
THS4051M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
70
MAX
§
Unity gain bandwidth
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= ±15 V,
= ±15 V
= ±5 V
Closed loop
R
= 1 kΩ
L
50
MHz
CC
70
CC
Gain = 1
Gain = 2
Gain = 1
70
Dynamic performance small-signal bandwidth
(–3 dB)
CC
MHz
= ±15 V
= ±5 V
38
CC
BW
SR
38
CC
= ±15 V
= ±5 V
30
CC
Bandwidth for 0.1 dB flatness
MHz
MHz
V/µs
ns
30
CC
= 20 V,
= 5 V,
V
V
= ±15 V
= ±5 V
3.8
12.7
300
200
60
O(pp)
O(pp)
CC
‡
Full power bandwidth
CC
§
= ±15 V,
= ±5 V,
= ±15 V,
= ±5 V,
= ±15 V,
= ±5 V,
R
= 1 kΩ
L
240
CC
CC
CC
CC
CC
CC
Slew rate
5-V step
5-V step
2-V step
5-V step
2-V step
Gain = –1
Settling time to 0.1%
Settling time to 0.01%
Gain = –1
60
t
s
130
140
Gain = –1
ns
†
Full range = –55°C to 125°C for the THS4051M.
‡
§
Full power bandwidth = slew rate/2 πV
This parameter is not tested.
.
O(Peak)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at T = full range, V
A
= ±15 V, R = 1 kΩ (unless otherwise noted)
CC
L
noise/distortion performance
THS4051M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
–82
–89
–78
–87
MAX
R
R
R
R
= 150 Ω
= 1 kΩ
L
L
L
L
V
= ±15 V
= ±5 V
CC
CC
V
= 2 V,
O(pp)
f = 1 MHz, Gain = 2,
= 25°C
THD
Total harmonic distortion
dBc
= 150 Ω
= 1 kΩ
T
A
V
V
T
A
= ±5 V or ±15 V,
f = 10 kHz,
f = 10 kHz,
CC
= 25°C
V
Input voltage noise
Input current noise
R
R
= 150 Ω
= 150 Ω
14
nV/√Hz
pA/√Hz
n
L
L
V
T
A
= ±5 V or ±15 V,
CC
= 25°C
I
n
0.9
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp,
R = 150 Ω
L
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
0.01%
0.01%
0.01°
Differential gain error
Differential phase error
T
A
= 25°C,
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp,
R = 150 Ω
L
0.03°
T
A
= 25°C,
†
Full range = –55°C to 125°C for the THS4051M.
dc performance
THS4051M
†
PARAMETER
UNIT
V/mV
V/mV
TEST CONDITIONS
MIN
5
TYP
MAX
T
= 25°C
9
A
V
V
= ±15 V, V = ±10 V
O
CC
T
A
= full range
= 25°C
3
Open loop gain
T
A
2.5
2
6
= ±5 V, V = ±2.5 V
CC
O
T
A
= full range
= 25°C
T
A
2.5
10
13
V
IO
Input offset voltage
Offset voltage drift
Input bias current
V
CC
V
CC
V
CC
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
mV
µV/°C
µA
T
A
= full range
= full range
= 25°C
T
A
15
T
A
2.5
6
8
I
I
IB
T
A
= full range
= 25°C
T
A
35
250
400
Input offset current
Offset current drift
V
CC
= ±5 V or ±15 V
nA
IO
T
A
= full range
T
A
= full range
0.3
nA/°C
†
Full range = –55°C to 125°C for the THS4051M.
input characteristics
THS4051M
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
±13.8 ±14.3
V
Common-mode input voltage range
ICR
±3.8
70
±4.3
100
100
1
= ±15 V,
= ±5 V,
V
V
= ±12 V
= ±2.5 V
ICR
CMRR Common mode rejection ratio
T
A
= full range
dB
70
ICR
r
Input resistance
MΩ
i
C
Input capacitance
1.5
pF
i
†
Full range = –55°C to 125°C for the THS4051M.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at T = full range, V
A
= ±15 V, R = 1 kΩ (unless otherwise noted)
CC
L
(continued)
output characteristics
PARAMETER
THS4051M
†
UNIT
V
TEST CONDITIONS
MIN
±12
TYP
±13
MAX
V
V
V
V
V
= ±15 V
= ±5 V
R
R
= 250 Ω
= 150 Ω
CC
CC
CC
CC
CC
L
L
±3.2
±3.5
V
O
Output voltage swing
= ±15 V
= ±5 V
±13 ±13.6
R
= 1 kΩ
V
L
±3.5
±3.8
= ±15 V,
= 25°C
80
100
T
A
‡
I
V
T
A
= ±15 V,
= full range
R
= 20 Ω
mA
Output current
O
CC
L
70
50
V
= ±5 V
75
150
13
CC
CC
‡
I
V
= ±15 V
mA
Short-circuit current
SC
R
Output resistance
Open loop
Ω
O
†
‡
Full range = –55°C to 125°C for the THS4051M.
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
power supply
THS4051M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
±16.5
33
Dual supply
±4.5
V
Supply voltage operating range
Supply current (per amplifier)
V
CC
Single supply
9
T
= 25°C
8.5
7.5
84
10.5
11.5
9.5
A
V
= ±15 V
= ±5 V
CC
T
A
= full range
= 25°C
I
mA
dB
CC
T
A
V
V
CC
T
A
= full range
= full range
10.5
PSRR Power supply rejection ratio
= ±5 V or ±15 V
T
A
70
CC
†
Full range = –55°C to 125°C for the THS4051M.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
OUTPUT VOLTAGE
vs
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
2.8
2.7
2.6
2.5
2.4
2.3
2.2
14
12
10
8
T
=25°C
A
V
= ± 5 V & ±15 V
CC
V
= ± 5 V
CC
R
= 1 kΩ
L
R
= 150 Ω
L
6
V
= ± 15 V
CC
4
2
–40 –20
0
20
40
60
80 100
–40 –20
0
20
40
60
80 100
5
7
9
11
13
15
T
- Free-Air Temperature - °C
T
- Free-Air Temperature - °C
±V - Supply Voltage - V
CC
A
A
Figure 3
Figure 4
Figure 5
COMMON-MODE INPUT VOLTAGE
SUPPLY CURRENT
vs
OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
SUPPLY VOLTAGE
14
13.5
13
15
13
11
9
11
10
9
T
=25°C
A
T
T
=85°C
=25°C
A
A
V
R
= ± 15 V
V
R
= ± 15 V
= 250 Ω
CC
= 1 kΩ
CC
L
12.5
12
L
8
V
R
= ± 5 V
CC
= 1 kΩ
4.5
4
L
7
7
T
=–40°C
A
3.5
5
6
V
R
= ± 5 V
= 150 Ω
CC
L
3
2.5
3
5
–40 –20
0
20
40
60
80 100
5
7
9
11
13
15
5
7
9
11
13
15
±V
- Supply Voltage - V
T
– Free-Air Temperature –
C
± V - Supply Voltage - V
CC
CC
A
Figure 6
Figure 7
Figure 8
POWER SUPPLY REJECTION
VOLTAGE & CURRENT NOISE
CMRR
vs
RATIO
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
–20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1000
100
10
V
R
V
= ±15 V or ±5 V
= 1 kΩ
CC
F
V
T
A
= ± 15 V and ± 5V
= 25°C
CC
V
= ±15 V & ±5 V
CC
–30
–40
= 2 V
I(PP)
–V
CC
V
N
–50
–60
–70
+V
CC
I
N
–80
–90
1
–100
0.10
10k
100k
1M
10M
100M
10
100
1k
10k
100k
100k
1M
10M
100M
f - Frequency - Hz
f - Frequency - Hz
f – Frequency – Hz
Figure 9
Figure 10
Figure 11
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
OPEN LOOP GAIN AND
PHASE RESPONSE
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
–20
–30
100
80
60
40
20
0
30
V
= ± 15 V
CC
Gain = 2
V
= ± 5 V & ±15 V
CC
0
R
R
= 3.6 kΩ
= 150 Ω
F
L
Gain
–40
–50
–60
–30
–60
–90
–120
–150
Phase
–70
–80
–20
100k
1M
10M
100M
100k
1M
10M
100M
f – Frequency – Hz
f - Frequency - Hz
Figure 12
Figure 13
TOTAL HARMONIC DISTORTION
DISTORTION
vs
DISTORTION
vs
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
FREQUENCY
–50
–50
–40
–50
–60
–70
–80
–90
–100
V
R
= ± 15 V
= 1 kΩ
V
R
= ± 15 V
CC
V
= ± 15 V
CC
L
CC
Gain = 2
= 2 V
= 150 Ω
L
–55
–60
–55
–60
G = 5
f = 1 MHz
G = 5
f = 1 MHz
V
O(PP)
–66
–70
–75
–66
–70
–75
2nd Harmonic
R
= 150 Ω
L
2nd Harmonic
3rd Harmonic
–80
–85
–90
–80
–85
–90
R
= 1 kΩ
L
3rd Harmonic
15
0
0
5
10
15
20
5
10
20
100k
1M
10M 20M
f - Frequency - Hz
V
– Output Voltage – V
V
– Output Voltage – V
O
O
Figure 14
Figure 15
Figure 16
DISTORTION
vs
DISTORTION
vs
DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
–40
–40
–40
V
R
G = 2
V
= ± 15 V
CC
= 1 kΩ
V
R
G = 2
V
= ± 5 V
= 1 kΩ
V
R
G = 2
V
= ± 15 V
= 150 Ω
CC
L
CC
L
L
–50
–60
–70
–50
–60
–70
–50
–60
–70
= 2 V
O(PP)
= 2 V
= 2 V
O(PP)
O(PP)
2nd Harmonic
2nd Harmonic
2nd Harmonic
–80
–90
–80
–90
–80
–90
3rd Harmonic
3rd Harmonic
3rd Harmonic
10M
–100
–100
–100
100k
1M
100M
100k
1M
10M
100M
100k
1M
10M
100M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 17
Figure 18
Figure 19
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
–40
2
1
2
1
V
R
G = 2
V
= ± 5 V
CC
= 150 Ω
R
= 750 Ω
R
= 750 Ω
F
L
F
–50
–60
–70
= 2 V
O(PP)
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
R
= 620 Ω
F
2nd Harmonic
R
= 620 Ω
F
R
= 0 Ω
F
3rd Harmonic
R
= 0 Ω
F
–80
–90
V
= ± 15 V
V
= ± 5 V
CC
Gain = 1
= 150 Ω
CC
Gain = 1
R = 150 Ω
L
R
V
L
= 62 mV
V
= 62 mV
O(PP)
O(PP)
–100
100k
1M
10M
100M
100k
1M
10M
100M
100M
100M
100k
1M
10M
100M
100M
100M
f – Frequency – Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 20
Figure 21
Figure 22
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
0.4
0.3
0.4
0.3
8
7
6
5
4
3
2
1
0
V
= ± 5 V
CC
Gain = –1
= 150 Ω
V
= ± 15 V
CC
Gain = 1
= 150 Ω
R
= 3.6 kΩ
F
R
= 750 Ω
R
F
L
R
V
L
0.2
0.2
V
= 62 mV
O(PP)
= 62 mV
O(PP)
R
= 750 Ω
F
0.1
0.1
R
= 2.7 kΩ
F
–0.0
–0.1
–0.2
–0.3
–0.4
–0.0
–0.1
–0.2
–0.3
–0.4
R
= 1 kΩ
R
= 620 Ω
F
F
R
= 620 Ω
F
V
= ±15 V
CC
Gain = 2
= 150 Ω
R
= 0 Ω
F
R
V
L
R
= 0 Ω
F
= 125 mV
O(PP)
100k
1M
10M
100M
100k
1M
10M
100k
1M
10M
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 23
Figure 24
Figure 25
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
8
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
V
= ±15 V
V
= ±5 V
CC
Gain = 2
= 150 Ω
CC
Gain = 2
R = 150 Ω
L
7
6
5
4
3
2
1
0
R
= 3.6 kΩ
F
R
V
L
= 125 mV
V
= 125 mV
O(PP)
O(PP)
R
= 3.6 kΩ
F
R
= 3.6 kΩ
F
R
= 2.7 kΩ
F
R
= 1 kΩ
F
R
= 2.7 kΩ
F
R
= 2.7 kΩ
F
V
= ±5 V
CC
Gain = 2
R
= 1 kΩ
R
= 1 kΩ
R
V
= 150 Ω
F
F
L
= 125 mV
O(PP)
100k
1M
10M
100M
100k
1M
10M
100k
1M
10M
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 26
Figure 27
Figure 28
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
8
7
6
5
4
3
2
1
0
2
1
2
1
C = 10 pF
L
R
= 5.6 kΩ
R
= 5.6 kΩ
F
F
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
R
= 3.9 kΩ
F
R
= 3.9 kΩ
F
R
= 1 kΩ
L
R
= 1 kΩ
R
= 1 kΩ
F
R
= 150 Ω
F
L
V
= ± 15 V
V
= ±15 V
CC
Gain = 2
= 2.7 k Ω
CC
Gain = –1
V
= ± 5 V
CC
Gain = –1
R
V
= 150 Ω
R
V
L
R
V
= 150 Ω
L
L
= 62 mV
= 125 mV
O(PP)
= 62 mV
O(PP)
O(PP)
100k
1M
10M
100M
100k
1M
10M
100M
100k
1M
10M
100M
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 29
Figure 30
Figure 31
SETTING TIME
vs
OUTPUT AMPLITUDE
vs
DIFFERENTIAL GAIN
vs
OUTPUT STEP
NUMBER OF 150-Ω LOADS
FREQUENCY
0.12
0.10
10
5
180
160
140
120
100
80
Gain = 2
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
V
= ± 5 V
CC
0.01%
V
V
=2.25 V
O(PP)
O(PP)
0
0.08
0.06
V
= ± 15 V
–5
V
= ± 15 V
=0.4 V
CC
0.01%
CC
–10
–15
–20
–25
–30
V
0.1%
= ± 15 V
CC
V
=125 mV
O(PP)
0.04
0.02
60
V
= ± 15 V
V
= ± 5 V
CC
Gain = 2
CC
V
0.1%
= ± 5 V
CC
R
= 360 Ω
F
40
R
R
= 2.7 kΩ
= 150 Ω
F
L
20
0
1
2
3
4
1
2
3
4
5
100k
1M
10M
100M
f - Frequency - Hz
V
- Output Step Voltage - V
Number of 150-Ω Loads
O
Figure 32
Figure 33
Figure 34
DIFFERENTIAL GAIN
vs
DIFFERENTIAL PHASE
vs
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
0.5°
0.4°
0.3°
0.2°
0.1°
0.6°
0.5°
0.2
0.16
0.12
Gain = 2
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
Gain = 2
Gain = 2
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
R = 1 kΩ
F
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
V
= ± 15 V
CC
0.4°
0.3°
V
= ± 15 V
V
= ± 15 V
CC
CC
V
= ± 5 V
CC
0.08
0.04
V
3
= ± 5 V
0.2°
0.1°
CC
V
= ± 5 V
CC
0
0°
0°
1
2
3
4
1
2
4
1
2
3
4
Number of 150-Ω Loads
Number of 150-Ω Loads
Number of 150-Ω Loads
Figure 35
Figure 36
Figure 37
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
1-V STEP RESPONSE
5-V STEP RESPONSE
1-V STEP RESPONSE
0.6
0.4
3
2
0.6
0.4
V
= ± 15 V
V
= ± 5 V
CC
Gain = 2
CC
Gain = 2
R
R
= 2.7 kΩ
= 150 Ω
R
R
= 2.7 kΩ
= 150 Ω
F
L
F
L
0.2
1
0.2
–0.0
–0.2
–0.4
–0.6
0
–0.0
–0.2
–0.4
–0.6
–1
–2
–3
V
= ± 5 V
CC
Gain = –1
R
R
= 3.9 kΩ
= 150 Ω
F
L
0
50 100 150 200 250 300 350 400
t - Time - ns
0
50 100 150 200 250 300 350 400
t - Time - ns
0
50 100 150 200 250 300 350 400
t - Time - ns
Figure 38
Figure 39
Figure 40
20-V STEP RESPONSE
15
V
= ± 15 V
CC
Gain = 5
10
5
R
R
= 2.7 kΩ
= 150 & 1 kΩ
F
L
0
–5
–10
–15
0
100
200
300
400
500
t - Time - ns
Figure 41
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
theory of operation
The THS405x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
f s of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
T
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 42.
(7) V
+
CC
(6) OUT
IN– (2)
IN+ (3)
(4) V
–
CC
NULL (1)
NULL (8)
Figure 42. THS4051 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where
signal-to-noise ratio (SNR) is very important. The noise model for the THS405x is shown in Figure 43. This
model includes all of the noise sources as follows:
•
•
•
•
e = Amplifier internal voltage noise (nV/√Hz)
n
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
e
= Thermal voltage noise associated with each resistor (e = 4 kTR )
Rx x
Rx
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
e
Rs
e
n
R
Noiseless
S
+
_
e
ni
e
no
IN+
IN–
e
Rf
R
F
e
Rg
R
G
Figure 43. Noise Model
The total equivalent input noise density (e ) is calculated by using the following equation:
ni
2
2
2
e
e
IN
R
IN–
R
R
4 kTR
4 kT R
R
n
s
ni
S
F
G
F
G
Where:
–23
k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
R || R = Parallel resistance of R and R
F
G
F
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the
ni
overall amplifier gain (A ).
V
R
R
F
e
e
A
e
1
(noninverting case)
no
ni
ni
V
G
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel
G
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares
S
n
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier
Circuits Applications Report (literature number SLVA043).
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
2
e
ni
NF
10log
2
e
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
2
2
e
IN
R
n
S
NF
10log 1
4 kTR
S
Figure 44 shows the noise figure graph for the THS405x.
NOISE FIGURE
vs
SOURCE RESISTANCE
40
f = 10 kHz
35
T
A
= 25°C
30
25
20
15
10
5
0
10
100
1k
10k
100k
Source Resistance - Ω
Figure 44. Noise Figure vs Source Resistance
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS405x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 45. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kΩ
1 kΩ
_
Input
20 Ω
Output
LOAD
THS405x
+
C
Figure 45. Driving a Capacitive Load
offset nulling
The THS405x has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4051. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This
is shown in Figure 46.
V
CC
+
0.1 µF
+
_
THS4051
10 kΩ
0.1 µF
V
CC
–
Figure 46. Offset Nulling Schematic
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
offset voltage
Theoutputoffsetvoltage,(V )isthesumoftheinputoffsetvoltage(V )andbothinputbiascurrents(I )times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB–
R
G
+
–
+
V
I
V
O
R
S
I
IB+
R
R
R
R
F
F
V
V
1
I
R
1
I
R
OO
IO
IB
S
IB–
F
G
G
Figure 47. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 620 Ω should
be used as shown in Figure 48. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS406x
_
620 Ω
Figure 48. Noninverting, Unity Gain Schematic
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 49).
R
R
F
G
–
V
R
R
O
F
1
V
1
O
1
+
V
I
V
1
sR1C1
I
G
R1
C1
f
–3dB
2 R1C1
Figure 49. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
–3dB
2 RC
C2
R
F
1
R
=
G
R
F
2 –
)
(
R
Q
G
Figure 50. 2-Pole Low-Pass Sallen-Key Filter
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS405x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS405x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductancein the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mountcomponents, theproblemwithstrayseriesinductanceisgreatlyreduced. Second, thesmall
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS405x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die
is mounted [see Figure 51(a) and Figure 51(b)]. This arrangement results in the lead frame being exposed as
a thermal pad on the underside of the package [see Figure 51(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 51. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 52. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 52. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additionalvias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS405xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Webconnectionshaveahighthermalresistanceconnectionthatisusefulforslowingtheheat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS405xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS405xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS405xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ , is about 58.4°C/W. For comparison, the non-PowerPAD version
JA
of the THS405x IC (SOIC) is shown. For a given θ , the maximum power dissipation is shown in Figure 53 and
JA
is calculated by the following formula:
T
–T
MAX
A
P
D
JA
Where:
P
= Maximum power dissipation of THS405x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
DGN Package
T
= 150°C
J
θ
= 58.4°C/W
JA
2 oz. Trace And Copper Pad
With Solder
3
2.5
2
DGN Package
= 158°C/W
2 oz. Trace And
Copper Pad
θ
JA
SOIC Package
High-K Test PCB
θ
= 98°C/W
JA
Without Solder
1.5
1
SOIC Package
Low-K Test PCB
0.5
0
θ
= 167°C/W
JA
–40
–20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be
foundintheTexasInstrumentsTechnicalBrief, PowerPAD ThermallyEnhancedPackage. Thisdocumentcan
be found at the TI web site (www.ti.com) by searching on the key word PowerPAD . The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially devices with multiple amplifiers. Because these devices have linear output stages (Class
A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 54 to Figure 57 show
this effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient
temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is
considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure
may result. When using V = ±5 V, there is generally not a heat problem, even with SOIC packages. But, when
CC
using V
= ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key
CC
factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are
extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD . The SOIC package, on the other hand, is highly dependent
on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ decreases
JA
and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total
package. For the dual amplifier package (THS4052), the sum of the RMS output currents and voltages should
be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical.
THS4051
MAXIMUM RMS OUTPUT CURRENT
vs
THS4051
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
100
10
200
T
T
A
= 150°C
= 50°C
J
Maximum Output
Current Limit Line
V
= ± 5 V
= 150°C
= 50°C
V
= ± 15 V
CC
CC
T
T
A
180
160
140
120
100
j
Maximum Output
Current Limit Line
DGN Package
= 58.4°C/W
θ
JA
Package With
θ
< = 120°C/W
JA
SO-8 Package
= 167°C/W
80
60
40
θ
SO-8 Package
= 98°C/W
JA
Low-K Test PCB
θ
JA
High-K Test PCB
SO-8 Package
= 167°C/W
θ
JA
Low-K Test PCB
Safe Operating
Area
Safe Operating
Area
20
0
0
3
6
9
12
15
0
1
2
3
4
5
| V | – RMS Output Voltage – V
O
| V | – RMS Output Voltage – V
O
Figure 54
Figure 55
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4052
THS4052
MAXIMUM RMS OUTPUT CURRENT
vs
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
100
200
Maximum Output
Current Limit Line
Package With
≤ 60°C/W
V
T
= ± 15 V
Maximum Output
Current Limit Line
CC
= 150°C
θ
JA
180
160
140
120
100
J
T
= 50°C
A
Both Channels
SO-8 Package
= 167°C/W
SO-8 Package
= 98°C/W
θ
80
60
40
JA
Low-K Test PCB
θ
10
JA
High-K Test PCB
Safe Operating Area
= ± 5 V
DGN Package
= 58.4°C/W
V
CC
= 150°C
SO-8 Package
SO-8 Package
= 98°C/W
θ
JA
T
J
θ
= 167°C/W
θ
JA
Low-K Test PCB
JA
High-K Test PCB
20
0
T = 50°C
A
Safe Operating Area
Both Channels
4
1
0
3
6
9
12
15
0
1
2
3
5
| V | – RMS Output Voltage – V
O
| V | – RMS Output Voltage – V
O
Figure 56
Figure 57
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
evaluation board
AnevaluationboardisavailablefortheTHS4051(literaturenumberSLOP220)andTHS4052(literaturenumber
SLOP234). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 58. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, please refer to the THS4051 EVM User’s Guide or the THS4052 EVM User’s Guide. To order the
evaluation board, contact your local TI sales office or distributor.
V
CC
+
+
C2
C5
6.8 µF
0.1 µF
R4
2 kΩ
NULL
R5
49.9 Ω
IN+
+
_
R3
49.9 Ω
OUT
THS4051
NULL
R2
C1
2 kΩ
6.8 µF
+
C4
0.1 µF
IN–
V
CC
–
R1
49.9 Ω
Figure 58. THS4051 Evaluation Board
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
M
0,25
8
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073271/A 01/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.063 (1,60)
0.015 (0,38)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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