THS4061CDG4 [TI]
180-MHz HIGH-SPEED AMPLIFIERS; 180 MHz的高速放大器
| 型号： | THS4061CDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 180-MHz HIGH-SPEED AMPLIFIERS |
| 文件： | 总30页 (文件大小：870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢆ ꢉ ꢄ ꢊꢋꢁ ꢌ ꢁꢍ ꢎꢁ ꢊꢂꢏꢐ ꢐꢑ ꢒꢋ ꢏ ꢓꢍ ꢔꢍ ꢐꢕ ꢂ
ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
THS4061
JG, D AND DGN PACKAGE
(TOP VIEW)
THS4062
D AND DGN PACKAGE
(TOP VIEW)
D
High Speed
− 180 MHz Bandwidth (G = 1, −3 dB)
− 400 V/µs Slew Rate
− 40-ns Settling Time (0.1%)
NULL
IN−
NULL
1OUT
1IN−
1IN+
V
CC+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
2OUT
2IN−
2IN+
D
D
High Output Drive, I = 115 mA (typ)
O
CC+
IN+
OUT
NC
Excellent Video Performance
− 75 MHz 0.1 dB Bandwidth (G = 1)
− 0.02% Differential Gain
V
−V
CC
CC−
NC − No internal connection
− 0.02° Differential Phase
D
D
D
D
Very Low Distortion
− THD = −72 dBc at f = 1 MHz
Cross-Section View Showing
PowerPAD Option (DGN)
Wide Range of Power Supplies
− V
= 5 V to 15 V
CC
THS4061
FK PACKAGE
(TOP VIEW)
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Package
Evaluation Module Available
description
3
2
1
20 19
The THS4061 and THS4062 are general-
NC
IN−
NC
IN+
NC
NC
V
4
5
6
7
8
18
17
16
15
14
purpose, single/dual, high-speed voltage feed-
back amplifiers ideal for a wide range of
applications including video, communication, and
imaging. The devices offer very good ac
performance with 180-MHz bandwidth, 400-V/µs
slew rate, and 40-ns settling time (0.1% ). The
THS4061/2 are stable at all gains for both
inverting and noninverting configurations. These
amplifiers have a high output drive capability of
115 mA and draw only 7.8 mA supply current per
channel. Excellent professional video results can
be obtained with the low differential gain/phase
errors of 0.02%/0.02° and wide 0.1 db flatness to
75 MHz. For applications requiring low distortion,
the THS4061/2 is ideally suited with total
harmonic distortion of −72 dBc at f = 1 MHz.
CC+
NC
OUT
NC
9
10 11 12 13
V
I
+
_
75 Ω
75 Ω
75 Ω
V
O
THS4061
2 kΩ
2 kΩ
LINE DRIVER (G = 2)
CAUTION: The THS4061 and THS4062 provide ESD protection circuitry. However, permanent damage can still occur if this
device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any
performance degradation or loss of functionality
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
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Copyright 1998 − 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆꢉ ꢄꢊꢋ ꢁꢌ ꢁ ꢍ ꢎꢁꢊꢂꢏ ꢐ ꢐꢑ ꢒꢋ ꢏꢓ ꢍ ꢔꢍ ꢐꢕ ꢂ
ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
RELATED DEVICES
DESCRIPTION
DEVICE
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
NUMBER OF
CHANNELS
MSOP
SYMBOL
EVALUATION
MODULES
PLASTIC
MSOP
(DGN)
CERAMIC
DIP
CHIP
CARRIER
(FK)
T
A
SMALL
OUTLINE
(D)
†
†
(JG)
1
2
1
2
THS4061CD
THS4062CD
THS4061ID
THS4062ID
THS4061CDGN
THS4062CDGN
THS4061IDGN
THS4062IDGN
—
—
—
—
—
—
—
—
TIABS
TIABM
TIABT
TIABN
THS4061EVM
0°C to
70°C
THS4062EVM
—
—
−40°C to
85°C
−55°C to
125°C
1
—
—
THS4061MJG
THS4061MFK
—
—
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4061CDGNR).
functional block diagram
Null
1
2
8
IN−
IN+
−
6
OUT
3
+
Figure 1. THS4061 − Single Channel
V
CC
8
2
3
1IN−
1IN+
−
1
7
1OUT
2OUT
+
6
5
2IN−
2IN+
−
+
4
−V
CC
Figure 2. THS4062 − Dual Channel
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V + to V
−
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
CC
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I
CC
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
O
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
IO
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D and DGN package . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
740 mW
6 mW/°C
17.1 mW/°C
8.4 mW/°C
11 mW/°C
475 mW
385 mW
—
‡
DGN
2.14 W
1.37 W
1.11 W
—
JG
FK
1057 mW
1375 mW
627 mW
546 mW
210 mW
275 mW
880 mW
715 mW
‡
The DGN package incorporates a PowerPAD on the underside of the device. This acts as a heatsink and must be connected to a thermal dissipation
plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently
damage the device.
recommended operating conditions
MIN NOM
MAX
16
UNIT
Dual supply
Single supply
C-suffix
4.5
9
Supply voltage, V + and V
CC CC
−
V
32
0
70
I-suffix
−40
−55
85
Operating free-air temperature, T
°C
A
M-suffix
125
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at T = 25°C, V
= 15 V, R = 150 Ω (unless otherwise noted)
A
CC
L
dynamic performance
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
180
50
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
=
=
=
=
=
=
=
=
=
=
=
5 V
Gain = 1
MHz
MHz
Dynamic performance small-signal
bandwidth (−3 dB)
15 V
5 V
Gain = −1
50
BW
SR
15 V
5 V
75
Bandwidth for 0.1 dB flatness
Slew rate
Gain = 1
MHz
V/µs
ns
20
15 V
5 V
400
350
40
Gain = −1
Gain = −1
Gain = −1
15 V, 5-V step (0 V to 5 V)
5 V, = −2.5 V to 2.5 V,
15 V, 5-V step (0 V to 5 V)
Settling time to 0.1%
Settling time to 0.01%
V
40
O
t
s
140
150
ns
5 V,
V
O
= −2.5 V to 2.5 V,
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
noise/distortion performance
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
−72
14.5
1.6
MAX
THD
Total harmonic distortion
Input voltage noise
Input current noise
f = 1 MHz
f = 10 kHz,
f = 10 kHz,
dBc
V
n
V
V
=
=
5 V or 15 V
5 V or 15 V
nV/√Hz
pA/√Hz
CC
I
n
CC
0.02
%
V
V
=
=
15 V
5 V
CC
Differential gain error
Gain = 2,
Gain = 2,
NTSC, 40 IRE modulation
NTSC, 40 IRE modulation
0.02
%
CC
V
V
=
=
15 V
5 V
0.02°
0.06°
CC
Differential phase error
CC
Channel-to-channel crosstalk
(THS4062 only)
V
CC
=
5 V or 15 V,
f = 1 MHz
65
dB
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
dc performance
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
T
= 25°C
5
4
15
A
V
V
=
=
15 V,
5 V,
V
V
=
=
10 V,
R
R
= 1 kΩ
V/mV
V/mV
CC
O
L
T
A
= full range
= 25°C
Open loop gain
T
A
2.5
2
8
2.5 V,
= 1 kΩ
CC
O
L
T
A
= full range
Input offset voltage
Offset drift
V
V
V
V
=
=
=
=
5 V or 15 V
5 V or 15 V
5 V or 15 V
5 V or 15 V
2.5
15
3
8
mV
µV/°C
µA
CC
CC
CC
CC
V
T
= full range
OS
A
I
I
Input bias current
Input offset current
Offset current drift
T
A
= full range
= full range
6
IB
T
A
75
0.3
250
nA
OS
T
A
= full range
nA/°C
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at T = 25°C, V = 15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
input characteristics
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
14.1
4.3
110
95
MAX
V
CC
V
CC
V
CC
V
CC
=
=
=
=
15 V
13.8
3.8
70
V
Common-mode input voltage range
V
ICR
5 V
15 V,
5 V,
V
V
=
=
12 V
ICR
CMRR Common mode rejection ratio
T
A
= full range
dB
2.5 V
70
ICR
R
C
Input resistance
1
MΩ
I
i
Input capacitance
2
pF
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
output characteristics
THS4061C/I,
THS4062C/I
†
TEST CONDITIONS
PARAMETER
UNIT
MIN
TYP
12.5
3.5
MAX
V
V
V
V
V
V
V
=
=
=
=
=
=
=
15 V
5 V
R
R
= 250 Ω
= 150 Ω
11.5
3.2
13
CC
CC
CC
CC
CC
CC
CC
L
L
V
V
V
Output voltage swing
Output current
O
15 V
5 V
13.5
3.7
R
R
= 1 kΩ
= 20 Ω
L
L
3.5
80
15 V
5 V
115
75
I
I
mA
O
50
Short-circuit current
Output resistance
15 V
150
12
mA
SC
R
Open loop
Ω
O
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
power supply
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
16.5
33
Dual supply
4.5
9
V
Supply voltage operating range
Quiescent current (per amplifier)
V
CC
Single supply
V
V
=
=
15 V
5 V
7.8
7.3
78
10.5
10
CC
I
T
= full range
mA
dB
CC
A
CC
T
A
= 25°C
70
68
PSRR Power supply rejection ratio
V
CC
=
5 V or 15 V
T
A
= full range
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at T = 25°C, V
= 15 V, R = 150 Ω (unless otherwise noted)
A
CC
L
dynamic performance
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
180
180
180
50
MAX
Unity-gain bandwidth
Closed loop,
R
= 1 kΩ
V
=
15 V
*140
MHz
L
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
=
=
=
=
=
=
=
=
=
=
=
15 V
5 V
Gain = 1
MHz
MHz
Dynamic performance small-signal
bandwidth (−3 dB)
15 V
5 V
BW
SR
Gain = −1
Gain = 1
50
15 V
5 V
75
Bandwidth for 0.1 dB flatness
Slew rate
MHz
20
15 V
R
= 1 kΩ
*400
500
40
V/µs
L
15 V, 5-V step (0 V to 5 V)
5 V, = −2.5 V to 2.5 V,
15 V, 5-V step (0 V to 5 V)
Settling time to 0.1%
Settling time to 0.01%
Gain = −1
Gain = −1
ns
ns
V
O
40
t
s
140
150
5 V,
V
O
= −2.5 V to 2.5 V,
†
Full range = −55°C to 125°C for M suffix
*This parameter is not tested.
noise/distortion performance
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
−72
MAX
THD
Total harmonic distortion
Input voltage noise
Input current noise
f = 1 MHz
f = 10 kHz,
f = 10 kHz,
dBc
V
n
V
V
=
=
5 V or 15 V
5 V or 15 V
14.5
1.6
nV/√Hz
pA/√Hz
CC
I
n
CC
V
CC
V
CC
V
CC
V
CC
=
=
=
=
15 V
5 V
0.02
0.02
0.02°
0.06°
Differential gain error
Differential phase error
Gain = 2,
Gain = 2,
NTSC, 40 IRE Modulation
NTSC, 40 IRE Modulation
%
15 V
5 V
†
Full range = −55°C to 125°C for M suffix
dc performance
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
9
MAX
V
V
=
=
15 V,
5 V,
V
V
=
=
10 V,
R
R
= 1 kΩ
= 1 kΩ
5
CC
O
L
Open loop gain
T
A
= full range
V/mV
2.5 V,
2.5
6
CC
O
L
T
= 25°C
2.5
8
9
mV
mV
A
Input offset voltage
V
=
5 V or 15 V
R
= 1 kΩ
CC
L
T
A
= full range
= full range
= full range
= full range
= full range
V
IO
Offset drift
V
CC
V
CC
V
CC
V
CC
=
=
=
=
5 V or 15 V
5 V or 15 V
5 V or 15 V
5 V or 15 V
R
R
R
R
= 1 kΩ
= 1 kΩ
= 1 kΩ
= 1 kΩ
T
A
15
3
µV/°C
µA
L
L
L
L
I
I
Input bias current
Input offset current
Offset current drift
T
A
6
IB
T
A
75
0.3
250
nA
IO
T
A
nA/°C
†
Full range = −55°C to 125°C for M suffix
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
electrical characteristics at T = full range, V
A
= 15 V, R = 1 kΩ (unless otherwise noted)
CC
L
(continued)
input characteristics
THS4061M
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
13.8
3.8
70
TYP
14.1
4.3
86
MAX
V
CC
V
CC
V
CC
V
CC
=
=
=
=
15 V
5 V
V
ICR
Common-mode input voltage range
15 V,
5 V,
V
V
=
=
12 V
ICR
CMRR Common mode rejection ratio
dB
2.5 V
80
90
ICR
R
C
Input resistance
1
MΩ
I
i
Input capacitance
2
pF
†
Full range = −55°C to 125°C for M suffix
output characteristics
THS4061M
†
TEST CONDITIONS
PARAMETER
UNIT
V
MIN
TYP
13.1
3.5
MAX
V
V
V
V
V
V
V
=
=
=
=
=
=
=
15 V
5 V
R
R
= 250 Ω
= 150 Ω
12
3.2
13
CC
CC
CC
CC
CC
CC
CC
L
L
V
O
Output voltage swing
Output current
15 V
5 V
13.5
3.7
R
R
= 1 kΩ
V
L
L
3.5
70
15 V
5 V
115
75
I
I
= 20 Ω
= 25°C
mA
O
50
Short-circuit current
Output resistance
15 V
T
A
150
12
mA
SC
R
Open loop
Ω
O
†
Full range = −55°C to 125°C for M suffix
power supply
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
16.5
33
Dual supply
4.5
9
V
Supply voltage operating range
Quiescent current
V
CC
Single supply
V
CC
V
CC
V
CC
V
CC
=
=
=
=
15 V
5 V
7.8
7.3
9
T
= 25°C
A
8.5
11
I
mA
dB
CC
15 V
5 V
T
A
= full range
10.5
T
A
= 25°C
76
74
80
78
PSRR Power supply rejection ratio
V
CC
=
5 V or 15 V
T
A
= full range
†
Full range = −55°C to 125°C for M suffix
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
FIGURE
3
I
Input bias current
Input offset voltage
Open-loop gain
Phase
vs Free-air temperature
vs Free-air temperature
vs Frequency
IB
V
4
IO
5
vs Frequency
5
Differential gain
Differential phase
Closed-loop gain
Output amplitude
vs Number of loads
vs Number of loads
vs Frequency
6, 8
7, 9
10, 11
12, 13
14
vs Frequency
CMRR Common-mode rejection ratio
vs Frequency
vs Frequency
15
PSRR
Power supply rejection ratio
vs Free-air temperature
vs Supply voltage
vs Free-air temperature
vs Frequency
16
V
Output voltage swing
Supply current
17
O(PP)
I
18
CC
E
nv
Noise spectral density
Total harmonic distortion
Crosstalk
19
THD
vs Frequency
20, 21
22, 23
vs Frequency
8
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT
vs
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4
3.5
3
0
−0.5
−1
VCC = 15 V, 5 V
VCC = 5 V
−1.5
−2
VCC = 15 V
−2.5
−3
2.5
2
−3.5
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 3
Figure 4
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
90
80
70
60
50
40
30
VCC = 15 V
VCC = 5 V
0°
−45°
−90°
−135°
−180°
Phase
20
10
0
1k
10k
100k
1M
10M
100M
1G
f − Frequency − Hz
Figure 5
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.14%
0.7°
Gain = 2
Gain = 2
RF = 680 Ω
RF = 680 Ω
0.12%
0.1%
0.6
0.5°
0.4°
0.3°
0.2°
0.1°
0°
40 IRE − NTSC
40 IRE − NTSC
Worst Case 100 IRE Ramp
Worst Case 100 IRE Ramp
V
= 5
CC
Phase
0.08%
0.06%
0.04%
0.02%
0%
V
= 15
CC
Gain
V
CC
=
15
Phase
V
CC
Gain
= 5
1
2
3
4
1
2
3
4
Number of 150 Ω Loads
Number of 150 Ω Loads
Figure 6
Figure 7
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.2%
0.18%
0.16%
0.14%
0.12%
1°
Gain = 2
= 680 Ω
40 IRE − PAL
Worst Case 100 IRE Ramp
Gain = 2
= 680 Ω
0.9°
0.8°
0.7°
0.6°
R
R
F
F
40 IRE − PAL
Worst Case 100 IRE Ramp
V = 15
CC
Gain
0.1%
0.08%
0.06%
0.04%
0.02%
0.5°
0.4°
0.3°
0.2°
0.1°
V
= 5
Gain
CC
V
= 5
CC
Phase
V
3
=
15
Phase
CC
0%
0°
1
2
3
4
1
2
4
Number of 150 Ω Loads
Number of 150 Ω Loads
Figure 8
Figure 9
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN
vs
CLOSED-LOOP GAIN
vs
FREQUENCY
FREQUENCY
2
0
5
0
V
CC
=
15 V
−2
−4
V
CC
= 5 V
−5
−10
−6
−8
−10
V
=
15 V, 5 V
CC
−15
−20
Gain = −1
R
R
Gain = 1
−12
−14
= 510 Ω
= 150 Ω
R
R
= 270 Ω
= 150 Ω
F
L
F
L
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
f − Frequency − Hz
f − Frequency − Hz
Figure 10
Figure 11
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
4
2
R
= 510 Ω
F
R
= 1 kΩ
F
2
0
0
R
= 3 kΩ
−2
F
R
= 270 Ω
F
−2
−4
R = 200 Ω
F
−4
−6
−6
−8
−8
Gain = 1
Gain = −1
R
= 150 Ω
L
R
= 150 Ω
L
−10
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
f − Frequency − Hz
f − Frequency − Hz
Figure 12
Figure 13
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
120
100
80
−80
V
CC
= 15 V, 5 V
−70
−60
−50
−40
−30
−20
60
40
20
0
−10
0
V
CC
=
15 V, 5 V
10k
100k
1M
10M
100M
1k
10k 100k
1M
10M
100M
f − Frequency − Hz
f − Frequency − Hz
Figure 14
Figure 15
POWER SUPPLY REJECTION RATIO
OUTPUT VOLTAGE SWING
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
90
30
25
20
15
88
86
84
82
80
78
76
R
= 1 kΩ
V
= −15 V
L
CC
R
= 150 Ω
L
V
CC
= 15 V
10
5
74
72
0
−40
−20
0
20
40
60
80
100
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
CC
− Supply Voltage − V
Figure 16
Figure 17
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
NOISE SPECTRAL DENSITY
vs
FREQUENCY
10
9
180
160
140
120
100
80
T
A
= 25°C
V
CC
= 15 V
8
V
CC
= 5 V
7
6
5
4
60
40
20
0
−40
−20
0
20
40
60
80
100
10
100
1k
10k
100k
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 18
Figure 19
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
−40
−50
−60
−70
−80
−90
−40
−50
−60
−70
−80
−90
Gain = 2
15 V
= 150 Ω
Gain = 2
5 V
= 150 Ω
V
R
=
V
R
=
CC
L
CC
L
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
−100
−110
−100
−110
100k
1M
10M
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 20
Figure 21
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
CROSSTALK
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
G = 2,
G = 2,
−10
R
R
V
= 300 W,
R
R
V
= 300 W,
F
L
O
S
F
L
O
S
= 100 W,
= 200 mV
= + 5 V
= 100 W,
= 200 mV
= + 15 V
−20
−30
−40
−50
−60
−70
−80
,
,
PP
PP
V
V
See Figure 24
See Figure 24
CH B to A
CH B to A
CH A to B
CH A to B
−90
−100
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
Figure 22
Figure 23
300 W
300 W
−
THS4062
A
+
V
IN
100 W
49.9 W
300 W
300 W
50 W Load
Measured
−
THS4062
49.9 W
B
+
49.9 W
Figure 24. Test Circuits
14
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
theory of operation
The THS406x is a high speed, operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f s of
T
several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 25.
(7) V
CC
+
(6) OUT
IN− (2)
IN+ (3)
(4) V
CC
−
NULL (1)
NULL (8)
Figure 25. THS4061 Simplified Schematic
15
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
offset nulling
The THS4061 has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided. By placing a potentiometer between terminals 1 and 8
and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in
Figure 26.
V
CC
+
0.1 µF
+
_
THS4061
10 kΩ
0.1 µF
V
CC
−
Figure 26. Offset Nulling Schematic
optimizing unity gain response
Internal frequency compensation of the THS406x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 270 Ω should
be used as shown in Figure 27. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS406x
_
270 Ω
Figure 27. Noninverting, Unity Gain Schematic
16
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ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 28. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
510 Ω
510 Ω
_
Input
20 Ω
Output
LOAD
THS406x
+
C
Figure 28. Driving a Capacitive Load
circuit layout considerations
In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper
printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below.
In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device
performance.
D
Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
17
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁ ꢂꢃꢄ ꢅ ꢈ
ꢆꢉ ꢄꢊꢋ ꢁꢌ ꢁ ꢍ ꢎꢁꢊꢂꢏ ꢐ ꢐꢑ ꢒꢋ ꢏꢓ ꢍ ꢔꢍ ꢐꢕ ꢂ
ꢖ
SLOS234E − DECEMBER 1998 − REVISED DECEMBER 2003
APPLICATION INFORMATION
circuit layout considerations (continued)
D
Surface-mount passive components − Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance
of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the
small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both
stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths
be kept as short as possible.
evaluation board
An evaluation board is available for the THS4061 (literature number SLOP226) and THS4062 (literaure number
SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 29. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the
evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the
THS4061 EVM User’s Manual (literature number SLOU038) or the THS4062 EVM User’s Manual (literature
number SLOU040)
V
CC
+
+
C2
C3
0.1 µF
6.8 µF
R4
1 kΩ
NULL
R5
49.9 Ω
IN+
+
_
R3
49.9 Ω
OUT
THS4061
NULL
R2
C1
1 kΩ
6.8 µF
+
C4
0.1 µF
IN−
V
CC
−
R1
49.9 Ω
Figure 29. THS4061 Evaluation Board Schematic
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
SOIC
Drawing
5962-9960101Q2A
5962-9960101QPA
THS4061CD
ACTIVE
ACTIVE
ACTIVE
FK
JG
D
20
8
1
1
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061CDG4
THS4061CDGN
ACTIVE
ACTIVE
SOIC
D
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061CDGNG4
THS4061CDGNR
THS4061CDGNRG4
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061CDR
THS4061CDRG4
THS4061ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061IDG4
THS4061IDGNG4
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
TBD
Call TI
Call TI
THS4061IDGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061IDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061IDR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061IDRG4
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4061MFKB
THS4061MJG
THS4061MJGB
THS4062CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
SOIC
FK
JG
JG
D
20
8
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062CDG4
THS4062CDGN
ACTIVE
ACTIVE
SOIC
D
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062CDGNG4
ACTIVE
MSOP-
DGN
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
Power
PAD
no Sb/Br)
THS4062CDGNRG4
ACTIVE
MSOP-
Power
PAD
DGN
8
TBD
Call TI
Call TI
THS4062CDR
THS4062CDRG4
THS4062ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062IDG4
THS4062IDGN
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062IDGNG4
THS4062IDGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062IDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062IDR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4062IDRG4
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2007
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
(mm)
12
THS4061CDGNR
THS4061CDR
THS4061IDGNR
THS4061IDR
DGN
D
8
8
8
8
8
8
8
SITE 40
SITE 60
SITE 40
SITE 60
SITE 60
SITE 40
SITE 60
5.2
6.4
5.2
6.4
6.4
5.2
6.4
3.3
5.2
3.3
5.2
5.2
3.3
5.2
1.6
2.1
1.6
2.1
2.1
1.6
2.1
8
8
8
8
8
8
8
12
12
12
12
12
12
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
12
DGN
D
12
12
THS4062CDR
THS4062IDGNR
THS4062IDR
D
12
DGN
D
12
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
THS4061CDGNR
THS4061CDR
THS4061IDGNR
THS4061IDR
DGN
D
8
8
8
8
8
8
8
SITE 40
SITE 60
SITE 40
SITE 60
SITE 60
SITE 40
SITE 60
338.1
346.0
338.1
346.0
346.0
338.1
346.0
340.5
346.0
340.5
346.0
346.0
340.5
346.0
21.1
29.0
21.1
29.0
29.0
21.1
29.0
DGN
D
THS4062CDR
THS4062IDGNR
THS4062IDR
D
DGN
D
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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