THS4082IDRG4 [TI]
175-MHz Low-Power Voltage-Feedback Amplifier, Dual 8-SOIC -40 to 85;
| 型号： | THS4082IDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 175-MHz Low-Power Voltage-Feedback Amplifier, Dual 8-SOIC -40 to 85 放大器 光电二极管 商用集成电路 |
| 文件： | 总32页 (文件大小：971K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
THS4081
D OR DGN PACKAGE
(TOP VIEW)
D
D
Ultralow 3.4 mA Per Channel Quiescent
Current
High Speed
− 175 MHz Bandwidth (−3 dB, G = 1)
− 230 V/µs Slew Rate
− 43 ns Settling Time (0.1%)
NC
IN−
IN+
NC
1
2
3
4
8
7
6
5
V
+
CC
OUT
NC
D
D
High Output Drive, I = 85 mA (typ)
O
V
CC−
Excellent Video Performance
− 35 MHz Bandwidth (0.1 dB, G = 1)
− 0.01% Differential Gain
NC − No internal connection
THS4082
D OR DGN PACKAGE
(TOP VIEW)
− 0.05° Differential Phase
D
Very Low Distortion
− THD = −64 dBc (f = 1 MHz, R = 150 Ω)
− THD = −79 dBc (f = 1 MHz, R = 1 kΩ)
1OUT
1IN−
1IN+
V
+
CC
1
2
3
4
8
7
6
5
L
L
2OUT
2IN−
2IN+
D
D
D
Wide Range of Power Supplies
V
CC−
− V
= 5 V to 15 V
CC
Available in Standard SOIC or MSOP
PowerPAD Package
Evaluation Module Available
Cross Section View Showing
PowerPAD Option (DGN)
description
The THS4081 and THS4082 are ultralow-power,
high-speed voltage feedback amplifiers that are
ideal for communication and video applications.
These amplifiers operate off of a very low 3.4-mA
quiescent current per channel and have a high
output drive capability of 85ĂmA. The signal-
amplifier THS4081 and the dual-amplifier
THS4082 offer very good ac performance with
175-MHz bandwidth, 230-V/µs slew rate, and
43-ns settling time (0.1%). With total harmonic
distortion (THD) of −64 dBc at f = 1 MHz, the
THS4081 and THS4082 are ideally suited for
applications requiring low distortion.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
T
=85°C
A
T
=25°C
A
T
=−40°C
A
5
7
9
11
13
15
RELATED DEVICES
V
- Supply Voltage - V
CC
DEVICE
DESCRIPTION
THS4011/2 290-MHz Low Distortion High-Speed Amplifiers
THS4031/2 100-MHz Low Noise High Speed-Amplifiers
THS4051/2
70-MHz High-Speed Amplifiers
CAUTION: The THS4081 and THS4082 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
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Copyright 2001, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
AVAILABLE OPTIONS
PACKAGED DEVICES
NUMBER OF
CHANNELS
MSOP
SYMBOL
EVALUATION
MODULE
PLASTIC
SMALL OUTLINE
(D)
PLASTIC
MSOP
(DGN)
T
A
†
†
1
2
1
2
THS4081CD
THS4082CD
THS4081ID
THS4082ID
THS4081CDGN
THS4082CDGN
THS4081IDGN
THS4082IDGN
AEO
AER
AEQ
AEP
THS4081EVM
0°C to 70°C
THS4082EVM
—
—
−40°C to 85°C
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4081CDGN).
functional block diagram
2
3
IN−
IN+
6
OUT
Figure 1. THS4081 − Single Channel
V
CC
1IN−
1IN+
1OUT
2OUT
2IN−
2IN+
−V
CC
Figure 2. THS4082 − Dual Channel
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I
CC
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
O
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
IO
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
θ
θ
T = 25°C
A
JA
(°C/W)
JC
PACKAGE
(°C/W)
38.3
4.7
POWER RATING
‡
D
167
58.4
740 mW
§
DGN
2.14 W
‡
§
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θ is 95°C/W with a power rating at T = 25°C of 1.32 W.
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to Application Information section of this data sheet.
JA
A
recommended operating conditions
MIN NOM
MAX
15
UNIT
Dual supply
Single supply
C-suffix
5
10
Supply voltage, V
CC+
and V
CC−
V
30
0
70
Operating free-air temperature, T
°C
A
I-suffix
−40
85
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
electrical characteristics at T = 25°C, V
= 15 V, R = 150 Ω (unless otherwise noted)
L
A
CC
dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
175
160
70
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
=
=
=
=
=
=
15 V
CC
CC
CC
CC
CC
CC
Gain = 1
Gain = −1
Gain = 1
MHz
MHz
MHz
MHz
V/µs
ns
5 V
15 V
5 V
Small-signal bandwidth (−3 dB)
Bandwidth for 0.1 dB flatness
65
BW
SR
15 V
5 V
35
35
= 20 V,
= 5 V,
15 V,
5 V,
V
V
=
=
15 V
5 V
2.7
7.1
230
170
43
O(pp)
O(pp)
CC
†
Full power bandwidth
CC
=
=
=
=
=
=
20-V step,
5-V step
5-V step
2-V step
5-V step
2-V step
Gain = 5
Gain = 1
CC
CC
CC
CC
CC
CC
‡
Slew rate
15 V,
5 V,
Settling time to 0.1%
Gain = −1
Gain = −1
30
t
s
15 V,
5 V,
233
280
Settling time to 0.01%
ns
†
‡
Slew rate is measured from an output level range of 25% to 75%.
Full power bandwidth = slew rate/2π V
O(Peak)
.
noise/distortion performance
PARAMETER
TEST CONDITIONS
MIN
TYP
−64
−79
−64
−77
10
MAX
UNIT
R
R
R
R
= 150 Ω
= 1 kΩ
L
L
L
L
V
=
=
15 V
5 V
CC
V
= 2 V,
O(pp)
f = 1 MHz, Gain = 2
THD
Total harmonic distortion
dBc
= 150 Ω
= 1 kΩ
V
CC
V
n
Input voltage noise
Input current noise
V
V
=
=
5 V or 15 V, f = 10 kHz
5 V or 15 V, f = 10 kHz
nV/√Hz
pA/√Hz
CC
I
n
0.7
CC
V
CC
V
CC
V
CC
V
CC
=
=
=
=
15 V
5 V
0.01%
0.01%
0.05°
Gain = 2,
40 IRE modulation,
NTSC,
100 IRE ramp
Differential gain error
Differential phase error
15 V
5 V
Gain = 2,
40 IRE modulation,
NTSC,
100 IRE ramp
0.05°
Channel-to-channel crosstalk
(THS4082 only)
X
T
V
CC
=
5 V or 15 V, f = 1 MHz
−75
dB
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
electrical characteristics at T = 25°C, V = 15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
dc performance
PARAMETER
TEST CONDITIONS
MIN
10
9
TYP
MAX
UNIT
T
= 25°C
19
A
V
=
=
15 V,
5 V,
V
=
10 V,
R
= 1 kΩ
V/mV
CC
O
L
L
†
†
T
A
= full range
= 25°C
Open loop gain
T
A
8
16
1
V
CC
V
O
=
2.5 V,
R
= 250 Ω
V/mV
T
A
= full range
7
T
A
= 25°C
7
8
V
OS
Input offset voltage
Offset voltage drift
mV
†
†
T
A
= full range
= full range
= 25°C
T
A
15
µV/°C
T
A
1.2
6
8
V
CC
=
5 V or 15 V
I
I
Input bias current
µA
IB
†
T
A
= full range
= 25°C
T
A
20
250
400
Input offset current
Offset current drift
nA
OS
†
T
A
= full range
†
= full range
T
A
0.3
nA/°C
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
input characteristics
PARAMETER
TEST CONDITIONS
MIN
13.8
3.8
78
TYP
14.1
3.9
90
MAX
UNIT
V
CC
V
CC
V
CC
V
CC
=
=
=
=
15 V
5 V
V
ICR
Common mode input voltage range
V
†
†
15 V,
5 V,
V
V
=
=
12 V,
2 V,
T
= full range
dB
dB
ICR
A
CMRR Common mode rejection ratio
T
A
= full range
84
93
ICR
R
C
Input resistance
1
MΩ
pF
I
I
Input capacitance
1.5
†
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
output characteristics
PARAMETER
TEST CONDITIONS
MIN
12
TYP
13.6
3.8
MAX
UNIT
V
=
15 V,
5 V,
R
R
= 250 Ω
CC
CC
CC
CC
CC
CC
CC
L
L
V
V
=
=
=
=
=
=
= 150 Ω
3.4
13.5
3.5
65
V
O
Output voltage swing
V
V
V
V
V
15 V
5 V
13.8
3.9
R
R
= 1 kΩ
V
L
L
15 V
5 V
85
Output current
I
I
= 20 Ω
mA
O
50
70
‡
Short-circuit current
15 V
100
mA
SC
R
Output resistance
Open loop
13
Ω
O
‡
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
electrical characteristics at T = 25°C, V = 15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
power supply
PARAMETER
TEST CONDITIONS
MIN
4.5
9
TYP
MAX
16.5
33
UNIT
Dual supply
Single supply
V
Supply voltage operating range
Supply current (per amplifier)
V
CC
T
= 25°C
3.4
2.9
90
4.2
5
A
V
=
15 V
CC
†
T
A
= full range
I
mA
dB
CC
T
= 25°C
3.7
4.5
A
V
V
=
=
5 V
CC
†
†
T
A
= full range
PSRR Power supply rejection ratio
†
5 V or 15 V
T
A
= full range
79
CC
Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
TYPICAL CHARACTERISTICS
OPEN LOOP GAIN
& PHASE RESPONSE
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
100
80
60
40
20
0
45°
0°
20
0
V
=
15 V
CC
Gain = 1
R
R
= 0 Ω
= 150 Ω
F
L
Gain
−45°
90°
−20
−40
−60
−80
Phase
135°
180°
V
= 5 V and 15 V
CC
1k
−225°
−20
100
10k 100k 1M 10M 100M 1G
100k
1M
10M
100M
1G
f − Frequency − Hz
f − Frequency − Hz
Figure 3
Figure 4
SETTLING
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
vs
OUTPUT STEP
FREQUENCY
FREQUENCY
−40
−40
−50
−60
−70
−80
−90
−100
330
290
250
210
170
130
90
V
=
15 V
V
=
5 V
CC
Gain = 2
CC
Gain = 2
−50
−60
V
= 2 V
V
= 2 V
O(PP)
O(PP)
R
= 150 Ω
R
= 150 Ω
V =
CC
5 V(0.01%)
L
L
−70
V
= 15 V(0.01%)
CC
R
= 1 kΩ
L
V
=
5 V(0.1%)
= 15 V(0.1%)
−80
CC
R
= 1 kΩ
L
V
CC
−90
50
10
−100
2
3
4
5
100k
1M
10M
100k
1M
10M
f - Frequency - Hz
f - Frequency - Hz
V
− Output Step Voltage − V
O
Figure 5
Figure 6
Figure 7
POWER SUPPLY REJECTION
DISTORTION
vs
OUTPUT VOLTAGE
DISTORTION
vs
OUTPUT VOLTAGE
RATIO
vs
FREQUENCY
−50
−50
−60
0
−20
2nd Harmonic
V
=
15 V & 5 V
CC
2nd Harmonic
−60
−70
−V
CC
3rd Harmonic
3rd Harmonic
−70
−40
+V
CC
−80
−80
−60
V
R
=
15 V
V
R
=
CC
L
15 V
= 150 Ω
CC
L
−90
−90
−80
= 1 kΩ
Gain = 5
Gain = 5
f = 1 MHz
f = 1 MHz
−100
−100
−100
0
5
10
15
20
0
5
10
15
20
100k
1M
10M
100M
f - Frequency - Hz
V
− Output Voltage − V
V
− Output Voltage − V
O
O
Figure 8
Figure 9
Figure 10
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
TYPICAL CHARACTERISTICS
DISTORTION
vs
DISTORTION
vs
DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−50
−50
−60
V
R
=
15 V
V
R
=
5 V
V =
CC
15 V
R = 150 Ω
L
CC
L
CC
L
= 1 kΩ
= 1 kΩ
Gain = 2
V
Gain = 2
= 2 V
Gain = 2
V = 2 V
−60
−70
−60
−70
= 2 V
V
O(PP)
O(PP)
O(PP)
3rd Harmonic
−70
2nd Harmonic
2nd Harmonic
2nd Harmonic
−80
−80
−80
3rd Harmonic
−90
−90
−90
3rd Harmonic
−100
−100
−100
100k
1M
10M
100k
1M
10M
.
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 12
f − Frequency − Hz
Figure 11
Figure 13
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
−60
4
4
V
R
=
5 V
= 150 Ω
Gain = 2
= 2 V
CC
L
R
= 130 Ω
F
R
= 51 Ω
= 0 Ω
F
2
0
2
0
V
O(PP)
R
= 51 Ω
R
= 130 Ω
F
F
3rd Harmonic
−70
R
R
= 0 Ω
F
F
2nd Harmonic
−80
−2
−4
−6
−2
−4
−6
V
=
15 V
V
=
5 V
CC
Gain = 1
CC
Gain = 1
−90
R
V
= 150 Ω
R
= 150 Ω
L
L
= 63 mV
V
= 63 mV
O(PP)
O(PP)
−100
100k
1M
10M
100k
1M
10M 100M 1G
100k
1M
10M 100M 1G
f − Frequency − Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 14
Figure 15
Figure 16
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
2
2
0
2
R
= 51 Ω
F
R = 1.3 kΩ
F
R
= 51 Ω
F
R
= 2 kΩ
F
0
−2
−4
−6
−8
0
−2
−4
−6
−8
R
= 1 kΩ
F
R
= 0 Ω
R
F
= 0 Ω
F
−2
−4
−6
−8
V
=
15 V
V
=
5 V
V =
15 V
Gain = −1
R = 150 Ω
L
CC
Gain = 1
CC
Gain = 1
CC
R
V
= 1 kΩ
R
V
= 1 kΩ
L
L
= 63 mV
= 63 mV
V
= 63 mV
O(PP)
O(PP)
O(PP)
100k
1M
10M 100M 1G
10
1M
10M 100M 1G
100k
1M
10M 100M 1G
100k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 17
Figure 18
Figure 19
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
TYPICAL CHARACTERISTICS
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
2
0
2
2
R
= 1.3 kΩ
R = 1.5 kΩ
F
F
R
= 1.5 kΩ
F
R
= 2 kΩ
R
= 2 kΩ
F
F
0
−2
−4
−6
−8
0
−2
−4
−6
−8
R
= 1.3 kΩ
R = 1.3 kΩ
F
F
R
= 1 kΩ
F
−2
−4
−6
−8
V
=
5 V
Gain = −1
= 150 Ω
V
=
15 V
Gain = −1
= 1 kΩ
V =
5 V
Gain = −1
R = 1 kΩ
L
CC
CC
CC
R
V
R
V
L
L
= 63 mV
= 63 mV
V
= 63 mV
O(PP)
O(PP)
O(PP)
100k
1M
10M 100M 1G
100k
1M
10M 100M 1G
100k
1M
10M 100M 1G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 20
Figure 21
Figure 22
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
8
8
8
R = 1.2 kΩ
F
R
= 1.2 kΩ
R
= 1.5 kΩ
F
F
R
= 1.5 kΩ
F
R
= 1.5 kΩ
F
6
4
6
4
6
4
R
= 1.2 kΩ
F
R
= 750 Ω
F
R
= 750 Ω
F
2
2
2
V
=
15 V
V
=
5 V
V
=
15 V
CC
Gain = 2
CC
Gain = 2
CC
Gain = 2
0
0
0
R
= 150 Ω
R
= 150 Ω
R
= 1 kΩ
L
L
L
V
= 126 mV
V
= 126 mV
V
= 126 mV
O(PP)
O(PP)
O(PP)
−2
−2
−2
10.00
100k
100.00
1M
1000.00 10000.00 100000.00
10M 100M 1G
10.00
100k
100.00
1M
1000.00 10000.00 100000.00
100k
1M
10M 100M 1G
10M
100M
1G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 23
Figure 24
Figure 25
OUTPUT AMPLITUDE
vs
FREQUENCY
2-V STEP RESPONSE
5-V STEP RESPONSE
8
1.2
3
V
=
5 V
CC
Gain = 2
R
= 1.2 kΩ
F
0.8
0.4
2
1
R
R
= 1.2 kΩ
= 150 Ω
6
4
F
L
R
= 1.5 kΩ
F
0.0
0
2
−0.4
−0.8
−1.2
−1
−2
−3
V
=
5 V
CC
V
=
5 V
CC
Gain = 2
Gain = −1
R
R
0
= 1.3 kΩ
= 150 Ω
F
L
R
V
= 1 kΩ
L
= 126 mV
O(PP)
−2
100k
1M
10M 100M 1G
0
200
400
600
800
1000
0
200
400
600
800
1000
f - Frequency - Hz
t - Time - ns
t - Time - ns
Figure 26
Figure 27
Figure 28
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
2-V STEP RESPONSE
20-V STEP RESPONSE
1.2
12
1.5
1.3
1.1
0.9
0.7
0.5
0.3
V
=
15 V
V
=
15 V
CC
Gain = 2
CC
Gain = 5
1.0
0.8
10
8
R
R
= 1.2 kΩ
= 150 Ω
R
R
= 1.2 kΩ
= 150 Ω
F
L
F
L
V =
CC
15 V
0.6
6
0.4
4
0.2
2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−1.2
0
−2
−4
−6
−8
−10
−12
V
=
5 V
CC
0
200
400
600
800
1000
0
200
400
600
800
1000
−40 −20
0
20
40
60
80 100
t - Time - ns
t - Time - ns
T
- Free-Air Temperature - °C
A
Figure 29
Figure 30
Figure 31
OUTPUT VOLTAGE
vs
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
15
13
11
9
15
13
11
9
T
=25°C
T
=25°C
A
A
R
= 1 kΩ
V
= 15 V
L
CC
R
= 150 Ω
L
7
7
V
=
5 V
CC
5
5
3
3
−40 −20
0
20
40
60
80 100
5
7
9
11
13
15
5
7
9
11
13
15
T
- Free-Air Temperature - °C
V
- Supply Voltage - V
V
CC
- Supply Voltage - V
A
CC
Figure 32
Figure 33
Figure 34
SUPPLY CURRENT
vs
VOLTAGE & CURRENT NOISE
OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
FREQUENCY
15
13
11
9
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
100
10
V
=
15 V and 5 V
CC
T
A
= 25°C
V
=
15 V
CC
T
=85°C
A
R
= 150 Ω
L
V
N
V
=
15 V
CC
R
= 1 kΩ
L
T
=25°C
A
7
V
=
5 V
CC
I
N
1
R
= 1 kΩ
5
L
T
=−40°C
A
3
V
=
5 V
CC
R
= 150 Ω
L
1
0.1
−40 −20
0
20
40
60
80 100
5
7
9
11
- Supply Voltage - V
CC
13
15
10
100
1k
10k
100k
T
− Free-Air Temperature − _C
V
f - Frequency - Hz
A
Figure 35
Figure 36
Figure 37
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
theory of operation
The THS408x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
f s of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
T
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 38.
(7) V
CC
+
(6) OUT
IN− (2)
IN+ (3)
(4) V
CC
−
Figure 38. THS4081 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where
signal-to-noise ratio (SNR) is very important. The noise model for the THS408x is shown in Figure 39. This
model includes all of the noise sources as follows:
• e = Amplifier internal voltage noise (nV/√Hz)
n
• IN+ = Noninverting current noise (pA/√Hz)
• IN− = Inverting current noise (pA/√Hz)
• e = Thermal voltage noise associated with each resistor (e = 4 kTR )
Rx
Rx
x
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
noise calculations and noise figure (continued)
e
Rs
e
n
R
Noiseless
S
+
_
e
ni
e
no
IN+
IN−
e
Rf
R
F
e
Rg
R
G
Figure 39. Noise Model
The total equivalent input noise density (e ) is calculated by using the following equation:
ni
2
) ǒIN ) RSǓ2
ǒ
Ǔ
) 4 kTR ) 4 kTǒR GǓ
2
Ǹ
ǒ Ǔ
) ǒIN– R G Ǔ
e
+
e
ø R
ø R
n
s
ni
F
F
Where:
−23
k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
R || R = Parallel resistance of R and R
F
G
F
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the
ni
overall amplifier gain (A ).
V
R
F
+ e ǒ1 ) Ǔ(noninverting case)
e
+ e
A
no
ni
R
G
ni
V
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel
G
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares
S
n
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier
Circuits Applications Report (literature number SLVA043).
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
ȱ
2 ȳ
e
ni
NF + 10log
ȧ
ȧ
ȧ
ȧ
ǒe Ǔ2
Ȳ
ȴ
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
2
2
ȱ
ȳ
ȣ
ȡ
) ǒIN ) R
Ǔ
S
ǒe Ǔ
ȧ
ȧ
n
ȧ
ȧ
ȧ
Ȣ
Ȥ
ȧ
NF + 10log 1 )
ȧ
ȧ
ȧ
ȧ
4 kTR
S
ȧ
ȧ
Ȳ
ȴ
Figure 40 shows the noise figure graph for the THS408x.
NOISE FIGURE
vs
SOURCE RESISTANCE
40
f = 10 kHz
35
T
A
= 25°C
30
25
20
15
10
5
0
10
100
1k
10k
100k
Source Resistance − R (Ω)
S
Figure 40. Noise Figure vs Source Resistance
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS408x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 41. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1.3 kΩ
1.3 kΩ
_
Input
20 Ω
Output
LOAD
THS408x
+
C
Figure 41. Driving a Capacitive Load
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
R
R
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB–
F
R
R
G
G
Figure 42. Output Offset Voltage Model
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SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals is often required. The simplest
way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 43).
R
R
F
G
−
V
1
O
+
V
I
R1
V
C1
f
+
–3dB
2pR1C1
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
Figure 43. Single-Pole Low-Pass Filter
circuit layout considerations
To achieve the levels of high frequency performance of the THS408x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS408x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements − Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D
Surface-mount passive components − Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
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ꢆꢉ ꢊꢋꢌ ꢁꢍ ꢎ ꢏꢐꢋꢑꢏ ꢐꢒ ꢓ ꢁꢔ ꢕ ꢁꢋꢂ ꢑꢒ ꢒ ꢖ ꢗꢌꢑ ꢎꢔ ꢘ ꢔꢒꢓꢂ
ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
general PowerPAD design considerations
The THS408x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die
is mounted [see Figure 44(a) and Figure 44(b)]. This arrangement results in the lead frame being exposed as
a thermal pad on the underside of the package [see Figure 44(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 44. Views of Thermally Enhanced DGN Package
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢆ ꢉ ꢊ ꢋꢌꢁ ꢍ ꢎ ꢏ ꢐꢋꢑꢏ ꢐ ꢒꢓ ꢁꢔ ꢕꢁ ꢋꢂꢑꢒ ꢒꢖ ꢗꢌ ꢑ ꢎꢔ ꢘꢔ ꢒꢓ ꢂ
ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 45. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 45. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS408xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered, so wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS408xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS408xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS408xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ , is about 58.4_C/W. For comparison, the non-PowerPAD version
JA
of the THS408x IC (SOIC) is shown. For a given θ , the maximum power dissipation is shown in Figure 46 and
JA
is calculated by the following formula:
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
T
T
θ
θ
θ
= Maximum power dissipation of THS408x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
MAX
A
JA
JC
CA
= θ + θ
JC CA
= Thermal coefficient from junction to case
= Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
DGN Package
T
= 150°C
J
θ
= 58.4°C/W
JA
2 oz. Trace And Copper Pad
3
2.5
2
With Solder
DGN Package
= 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
θ
JA
SOIC Package
High-K Test PCB
θ
= 98°C/W
JA
1.5
1
SOIC Package
Low-K Test PCB
0.5
0
θ
= 167°C/W
JA
−40
−20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 46. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 47 to Figure 50 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient temperature
increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered
the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result.
When using V
= 5 V, there is generally not a heat problem, even with SOIC packages. But, when using
CC
V
= 15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor
CC
when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are
extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent
on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ decreases
JA
and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total
package. For the dual amplifier package (THS4082), the sum of the RMS output currents and voltages should
be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical.
THS4081
MAXIMUM RMS OUTPUT CURRENT
vs
THS4081
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
1000
100
10
T
T
= 150°C
= 50°C
Maximum Output
Current Limit Line
V
T
T
A
=
5 V
J
A
CC
J
V
=
15 V
CC
= 150°C
= 50°C
180
160
140
120
100
Maximum Output
Current Limit Line
DGN Package
= 58.4°C/W
θ
JA
Package With
θ
JA
< = 127°C/W
SO-8 Package
= 167°C/W
θ
JA
Low-K Test PCB
80
60
40
SO-8 Package
= 98°C/W
θ
JA
High-K Test PCB
SO-8 Package
= 167°C/W
θ
JA
Low-K Test PCB
Safe Operating
Area
Safe Operating
Area
20
0
0
1
2
3
4
5
0
3
6
9
12
15
| V | − RMS Output Voltage − V
O
| V | − RMS Output Voltage − V
O
Figure 47
Figure 48
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁ ꢂꢃꢄ ꢅ ꢈ
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ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4082
THS4082
MAXIMUM RMS OUTPUT CURRENT
vs
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
200
Maximum Output
Current Limit Line
Package With
≤ 64°C/W
V
T
=
15 V
Maximum Output
Current Limit Line
CC
J
θ
JA
= 150°C
= 50°C
180
160
140
120
100
T
A
Both Channels
100
SO-8 Package
= 167°C/W
SO-8 Package
= 98°C/W
θ
80
60
40
JA
Low-K Test PCB
10
θ
JA
High-K Test PCB
Safe Operating Area
DGN Package
= 58.4°C/W
V
=
5 V
CC
SO-8 Package
SO-8 Package
= 98°C/W
θ
JA
T
= 150°C
T = 50°C
A
J
θ
= 167°C/W
θ
JA
Low-K Test PCB
JA
High-K Test PCB
20
0
Safe Operating Area
Both Channels
1
0
3
6
9
12
15
0
1
2
3
4
5
| V | − RMS Output Voltage − V
O
| V | − RMS Output Voltage − V
O
Figure 49
Figure 50
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢆ ꢉ ꢊ ꢋꢌꢁ ꢍ ꢎ ꢏ ꢐꢋꢑꢏ ꢐ ꢒꢓ ꢁꢔ ꢕꢁ ꢋꢂꢑꢒ ꢒꢖ ꢗꢌ ꢑ ꢎꢔ ꢘꢔ ꢒꢓ ꢂ
ꢙ
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS4081 (literature number SLOP242) and THS4082 (literature number
SLOP239). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 51. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, please refer to the THS4081 EVM User’s Guide or the THS4082 EVM User’s Guide. To order the
evaluation board, contact your local TI sales office or distributor.
V
CC
+
+
C2
C3
0.1 µF
6.8 µF
R4
1.3 kΩ
R5
49.9 Ω
IN+
+
_
R3
49.9 Ω
OUT
THS4081
R2
C1
1.3 kΩ
6.8 µF
+
C4
0.1 µF
IN−
V
CC
−
R1
49.9 Ω
Figure 51. THS4081 Evaluation Board
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
THS4081CD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
4081C
THS4081CDG4
THS4081CDGN
THS4081CDGNR
THS4081CDR
THS4081CDRG4
THS4081ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
DGN
DGN
D
75
80
Green (RoHS
& no Sb/Br)
0 to 70
4081C
AEO
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
0 to 70
AEO
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
4081C
4081C
4081I
4081I
AEQ
D
Green (RoHS
& no Sb/Br)
0 to 70
D
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
THS4081IDG4
THS4081IDGN
THS4081IDGNG4
THS4081IDGNR
THS4082CD
D
75
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
AEQ
MSOP-
PowerPAD
2500
75
Green (RoHS
& no Sb/Br)
AEQ
SOIC
Green (RoHS
& no Sb/Br)
4082C
4082C
AER
THS4082CDG4
THS4082CDGNR
THS4082CDR
THS4082CDRG4
THS4082ID
SOIC
D
75
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
DGN
D
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
4082C
4082C
4082I
D
Green (RoHS
& no Sb/Br)
0 to 70
D
Green (RoHS
& no Sb/Br)
-40 to 85
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
THS4082IDG4
THS4082IDGN
THS4082IDGNG4
THS4082IDGNR
THS4082IDR
ACTIVE
SOIC
D
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU | Call TI
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
4082I
AEP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
AEP
MSOP-
PowerPAD
2500
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
AEP
SOIC
Green (RoHS
& no Sb/Br)
4082I
4082I
THS4082IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4081CDGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
THS4081CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
THS4081IDGNR
MSOP-
Power
PAD
DGN
THS4082CDGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4082CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
THS4082IDGNR
MSOP-
Power
PAD
DGN
THS4082IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4081CDGNR
THS4081CDR
MSOP-PowerPAD
SOIC
DGN
D
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
346.0
367.0
364.0
358.0
367.0
358.0
367.0
346.0
367.0
364.0
335.0
367.0
335.0
367.0
35.0
35.0
27.0
35.0
35.0
35.0
35.0
THS4081IDGNR
THS4082CDGNR
THS4082CDR
MSOP-PowerPAD
MSOP-PowerPAD
SOIC
DGN
DGN
D
THS4082IDGNR
THS4082IDR
MSOP-PowerPAD
SOIC
DGN
D
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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