THS4130IDGNRG4 [TI]
HIGH-SPEED, LOW-NOISE, FULLY-DIFFERENTIAL I/O AMPLIFIERS; 高速，低噪声，全差分I / O放大器
| 型号： | THS4130IDGNRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED, LOW-NOISE, FULLY-DIFFERENTIAL I/O AMPLIFIERS |
| 文件： | 总36页 (文件大小：1124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4130
THS4131
D−8
DGN−8 DGK−8
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
HIGH-SPEED, LOW-NOISE, FULLY-DIFFERENTIAL I/O AMPLIFIERS
Check for Samples: THS4130, THS4131
1
FEATURES
DESCRIPTION
The THS413x is one in a family of fully-differential
input/differential output devices fabricated using
Texas Instruments' state-of-the-art BiComI
complementary bipolar process.
23
•
High Performance
–
–
–
150 MHz, –3 dB Bandwidth (VCC = ±15 V)
51 V/µs Slew Rate
–100 dB Third Harmonic Distortion at
The THS413x is made of a true fully-differential signal
path from input to output. This design leads to an
excellent common-mode noise rejection and
improved total harmonic distortion.
250 kHz
Low Noise
•
–
1.3 nV/√Hz Input-Referred Noise
•
Differential-Input/Differential-Output
THS4130
D, DGN, OR DGK PACKAGE
(TOP VIEW)
THS4131
D, DGN, OR DGK PACKAGE
(TOP VIEW)
–
Balanced Outputs Reject Common-Mode
Noise
V
V
V
V
IN+
–
Reduced Second-Harmonic Distortion Due
to Differential Output
IN−
1
2
3
4
8
7
6
5
IN+
IN−
1
2
3
4
8
7
6
5
V
OCM
PD
V
V
OCM
NC
V
V
CC+
V
CC+
CC−
CC−
•
•
Wide Power-Supply Range
–
V
V
OUT−
V
V
OUT−
OUT+
OUT+
VCC = 5 V Single Supply to ±15 V Dual
Supply
HIGH-SPEED DIFFERENTIAL I/O FAMILY
NUMBER OF
ICC(SD) = 860 µA in Shutdown Mode (THS4130)
DEVICE
SHUTDOWN
CHANNELS
APPLICATIONS
THS4130
THS4131
1
1
X
−
•
•
•
•
•
Single-Ended To Differential Conversion
Differential ADC Driver
Differential Antialiasing
Differential Transmitter And Receiver
Output Level Shifter
RELATED DEVICES
DEVICE
THS412x
THS414x
THS415x
DESCRIPTION
100 MHz, 43 V/µs, 3.7 nV/√Hz
160 MHz, 450 V/µs, 6.5 nV/√Hz
180 MHz, 850 V/µs, 9 nV/√Hz
TOTAL HARMONIC DISTORTION vs FREQUENCY
−20
Typical A/D Application Circuit
5 V
VDD
V
= 2 V
OUT
PP
−30
−40
AVDD DVDD
VIN
+
−
−50
−60
AIN
AIN
VOCM
DIGITAL
OUTPUT
+
V
= 5 V to ± 5 V
AVSS
Vref
−
CC
−70
−80
−5 V
−90
V
= ± 15 V
CC
−100
100 k
1 M
f − Frequency − Hz
10 M
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2011, Texas Instruments Incorporated
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICES
MSOP PowerPAD™
MSOP
SMALL OUTLINE
(D)
EVALUATION
MODULES
TA
(DGN)
SYMBOL
(DGK)
SYMBOL
ATP
THS4130CD
THS4131CD
THS4130ID
THS4131ID
THS4130CDGN
THS4131CDGN
THS4130IDGN
THS4131IDGN
AOB
AOD
AOC
AOE
THS4130CDGK
THS4131CDGK
THS4130IDGK
THS4131IDGK
THS4130EVM
0°C to +70°C
ATQ
THS4131EVM
ASO
—
—
–40°C to +85°C
ASP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range,unless otherwise noted.
UNIT
VCC– to VCC+
VI
Supply voltage
±33 V
±VCC
Input voltage
(2)
IO
Output current
150 mA
VID
Differential input voltage
±6 V
Continuous total power dissipation
Maximum junction temperature
Maximum junction temperature, continuous operation, long-term reliability
See Dissipation Rating table
+150°C
(3)
TJ
(4)
TJ
+125°C
TA
Operating free-air temperature
C-suffix
I-suffix
0°C to +70°C
–40°C to +85°C
–65°C to +150°C
2500 V
TSTG
Storage temperature
ESD ratings:
HBM
CDM
MM
1500 V
200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS413x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD
thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATING TABLE
POWER RATING(2)
PACKAGE
D
θJA(1) (°C/W)
97.5
θJC (°C/W)
38.3
TA= +25°C
1.02 W
TA = +85°C
410 mW
685 mW
300 mW
DGN
58.4
4.7
1.71 W
DGK
134
72
750 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
2
Copyright © 2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
RECOMMENDED OPERATING CONDITIONS
MIN
±2.5
TYP
MAX
±15
30
UNIT
Dual supply
Supply voltage, VCC+ to VCC–
V
Single supply
5
0
C-suffix
Operating free-air temperature, TA
I-suffix
+70
+85
°C
–40
ELECTRICAL CHARACTERISTICS(1)
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
DYNAMIC PERFORMANCE
VCC = 5
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain = 1, Rf = 390 Ω
125
Small-signal bandwidth (–3 dB), single-ended input,
differential output, VI = 63 mVPP
VCC = ±5
Gain = 1, Rf = 390 Ω
Gain = 1, Rf = 390 Ω
Gain = 2, Rf = 750 Ω
Gain = 2, Rf = 750 Ω
Gain = 2, Rf = 750 Ω
135
150
80
VCC = ±15
BW
MHz
VCC = 5
Small-signal bandwidth (–3 dB), single-ended input,
differential output, VI = 63 mVPP
VCC = ±5
85
VCC = ±15
90
SR
ts
Slew rate(2)
Gain = 1
52
V/µs
ns
Settling time to 0.1%
Settling time to 0.01%
78
Step voltage = 2 V, gain = 1
213
ns
DISTORTION PERFORMANCE
f = 250 kHz
–95
–81
–96
–80
–97
–80
–91
–75
–91
–75
97
VCC = 5
f = 1 MHz
f = 250 kHz
f = 1 MHz
f = 250 kHz
f = 1 MHz
f = 250 kHz
f = 1 MHz
f = 250 kHz
f = 1 MHz
VCC = ±2.5
VCC = ±5
Total harmonic distortion, differential input, differential
output, gain = 1, Rf = 390 Ω, RL = 800 Ω, VO= 2 VPP
VCC = ±5
VCC = ±15
VCC = ±5
VCC = ±15
THD
dBc
VO = 4 VPP
VO= 2 VPP
98
Spurious-free dynamic range, differential input,
differential output, gain = 1, Rf = 390 Ω,
RL = 800 Ω, f = 250 kHz
SFDR
VCC = ±15
VCC = ±5
99
dB
93
VO = 4 VPP
VCC = ±15
95
Third intermodulation distortion
Third-order intercept
VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz
VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz
–53
41.5
dBc
dB
NOISE PERFORMANCE
Vn
In
Input voltage noise
Input current noise
f = 10 kHz
f = 10 kHz
1.3
1
nV/√Hz
pA/√Hz
DC PERFORMANCE
TA = +25°C
71
69
78
Open-loop gain
dB
TA = full range
TA = +25°C
0.2
2
3
Input offset voltage
V(OS)
TA = full range
TA = +25°C
mV
Common-mode input offset voltage, referred to VOCM
0.2
4.5
2
3.5
Input offset voltage drift
Input bias current
Input offset current
Offset drift
TA = full range
TA = full range
TA = full range
µV/°C
µA
IIB
6
IOS
100
2
500
nA
nA/°C
(1) The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
(2) Slew rate is measured from an output level range of 25% to 75%.
Copyright © 2000–2011, Texas Instruments Incorporated
3
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS(1) (continued)
VCC= ±5 V, RL = 800Ω, and TA = +25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio
TA = full range
80
95
dB
V
–3.77 to
VICR
Common-mode input voltage range
–4 to 4.5
4.3
RI
CI
ro
Input resistance
Measured into each input terminal
Open loop
34
4
MΩ
pF
Ω
Input capacitance, closed loop
Output resistance
41
OUTPUT CHARACTERISTICS
1.2 to
3.8
0.9 to
4.1
TA = +25°C
VCC = 5 V
1.3 to
3.7
TA = full range
±4
Output voltage swing
V
TA = +25°C
±3.7
±3.6
±10.5
±10.2
25
VCC = ±5 V
TA = full range
TA = +25°C
±12.4
45
VCC = ±15 V
TA = full range
TA = +25°C
VCC = 5 V, RL = 7 Ω
VCC = ±5 V, RL = 7 Ω
VCC = ±15 V, RL = 7 Ω
TA = full range
TA = +25°C
20
30
55
IO
Output current
mA
TA = full range
TA = +25°C
28
60
85
TA = full range
65
POWER SUPPLY
VCC Supply voltage range
Single supply
Split supply
4
33
V
±2
±16.5
15
TA = +25°C
12.3
VCC = ±5 V
VCC = ±15 V
V = –5 V
ICC
Quiescent current
TA = full range
TA = +25°C
16
mA
14
TA = +25°C
0.86
1.4
1.5
ICC(SD)
PSRR
Quiescent current (shutdown) (THS4130 only)(3)
Power-supply rejection ratio (dc)
mA
dB
TA = full range
TA = +25°C
73
70
98
TA = full range
(3) For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section in the Principles of Operation.
4
Copyright © 2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Figure 1,
Figure 2
Small-signal frequency response
Small-signal frequency response (various supplies)
Small-signal frequency response (various CF)
Small-signal frequency response (various CL)
Large-signal transient response (differential in/single out)
Large-signal frequency response
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
CMMR
ICC
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
Supply current
vs Free-air temperature (shutdown state)
vs Free-air temperature
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
IIB
Input bias current
Settling time
PSRR
THD
Power-supply rejection ratio
Large-signal transient response
Total harmonic distortion
vs Frequency (differential out)
vs Frequency
vs Frequency
Figure 16,
Figure 17
Second-harmonic distortion
Third-harmonic distortion
Figure 18,
Figure 19
vs Output voltage
vs Frequency
Figure 20,
Figure 21
Figure 22,
Figure 23
vs Output voltage
Vn
Voltage noise
vs Frequency
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
In
Current noise
vs Frequency
V(OS)
VO
zo
Input offset voltage
Output voltage
Output impedance
vs Common-mode output voltage
vs Differential load resistance
vs Frequency
Copyright © 2000–2011, Texas Instruments Incorporated
5
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SMALL-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
25
20
3
2
1
0
Gain = 1,
R = 620 Ω
f
R
= 800 Ω,
= ±5 V,
L
Gain = 10_R = 4 kΩ
R
L
= 800 Ω,
f
V
CC
V
CC
= ±5 V,
V = 63 mV
I
PP
V = 63 mV
I
PP
Gain = 5_R = 2 kΩ
f
15
10
−1
R = 390 Ω
f
−2
−3
−4
Gain = 2_R = 750 Ω
f
5
Gain = 1_R = 390 Ω
f
−5
−6
0
−5
−7
−8
−10
100 k
100 k
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
SMALL-SIGNAL FREQUENCY RESPONSE
(VARIOUS SUPPLIES)
SMALL-SIGNAL FREQUENCY RESPONSE
(VARIOUS CF)
2
1
3
2
1
V = ±15
CC
C
F
= 0 pF
0
0
−1
−2
−3
−1
V = 5
CC
−2
−3
−4
C
F
= 1 pF
−4
−5
−6
−7
−8
−5
−6
−7
−8
Gain = 1,
= 800 Ω,
R
L
R = 390 Ω,
f
V = 63 mV
−9
I
PP
−10
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
Figure 3.
Figure 4.
6
Copyright © 2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL TRANSIENT RESPONSE
(VARIOUS CL)
(DIFFERENTIAL IN/SINGLE OUT)
5
4
3
1
0.5
0
Gain = 1,
R = 800 Ω,
C
L
= 10 pF
V
O+
O−
L
V
CC
= ±5 V,
V = 63 mV
,
I
PP
2
1
R = 390 Ω
f
V
−0
−0.5
0.5
0
C
L
= 0 pF
−1
−2
−3
−4
−5
−6
V (Diff)
I
−0.5
−1
−7
−8
100 k
1 M
10 M
100 M
1 G
0.2
0.3
0.4
0.5
0.6
0
0.1
f − Frequency − Hz
t − Time − µs
Figure 5.
Figure 6.
COMMON-MODE REJECTION RATIO
vs
LARGE-SIGNAL FREQUENCY RESPONSE
FREQUENCY
5
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
R = 1 kΩ,
f
V
= ±15 V
V
CC
= ±5 V
CC
0
−5
−10
−15
−20
−25
V
= ±5 V
CC
Gain = 1
R = 390 Ω,
f
V
= 5 V
CC
R
L
C
F
= 800 Ω,
= 0 pF,
V = 0.2 V
I
RMS
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
Copyright © 2000–2011, Texas Instruments Incorporated
7
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
(SHUTDOWN STATE)
FREE-AIR TEMPERATURE
940
920
900
880
860
840
15
14.5
14
V
CC
= ±15 V
13.5
13
12.5
12
V
CC
= ±5 V
11.5
11
820
800
10.5
10
−40
−20
0
20
40
60
80
100
−50
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature (Shutdown State) − °C
Figure 9.
Figure 10.
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
SETTLING TIME
2.4
2.35
2.3
2.04
2.02
2
I
IB+
R
C
= 510 Ω
= 1 pF,
= 5 V
F
2.25
2.2
1.98
1.96
1.94
F
V
V
CC
= 4 V
O
PP
R
L
= 800 Ω
2.15
2.1
I
IB−
1.92
1.9
2.05
−50
−25
0
25
50
75
100
0
25
50
75
100
125
150
T
A
− Free-Air Temperature − °C
t − Time − ns
Figure 11.
Figure 12.
8
Copyright © 2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY (DIFFERENTIAL OUT)
LARGE-SIGNAL TRANSIENT RESPONSE
−40
−50
−60
−70
−80
−90
−100
2.5
2
Gain = 1,
R = 330 Ω,
V +
O
f
R
L
= 400 Ω
1.5
1
G = 1,
R = 390 Ω,
f
R
L
C
F
C
L
= 800 Ω,
= 0 pF,
= 10 pF,
= 2 V,
= ±15 V
5
V
= 5 V
CC
0
V
V
T
I_Peak
−5
−1
−1.5
−2
−2.5
CC
= 25°C
A
V
= −5 V
CC
V −
O
10 k
100 k
1 M
10 M
100 M
0
40
80
120
160
200
f − Frequency (Differential Out) − Hz
t − Time − nS
Figure 13.
Figure 14.
TOTAL HARMONIC DISTORTION
SECOND-HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
−30
−40
−20
−30
−40
−50
−60
−70
−80
−90
−100
V
R
= 2 V
PP,
= 800 Ω,
Single Ended Input
Differential Output
O
V
OUT
= 2 V
PP
L
R = 390 Ω,
G = 1
f
−50
−60
V
CC
= 5 V
V
CC
= 5 V to ± 5 V
−70
−80
−90
V
= ± 15 V
CC
−100
−110
V
CC
= ±15V, ±5V
100k
1M
10M
100 k
1 M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 15.
Figure 16.
Copyright © 2000–2011, Texas Instruments Incorporated
9
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SECOND-HARMONIC DISTORTION
SECOND-HARMONIC DISTORTION
vs
vs
FREQUENCY
OUTPUT VOLTAGE
−92
−94
−96
−98
−30
−40
f = 250 KHz
= 800 Ω,
Single Ended Input
Differential Output
V
R
= 4 V
PP,
= 800 Ω,
O
V
= ±5 V
CC
R
L
L
R = 390 Ω,
f
R = 390 Ω,
G = 1
f
G = 1
−50
V
CC
= 5 V
V
CC
= ±5 V
−60
V
CC
= ±15 V
−70
−100
−102
−104
−106
−80
V
CC
= ±15 V
−90
Single Ended Input
Differential Output
−100
−110
0
1
2
3
4
5
6
7
100 k
1 M
10 M
V
O
− Output Voltage − V
f − Frequency − Hz
Figure 17.
Figure 18.
SECOND-HARMONIC DISTORTION
THIRD-HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE
FREQUENCY
−88
−90
−30
−40
V
CC
= ±15 V
V = 4 V
O PP
R
L
= 800 Ω,
R = 390 Ω,
f
V
CC
= ±5 V
G = 1
−92
−50
−94
V
CC
= ±5 V
−60
−96
V
CC
= ±15 V
−70
−98
−80
V
= 5 V
CC
−100
−102
−104
−106
−90
f = 500 KHz
= 800 Ω,
R
L
Single Ended Input
Differential Output
−100
−110
Single Ended Input
Differential Output
R = 390 Ω,
f
G = 1
0
1
2
3
4
5
6
7
100 k
1 M
10 M
V
O
− Output Voltage − V
f − Frequency − Hz
Figure 19.
Figure 20.
10
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TYPICAL CHARACTERISTICS (continued)
THIRD-HARMONIC DISTORTION
THIRD-HARMONIC DISTORTION
vs
vs
FREQUENCY
OUTPUT VOLTAGE
−30
−40
−88
−90
V
R
= 2 V ,
PP
= 800 Ω,
O
L
V
CC
= ±15 V
R = 390 Ω,
f
Gain = 1
−92
−50
−94
V
= ±5 V
Single Ended Input
Differential Output
CC
−60
−96
V
CC
= 5 V
−70
−98
V
= ±15 V
CC
−80
f = 500 KHz
= 800 Ω,
−100
−102
−104
−106
V
CC
= ±5 V
R
L
−90
R = 390 Ω,
f
G = 1
V
CC
= 5 V
−100
−110
Single Ended Input
Differential Output
0
1
2
3
4
5
6
7
100 k
1 M
10 M
f − Frequency − Hz
V
O
− Output Voltage − V
Figure 21.
Figure 22.
THIRD-HARMONIC DISTORTION
VOLTAGE NOISE
vs
vs
OUTPUT VOLTAGE
FREQUENCY
−88
−90
10
f = 250 KHz
= 800 Ω,
R
L
R = 390 Ω,
G = 1
f
V
CC
= ±5 V
−92
−94
−96
V
CC
= 5 V
−98
V
CC
= ±15 V
−100
−102
−104
−106
Single Ended Input
Differential Output
1
10
100
1 k
10 k
100 k
0
1
2
3
4
5
6
7
V
O
− Output Voltage − V
f − Frequency − Hz
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
CURRENT NOISE
INPUT OFFSET VOLTAGE
vs
vs
FREQUENCY
COMMON-MODE OUTPUT VOLTAGE
7E−12
6E−12
1000
800
600
400
200
0
R = 1 k,
f
R
L
= 800 Ω,
G = 1
V
CC
=± 2.5 V
5E−12
4E−12
V
CC
=± 5 V
3E−12
2E−12
V
CC
=± 15 V
−200
1E−12
0
−400
−600
1
10
100
1 k
10 k
100 k
−12
−9
−6
−3
0
3
6
9
12
f − Frequency − Hz
V
OCM
− Common-Mode Output Voltage − V
Figure 25.
Figure 26.
OUTPUT VOLTAGE
vs
OUTPUT IMPEDANCE
vs
DIFFERENTIAL LOAD RESISTANCE
FREQUENCY
15
10
5
100
10
R = 1 k
G = 2
V
CC
=± 5 V
f
V
= ±15 V
= ±5 V
CC
V
OUT+
V
CC
CC
V
OUT+
0
V
OUT−
V
= ±5 V
−5
1
V
OUT−
−10
−15
V
CC
= ±15 V
0.1
100 k
1 M
10 M
100 M
1 G
100
1000
10 k
100 k
f − Frequency − Hz
R
L
− Differential Load Resistance − Ω
Figure 27.
Figure 28.
12
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APPLICATION INFORMATION
RESISTOR MATCHING
Resistor matching is important in fully-differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistor. CMRR, PSRR, and cancellation of the second-harmonic distortion
diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCMpin, it is set to the midrail voltage
internally defined as:
ǒVCC)Ǔ ) ǒVCC–Ǔ
2
(1)
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM
pin as a bypass capacitor. Figure 29 shows the simplified diagram of the THS413x.
V
CC+
Output Buffer
V
IN−
x1
V
V
OUT+
C
R
R
V
IN+
Vcm Error
Amplifier
+
_
C
x1
OUT−
Output Buffer
V
CC+
30 kΩ
V
CC−
30 kΩ
V
CC−
V
OCM
Figure 29. THS413x Simplified Diagram
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DATA CONVERTERS
Data converters are one of the most popular applications for the fully-differential amplifiers. Figure 30 shows a
typical configuration of a fully-differential amplifier attached to a differential analog-to-digital converter (ADC).
V
DD
V
CC
5 V
AV
DV
DD
DD
V
IN
+
−
A
A
IN1
V
OCM
IN2
+
0.1 µF
−
AV
V
ref
SS
−5 V
V −
CC
Figure 30. Fully-Differential Amplifier Attached to a Differential ADC
Fully-differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.
If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the
amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input
terminal of the amplifier should not exceed the common-mode input voltage range.
V
DD
V
CC
5 V
AV
DV
DD
DD
V
IN
+
−
A
A
IN1
V
OCM
IN2
+
−
0.1 µF
AV
V
ref
SS
Figure 31. Fully-Differential Amplifier Using a Single Supply
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Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the circuit configuration of Figure 32 is suggested to bring the common-mode input voltage within
the specifications of the amplifier.
V
DD
V
CC
R
f
V
CC
R
PU
5 V
R
g
V
V
OUT
AV
AV
DV
DD
DD
V
IN
+
−
V
A
A
P
IN1
V
OCM
THS1206
IN2
+
−
0.1 µF
V
ref
SS
R
g
OUT
R
PU
V
CC
R
f
Figure 32. Circuit With Improved Common-Mode Input Voltage
Equation 2 is used to calculate RPU
:
V
– V
P
ǒVIN PǓ ) ǒVCC
PǓ
R
+
PU
1
RG
1
RF
– V
– V
OUT
(2)
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS413x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 33. A minimum value of 20 Ω should work well for most applications. For
example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
390 Ω
20 Ω
Output
390 Ω
THS413x
20 Ω
390 Ω
Output
390 Ω
Figure 33. Driving a Capacitive Load
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ACTIVE ANTIALIAS FILTERING
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 34 presents a
method by which the noise may be filtered in the THS413x.
C1
R2
V
CC
R4
+
C3
C3
R1
R1
R3
R3
−
+
V
−
V
V
+
IN
IN
R
(t)
THS413x
C2
THS1050
−
Vs
−
+
IN
V
+
IN
V
OCM
V
OCM
V
IC
R4
V −
CC
+
C1
R2
Figure 34. Antialias Filtering
The transfer function for this filter circuit is:
ȡ
ȣ
Rt
ȡ
ȣ
2R4 ) Rt
K
R2
R1
ȧ
ȧ
ȧx
H (f) + ȧ
Where K +
ȧ
j2πfR4RtC3ȧ
d
–ǒ
Ǔ2
jf
1 )
f
1
Ȣ
2R4 ) Rt Ȥ
)
) 1
FSF x fc
Q FSF x fc
(3)
(4)
Ǹ
2 x R2R3C1C2
R3C1 ) R2C1 ) KR3C1
1
FSF x fc +
and Q +
Ǹ
2π 2 x R2R3C1C2
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
2
ǸRe2
|
|
) Im
2
2
ǸRe
|
|
FSF +
) Im
and Q +
2Re
(5)
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
Ǹ
2 x mn
1
FSF x fc +
and Q +
Ǹ
(
)
1 ) m 1 ) K
2πRC 2 x mn
(6)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
16
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PRINCIPLES OF OPERATION
THEORY OF OPERATION
The THS413x is a fully-differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully-differential amplifiers are differential in/differential out.
Differential Amplifier
THS413x
Fully differential Amplifier
R
f
V
CC+
R
R
(g)
_
_
+
V
V
V
IN−
O+
+
_
V
IN+
O−
+
(g)
R
f
V
OCM
V
CC−
Figure 35. Differential Amplifier Versus a Fully-Differential Amplifier
To understand the THS413x fully-differential amplifiers, the definition for the pin outs of the amplifier are
provided.
ǒV Ǔ ǒV Ǔ
)
I)
I–
ǒVI)Ǔ – ǒVI–Ǔ
Input voltage definition
V
+
V
+
ID
IC
2
(7)
ǒVO)Ǔ ) ǒVO–Ǔ
ǒVO)Ǔ – ǒVO–Ǔ
Output voltage definition
V
+
V
+
OD
OC
2
(8)
Transfer function
V
+ V
x A
ǒ Ǔ
f
OD
ID
(9)
Output common mode voltage V
+ V
OC
OCM
(10)
Differential Structure Rejects
Coupled Noise at The Input
Differential Structure Rejects
Coupled Noise at The Output
V
CC+
_
V
V
V
IN−
O+
+
_
V
IN+
O−
+
Differential Structure Rejects
Coupled Noise at The Power Supply
V
OCM
V
CC−
Figure 36. Definition of the Fully-Differential Amplifier
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Figure 37 and Figure 38 depict the differences between the operation of the THS413x fully-differential amplifier in
two different modes. Fully-differential amplifiers can work with differential input or can be implemented as single
in/differential out.
R
f
V
CC+
R
(g)
(g)
V
V
IN−
−
+
V
V
O+
+
−
Vs
O−
IN+
V
OCM
R
V
CC−
R
f
Note: For proper operation, maintain symmetry by setting
R 1 = R 2 = R and R 1 = R 2 = R A = R /R
f
f
f
(g)
(g)
(g)
f
(g)
Figure 37. Amplifying Differential Signals
R
f
V
CC+
RECOMMENDED RESISTOR VALUES
R
R
(g)
V
V
IN−
GAIN
R
(g)
Ω
R Ω
f
−
+
V
V
O+
+
−
1
2
5
10
390
374
402
402
390
750
2010
4020
O−
IN+
V
OCM
(g)
Vs
V
CC−
R
f
Figure 38. Single In With Differential Out
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
1
2
V
+
V
O
I
(11)
The second output is equal and opposite in sign:
1
2
V
+ –
V
O
I
(12)
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Fully-differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully-differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it is not as practical to feed a 2-VPP signal into the
targeted ADC. Using a fully-differential amplifier enables the user to break down the output into two 1-VPP signals
with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been
able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully-differential amplifier. The
final result indicates twice as much dynamic range. Figure 39 illustrates the increase in dynamic range. The gain
factor should be considered in this scenario. The THS413x fully-differential amplifier offers an improved CMRR
and PSRR due to its symmetrical input and output. Furthermore, second-harmonic distortion is improved. Second
harmonics tend to cancel because of the symmetrical output.
a
V = 1−0 = 1
OD
V
CC+
+1
_
V
V
V
IN−
O+
+
_
0
V
+1
IN+
O−
+
0
V
OCM
V
OD
= 0−1 = −1
V
CC−
b
Figure 39. Fully-Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully-differential amplifier is selected
by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the
differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the
fully-differential amplifier. Figure 40 depicts the general format of instrumentation amplifiers.
The general transfer function for this circuit is:
V
R
OD
– V
f
2R2
R1
ǒ1 )
Ǔ
+
V
R
IN1
IN2
(g)
(13)
THS4012
R
(g)
R
f
+
_
V
IN1
R2
_
+
R1
R2
THS413x
_
+
V
IN2
R
(g)
R
f
THS4012
Figure 40. Instrumentation Amplifier
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CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high-frequency performance of the THS413x, follow proper printed-circuit board (PCB)
high-frequency design techniques. A general set of guidelines is given below. In addition, a THS413x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
•
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
•
•
Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often lead to stability problems. Surface-mount packages soldered directly to
the printed-circuit board are the best implementation.
Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
•
Surface-mount passive components—Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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POWER-DOWN MODE
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS413x is an active low terminal. If it is left as a no-connect terminal, the device always stays on due to an
internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC– = –5 V, then the device is on when PD reaches –3.6 V, (–5 V
+ 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal
to VCC– in order to turn the device off. Figure 41 shows the simplified version of the power-down circuit. While in
the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically
greater than 1 MΩ in the power-down state.
V
CC
50 kΩ
To Internal Bias
Circuitry Control
PD
V
CC−
Figure 41. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed loop output impedance is shown in Figure 42.
2200
V
CC
=± 5 V
G = 1
R = 1 kΩ
f
PD = V
CC−
1200
200
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
Figure 42. Output Impedance (In Power-Down) vs Frequency
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GENERAL PowerPAD DESIGN CONSIDERATIONS
The THS413x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted (see Figure 43a and Figure 43b). This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package (see Figure 43c). Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the previously awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, (PowerPAD Thermally-Enhanced Package SLMA002). This document
can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A. The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from
VCC– to VCC+. Typically, the thermal pad is connected to the ground plane becase this plane tends to physically be the
largest and is able to dissipate the most amount of heat.
Figure 43. Views of Thermally-Enhanced DGN Package
22
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2010) to Revision H
Page
•
Changed footnote A in Figure 43 ........................................................................................................................................ 22
Changes from Revision F (January 2006) to Revision G
Page
•
Changed DGK package specifications in the Dissipation Rating table ................................................................................ 2
Copyright © 2000–2011, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
THS4130CD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
4130C
THS4130CDG4
THS4130CDGK
THS4130CDGKG4
ACTIVE
ACTIVE
ACTIVE
D
75
80
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
0 to 70
4130C
ATP
VSSOP
VSSOP
DGK
DGK
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
ATP
THS4130CDGKR
THS4130CDGKRG4
THS4130CDGN
OBSOLETE
OBSOLETE
ACTIVE
VSSOP
VSSOP
DGK
DGK
DGN
8
8
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
ATP
MSOP-
PowerPAD
80
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
AOB
AOB
AOB
AOB
4130I
4130I
ASO
ASO
ASO
ASO
AOC
AOC
THS4130CDGNG4
THS4130CDGNR
THS4130CDGNRG4
THS4130ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
DGN
D
8
8
8
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU | Call TI
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
MSOP-
PowerPAD
2500
2500
75
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
THS4130IDG4
D
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
THS4130IDGK
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
DGN
DGN
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
THS4130IDGKG4
THS4130IDGKR
THS4130IDGKRG4
THS4130IDGN
80
Green (RoHS
& no Sb/Br)
2500
2500
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
THS4130IDGNG4
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
THS4130IDGNR
THS4130IDGNRG4
THS4130IDR
ACTIVE
MSOP-
PowerPAD
DGN
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
AOC
AOC
4130I
4130I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
D
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
THS4130IDRG4
THS4131CD
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
4131C
4131C
ATQ
THS4131CDG4
THS4131CDGK
THS4131CDGKG4
THS4131CDGKR
THS4131CDGKRG4
THS4131CDGN
THS4131CDGNG4
THS4131CDGNR
THS4131CDGNRG4
THS4131CDR
SOIC
D
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
0 to 70
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
0 to 70
80
Green (RoHS
& no Sb/Br)
0 to 70
ATQ
2500
2500
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
0 to 70
ATQ
Green (RoHS
& no Sb/Br)
0 to 70
ATQ
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
0 to 70
AOD
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
0 to 70
AOD
MSOP-
PowerPAD
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
0 to 70
AOD
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
0 to 70
AOD
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
0 to 70
4131C
4131C
4131I
4131I
THS4131CDRG4
THS4131ID
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
0 to 70
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
-40 to 85
-40 to 85
THS4131IDG4
D
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
THS4131IDGK
THS4131IDGKG4
THS4131IDGKR
THS4131IDGKRG4
THS4131IDGN
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
DGK
8
8
8
8
8
8
8
8
8
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ASP
ASP
ASP
ASP
AOE
AOE
AOE
AOE
4131I
4131I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
DGK
DGK
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
2500
2500
80
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
THS4131IDGNG4
THS4131IDGNR
THS4131IDGNRG4
THS4131IDR
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
CU NIPDAU
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
THS4131IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4130CDGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4130IDGKR
THS4130IDGNR
VSSOP
DGK
DGN
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
MSOP-
Power
PAD
THS4130IDR
THS4131CDGKR
THS4131CDGNR
SOIC
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
5.3
5.3
5.2
3.4
3.4
2.1
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
VSSOP
DGK
DGN
MSOP-
Power
PAD
THS4131CDR
THS4131IDGKR
THS4131IDGNR
SOIC
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
5.3
5.3
5.2
3.4
3.4
2.1
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
VSSOP
DGK
DGN
MSOP-
Power
PAD
THS4131IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4130CDGNR
THS4130IDGKR
THS4130IDGNR
THS4130IDR
MSOP-PowerPAD
VSSOP
DGN
DGK
DGN
D
8
8
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
358.0
358.0
358.0
367.0
358.0
358.0
367.0
358.0
358.0
367.0
335.0
335.0
335.0
367.0
335.0
335.0
367.0
335.0
335.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
MSOP-PowerPAD
SOIC
THS4131CDGKR
THS4131CDGNR
THS4131CDR
VSSOP
DGK
DGN
D
MSOP-PowerPAD
SOIC
THS4131IDGKR
THS4131IDGNR
THS4131IDR
VSSOP
DGK
DGN
D
MSOP-PowerPAD
SOIC
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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