THS4211DRBR [TI]
LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER; 低失真高速电压反馈放大器
| 型号： | THS4211DRBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER |
| 文件： | 总41页 (文件大小：1560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4211
DGN-8 DGK-8
D-8
DRB-8
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
LOW-DISTORTION, HIGH-SPEED, VOLTAGE FEEDBACK AMPLIFIER
FEATURES
DESCRIPTION
•
•
•
•
Unity Gain Stability
The THS4211 and THS4215 are high slew rate, unity
gain stable voltage feedback amplifiers designed to
run from supply voltages as low as 5 V and as high
as 15 V. The THS4215 offers the same performance
as the THS4211 with the addition of power-down
capability. The combination of high slew rate, wide
bandwidth, low distortion, and unity gain stability
make the THS4211 and THS4215 high performance
devices across multiple ac specifications.
Wide Bandwidth: 1 GHz
High Slew Rate: 970 V/µs
Low Distortion
– –90 dBc THD at 30 MHz
– 130 MHz Bandwidth (0.1 dB, G = 2)
– 0.007% Differential Gain
– 0.003° Differential Phase
High Output Drive, IO = 200 mA
Excellent Video Performance
– 130 MHz Bandwidth (0.1 dB, G = 2)
– 0.007% Differential Gain
– 0.003° Differential Phase
Supply Voltages
Designers using the THS4211 are rewarded with
higher dynamic range over a wider frequency band
without the stability concerns of decompensated
amplifiers. The devices are available in SOIC, MSOP
with PowerPAD™, and leadless MSOP with
PowerPAD packages.
•
•
THS4211
•
– +5 V, ±5 V, +12 V, +15 V
Power Down Functionality (THS4215)
Evaluation Module Available
NC
IN-
IN+
NC
1
2
3
4
8
7
6
5
V +
S
•
•
V
OUT
V
S-
NC
APPLICATIONS
•
•
•
•
•
High Linearity ADC Preamplifier
Differential to Single-Ended Conversion
DAC Output Buffer
Active Filtering
Video Applications
RELATED DEVICES
DEVICE
DESCRIPTION
THS4271
THS4503
THS3202
1.4 GHz voltage feedback amplifier
Wideband fully differential amplifier
Dual, wideband current feedback amplifier
Low-Distortion, Wideband Application Circuit
HARMONIC DISTORTION
vs
+5 V
FREQUENCY
50 Ω Source
-50
Gain = 2
R = 392 Ω
50 Ω
-55
-60
f
+
R
L
= 150 Ω
V
V
= 2 V
PP
= ±5 V
O
S
V
O
THS4211
V
-65
I
49.9 Ω
_
-70
-75
-80
-85
-90
-5 V
HD2
HD3
392 Ω
392 Ω
-95
-100
NOTE: Power supply decoupling capacitors not shown
1
10
f - Frequency - MHz
100
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Output current, IO
100 mA
Continuous power dissipation
Maximum junction temperature, TJ
See Dissipation Rating Table
(2)
150°C
125°C
(3)
Maximum junction temperature, continuous operation, long term reliability TJ
Storage temperature range, Tstg
–65°C to 150°C
300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
4000 V
ESD ratings
CDM
MM
1500 V
200 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS(1)
(3)
(2)
POWER RATING
TA≤ 25°C
θJC
(°C/W)
θJA
PACKAGE
(°C/W)
TA= 85°C
410 mW
685 mW
154 mW
873 mW
D (8 pin)
DGN (8 pin)(1)
DGK (8 pin)
DRB (8 pin)
38.3
4.7
54.2
5
97.5
58.4
260
1.02 W
1.71 W
385 mW
2.18 W
45.8
(1) The THS4211/5 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
(2) This data was taken using the JEDEC standard High-K test PCB.
(3) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
±2.5
MAX
±7.5
UNIT
V
Dual supply
Supply voltage, (VS+ and VS–
)
Single supply
5
15
Input common-mode voltage range
VS–+ 1.2
VS+ – 1.2
V
2
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
PACKAGING/ORDERING INFORMATION
PACKAGED DEVICES
Non-power-down
THS4211D
PACKAGE TYPE
PACKAGE MARKING
TRANSPORT MEDIA, QUANTITY
Rails, 75
SOIC-8
MSOP-8
—
THS4211DR
Tape and Reel, 2500
Rails, 100
THS4211DGK
THS4211DGKR
THS4211DRBT
THS4211DRBR
THS4211DGN
THS4211DGNR
Power-down
BEJ
BET
BFN
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 80
QFN-8-PP(1)
MSOP-8-PP(1)
Tape and Reel, 2500
THS4215D
Rails, 75
SOIC-8
MSOP-8
—
THS4215DR
Tape and Reel, 2500
Rails, 100
THS4215DGK
THS4215DGKR
THS4215DRBT
THS4215DRBR
THS4215DGN
THS4215DGNR
BEZ
BEU
BFQ
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
Rails, 80
QFN-8-PP(1)
MSOP-8-PP(1)
Tape and Reel, 2500
(1) The PowerPAD is electrically isolated from all other pins.
PIN ASSIGNMENTS
D, DRB, DGK, DGN
D, DRB, DGK, DGN
(TOP VIEW)
(TOP VIEW)
THS4211
THS4215
NC
IN-
IN+
NC
1
2
8
7
REF
IN-
PD
1
2
8
7
V +
S
V +
S
3
4
6
5
V
OUT
3
4
6
5
IN+
V
OUT
V
S-
NC
V
S-
NC
NC = No Connetion
NC = No Connection
See Note A.
NOTE A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin.
3
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS, VS = ±5 V
RF = 392 Ω, RL = 499 Ω, G = +2, unless otherwise noted
TYP
OVER TEMPERATURE
MIN/
PARAMETER
TEST CONDITIONS
TYP/
MAX
0°C to –40°C
70°C to 85°C
25°C
25°C
UNITS
AC PERFORMANCE
G = 1, POUT = –7 dBm
G = –1, POUT = –16 dBm
G = 2, POUT = –16 dBm
G = 5, POUT = –16 dBm
G = 10, POUT = –16 dBm
G = 1, POUT = –7 dBm
G > 10 , f = 1 MHz
1
GHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
325
325
70
Small signal bandwidth
35
0.1 dB flat bandwidth
Gain bandwidth product
Full-power bandwidth
70
350
77
G = –1, VO = 2 Vp
G = 1, VO = 2 V Step
G = –1, VO = 2 V Step
970
850
22
Slew rate
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
G = –1, VO = 4 V Step
55
ns
RL = 150 Ω
RL = 499 Ω
RL = 150Ω
RL = 499 Ω
–78
–90
dBc
dBc
dBc
dBc
Typ
Typ
Typ
Typ
2nd-order harmonic distortion
G = 1, VO = 1 VPP
f = 30 MHz
,
,
–100
–100
3rd-order harmonic distortion
Harmonic distortion
RL = 150 Ω
RL = 499 Ω
RL = 150Ω
RL = 499 Ω
–68
–70
–80
–82
–53
32
dBc
dBc
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
2nd-order harmonic distortion
G = 2, VO = 2 VPP
f = 30 MHz
dBc
3rd-order harmonic distortion
dBc
3rd-order intermodulation (IMD3)
3rd-order output intercept (OIP3)
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
Input voltage noise
G = 2, VO = 2 VPP, RL = 150 Ω, f = 70 MHz
G = 2, VO = 2 VPP, RL = 150 Ω, f = 70 MHz
dBc
dBm
%
0.007
0.003
7
G = 2, RL = 150 Ω
°
f = 1 MHz
nV/√Hz
pA√Hz
Input current noise
f = 10 MHz
4
DC PERFORMANCE
Open-loop voltage gain (AOL
)
VO = ±0.3 V, RL = 499 Ω
70
3
65
12
62
14
60
14
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
Input offset voltage
Average offset voltage drift
Input bias current
±40
18
±40
20
µV/°C
µA
7
15
6
VCM = 0 V
Average bias current drift
Input offset current
±10
7
±10
8
nA/°C
µA
0.3
Average offset current drift
±10
±10
nA/°C
4
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
TYP
OVER TEMPERATURE
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to –40°C
25°C
25°C
UNITS
70°C to 85°C
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
±4
56
±3.8
±3.7
±3.6
V
Min
Min
Typ
Typ
VCM = ± 1 V
52
50
48
dB
MΩ
pF
Common-mode
4
Input capacitance
Common-mode/differential
0.3/0.2
OUTPUT CHARACTERISTICS
Output voltage swing
±4.0
220
170
0.3
±3.8
200
140
±3.7
190
130
±3.6
180
120
V
Min
Min
Min
Typ
Output current (sourcing)
Output current (sinking)
Output impedance
mA
mA
Ω
RL = 10 Ω
f = 1 MHz
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (–PSRR)
±5
19
19
64
65
±7.5
22
±7.5
23
±7.5
24
V
Max
Max
Min
Min
Min
mA
mA
dB
dB
16
15
14
VS+ = 5.5 V to 4.5 V, VS– = 5 V
VS+ = 5 V, VS– = –5.5 V to –4.5 V
58
54
54
60
56
56
POWER-DOWN CHARACTERISTICS (THS4215 ONLY)
Enable
REF+1.8
REF+1
REF–1
REF–1.5
850
V
V
Min
Max
Min
Max
Max
Max
Typ
Typ
Typ
Typ
REF = 0 V, or VS–
Power-down voltage level
Power-down
Enable
V
REF = VS+ or Floating
Power-down
V
PD = Ref +1.0 V, Ref = 0 V
Power-down quiescent current
650
450
4
900
800
1000
900
µA
µA
µs
µs
GΩ
kΩ
PD = Ref –1.5 V, Ref = 5 V
650
Turnon time delay(t(ON)
)
50% of final supply current value
Turnoff time delay (t(Off)
)
50% of final supply current value
3
Input impedance
4
Output impedance
f = 1 MHz
250
5
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS, VS = 5 V
RF = 392 Ω, RL = 499 Ω, G = +2, unless otherwise noted
TYP
OVER TEMPERATURE
MIN/
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
TYP/
MAX
0°C to –40°C
70°C to 85°C
25°C
25°C
UNITS
G = 1, POUT = –7 dBm
G = –1, POUT = –16 dBm
G = 2, POUT = –16 dBm
G = 5, POUT = –16 dBm 65
G = 10, POUT = –16 dBm
G = 1, POUT = –7 dBm
G > 10, f = 1 MHz
980
300
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Small signal bandwidth
30
90
0.1 dB flat bandwidth
Gain bandwidth product
Full-power bandwidth
300
64
G = –1, VO = 2 Vp
G = 1, VO = 2 V Step
G = –1, VO = 2 V Step
800
750
22
Slew rate
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
G = –1, VO = 2 V Step
84
ns
RL = 150 Ω
RL = 499 Ω
RL = 150 Ω
RL = 499 Ω
–60
–60
–68
–68
–70
34
dBc
dBc
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
2nd-order harmonic distortion
3rd-order harmonic distortion
G = 1, VO = 1 VPP
f = 30 MHz
,
dBc
dBc
3rd-order intermodulation (IMD3)
3rd-order output intercept (OIP3)
Input-voltage noise
dBc
G = 1, VO = 1 VPP, RL = 150 Ω , f = 70 MHz
dBm
nV/√Hz
pA/√Hz
f = 1 MHz
7
Input-current noise
f = 10 MHz
4
DC PERFORMANCE
Open-loop voltage gain (AOL
)
VO = ± 0.3 V, RL = 499 Ω
68
3
63
12
60
14
60
14
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
Input offset voltage
Average offset voltage drift
Input bias current
±40
17
±40
18
µV/°C
µA
7
15
6
VCM = VS/2
Average bias current drift
Input offset current
±10
7
±10
8
nA/°C
µA
0.3
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
±10
±10
nA/°C
1/4
54
1.2/3.8 1.3/3.7 1.4/3.6
50 48 45
V
Min
Min
Typ
Typ
VCM = ± 0.5 V, VO = 2.5 V
Common-mode
dB
MΩ
pF
4
Input capacitance
Common-mode/differential
0.3/0.2
OUTPUT CHARACTERISTICS
Output voltage swing
1/4
230
150
0.3
1.2/3.8 1.3/3.7 1.4/3.6
V
Min
Min
Min
Typ
Output current (sourcing)
Output current (sinking)
Output impedance
210
120
190
100
180
90
mA
mA
Ω
RL = 10 Ω
f = 1 MHz
6
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
TYP
OVER TEMPERATURE
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to –40°C
25°C
25°C
UNITS
70°C to 85°C
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (–PSRR)
5
15
22
16
58
60
15
23
15
54
56
15
24
14
54
56
V
Max
Max
Min
Min
Min
19
19
63
65
mA
mA
dB
dB
VS+ = 5.5 V to 4.5 V, VS– = 0 V
VS+ = 5 V, VS– = –0.5 V to 0.5 V
POWER-DOWN CHARACTERISTICS (THS4215 ONLY)
Enable
REF+1.8
REF+1
REF–1
REF–1.5
650
V
V
Min
Max
Min
Max
Max
Max
Typ
Typ
Typ
Typ
REF = 0 V, or VS–
Power-down voltage level
Power down
Enable
V
REF = VS+ or floating
Power down
V
Power-down quiescent current
Power-down quiescent current
PD = Ref +1.0 V, Ref = 0 V
PD = Ref –1.5 V, Ref = 5 V
450
400
4
750
750
850
850
µA
µA
µs
µns
GΩ
kΩ
650
Turnon-time delay(t(ON)
)
50% of final value
Turnoff-time delay (t(Off)
)
3
Input impedance
6
Output impedance
f = 1 MHz
75
7
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small-signal unity gain frequency response
Small-signal frequency response
1
2
0.1 dB gain flatness frequency response
Large-signal frequency response
3
4
Slew rate
vs Output voltage
5
Harmonic distortion
vs Frequency
6, 7, 8, 9
Harmonic distortion
vs Output voltage swing
vs Frequency
10, 11, 12, 13
3rd-order intermodulation distortion
3rd-order output intercept point
Voltage and current noise
Differential gain
14, 16
15, 17
18
vs Frequency
vs Frequency
vs Number of loads
vs Number of loads
19
Differential phase
20
Settling time
21
Quiescent current
vs supply voltage
22
Output voltage
vs Load resistance
vs Capacitive load
vs Frequency
23
Frequency response
24
Open-loop gain and phase
Open-loop gain
25
vs Case temperature
vs Frequency
26
Rejection ratios
27
Rejection ratios
vs Case temperature
vs Input common-mode range
vs Case temperature
vs Case temperature
28
Common-mode rejection ratio
Input offset voltage
29
30
Input bias and offset current
Small signal transient response
Large signal transient response
Overdrive recovery
31
32
33
34
Closed-loop output impedance
Power-down quiescent current
Power-down output impedance
Turnon and turnoff delay times
vs Frequency
35
vs Supply voltage
vs Frequency
36
37
38
8
THS4211
THS4215
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SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
Table of Graphs (5 V)
FIGURE
Small-signal unity gain frequency response
Small-signal frequency response
39
40
0.1 dB gain flatness frequency response
Large signal frequency response
41
42
Slew rate
vs Output voltage
43
Harmonic distortion
vs Frequency
44, 45, 46, 47
Harmonic distortion
vs Output voltage swing
vs Frequency
48, 49, 50, 51
3rd-order intermodulation distortion
3rd-order intercept point
Voltage and current noise
Settling time
52, 54
53, 55
56
vs Frequency
vs Frequency
57
Quiescent current
vs Supply voltage
58
Output voltage
vs Load resistance
vs Capacitive load
vs Frequency
59
Frequency response
60
Open-loop gain and phase
Open-loop gain
61
vs Case temperature
vs Frequency
62
Rejection ratios
63
Rejection ratios
vs Case temperature
vs Input common-mode range
vs Case temperature
vs Case temperature
64
Common-mode rejection ratio
Input offset voltage
65
66
Input bias and offset current
Small signal transient response
Large signal transient response
Overdrive recovery
67
68
69
70
Closed-loop output impedance
Power-down quiescent current
Power-down output impedance
Turnon and turnoff delay times
vs Frequency
71
vs Supply voltage
vs Frequency
72
73
74
9
THS4211
THS4215
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SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY
RESPONSE
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
22
20
18
16
14
0.1
0
5
4
3
2
1
0
Gain = 1
Gain = 10
Gain = 5
R
= 499 Ω
= 250 mV
= ±5 V
L
-0.1
V
V
O
S
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
R
L
= 499 Ω
12
10
R = 392 Ω
f
V
V
= 250 mV
= ±5 V
O
S
8
6
4
2
0
Gain = 2
-1
Gain = 1
-2
R
= 499 Ω
= 250 mV
= ±5 V
L
-0.8
V
V
O
S
-3
-4
Gain = -1
-0.9
-1
-2
-4
100 k
100 k
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
1 M
1 G
10 M
100 M
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 1.
Figure 2.
Figure 3.
SLEW RATE
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
LARGE SIGNAL FREQUENCY
RESPONSE
vs
FREQUENCY
1400
1200
1000
800
600
400
200
0
-60
-65
1
0
Gain = 1
Rise, Gain = 1
V
V
= 1 V
PP
= ±5 V
O
S
Fall, Gain = 1
HD3, R = 150 Ω
-70
-75
L
and R = 499 Ω
L
-1
HD2, R = 150 Ω
L
-80
-85
-90
Fall, Gain =- 1
Rise, Gain = -1
-2
-3
-4
HD2, R = 499 Ω
L
Gain = 1
R
V
V
= 499 Ω
= 2 V
PP
= ±5 V
L
O
S
R = 499 Ω
L
R = 392 Ω
f
-95
V
= ±5 V
S
-100
100 k
1 M
10 M
100 M
1 G
1
10
100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
f - Frequency - Hz
f - Frequency - MHz
V
- Output Voltage - V
O
Figure 4.
Figure 5.
Figure 6.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
-50
-55
-50
-55
-60
-65
-70
-55
-60
Gain = 1
HD3, R = 150 Ω
Gain = 2
Gain = 2
L
V
V
= 2 V
PP
= ±5 V
O
S
and R = 499 Ω
R = 392 Ω
R = 392 Ω
L
f
f
V
V
= 1 V
PP
= ±5 V
V
V
= 2 V
PP
= ±5 V
-60
-65
-70
O
S
O
S
-65
-70
-75
-80
-85
HD2, R = 499 Ω
L
HD3, R = 150Ω,
L
HD2, R = 499Ω
L
and R = 499 Ω
L
-75
-75
HD2, R = 150 Ω
L
HD2, R = 150Ω
L
HD2, R = 499Ω
L
-80
-85
-80
-85
HD3, R = 150Ω,
L
and R = 499 Ω
L
HD2, R = 150Ω
L
-90
-95
-90
-90
-95
-95
-100
-100
-100
10
100
1
1
10
100
1
10
100
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 7.
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
-50
-55
-60
-65
-70
-75
-80
-85
-90
-70
-75
-80
-85
-90
-65
-70
-75
-80
-85
Gain = 1
f= 8 MHz
Gain = 2
Gain = 1
f= 32 MHz
R = 249 Ω
f
HD3, R = 150Ω
HD3, R = 150Ω
L
L
V
= ±5 V
f = 8 MHz
S
V
= ±5 V
HD2, R = 499Ω
S
L
HD3, R = 499Ω
V = ±5 V
S
L
HD2, R = 499Ω
L
HD3, R = 150Ω
L
HD2, R = 150Ω
L
HD2, R = 150Ω
L
HD3, R = 499Ω
L
HD2, R = 150Ω
-90
-95
L
HD2, R = 499Ω
L
-95
-95
HD3, R = 499Ω
L
-100
-100
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
- Output Voltage Swing - ±V
V
- Output Voltage Swing - ±V
V
- Output Voltage Swing - ±V
O
O
O
Figure 10.
Figure 11.
Figure 12.
THIRD ORDER INTERMODULATION
THIRD ORDER OUTPUT
INTERCEPT POINT
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
DISTORTION
vs
FREQUENCY
FREQUENCY
60
55
50
45
40
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-45
Gain = 1
Gain = 2
HD3, R = 150Ω
L
Gain = 1
-50
-55
-60
-65
-70
R = 249 Ω
R
V
= 150 Ω
= ±5 V
f
L
R
L
= 150 Ω
f = 32 MHz
S
HD3, R = 499Ω
V
= ±5 V
L
S
V
= ±5 V
S
200 kHz Tone Spacing
200 kHz Tone Spacing
HD2, R = 499Ω
L
V
= 2 V
PP
O
-75
-80
V
= 1 V
PP
O
HD2, R = 150Ω
L
-85
V
= 2 V
PP
O
-90
35
30
-95
-95
V
= 1 V
PP
O
-100
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
20
40
60
80
100
10
100
V
- Output Voltage Swing - ±V
O
f - Frequency - MHz
f - Frequency - MHz
Figure 13.
Figure 14.
Figure 15.
THIRD ORDER INTERMODULATION
THIRD ORDER OUTPUT
INTERCEPT POINT
vs
DISTORTION
vs
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
-40
100
60
55
50
45
40
35
100
Gain = 2
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
Gain = 2
R
= 150 Ω
= ±5 V
L
R
= 150 Ω
= ±5 V
L
V
S
V
S
200 kHz Tone Spacing
200 kHz Tone Spacing
V
n
V
= 1 V
PP
10
O
10
V
= 2 V
PP
O
I
n
V
= 2 V
PP
O
30
25
20
V
= 1 V
PP
O
-95
1
1
-100
1 k
10 k
100 k
1 M
10 M
100 M
10
100
0
20
40
60
80
100
f - Frequency - Hz
f - Frequency - MHz
f - Frequency - MHz
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
SETTLING TIME
0.030
0.025
0.020
0.015
0.010
0.005
0
3
2
1
0
0.20
0.18
Gain = 2
Gain = 2
R = 392 Ω
R = 392 Ω
f
f
V
= ±5 V
S
V
= ±5 V
0.16
0.14
S
Rising Edge
Gain = -1
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
°
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
0.12
0.10
0.08
0.06
0.04
R
L
= 499 Ω
PAL
R = 392 Ω
f
PAL
f= 1 MHz
NTSC
-1
V
= ±5 V
S
NTSC
Falling Edge
-2
-3
0.02
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
0
1
2
3
4
5
6
7
8
Number of Loads - 150 Ω
t - Time - ns
Number of Loads - 150 Ω
Figure 19.
Figure 20.
Figure 21.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
22
1
5
4
3
2
1
V
=±5 V
S
R
C
= 10 Ω
(ISO)
= 100 pF
0.5
T
A
= 85°C
L
20
18
T
A
= 25°C
0
R
= 15 Ω
-0.5
(ISO)
= 50 pF
C
L
T
= -40°C
T
A
= -40 to 85°C
A
-1
-1.5
-2
16
14
0
R
= 25 Ω
(ISO)
= 10 pF
-1
C
L
-2
-3
12
10
-2.5
-3
-4
-5
100 k
1 M
10 M
100 M
1 G
10
100
1000
2.5
3
3.5
4
4.5
5
R
L
- Load Resistance - Ω
V
- Supply Voltage - ±V
Capacitive Load - Hz
S
Figure 22.
Figure 23.
Figure 24.
OPEN-LOOP GAIN AND PHASE
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
REJECTION RATIOS
vs
vs
FREQUENCY
FREQUENCY
90
80
70
180
160
V
= ±5 V
S
V
= ±5 V
S
70
60
50
40
30
T
= 25°C
PSRR-
A
60
50
85
80
T
A
= 85°C
140
120
CMRR
40
30
100
80
75
70
T
= -40°C
A
60
40
20
10
PSRR+
20
10
0
65
60
20
0
0
-10
10 k
2.5
3
3.5
4
4.5
5
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
Case Temperature - °C
f - Frequency - Hz
f - Frequency - Hz
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
REJECTION RATIOS
COMMON-MODE REJECTION RATIO
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
vs
vs
CASE TEMPERATURE
INPUT COMMON-MODE RANGE
80
70
9
8
7
6
5
4
60
55
50
45
40
35
30
25
20
15
10
V
= ±5 V
S
PSRR-
V
= ±5 V
60
50
40
30
20
10
0
S
CMMR
PSRR+
V
= 5 V
S
3
2
V
T
A
= ±5 V
= 25°C
S
1
5
0
0
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
-4.5
-3
-1.5
0
1.5
3
4.5
Case Temperature - °C
T
C
- Case Temperature - °C
Input Common-Mode Range - V
Figure 28.
Figure 29.
Figure 30.
INPUT BIAS AND OFFSET
CURRENT
vs
SMALL SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
CASE TEMPERATURE
0.7
6.6
6.5
6.4
0.12
0.1
1.5
1
V
= ±5 V
S
0.65
0.6
0.08
0.06
0.04
6.3
0.55
0.5
I
0.5
0
IB-
6.2
6.1
0.02
0
I
OS
0.45
0.4
-0.02
-0.04
-0.06
-0.08
-0.1
6
Gain = -1
Gain = -1
R = 499 Ω
L
R = 392 Ω
f
-0.5
-1
0.35
5.9
I
IB+
R
L
= 499 Ω
R =392 Ω
f
5.8
5.7
0.3
t /t = 300 ps
t /t = 300 ps
r
f
r
f
0.25
0.2
V
= ±5 V
V
= ±5 V
S
S
5.6
-1.5
-0.12
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
-2
0
2
4
6
8 10 12 14 16 18 20
-1
0
1
2
3
4
5
6
7
8
9
10
T
C
- Case Temperature - °C
t - Time - ns
t - Time - ns
Figure 31.
Figure 32.
Figure 33.
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
POWER-DOWN QUIESCENT
CURRENT
vs
OVERDRIVE RECOVERY
FREQUENCY
SUPPLY VOLTAGE
800
6
5
100 k
3
R
R
= 499 Ω,
= 392 Ω,
= -4 dBm
L
2.5
2
V
= ±5 V
S
T
A
= 85°C
700
600
F
10 k
1 k
4
3
P
V
IN
S
1.5
1
= ±5 V
2
1
500
400
0.5
100
10
T
A
= 25°C
0
0
T
A
= -40°C
-1
-0.5
-1
300
200
100
0
-2
-3
-4
1
-1.5
-2
0.1
-5
-6
-2.5
-3
0.01
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
100 k
1 M
10 M
100 M
1 G
2.5
3
3.5
4
4.5
5
t - Time - µs
f - Frequency - Hz
V
- Supply Voltage - ±V
S
Figure 34.
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
POWER-DOWN
OUTPUT IMPEDANCE
vs
TURNON AND TURNOFF TIMES
DELAY TIME
FREQUENCY
0.04
0.035
0.03
6
Gain = 1
4.5
R
L
= 499 Ω
= -1 dBm
= ±5 V
1000
10
P
V
IN
S
3
1.5
0.025
0.02
0.015
0.01
0
-1.5
-3
Gain = -1
R
L
= 499 Ω
= ±5 V
V
S
0.1
-4.5
-6
0.005
0
0.001
-7.5
-0.005
100 k 1 M
10 M
100 M
1 G
10 G
-0.01
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07
f - Frequency - Hz
t - Time - ns
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS (5 V Graphs)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
SMALL SIGNAL
FREQUENCY RESPONSE
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
22
20
18
16
14
12
10
4
3
2
1
0
0.1
Gain = 1
0
Gain = 10
Gain = 5
= 499 Ω
R
L
= 499 Ω
= 250 mV
= 5 V
-0.1
V
V
O
S
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
R
L
R = 392 Ω
f
V
V
= 250 mV
= 5 V
O
S
8
6
4
2
-1
Gain = 2
Gain = 1
-2
R
= 499 Ω
= 250 mV
= 5 V
L
-0.8
-0.9
-1
V
V
O
S
0
-2
-4
-3
-4
Gain = -1
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 39.
Figure 40.
Figure 41.
SLEW RATE
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
LARGE SIGNAL
FREQUENCY RESPONSE
vs
FREQUENCY
1
0
1000
900
800
700
600
500
400
300
200
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
Fall, G = 1
Gain = 1
= 1 V
V
O
PP
R
L
= 150 Ω, and 499 Ω
Rise, G = 1
V
= 5 V
S
-1
Rise, G = -1
Fall, G = -1
HD2
-2
HD3
Gain = 1
R
L
= 499 Ω
-3
-4
R = 499 Ω
L
R = 392 Ω
f
V
V
= 2 V
= 5 V
O
S
PP
100
0
V
= 5 V
S
1
10
100
100 K
1 M
10 M
100 M
1 G
0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
f - Frequency - MHz
V
O
- Output Voltage -V
f - Frequency - Hz
Figure 42.
Figure 43.
Figure 44.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
-40
-50
-60
-70
-80
-30
-40
-50
-60
-40
-45
Gain = 1
= 2 V
V
O
PP
-50
R
L
= 150 Ω, and 499 Ω
V
= 5 V
S
-55
-60
HD2
HD2
HD3
HD3
-65
-70
-75
-80
HD3
HD2
-70
-80
-90
Gain = 2
Gain = 2
V
= 2 V
V
= 1 V
O
PP
O
PP
R = 392 Ω
R = 392 Ω
-90
f
f
R
L
= 150 Ω and 499 Ω
R
L
= 150 Ω and 499 Ω
-85
-90
V
= 5 V
V
= 5 V
S
S
-100
10
100
10
100
1
1
1
10
100
f - Frequency - MHz
f - Frequency - MHz
f - Frequency - MHz
Figure 45.
Figure 46.
Figure 47.
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TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
FREQUENCY
-60
-65
-70
-75
-80
-85
-90
-50
-55
-60
-65
-70
-75
-80
-85
-90
-45
-50
-55
-60
-65
-70
-75
-80
HD2
HD3
HD2
HD2
HD3
HD3
Gain = 2
R = 392 Ω
R
f
Gain = 1
Gain = 1
R
= 150 Ω and 499 Ω
L
R
L
= 150 Ω, and 499 Ω,
= 150 Ω, and 499 Ω,
L
f = 8 MHz
= 5 V
-95
f = 8 MHz
f = 32 MHz
= 5 V
-85
-90
-95
V
S
V
= 5 V
V
S
S
-100
-100
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
V
- Output Voltage Swing - V
V
- Output Voltage Swing - V
O
V
- Output Voltage Swing - V
O
O
Figure 48.
Figure 49.
Figure 50.
THIRD ORDER INTERMODULATION
THIRD ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
DISTORTION
vs
POINT
vs
FREQUENCY
FREQUENCY
-40
50
-40
-45
-50
-55
Gain = 1
Gain = 1
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
R
L
= 150 Ω
R
L
= 150 Ω
HD2
V
= 5 V
V
= 5 V
S
S
45
40
35
30
200 kHz Tone Spacing
200 kHz Tone
Spacing
V
= 1V
PP
O
HD3
V
= 2V
O PP
-60
-65
-70
Gain = 2
V
= 2V
PP
O
R = 392 Ω
f
V
= 1V
PP
O
R
L
= 150 Ω and 499 Ω
f = 32 MHz
-75
-80
V
= 5 V
-95
S
-100
0
10 20 30 40 50 60 70 80
0
0.5
1
1.5
2
2.5
10
100
f - Frequency - MHz
V
- Output Voltage Swing - V
f - Frequency - MHz
O
Figure 51.
Figure 52.
Figure 53.
THIRD ORDER INTERMODULATION
THIRD ORDER OUTPUT INTERCEPT
DISTORTION
vs
POINT
vs
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
-30
100
10
1
50
100
Gain = 2
Gain = 1
45
40
35
30
25
20
15
10
R
V
= 150 Ω
= 5 V
-40
-50
-60
-70
R
V
= 150 Ω
= 5 V
L
L
S
S
200 kHz Tone Spacing
200 kHz Tone
Spacing
V
= 1 V
PP
O
V
n
10
V
= 2 V
PP
O
V
= 2 V
PP
O
I
n
-80
-90
V
= 1 V
PP
O
1
-100
1 k
10 k
100 k
1 M
10 M
100 M
10
100
0
20
40
60
80
100
f - Frequency - Hz
f - Frequency - MHz
f - Frequency - MHz
Figure 54.
Figure 55.
Figure 56.
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TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
SETTLING TIME
1.5
2
22
20
18
Rising Edge
1.5
T
A
= 85°C
1
T
A
= 25°C
1
0.5
T
A
= -40°C
Gain = -1
= 499 Ω
0.5
R
L
T
A
= -40 to 85°C
R = 392 Ω
f= 1 MHz
f
16
14
0
0
V
= 5 V
S
-0.5
-0.5
-1
Falling Edge
12
10
-1
-1.5
-2
-1.5
2.5
3
3.5
4
4.5
5
10
100
1000
0
5
10
15
20
25
R
L
- Load Resistance - Ω
t - Time - ns
V
- Supply Voltage - ±V
S
Figure 57.
Figure 58.
Figure 59.
FREQUENCY RESPONSE
vs
OPEN-LOOP GAIN AND PHASE
OPEN-LOOP GAIN
vs
CASSE TEMPERATURE
vs
CAPACITIVE LOAD
FREQUENCY
1
90
80
70
60
50
40
30
180
160
V
= 5 V
S
R
= 25 Ω, C = 10 pF
T = 25°C
A
0.5
(ISO)
L
85
80
T
A
= 85°C
140
120
0
-0.5
-1
-1.5
-2
-2.5
R
= 15 Ω
(ISO)
= 50 pF
100
80
C
L
75
70
T
A
= -40°C
R
= 10 Ω
(ISO)
= 100 pF
C
L
60
40
20
10
65
60
V
= 5 V
1 M
20
0
0
S
-3
100 k
-10
10 k
10 M
100 M
1 G
2.5
3
3.5
4
4.5
5
100 k
1 M
10 M
100 M
1 G
Capacitive Load - Hz
Case Temperature - °C
f - Frequency - Hz
Figure 60.
Figure 61.
Figure 62.
REJECTION RATIOS
vs
REJECTION RATIOS
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
FREQUENCY
80
70
70
60
V
= 5 V
V
= 5 V
S
S
V
= 5 V
S
55
50
45
40
35
30
25
20
15
PSRR-
PSRR-
60
50
60
50
40
30
20
10
0
CMRR
CMMR
PSRR+
40
30
PSRR+
20
10
0
10
5
0
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
100 k
1 M
10 M
100 M
1 G
0
1
2
3
4
5
Case Temperature - °C
f - Frequency - Hz
Input Common-Mode Voltage Range - V
Figure 63.
Figure 64.
Figure 65.
17
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
INPUT BIAS AND OFFSET
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
CURRENT
vs
SMALL SIGNAL TRANSIENT
RESPONSE
CASE TEMPERATURE
6.6
6.5
6.4
6.3
6.2
9
8
7
6
5
4
0.7
0.12
0.1
V
= 5 V
S
0.65
0.6
0.08
0.06
0.04
V
= ±5 V
I
S
IB-
0.55
0.5
0.02
0
V
= 5 V
6.1
6
0.45
0.4
S
I
IB+
-0.02
-0.04
-0.06
-0.08
-0.1
Gain = -1
3
2
5.9
5.8
0.35
0.3
R
L
= 499 Ω
I
OS
R =392 Ω
f
t /t = 300 ps
r
f
5.7
5.6
0.25
0.2
1
V
= 5 V
S
-0.12
0
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
-1
0
1
2
3
4
5
6
7
8
9
10
-40 -30-20-10
0 10 20 30 40 50 60 70 80 90
T
C
- Case Temperature - °C
t - Time - ns
T
C
- Case Temperature - °C
Figure 66.
Figure 67.
Figure 68.
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
LARGE SIGNAL TRANSIENT
RESPONSE
OVERDRIVE RECOVERY
FREQUENCY
3
2
1.5
1
100 k
10 k
1.5
1
R
R
= 499 Ω,
= 392 Ω,
= -4 dBm
= 5 V
L
V
= 5 V
S
F
P
V
IN
S
1 k
100
10
0.5
0.5
0
1
0
0
-0.5
-1
Gain = -1
-0.5
-1
R
L
= 499 Ω
1
R = 392 Ω
f
-1
-2
-3
t /t = 300 ps
r
f
0.1
V
= 5 V
S
-1.5
0.01
-1.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
-2
0
2
4
6
8 10 12 14 16 18 20
100 k
1 M
10 M
100 M
1 G
t - Time - ns
t - Time - µs
f - Frequency - Hz
Figure 69.
Figure 70.
Figure 71.
POWER-DOWN QUIESCENT
CURRENT
POWER-DOWN OUTPUT
IMPEDANCE
vs
vs
TURNON AND TURNOFF TIMES
DELAY TIME
SUPPLY VOLTAGE
FREQUENCY
800
1000
10
0.035
0.03
4.5
Gain = 1
700
600
3
R
L
= 499 Ω
= -1 dBm
= 5 V
T
= 85°C
A
P
V
IN
S
0.025
0.02
1.5
0
500
400
0.015
0.01
-1.5
-3
T
A
= 25°C
T
A
= -40°C
300
200
100
0
Gain = -1
0.1
0.005
-4.5
R
L
= 499 Ω
V
= 5 V
S
-6
0
-0.005
-7.5
-0.01
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07
0.001
t - Time - ns
2.5
3
3.5
4
4.5
5
100 k
1 M
10 M
100 M
1 G
10 G
V
- Supply Voltage - ±V
f - Frequency - Hz
S
Figure 72.
Figure 73.
Figure 74.
18
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
APPLICATION INFORMATION
with measurement equipment presenting a 50-Ω load
impedance. In Figure 75, the 49.9-Ω shunt resistor at
the VIN terminal matches the source impedance of the
test generator. The total 499-Ω load at the output,
combined with the 784-Ω total feedback-network
load, presents the THS4211 and THS4215 with an
effective output load of 305 Ω for the circuit shown in
Figure 75.
HIGH-SPEED OPERATIONAL AMPLIFIERS
The THS4211 and the THS4215 operational ampli-
fiers set new performance levels, combining low
distortion, high slew rates, low noise, and a unity-gain
bandwidth in excess of 1 GHz. To achieve the full
performance of the amplifier, careful attention must
be paid to printed-circuit board layout and component
selection.
Voltage-feedback amplifiers, unlike current-feedback
designs, can use a wide range of resistors values to
set their gain with minimal impact on their stability
and frequency response. Larger-valued resistors de-
crease the loading effect of the feedback network on
the output of the amplifier, but this enhancement
comes at the expense of additional noise and poten-
tially lower bandwidth. Feedback-resistor values be-
tween 392 Ω and 1 kΩ are recommended for most
applications.
The THS4215 provides a power-down mode, provid-
ing the ability to save power when the amplifier is
inactive. A reference pin is provided to allow the user
the flexibility to control the threshold levels of the
power-down control pin.
Applications Section Contents
•
•
•
•
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Single Supply Operation
Saving Power With Power-Down Functionality
and Setting Threshold Levels With the Reference
Pin
5 V
+V
S
+
100 pF
0.1 µF 6.8 µF
50 Ω Source
49.9 Ω
+
•
Power Supply Decoupling Techniques and
Recommendations
V
I
V
O
THS4211
_
499 Ω
•
•
•
•
•
Using the THS4211 as a DAC Output Buffer
Driving an ADC With the THS4211
Active Filtering With the THS4211
R
f
392 Ω
392 Ω
R
g
0.1 µF 6.8 µF
Building a Low-Noise Receiver With the THS4211
+
100 pF
Linearity:
Definitions,
Terminology,
Circuit
Techniques and Design Tradeoffs
An Abbreviated Analysis of Noise in Amplifiers
Driving Capacitive Loads
Printed-Circuit Board Layout Techniques for
Optimal Performance
-V
S
-5 V
•
•
•
Figure 75. Wideband, Noninverting Gain
Configuration
•
•
•
Power Dissipation and Thermal Considerations
Performance vs Package Options
WIDEBAND, INVERTING GAIN OPERATION
Since the THS4211 and THS4215 are gen-
eral-purpose, wideband voltage-feedback amplifiers,
several familiar operational-amplifier applications cir-
cuits are available to the designer. Figure 76 shows a
typical inverting configuration where the input and
output impedances and noise gain from Figure 75 are
retained in an inverting circuit configuration. Inverting
operation is a common requirement and offers sev-
eral performance benefits. The inverting configuration
shows improved slew rates and distortion due to the
pseudo-static voltage maintained on the inverting
input.
Evaluation Fixtures,
Applications Support
Spice
Models,
and
•
•
Additional Reference Material
Mechanical Package Drawings
WIDEBAND, NONINVERTING OPERATION
The THS4211 and the THS4215 are unity-gain,
stable 1-GHz voltage-feedback operational amplifiers,
with and without power-down capability, designed to
operate from a single 5-V to 15-V power supply.
Figure 75 shows the noninverting-gain configuration
of 2 V/V used to demonstrate the typical performance
curves. Most of the curves were characterized using
signal sources with 50-Ω source impedances, and
19
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
The last major consideration in inverting amplifier
design is setting the bias-current cancellation resistor
on the noninverting input. If the resistance is set
equal to the total dc resistance looking out of the
inverting terminal, the output dc error, due to the input
bias currents, is reduced to (input offset current) × Rf
in Figure 76, the dc source impedance looking out of
the inverting terminal is 392 Ω || (392 Ω + 26.8 Ω) =
200 Ω. To reduce the additional high-frequency noise
introduced by the resistor at the noninverting input,
and power-supply feedback, RT is bypassed with a
capacitor to ground.
5 V
+V
S
+
100 pF
0.1 µF
6.8 µF
+
V
O
R
200 Ω
T
THS4211
_
C
T
0.1 µF
499 Ω
50 Ω Source
R
R
f
g
V
I
392 Ω
392 Ω
R
M
0.1 µF
6.8 µF
57.6 Ω
SINGLE SUPPLY OPERATION
+
100 pF
The THS4211 is designed to operate from a single
5-V to 15-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to maximize output voltage swing. The circuits shown
in Figure 77 demonstrate methods to configure an
amplifier for single-supply operation.
-V
S
-5 V
Figure 76. Wideband, Inverting Gain
Configuration
In the inverting configuration, some key design con-
siderations must be noted. One is that the gain
resistor (Rg) becomes part of the signal-channel input
impedance. If input impedance matching is desired
(beneficial when the signal is coupled through a
cable, twisted pair, long PC board trace, or other
transmission line conductor), Rg may be set equal to
the required termination value and Rf adjusted to give
the desired gain. However, care must be taken when
dealing with low inverting gains, as the resultant
feedback resistor value can present a significant load
to the amplifier output. For an inverting gain of 2,
setting Rg to 49.9 Ω for input matching eliminates the
need for RM but requires a 100-Ω feedback resistor.
This has the advantage that the noise gain becomes
equal to 2 for a 50-Ω source impedance—the same
as the noninverting circuit in Figure 75. However, the
amplifier output now sees the 100-Ω feedback re-
sistor in parallel with the external load. To eliminate
this excessive loading, it is preferable to increase
both Rg and Rf, values, as shown in Figure 76, and
then achieve the input matching impedance with a
third resistor (RM) to ground. The total input im-
pedance becomes the parallel combination of Rg and
RM.
+V
S
50 Ω Source
+
V
I
THS4211
_
V
O
R
T
49.9 Ω
499 Ω
+V
2
S
R
f
392 Ω
R
g
392 Ω
+V
2
S
R
f
392 Ω
V
S
50 Ω Source
R
g
_
V
I
392 Ω
T
THS4211
+
V
O
57.6 Ω
R
499 Ω
+V
+V
2
S
S
2
Figure 77. DC-Coupled Single Supply Operation
The next major consideration is that the signal source
impedance becomes part of the noise gain equation
and hence influences the bandwidth. For example,
the RM value combines in parallel with the external
50-Ω source impedance (at high frequencies), yield-
ing an effective source impedance of 50 Ω || 57.6 Ω =
26.8 Ω. This impedance is then added in series with
Rg for calculating the noise gain. The result is 1.9 for
Figure 76, as opposed to the 1.8 if RM is eliminated.
The bandwidth is lower for the inverting gain-of-2
circuit in Figure 76 (NG=+1.9), than for the
noninverting gain of 2 circuit in Figure 75.
Saving Power With Power-Down
Functionality and Setting Threshold Levels
With the Reference Pin
The THS4215 features a power-down pin (PD) which
lowers the quiescent current from 19-mA down to
650-µA, ideal for reducing system power.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To conserve power, the amplifier is turned
off by driving the power-down pin towards the nega-
20
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
NO. OF CHANNELS PACKAGES
tive rail. The threshold voltages for power-on and
power-down are relative to the supply rails, and are
given in the specification tables. Above the Enable
Threshold Voltage, the device is on. Below the
Disable Threshold Voltage, the device is off. Behavior
between these threshold voltages is not specified.
Single (8-pin)
THS4215D, THS4215DGN, and
THS4215DRB
Power Supply Decoupling Techniques and
Recommendations
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high- impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of per-
formance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should put the smallest valued
capacitors closest to the device.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
3. Use of solid power and ground planes is rec-
ommended to reduce the inductance along power
supply return current paths, with the exception of
the areas underneath the input and output pins.
4. Recommended values for power supply decoup-
ling include a bulk decoupling capacitor (6.8 to 22
µF), a mid-range decoupling capacitor (0.1 µF)
and a high frequency decoupling capacitor (1000
pF) for each supply. A 100 pF capacitor can be
used across the supplies as well for extremely
high frequency return currents, but often is not
required.
Power-Down Reference Pin Operation
In addition to the power-down pin, the THS4215 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. Operation of the
reference pin as it relates to the power-down pin is
described below.
APPLICATION CIRCUITS
In most split-supply applications, the reference pin will
be connected to ground. In some cases, the user
may want to connect it to the negative or positive
supply rail. In either case, the user needs to be aware
of the voltage level thresholds that apply to the
power-down pin. The table below illustrates the re-
lationship between the reference voltage and the
power-down thresholds.
Driving an Analog-to-Digital Converter With the
THS4211
The THS4211 can be used to drive high-performance
analog-to-digital converters. Two example circuits are
presented below.
The first circuit uses a wideband transformer to
convert a single-ended input signal into a differential
signal. The differential signal is then amplified and
filtered by two THS4211 amplifiers. This circuit pro-
vides low intermodulation distortion, suppressed
even-order distortion, 14 dB of voltage gain, a 50-Ω
input impedance, and a single-pole filter at 100 MHz.
For applications without signal content at dc, this
method of driving ADCs can be very useful. Where dc
information content is required, the THS4500 family
of fully differential amplifiers may be applicable.
POWER-DOWN PIN VOLTAGE
REFERENCE
DEVICE
DEVICE
VOLTAGE
DISABLED
ENABLED
VS– to 0.5 (VS– + VS+
)
≤ Ref + 1.0 V
≤ Ref – 1.5 V
≥ Ref + 1.8 V
≥ Ref – 1 V
0.5 (VS– + VS+) to VS+
The recommended mode of operation is to tie the
reference pin to mid-rail, thus setting the threshold
levels to mid-rail +1.0 V and midrail +1.8 V.
21
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
converter. The first circuit performs a differential to
single-ended conversion with the THS4211 con-
figured as a difference amplifier. The difference
amplifier can double as the termination mechanism
for the DAC outputs as well.
5 V
+
V
CM
THS4211
_
3.3 V 3.3 V
50 Ω
Source 1:2
(1:4 Ω)
-5 V
392 Ω
392 Ω
196 Ω
196 Ω
24.9 Ω
24.9 Ω
100 Ω
100 Ω
+5 V
ADS5422
14-Bit, 62 Msps
15 pF
15 pF
392 Ω
196 Ω
392 Ω
_
DAC5675
14-Bit,
400 MSps
49.9 Ω
RF
THS4211
+
392 Ω
LO
-5 V
392 Ω
_
THS4211
+
V
CM
Figure 80. Differential to Single-Ended
Conversion of a High-Speed DAC Output
Figure 78. A Linear, Low Noise, High Gain
ADC Preamplifier
For cases where a differential signaling path is
desirable, a pair of THS4211 amplifiers can be used
as output buffers. The circuit depicts differential drive
into a mixer's IF inputs, coupled with additional signal
gain and filtering.
The second circuit depicts single-ended ADC drive.
While not recommended for optimum performance
using converters with differential inputs, satisfactory
performance can sometimes be achieved with
single-ended input drive. An example circuit is shown
here for reference.
THS4211
+
3.3 V 3.3 V
+5 V
50 Ω
Source
_
100 Ω
100 Ω
C
+
0.1 µF
F
V
R
I
ISO
1 nF
1 nF
THS4211
_
IN
R
T
IF+
49.9 Ω
68 pf
ADS807
16.5 Ω
DAC5675
14-Bit,
400 MSps
12-Bit,
53 Msps
392 Ω
100 Ω
392 Ω
392 Ω
392 Ω
49.9 Ω
49.9 Ω
CM
IN
-5 V
R
f
RF
(out)
1.82 kΩ
0.1 µF
IF-
392 Ω
1 nF
1 nF
R
g
392 Ω
C
F
_
+
NOTE: For best performance, high-speed ADCs should be driven
differentially. See the THS4500 family of devices for more
information.
THS4211
Figure 81. Differential Mixer Drive Circuit
Using the DAC5675 and the THS4211
Figure 79. Driving an ADC With a
Single-Ended Input
Active Filtering With the THS4211
Using the THS4211 as a DAC Output Buffer
High-frequency active filtering with the THS4211 is
achievable due to the amplifier's high slew-rate, wide
bandwidth, and voltage feedback architecture. Sev-
eral options are available for high-pass, low-pass,
bandpass, and bandstop filters of varying orders. A
simple two-pole low pass filter is presented here as
an example, with two poles at 100 MHz.
Two example circuits are presented here showing the
THS4211 buffering the output of a digital-to-analog
22
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
100 Ω
3.9 pF
+
R
g2
R
f2
V
I-
THS4211
50 Ω Source
_
392 Ω
V
I
R
f1
392 Ω
57.6 Ω
5 V
_
R
g1
49.9 Ω
THS4211
+
V
O
_
33 pF
R
f1
V
49.9 Ω
49.9 Ω
O
_
THS4211
R
g2
-5 V
THS4211
+
+
100 Ω
Figure 82. A Two-Pole Active Filter With
Two Poles Between 90 MHz and 100 MHz
R
f2
V
I+
A Low-Noise Receiver With the THS4211
Figure 84. A High-Speed Instrumentation
Amplifier
A combination of two THS4211 amplifiers can create
a high-speed, low-distortion, low-noise differential re-
ceiver circuit as depicted in Figure 83. With both
amplifiers operating in the noninverting mode of
operation, the circuit presents a high load impedance
to the source. The designer has the option of
controlling the impedance through termination re-
sistors if a matched termination impedance is desired.
2Rf1
Rg1
Rf2
Rg2
1
2
ǒ
Ǔ
i–
ǒ1 ) ǓV –V ǒ Ǔ
VO +
i)
(1)
THEORY AND GUIDELINES
Distortion Performance
100 Ω
V
The THS4211 provides excellent distortion perform-
ance into a 150-Ω load. Relative to alternative sol-
utions, it provides exceptional performance into
lighter loads, as well as exceptional performance on a
single 5-V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the 2nd harmonic dominates the total harmonic distor-
tion with a negligible 3rd harmonic component. Focus-
ing then on the 2nd harmonic, increasing the load
impedance directly improves distortion. The total load
includes the feedback network; in the noninverting
configuration (Figure 75) this is the sum of Rf and Rg,
while in the inverting configuration (Figure 76), only Rf
needs to be included in parallel with the actual load.
+
I+
49.9 Ω
V
O+
_
392 Ω
100 Ω
787 Ω
392 Ω
_
49.9 Ω
V
O-
100 Ω
V
I-
+
Figure 83. A High Input Impedance, Low Noise,
Differential Receiver
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
A modification on this circuit to include a difference
amplifier turns this circuit into a high-speed instru-
mentation amplifier, as shown in Figure 84.
The THS4211 features execllent distortion perform-
ance for monolithic operational amplifiers. This sec-
tion focuses on the fundamentals of distortion, circuit
techniques for reducing nonlinearity, and methods for
equating distortion of operational amplifiers to desired
linearity specifications in RF receiver chains.
Amplifiers are generally thought of as linear devices.
The output of an amplifier is a linearly-scaled version
of the input signal applied to it. However, amplifier
transfer functions are nonlinear. Minimizing amplifier
nonlinearity is a primary design goal in many appli-
cations.
23
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
Intercept points are specifications long used as key
design criteria in the RF communications world as a
metric for the intermodulation distortion performance
of a device in the signal chain (e.g., amplifiers,
mixers, etc.). Use of the intercept point, rather than
strictly the intermodulation distortion, allows simpler
system-level calculations. Intercept points, like noise
figures, can be easily cascaded back and forth
through a signal chain to determine the overall
receiver chain's intermodulation distortion perform-
ance. The relationship between intermodulation dis-
tortion and intercept point is depicted in Figure 85
and Figure 86.
Due to the intercept point's ease of use in system
level calculations for receiver chains, it has become
the specification of choice for guiding distor-
tion-related design decisions. Traditionally, these sys-
tems use primarily class-A, single-ended RF ampli-
fiers as gain blocks. These RF amplifiers are typically
designed to operate in a 50-Ω environment. Giving
intercept points in dBm implies an associated im-
pedance (50 Ω ).
However, with an operational amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to their outputs regardless of the impedance present,
it is important to comprehend this when evaluating
the intercept point of an operational amplifier. The
THS4211 yields optimum distortion performance
when loaded with 150 Ω to 1 kΩ, very similar to the
input impedance of an analog-to-digital converter
over its input frequency band.
P
O
P
O
∆f = f - f1
c
c
∆f = f2 - f
c
c
As a result, terminating the input of the ADC to 50 Ω
IMD = P - P
3
S
O
can actually be detrimental to system performance.
The discontinuity between open-loop, class-A ampli-
fiers and closed-loop, class-AB amplifiers becomes
apparent when comparing the intercept points of the
two types of devices. Equation 2 and Equation 3
define an intercept point, relative to the
intermodulation distortion.
P
P
S
S
f - 3∆f f1
f
c
f2
f + 3∆f
c
c
Ť
Ť
IMD3
2
f - Frequency - MHz
ǒ Ǔwhere
OIP3 + PO )
(2)
Figure 85.
V2P
P + 10 logǒ Ǔ
O
2RL 0.001
(3)
P
OUT
NOTE: PO is the output power of a single tone, RL is
the load resistance, and VP is the peak voltage for a
single tone.
(dBm)
1X
OIP
3
NOISE ANALYSIS
High slew rate, unity-gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate
at the expense of a higher input noise voltage. The 7
nV/√Hz input voltage noise for the THS4211 and
THS4215 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the
two input-referred current noise terms (4 pA/√Hz),
combine to give low output noise under a wide variety
of operating conditions. Figure 87 shows the amplifier
noise analysis model with all the noise terms in-
cluded. In this model, all noise terms are taken to be
noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
P
O
IMD
IIP
3
P
3
IN
(dBm)
3X
P
S
Figure 86.
24
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4211. Long PC board traces,
unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4211 output pin (see Board Layout
Guidelines).
THS4211/THS4215
+
E
NI
E
O
R
I
BN
_
S
E
RF
E
RS
4kTR
R
I
S
f
R
g
4kT
4kTR
f
BI
R
g
4kT = 1.6E-20J
at 290K
The criterion for setting this R(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load. For a gain of +2, the frequency response at the
output pin is already slightly peaked without the
capacitive load, requiring relatively high values of
R(ISO) to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
Figure 87. Noise Analysis Model
The total output shot noise voltage can be computed
as the square of all square output noise voltage
contributors. Equation 4 shows the general form for
the output noise voltage using the terms shown in
FREQUENCY RESPONSE
Equ+aǸtioǒn 4:
Ǔ
vs
CAPACITIVE LOAD
2
2
ǒ
SǓ2 Ǔ2
ǒ
) 4kTRS NG ) IBIRf ) 4kTRfNG
EO
ENI ) IBN
R
1
V
=±5 V
S
R
= 10 Ω
(ISO)
= 100 pF
0.5
C
L
(4)
0
Dividing this expression by the noise gain (NG=(1+
Rf/Rg)) gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
R
= 15 Ω
-0.5
(ISO)
= 50 pF
C
L
-1
-1.5
-2
R
= 25 Ω
(ISO)
= 10 pF
C
L
2
IBIRf
4kTRf
NG
2
ǒ
SǓ2
) 4kTRS )
Ǹ
ǒ Ǔ )
NG
EO +
ENI ) IBN
R
-2.5
-3
(5)
100 k
1 M
10 M
100 M
1 G
Capacitive Load - Hz
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4211 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is
considered, this capacitive load introduces an ad-
ditional pole in the signal path that can decrease the
phase margin. When the primary considerations are
frequency response flatness, pulse response fidelity,
or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback
loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This
does not eliminate the pole from the loop response,
but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the
phase lag from the capacitive load pole, thus increas-
ing the phase margin and improving stability.
Figure 88. Isolation Resistor Diagram
BOARD LAYOUT
Achieving optimum performance with a high fre-
quency amplifier like the THS4211 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include
the following:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
25
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PC board.
power planes opened up around them. Estimate
the total capacitive load and set RISO from the
plot of recommended RISO vs capacitive load
(See Figure 88). Low parasitic capacitive loads
(<4 pF) may not need an R(ISO), since the
THS4211 is nominally compensated to operate
with a 2-pF parasitic load. Higher parasitic ca-
pacitive loads without an R(ISO) are allowed as the
signal gain increases (increasing the unloaded
phase margin). If a long trace is required, and the
6-dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline lay-
out techniques). A 50-Ω environment is normally
not necessary onboard, and in fact a higher
impedance environment improves distortion as
shown in the distortion versus load plots. With a
characteristic board trace impedance defined on
the basis of board material and trace dimensions,
a matching series resistor into the trace from the
output of the THS4211 is used as well as a
terminating shunt resistor at the input of the
destination device. Remember also that the ter-
minating impedance is the parallel combination of
the shunt resistor and the input impedance of the
destination device: this total effective impedance
should be set to match the trace impedance. If
the 6-dB attenuation of a doubly terminated
transmission line is unacceptable, a long trace
can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the
plot of R(ISO) vs capacitive load (See Figure 88).
This setting does not preserve signal integrity or
a doubly-terminated line. If the input impedance
of the destination device is low, there is some
signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4211. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal-film and carbon composition, axi-
ally-leaded resistors can also provide good high
frequency performance. Again, keep their leads
and PC board trace length as short as possible.
Never use wire-wound type resistors in a high
frequency application. Since the output pin and
inverting input pin are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistor, if any, as
close as possible to the output pin. Other network
components,
such
as
noninverting
in-
put-termination resistors, should also be placed
close to the package. Where double-side
component mounting is allowed, place the
feedback resistor directly under the package on
the other side of the board between the output
and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors, ex-
cessively high resistor values can create signifi-
cant time constants that can degrade perform-
ance. Good axial metal-film or surface-mount
resistors have approximately 0.2 pF in shunt with
the resistor. For resistor values > 2.0 kΩ, this
parasitic capacitance can add a pole and/or a
zero below 400 MHz that can effect circuit oper-
ation. Keep resistor values as low as possible,
consistent with load driving considerations. A
good starting point for design is to set the Rf to
249 Ω for low-gain, noninverting applications.
This setting automatically keeps the resistor noise
terms low and minimizes the effect of their
parasitic capacitance.
5. Socketing a high speed part like the THS4211
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create a troublesome parasitic net-
work which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
THS4211 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4211 and THS4215 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 89(a) and Figure 89(b)]. This arrangement
results in the lead frame being exposed as a thermal
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
26
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
pad on the underside of the package [see Fig-
ure 89(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal per-
formance can be achieved by providing a good
thermal path away from the thermal pad.
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered, so wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4211
and THS4215 PowerPAD package should make
their connection to the internal ground plane, with
a complete connection around the entire circum-
ference of the plated-through hole.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
be soldered to a copper area underneath the pack-
age. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechan-
ical methods of heatsinking.
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
Bottom View (c)
Figure 89. Views of Thermally
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard sur-
face-mount component. This results in a part that
is properly installed.
Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
For a given θJA , the maximum power dissipation is
shown in Figure 91 and is calculated by Equation 6:
Single or Dual
Tmax TA
qJA
PD +
where
68 Mils x 70 Mils
(Via Diameter = 13 Mils)
P
= Maximum power dissipation of THS4211 (watts)
D
T
= Absolute maximum junction temperature (150°C)
MAX
T = Free-ambient temperature (°C)
A
Figure 90. PowerPAD PCB Etch and
Via Pattern
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to the case
= Thermal coefficient from the case to ambient air
(°C/W).
JC
CA
(6)
PowerPAD PCB LAYOUT CONSIDERATIONS
The next consideration is the package constraints.
The two sources of heat within an amplifier are
quiescent power and output power. The designer
should never forget about the quiescent heat gener-
ated within the device, especially multi-amplifier de-
vices. Because these devices have linear output
stages (Class AB), most of the heat dissipation is at
low output voltages with high output currents.
1. Prepare the PCB with a top side etch pattern as
shown in Figure 90. There should be etching for
the leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. They help dissipate the heat generated by
the THS4211 and THS4215 IC. These additional
vias may be larger than the 13-mil diameter vias
The other key factor when dealing with power dissi-
pation is how the devices are mounted on the PCB.
The PowerPAD devices are extremely useful for heat
dissipation. But, the device should always be
27
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
soldered to a copper plane to fully use the heat
dissipation properties of the PowerPAD. The SOIC
package, on the other hand, is highly dependent on
how it is mounted on the PCB. As more trace and
copper area is placed around the device, θJA de-
creases and the heat dissipation capability increases.
For a single package, the sum of the RMS output
currents and voltages should be used to choose the
proper package.
3.5
3
8-Pin DGN Package
2.5
2
8-Pin D Package
1.5
1
THERMAL ANALYSIS
0.5
0
The THS4211 device does not incorporate automatic
thermal shutoff protection, so the designer must take
care to ensure that the design does not violate the
absolute maximum junction temperature of the de-
vice. Failure may result if the absolute maximum
junction temperature of 150°C is exceeded.
-40
-20
0
20
40
60
80
T
- Ambient Temperature - °C
A
θ
θ
= 170°C/W for 8-Pin SOIC (D)
= 58.4°C/W for 8-Pin MSOP (DGN)
T = 150°C, No Airflow
JA
JA
J
Figure 91. Maximum Power Dissipation vs
Ambient Temperature
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using Equation 7:
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power dissi-
pation, but also dynamic power dissipation. Often
maximum power dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
Tmax–TA
qJA
PDmax
+
where
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
is the absolute maximum junction temperature (°C).
max
T is the ambient temperature (°C).
A
θ
θ
= θ + θ
JA
JC
JC CA
is the thermal coefficient from the silicon junctions to the
case (°C/W).
DESIGN TOOLS
θ
is the thermal coefficient from the case to ambient air
(°C/W).
CA
Performance vs Package Options
The THS4211 and THS4215 are offered in a different
package options. However, performance may be
limited due to package parasitics and lead inductance
in some packages. In order to achieve maximum
performance of the THS4211 and THS4215, Texas
Instruments recommends using the leadless MSOP
(DRB) or MSOP (DGN) packages, in additions to
proper high-speed PCB layout. Figure 92 shows the
unity gain frequency response of the THS4211 using
the leadless MSOP, MSOP, and SOIC package for
comparison. Using the THS4211 and THS4215 in a
unity gain with the SOIC package may result in the
device becoming unstable. In higher gain configur-
ations, this effect is mitigated by the reduced
bandwidth. As such, the SOIC is suitable for appli-
cation with gains equal to or higher than +2 V/V or
(–1 V/V).
(7)
For systems where heat dissipation is more critical,
the THS4211 is offered in an 8-pin MSOP with
PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over
the traditional SOIC. Maximum power dissipation
levels are depicted in the graph for the two packages.
The data for the DGN package assumes a board
layout that follows the PowerPAD layout guidelines
referenced above and detailed in the PowerPAD
application notes in the Additional Reference Material
section at the end of the data sheet.
28
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
17
12
SOIC, R = 0 Ω
f
R
15
13
R
f
f
_
_
R = 0 Ω
f
10
8
+
+
499 Ω
499 Ω
11
9
49.9 Ω
49.9 Ω
R = 50 Ω
f
6
7
R = 100 Ω
f
4
2
0
5
SOIC, R = 100 Ω
f
R = 200 Ω
f
3
1
-1
-2
-4
P
V
= -7 dB
=±5 V
IN
S
Leadless MSOP, &
P
V
= -7 dBm
= ±5 V
IN
S
-3
-5
MSOP R = 0 Ω
f
10 M
100 M
1 G
10 M
100 M
1 G
10 G
f - Frequency - Hz
f - Frequency - Hz
Figure 92. Effects of Unity Gain Frequency
Response for Differential Packages
Figure 93. Frequency Response vs Feedback
Resistor Using the EDGE #6439527 EVM
5
Evaluation
Fixtures,
SPICE
Models,
and
Applications Support
4
3
2
1
0
_
+
Texas Instruments is committed to providing its cus-
tomers with the highest quality of applications sup-
port. To support this goal, evaluation boards have
been developed for the THS4211 operational ampli-
fier. Three evaluation boards are available: one
THS4211 and one THS4215, both configurable for
different gains, and a third for untiy gain (THS4211
only). These boards are easy to use, allowing for
straightforward evaluation of the device. These evalu-
ation boards can be ordered through the Texas
Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. Sche-
matics for the evaluation boards are shown below.
499 Ω
49.9 Ω
-1
-2
P
V
= -7 dBm
= ±5 V
IN
S
-3
-4
100 k
1 M
10 M
f - Frequency - Hz
100 M
1 G
10 G
Figure 94. Frequency Response Using the
EDGE #6443547 G = +1 EVM
The THS4211/THS4215 EVM board shown in Fig-
ure 95 through Figure 99 accommodates different
gain configurations. Its default component values are
set to give a gain of 2. The EVM can be configured
for unity gain; however, it is strongly not rec-
ommended. Evaluating the THS4211/THS4215 in
unity gain using this EVM may cause the device to
become unstable. The stability of the device can be
controlled by adding a large resistor in the feedback
path, but performance is sacrificed. Figure 93 shows
the small signal frequency response of the THS4211
with different feedback resistors in the feedback path.
Figure 94 is the small frequency response of the
THS4211 using the unity gain EVM.
The frequency-response peaking is due to the lead
inductance in the feedback path. Each pad and trace
on a PCB has an inductance associated with it, which
in conjunction with the inductance associated with the
package may cause frequency-response peaking,
causing the device to become unstable.
In order to achieve the maximum performance of the
device, PCB layout is very critical. Texas Instruments
has developed an EVM for the evaluation of the
THS4211 configured for a gain of 1. The EVM is
shown in Figure 100 through Figure 104. This EVM is
designed to minimize peaking in the unity gain
configuration.
Minimizing the inductance in the feedback path is
critical for reducing the peaking of the frequency
response in unity gain. The recommended maximum
inductance allowed in the feedback path is 4 nH. This
inductance can be calculated using Equation 8:
29
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
2ȏ
W ) T
W ) T
L(nH) + Kȏƪln
) 0.5ƫ
) 0.223
ȏ
where
W = Width of trace in inches.
= Length of the trace in inches.
ȏ
T = Thickness of the trace in inches.
K = 5.08 for dimensions in inches, and K = 2 for dimensions
in cm.
(8)
Vs+
J9
Power Down
R8
R9
C8
R5
U1
Vs -
Vs+
7
8
R3
J1
Vin
2
_
+
R6
6
-
J4
Vout
3
R2
R7
4
1
Vs -
J8
Power Down Ref
J2
Vin+
Figure 96. THS4211/THS4215 EVM Board Layout
(Top Layer)
C7
R1
R4
J7
VS-
J5
VS+
J6
GND TP1
FB1
C6
FB2
VS-
VS+
+
C1
C2
C5
C3
C4
+
Figure 95. THS4211/THS4215 EVM
Circuit Configuration
Figure 97. THS4211/THS4215 EVM Board Layout
(Second Layer, Ground)
30
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
Vs+
7
2
8
U1
_
R6
6
J4
3
+
Vout
R7
4
1
J2
Vin+
Vs -
R4
J7
VS-
J5
VS+
J6
GND TP1
FB1
C6
FB2
VS-
VS+
+
C1
C2
C5
C3
C4
+
Figure 100. THS4211 Unity Gain EVM
Circuit Configuration
Figure 98. THS4211/THS4215 EVM Board Layout
(Third Layer, Power)
Figure 101. THS4211 Unity Gain EVM Board
Layout (Top Layer)
Figure 99. THS4211/THS4215 EVM Board Layout
(Bottom Layer)
31
THS4211
THS4215
www.ti.com
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
Figure 102. THS4211 Unity Gain EVM Board
Layout (Second Layer, Ground)
Figure 104. THS4211 Unity Gain EVM
Board Layout (Bottom Layer)
Computer simulation of circuit performance using
SPICE is often useful when analyzing the perform-
ance of analog circuits and systems. This is particu-
larly true for video and RF amplifier circuits, where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the Texas Instruments web site (www.ti.com).
The Product Information Center (PIC) is available for
design assistance and detailed product information.
These models do
a
good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac perform-
ance. Detailed information about what is and is not
modeled is contained in the model file itself.
ADDITIONAL REFERENCE MATERIAL
•
PowerPAD Made Easy, application brief
(SLMA004)
•
PowerPAD Thermally Enhanced Package, techni-
cal brief (SLMA002)
Figure 103. THS4211 Unity Gain EVM Board
Layout (Third Layer, Power)
32
THERMAL PAD MECHANICAL DATA
www.ti.com
DRB (S-PDSO-N8)
THERMAL INFORMATION
This package incorporates an exposed thermal pad that is designed to be attached directly to an external
heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB
can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly
to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer
from the integrated circuit (IC).
For additional information on the Quad Flatpack No-Lead (QFN) package and how to take advantage of its heat
dissipating abilities, refer to Application Report, Quad Flatpack No-Lead Logic Packages, Texas Instruments
Literature No. SCBA017 and Application Report, 56-Pin Quad Flatpack No-Lead Logic Package, Texas
Instruments Literature No. SCEA032. Both documents are available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
1
4
Exposed Thermal Pad
+0,10
0,15
2x0,65
1,50
4x0,23
8
5
4x0,625
NOM
+0,10
0,15
1,75
Bottom View
NOTE: All linear dimensions are in millimeters
QFND058
Exposed Thermal Pad Dimensions
www.ti.com
Thermal Pad Mechanical Data
DGN (S–PDSO–G8)
THERMAL INFORMATION
The DGN PowerPAD™ package incorporates an exposed thermal die pad that is designed to be attached directly
to an external heat sink. When the thermal die pad is soldered directly to the printed circuit board (PCB), the PCB
can be used as a heatsink. In addition, through the use of thermal vias, the thermal die pad can be attached directly
to a ground plane or special heat sink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to
Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and
Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available
at www.ti.com. See Figure 1 for DGN package exposed thermal die pad dimensions.
8
1
Exposed Thermal
Die Pad
1,78
MAX
5
4
1,73
MAX
Bottom View
PPTD041
NOTE: All linear dimensions are in millimeters.
Figure 1. DGN Package Exposed Thermal Die Pad Dimensions
PowerPAD is a trademark of Texas Instruments.
1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2005
PACKAGING INFORMATION
Orderable Device
THS4211D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4211DG4
THS4211DGK
THS4211DGKR
THS4211DGKRG4
THS4211DGN
SOIC
MSOP
MSOP
MSOP
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGN
100 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4211DGNG4
THS4211DGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4211DGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4211DR
THS4211DRBR
THS4211DRBRG4
THS4211DRBT
THS4211DRG4
THS4215D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
DRB
DRB
DRB
D
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
MSOP
MSOP
MSOP
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4215DGK
THS4215DGKR
THS4215DGKRG4
THS4215DGN
DGK
DGK
DGK
DGN
100 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4215DGNG4
THS4215DGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4215DGNRG4
MSOP-
Power
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PAD
THS4215DR
THS4215DRBR
THS4215DRBRG4
THS4215DRBT
THS4215DRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
SON
SON
SOIC
DRB
DRB
DRB
D
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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