THS4304DG4 [TI]
3GHz 低噪声宽带运算放大器 | D | 8 | -40 to 85;
| 型号： | THS4304DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3GHz 低噪声宽带运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 放大器电路 |
| 文件： | 总26页 (文件大小：854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
Wideband Operational Amplifier
FEATURES
APPLICATIONS
•
•
•
•
•
Active Filter
ADC Driver
Ultrasound
Gamma Camera
RF/Telecom
•
•
•
•
•
Wide Bandwidth: 3 GHz
High Slew Rate: 830 V/µs
Low Voltage Noise: 2.4 nV/√Hz
Single Supply: 5 V, 3 V
Quiescent Current: 18 mA
DESCRIPTION
The THS4304 is a wideband, voltage-feedback operational amplifier designed for use in high-speed analog
signal-processing chains operating with a single 5-V power supply. Developed in the BiCom3 silicon germanium
process technology, the THS4304 offers best-in-class performance using a single 5-V supply as opposed to
previous generations of operational amplifiers requiring ±5-V supplies.
The THS4304 is a traditional voltage-feedback topology that provides the following benefits: balanced inputs, low
offset voltage and offset current, low offset drift, high common mode and power supply rejection ratio.
The THS4304 is offered in 8-pin MSOP package (DGK), the 8-pin SOIC package (D), and the space-saving 5-pin
SOT-23 package (DBV).
DIFFERENTIAL ADC DRIVE
+5V
10 kΩ
90
V
(= 2.5V)
REF
Combined THS4304 and
ADS5500 SFDR
10 kΩ
0.1 µF
R
R
F
G
V
REF
85
80
75
+5V
+3.3 VA +3.3VD
THS 4304
1:1
100Ω
1nF
CM
V
IN
1kΩ
A
A
IN+
ADS 5500
D
A
49.9 Ω
V
G = 10 dB,
REF
+5V
R
R
= 249 Ω,
F
G
From
50−Ω
source
1kΩ
= 115 Ω,
IN−
CM
SNR = 69.6,
THS 4304
F
125 MSPS
S =
CM
0.1
100Ω
1nF
10
20
30
40
50
µF
f − Frequency − MHz
V
REF
R
R
F
G
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PINOUT DRAWING
TOP VIEW
DBV
TOP VIEW
D and DGK
+
V
V
1
2
5
4
NC
IN−
IN+
NC
S
1
2
3
4
8
7
6
5
OUT
+
V
S
V −
S
V
OUT
IN+
IN−
3
V −
S
V
OUT
NOTE: NC indicates there is no internal connection to these pins.
PACKAGING / ORDERING INFORMATION
TRANSPORT MEDIA,
QUANTITY
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKINGS
THS4304DBVT
THS4304DBVR
THS4304D
Tape and Reel, 250
Tape and Reel, 3000
Rails, 75
SOT-23-5
AKW
SOIC-8
—
THS4304DR
Tape and Reel, 2500
Rails, 100
THS4304DGK
THS4304DGKR
MSOP-8
AKU
Tape and Reel, 2500
DISSIPATION RATINGS
POWER RATING(2)
θJC
(°C/W)
θJA
PACKAGE
(°C/W)(1)
TA≤ 25°C
391 mW
1.02 W
TA = 85°C
156 mW
410 mW
221 mW
DBV (5)
D (8)
55
255.4
97.5
38.3
71.5
DGK (8)
180.8
553 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal
management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term
reliability.
2
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VS
VI
Supply voltage
+6.0 V
Input voltage
±VS
IO
Output current
150 mA
VID
Differential input voltage
±2 V
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature, any condition(2)
Operating free-air temperature range, continuous operation, long-term reliability(2)
Storage temperature range
150°C
125°C
TJ
Tstg
–65°C to 150°C
300°C
Lead temperature: 1,6 mm (1/16 inch) from case for 10 seconds
HBM
1600 V
ESD Ratings
CDM
MM
1000 V
100 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
±1.35
2.7
MAX UNIT
Dual supply
±2.5
V
Supply voltage, (VS+ and VS–
)
Single supply
5
Input common-mode voltage range
VS–– 0.2 VS+ + 0.2
V
3
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
TYP
OVER TEMPERATURE
TEST
PARAMETER
CONDITIONS
LEVEL(1)
0°C to –40°C to
MIN/
MAX
25°C
25°C
UNITS
70°C
85°C
AC PERFORMANCE
G = +1, VO = 100 mVpp
G = +2, VO = 100 mVpp
G = +5, VO = 100 mVpp
G = +10, VO = 100 mVpp
G >+10
3
GHz
GHz
MHz
MHz
MHz
MHz
Typ
Typ
Typ
Typ
Typ
Typ
C
C
C
C
C
1
Small-Signal Bandwidth
187
87
Gain Bandwidth Product
0.1-dB Flat Bandwidth
870
300
G= +2, VO = 100 mVpp,
CF = 0.5 pF
C
Large-Signal Bandwidth
Slew Rate
G = +2, VO = 2 VPP
240
830
790
4.5
7.5
35
MHz
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
C
C
C
C
C
C
C
G = +2, VO = 1-V Step
G = +2, VO = 2-V Step
G = –2, VO = 2-V Step
G = –2, VO = 2-V Step
G = –2, VO = 2-V Step
G = +2, VO = 2-V Step
Settling Time to 1%
Settling Time to 0.1%
Settling Time to 0.01%
Rise / Fall Times
ns
ns
2.5
ns
Harmonic Distortion
RL= 100 Ω
–84
–95
dBc
dBc
dBc
dBc
Typ
Typ
Typ
Typ
C
C
C
C
Second Harmonic Distortion
Third Harmonic Distortion
G = +2,
VO = 2 VPP
f = 10 MHz
RL = 1 kΩ
,
RL = 100 Ω
RL = 1 kΩ
–100
–100
Third-Order Intermodulation
Distortion (IMD3)
–84
48
dBc
Typ
Typ
C
C
G = +2, VO= 2-VPP envelope,
200-kHz tone spacing,
f = 20 MHz
Third-Order Output Intercept
(OIP3)
dBm
Noise Figure
G = +2, f = 1 GHz
f = 1 MHz
15
2.4
2.1
dB
Typ
Typ
Typ
C
C
C
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Open-Loop Voltage Gain
nV/√Hz
pA/√Hz
f = 1 MHz
VO = ± 0.8 V, VCM = 2.5 V
65
54
4
50
50
dB
Min
A
(AOL
)
Input Offset Voltage
0.5
5
5
5
5
mV
µV/°C
µA
Max
Typ
Max
Typ
Max
Typ
A
B
A
B
A
B
Input Offset Voltage Drift
Input Bias Current
7
12
1
18
50
1.2
10
18
50
1.2
10
VCM = 2.5 V
Input Bias Current Drift
Input Offset Current
nA/°C
µA
0.5
Input Offset Current Drift
INPUT CHARACTERISTICS
Common-Mode Input Range
nA/°C
–0.2 to
5.2
0.2 to
4.8
0.4 to
4.6
0.4 to
4.6
V
Min
Min
A
A
Common-Mode Rejection
Ratio
VO = ± 0.2 V, VCM = 2.5 V
95
80
73
73
dB
Input Resistance
Input Capacitance
100
1.5
kΩ
Typ
Typ
C
C
Each input, referenced to GND
pF
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
4
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS (continued)
Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +2 unless otherwise noted
TYP
OVER TEMPERATURE
TEST
PARAMETER
CONDITIONS
LEVEL(1)
0°C to –40°C to
MIN/
MAX
25°C
25°C
UNITS
70°C
85°C
OUTPUT CHARACTERISTICS
1.1 to
3.9
1.2 to
3.8
1.3 to
3.7
1.3 to
3.7
RL = 100 Ω
Output Voltage Swing
V
Min
A
1 to 4
1.1 to
3.9
1.2 to
3.8
1.2 to
3.8
RL = 1 kΩ
Output Current (Sourcing)
Output Current (Sinking)
Output Impedance
RL = 10 Ω
RL = 10 Ω
f = 100 kHz
140
92
100
65
57
40
57
40
mA
mA
Ω
Min
Min
Typ
A
A
A
0.016
POWER SUPPLY
Maximum Operating Voltage
Minimum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
5
5.5
2.7
5.5
2.7
5.5
2.7
Max
Min
Max
Min
Min
V
A
5
18
18
80
18.9
17.5
73
19.4
16.6
66
19.4
16.6
66
mA
mA
dB
A
A
A
Power Supply Rejection
(+PSRR)
VS+ = 5.5 V to 4.5 V, VS– = 0 V
Power Supply Rejection
(-PSRR)
VS+ = 5 V, VS– = –0.5 V to +0.5
V
60
57
54
54
dB
Min
A
5
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Specifications: VS = 3 V: RF = 249 Ω, RL = 499 Ω, and G = +2 unless otherwise noted
TYP
OVER TEMPERATURE
TEST
–40°C
to
85°C
PARAMETER
CONDITIONS
LEVEL(1)
0°C to
70°C
MIN/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = +1, VO = 100 mVpp
G = +2, VO = 100 mVpp
G = +5, VO = 100 mVpp
G = +10, VO = 100 mVpp
G >+10
3
GHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
C
C
C
C
C
C
C
C
C
C
C
900
190
83
Small-Signal Bandwidth
Gain Bandwidth Product
Large-Signal Bandwidth
830
450
750
675
4.5
20
G = +2, VO = 1 VPP
G = +2, VO = 1-V Step
G = +2, VO = 1-V Step
G = –2, VO = 0.5-V Step
G = –2, VO = 0.5-V Step
G = +2, VO = 0.5-V Step
Slew Rate
Settling Time to 1%
Settling Time to 0.1%
Rise / Fall Times
ns
1.5
ns
Harmonic Distortion
Second Harmonic Distortion
G = +2,
VO = 0.5 VPP
f = 10 MHz
–92
–91
dBc
dBc
Typ
Typ
C
C
,
RL = 499 Ω
Third Harmonic Distortion
Noise Figure
G = +2, f = 1 GHz
f = 1 MHz
15
2.4
2.1
dB
Typ
Typ
Typ
C
C
C
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
nV/√Hz
pA/√Hz
f = 1 MHz
Open-Loop Voltage Gain (AOL
)
VO = ± 0.5 V, VCM = 1.5 V
49
2
44
4
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
A
A
B
A
B
A
B
Input Offset Voltage
5
5
5
5
Input Offset Voltage Drift
Input Bias Current
µV/°C
µA
7
12
1
18
50
1.2
10
18
50
1.2
10
VCM = 1.5 V
Input Bias Current Drift
Input Offset Current
nA/°C
µA
0.4
Input Offset Current Drift
INPUT CHARACTERISTICS
nA/°C
–0.2
to 3.2
0.2 to 0.4 to 0.4 to
Common-Mode Input Range
V
Min
A
2.8
2.6
2.6
Common-Mode Rejection Ratio
Input Resistance
VO = ± 0.09 V, VCM = 1.5 V
92
100
1.5
80
70
70
dB
kΩ
pF
Min
Typ
Typ
A
C
C
Each input, referenced to GND
Input Capacitance
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
6
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS (continued)
Specifications: VS = 3 V: RF = 249 Ω, RL = 499 Ω, and G = +2 unless otherwise noted
TYP
OVER TEMPERATURE
TEST
–40°C
to
85°C
PARAMETER
OUTPUT CHARACTERISTIC
Output Voltage Swing
CONDITIONS
LEVEL(1)
0°C to
70°C
MIN/
MAX
25°C
25°C
UNITS
1.1 to 1.2 to 1.3 to 1.3 to
1.9 1.8 1.7 1.7
RL = 100 Ω
V
Min
A
1 to 2 1.1 to 1.2 to 1.2 to
RL = 1 kΩ
1.9
50
45
1.8
40
35
1.8
40
35
Output Current (Sourcing)
Output Current (Sinking)
Output Impedance
RL = 10 Ω
RL = 10 Ω
f = 100 kHz
57
57
mA
mA
Ω
Min
Min
Typ
A
A
A
0.016
POWER SUPPLY
Maximum Operating Voltage
Minimum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection (+PSRR)
Power Supply Rejection (-PSRR)
3
3
5.5
2.7
17.9
16.5
60
5.5
2.7
18.4
15.6
54
5.5
2.7
18.4
15.6
54
Max
Min
Max
Min
Min
Min
V
A
17.2
17.2
80
mA
mA
dB
A
A
A
A
VS+ = 3.3 V to 2.7 V, VS– = 0 V
VS+ = 5 V, VS– = –0.5 V to +0.5 V
60
55
52
52
dB
7
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
5 V
Frequency response
0.1-dB Flatness
1–3, 5, 6
4
Frequency response by package
S-Parameters
7
vs Frequency
8
2nd Harmonic distortion
3rd Harmonic distortion
2nd Harmonic distortion
3rd Harmonic distortion
vs Frequency
9, 11
10, 12
13
vs Frequency
vs Output voltage
vs Output voltage
vs Frequency
14
IMD3
OIP3
SR
3rd Order intermodulation distortion
3rd Order output intercept point
Slew rate
15
vs Frequency
16
vs Output voltage
vs Frequency
17
Vn/In
Noise
18
Noise figure
vs Frequency
19
Iq
Quiescent current
vs Supply voltage
vs Frequency
20
Rejection ratio
21
VO
Output voltage
vs Load resistance
vs Input common-mode voltage
vs Case temperature
vs Case temperature
vs Frequency
22
VOS
IIB
Input offset voltage
Input bias and offset current
Input offset voltage
Open-loop gain
23
24
VOS
25
26
VO
VO
VO
VO
ZO
3 V
Small-signal transient response
Large-signal transient response
Settling time
27
28
29
Overdrive recovery time
Output impedance
30
vs Frequency
31
Frequency response
2nd Harmonic distortion
3rd Harmonic distortion
Harmonic Distortion
Slew rate
32–35
36
vs Frequency
vs Frequency
37
vs Output voltage
vs Output voltage
38
SR
VO
VO
IIB
39
Settling time
40
Output voltage
vs Load resistance
vs Case temperature
vs Case temperature
41
Input bias and offset current
Input offset voltage
Large-signal transient response
Overdrive recovery time
Output impedance
42
VOS
VO
VO
ZO
43
44
45
vs Frequency
46
8
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
6
5
4
3
2
1
10
24
Gain = 1,
Gain = 2,
R
R
V
= 249 Ω,
= 100 Ω,
= 100 mV
= 5 V
F
L
O
S
22
20
18
R
V
= 100 Ω,
G = 10
G = 5
L
S
9
8
7
6
5
4
3
2
1
0
R
R
V
= 249 Ω,
= 100 Ω,
= 100 mV
= 5 V
V
= 100 mV
PP
F
L
O
S
O
C
= 0 pF
F
= 5 V
PP
V
PP,
V
16
14
12
10
8
V
= 200 mV
PP
O
C
= 0.5 pF
F
1 GHz
G = 2
0
6
V
= 400 mV
PP
C
= 1 pF
O
F
−1
4
−2
−3
−4
2
G = 1, R = 0 Ω
F
V
= 800 mV
PP
O
0
−2
3 GHz
100 M
−4
100 k
10 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
1 M
1 M
10 M 100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
0.1-dB FLATNESS
FREQUENCY RESPONSE
FREQUENCY RESPONSE
22
20
18
16
14
12
10
22
6.4
6.3
6.2
6.1
87 MHz
Gain = 2,
90 MHz
20
18
16
14
12
10
8
R
R
V
= 249 Ω,
= 100 Ω,
F
L
O
S
R
R
V
= 249 Ω,
= 100 Ω,
R
C
R
V
= 249 Ω,
F
L
O
S
F
F
L
O
S
= 0.5 pF,
= 100 Ω,
= 100 mV
= 5 V
,
= 2 V
PP
,
= 1 V
PP
V
= 5 V
,
PP
V
= 5 V
V
300 MHz
200 MHz
175 MHz
6
5.9
5.8
8
6
4
2
6
4
240 MHz
2
480 MHz
R
F
= 0 Ω
R
F
= 0 Ω
0
0
−2
5.7
5.6
−2
−4
1 M
560 MHz
100 M
290 MHz
−4
10 M
1 G
10 G
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
S-PARAMETERS
vs
FREQUENCY
2ND HARMONIC DISTORTION
FREQUENCY RESPONSE
BY PACKAGE
vs
FREQUENCY
−40
−50
−60
−70
−80
−90
10
9
8
7
6
5
4
3
2
1
0
Gain = 2
SOT-23
S21
0
R
V
V
= 249 Ω
= 2 V
= 5 V
F
O
S
PP
SOIC
SOT-23 R = 100 Ω
L
−20
−40
−60
S22
MSOP R = 100 Ω
L
MSOP
S11
S12
Gain = 2,
Gain = 2,
R
R
= 249 Ω,
= 100 Ω,
= 100 mV
= 5 V
F
L
O
S
R
R
O
S
= 249 Ω,
= 100 Ω,
= 100 mV
= 5 V
F
L
−80
,
PP
V
V
−100
−110
,
PP
V
V
MSOP and SOT-23 R = 499 to 1 k Ω
L
−100
10 M
100 M
1 G
10 G
1 M
1 M
10 M
100 M
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
9
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SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V) (continued)
3RD HARMONIC DISTORTION
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−40
−50
−60
−70
−80
−90
−40
−50
−60
−70
−80
−90
−30
−40
Gain = 2,
Gain = 2
Gain = 2,
R
= 249 Ω,
F
O
S
R
V
= 249 Ω
R
V
= 249 Ω,
F
O
S
F
O
S
V
V
= 2 V
,
PP
= 1 V
= 5 V
= 1 V
,
PP
PP
= 5 V
V
V
= 5 V
−50
SOT-23 R = 100 Ω
L
−60
−70
MSOP R = 100 Ω
L
MSOP and SOT-23
MSOP and SOT-23
R
−80
R
L
= 100 Ω to 1 kΩ
= 100 Ω to 1 kΩ
L
−90
−100
−110
−100
−110
−100
−110
MSOP and SOT-23 R = 499 Ω to 1 kΩ
L
10 M
100 M
10 M
100 M
1 M
1 M
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 10.
Figure 11.
Figure 12.
3RD ORDER
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
INTERMODULATION DISTORTION
vs
vs
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
FREQUENCY
−40
−30
−30
−40
Gain = 2,
Gain = 2,
Gain = 2,
R
R
= 249 Ω,
= 100 Ω,
F
L
R
R
= 249 Ω,
= 100 Ω,
R
R
= 249 Ω,
= 100 Ω,
−40
−50
−60
−70
−80
−90
F
L
F
L
−50
−60
200 kHz Spacing,
f = 10 MHz,
f = 10 MHz,
V
= 5 V
−50
S
V
= 5 V
V = 5 V
S
S
V
= 2 V
PP
O
−60
envelope
−70
−70
SOT-23 R = 100 Ω
L
−80
−80
SOT-23 R = 100 Ω to 1 kΩ
L
−90
V
= 1 V
O
PP
−90
envelope
−100
−110
−100
−110
−100
−110
SOT-23 R = 499 Ω to 1 kΩ
L
0
0.5
1
1.5
2
2.5
3
10 M
100 M
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage − V
V
− Output Voltage − V
f − Frequency − Hz
O
PP
O
PP
Figure 13.
Figure 14.
Figure 15.
3RD ORDER
OUTPUT INTERCEPT POINT
SLEW RATE
vs
OUTPUT VOLTAGE
NOISE
vs
FREQUENCY
vs
FREQUENCY
60
50
40
30
20
10
900
850
800
750
700
650
600
550
500
450
400
1000
Gain = 2,
R
R
= 249 Ω,
= 100 Ω,
= 5 V
F
L
S
V
100
Rise
Fall
I
n
10
1
Gain = 2,
R
R
= 249 Ω,
= 100 Ω,
F
L
O
V
n
V
= 2−V envelope,
PP
200−kHz Spacing,
S
V
= 5 V
10
100
1 k
10 k 100 k 1 M 10 M
100 M
0
0.5
1
1.5
2
2.5
3
10 M
f − Frequency − Hz
f − Frequency − Hz
V
− Output Voltage −V
O
PP
Figure 16.
Figure 17.
Figure 18.
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THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V) (continued)
NOISE FIGURE
vs
FREQUENCY
QUIESCENT CURRENT
REJECTION RATIO
vs
vs
SUPPLY VOLTAGE
FREQUENCY
110
22
20
18
16
14
12
10
8
20
18
16
14
12
10
8
V
= 5 V
S
100
90
CMRR
T
= 85°C
A
PSRR+
80
T
A
= 25°C
70
T
A
= −40°C
60
50
PSRR−
40
30
20
10
0
6
Gain = 2,
6
R
F
R
G
R
L
= 249 Ω,
= 249 Ω,
= 100 Ω,
= 5 V
4
4
2
2
V
S
0
0
500 M
1 G
10 M
2.5
3.5
4.5
2
3
4
5
10 k
100 k
1 M
10 M
100 M
1 G
V
− Supply Voltage − V
f − Frequency − Hz
S
f − Frequency − Hz
Figure 19.
Figure 20.
Figure 21.
INPUT BIAS AND OFFSET
CURRENT
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT OFFSET VOLTAGE
vs
INPUT COMMON-MODE VOLTAGE
vs
CASE TEMPERATURE
4
5
9
8
7
6
5
4
3
2
1
0
280
V
= 5 V
S
4.5
V = 5 V
S
I
−
260
240
220
200
180
160
140
120
100
IB
3.5
3
4
3.5
3
2.5
2
I
IB+
V
= 5 V
S
2.5
2
1.5
1
I
OS
1.5
1
0.5
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
10
100
1000
−1
0
1
2
3
4
5
6
Case Temperature − °C
R
L
− Load Resistance − Ω
V
− Input Common-Mode Range − V
ICR
Figure 22.
Figure 23.
Figure 24.
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
OPEN-LOOP GAIN
vs
SMALL-SIGNAL
TRANSIENT RESPONSE
FREQUENCY
600
500
400
300
200
100
0
2.8
80
20
V
= 5 V
V
= 5 V
S
S
Input
2.7
2.6
2.5
2.4
2.3
70
60
0
−20
Gain
50
40
30
20
10
−40
−60
−80
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
Output
Phase
−100
−120
Gain = 2
= 100 Ω
= 249 Ω
t /t = 300 ps
= 5 V
R
R
L
F
0
−10
−20
−140
−160
−180
r
f
V
S
0
10
20
30
40
50
60
10 k
100 k 1 M 10 M 100 M 1 G
10 G
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
t − Time − ns
f − Frequency − Hz
Case Temperature − °C
Figure 25.
Figure 26.
Figure 27.
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SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS (5 V) (continued)
LARGE-SIGNAL
TRANSIENT RESPONSE
OVERDRIVE
RECOVERY TIME
SETTLING TIME
3.5
3
3.5
4.5
4
Input
Input
Gain = 2
3.25
3
4
3.5
3
R
R
V
= 100 Ω
= 249 Ω
= 5 V
L
F
S
3.5
2.5
2
4
3
Output
2.75
2.5
2.25
2
Gain = 2
1.5
3.5
R
R
V
= 100 Ω
= 249 Ω
= 5 V
L
F
2.5
2
2.5
3
Output
S
Gain = 2
2.5
2
1.5
1
R
R
V
= 100 Ω
= 249 Ω
= 5 V
L
F
S
1.5
1
2
1.5
1
1.75
1.5
0.5
0
10
20
30
40
50
60
0
0.1
0.2 0.3 0.4
t − Time − µs
0.5
0.6 0.7
0
1
2
3
4
5
6
7
t − Time − ns
t − Time − ns
Figure 28.
Figure 29.
Figure 30.
OUTPUT IMPEDANCE
vs
FREQUENCY
10 k
Gain = 2,
R
V
= 249 Ω,
= 5 V
1 k
100
10
F
S
1
0.1
0.01
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
Figure 31.
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SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS (3 V)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
24
10
9
8
7
6
5
4
3
2
1
0
10
R
R
= 249 Ω,
= 499 Ω,
= 100 mV
= 3 V
V
= 100 mV
PP
O
F
Gain = 2
9
22
20
18
16
14
12
10
G 10
Gain = 2
R
R
V
= 499 Ω
= 249 Ω,
= 100 mV
= 3 V
C
F
= 0 pF
L
L
F
O
S
R
R
V
= 499 Ω
= 249 Ω,
= 3 V
L
F
S
V
V
,
PP
O
S
8
7
6
5
4
3
2
1
0
PP,
V
G 5
C
= 0.5 pF
F
V
= 200 mV
PP
O
V
V
= 400 mV
O
O
PP
PP
8
6
4
2
G 2
C
F
= 1 pF
−3dB 900 MHz
= 800 mV
G 1, R 0Ω
F
0
−2
−4
1 M
10 M
100 M
1 G
10 G
10 M
100 M
1 G
10 G
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 32.
Figure 33.
Figure 34.
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
vs
vs
FREQUENCY RESPONSE
FREQUENCY
FREQUENCY
22
20
18
16
14
12
10
8
−50
−50
−3 dB 85 MHz
Gain = 2
Gain = 2
R
R
= 499 Ω
= 249 Ω,
= 500 mV
= 3 V
L
R
R
= 499 Ω
= 249 Ω,
= 500 mV
= 3 V
L
F
O
S
F
O
S
−60
−70
−60
−70
V
V
PP,
V
V
PP,
−3 dB 90 MHz
−3 dB 450 MHz
−80
−90
−80
6
4
R
R
= 249 Ω,
= 499 Ω,
F
2
L
−90
0
−2
V
V
= 1 V
= 3 V
,
PP
O
S
−100
−4
−100
1 M
10 M
100 M
1 M
10 M
100 M
1 G
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 35.
Figure 36.
Figure 37.
HARMONIC DISTORTION
vs
SLEW RATE
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
SETTLING TIME
−40
−50
−60
−70
−80
−90
−100
900
850
800
750
700
650
600
550
500
450
400
1.75
Gain = 2
Gain = 2,
Rise
R
R
= 499 Ω
R
R
= 249 Ω,
L
F
F
L
S
= 249 Ω,
= 499 Ω,
= 3 V
1.65
1.55
f = 10 MHz,
V
V
= 3 V
S
Gain = 2
Fall
R
R
V
= 499 Ω
= 249 Ω
= 3 V
L
F
S
1.45
1.35
1.25
HD 2
HD 3
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0
1
2
3
4
5
6
7
8
9
10
V
− Output Voltage − V
V
− Output Voltage − V
t − Time − ns
O
PP
O
PP
Figure 38.
Figure 39.
Figure 40.
13
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
TYPICAL CHARACTERISTICS (3 V) (continued)
INPUT BIAS AND
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
OFFSET CURRENT
vs
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
CASE TEMPERATURE
9
8
7
6
5
4
2.5
2.25
2
2.25
640
620
600
580
560
540
520
500
V
= 3 V
V
= 3 V
V
= 3 V
S
S
S
2
1.75
1.5
I
−
IB
I
IB+
1.75
1.5
1.25
I
OS
3
2
1
0.75
0.5
1.25
1
1
0
480
460
−40
−20
0
20
40
60
80
−40 −20
0
20
40
60
80
10
100
1000
T
C
− Case Temperature − °C
T
C
− Case Temperature − °C
R
L
− Load Resistance − W
Figure 41.
Figure 42.
Figure 43.
OUTPUT IMPEDANCE
vs
LARGE-SIGNAL
TRANSIENT RESPONSE
OVERDRIVE RECOVERY TIME
FREQUENCY
2.5
2.25
2
10 k
1 k
2.25
Input
G = 2,
Gain = 2,
2
R
R
V
= 499 Ω,
= 249 Ω,
= 3 V
2
L
F
R
V
= 249 Ω,
= 3 V
F
S
1.5
1.75
1.5
1.75
S
3
1
100
10
Output
1.5
Input
0.5
2.5
2
1.25
1
1.25
1
1.5
1
Output
Gain = 2,
1
R
F
R
L
= 249 Ω,
= 499 Ω,
= 3 V
0.75
0.5
0.75
0.5
0.1
0.5
0
V
S
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0.01
−10
0
10
20
30
40
50
60
100 k
1 M
10 M
100 M
1 G
t − Time − µs
t − Time − ns
f − Frequency − Hz
Figure 44.
Figure 45.
Figure 46.
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THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
APPLICATION INFORMATION
For many years, high-performance analog design has required the generation of split power supply voltages, like
±15 V, ±8 V, and more recently ±5 V, in order to realize the full performance of the amplifiers available. Modern
trends in high-performance analog are moving towards single-supply operation at 5 V, 3 V, and lower. This
reduces power supply cost due to less voltages being generated and conserves energy in low power
applications. It can also take a toll on available dynamic range, a valuable commodity in analog design, if the
available voltage swing of the signal must also be reduced.
Two key figures of merit for dynamic range are signal-to-noise ratio (SNR) and spurious free dynamic range
(SFDR).
SNR is simply the signal level divided by the noise:
Signal
Noise
SNR +
and SFDR is the signal level divided by the highest spur:
Signal
SFDR +
Spur
In an operational amplifier, reduced supply voltage typically results in reduced signal levels due to lower voltage
available to operate the transistors within the amplifier. When noise and distortion remain constant, the result is a
commensurate reduction in SNR and SFDR. To regain dynamic range, the process and the architecture used to
make the operational amplifier must have superior noise and distortion performance with lower power supply
overhead required for proper transistor operation.
The THS4304 BiCom3 operational amplifier is just such a device. It is able to provide 2-Vpp signal swing at its
output on a single 5-V supply with noise and distortion performance similar to the best 10-V operational
amplifiers on the market today
GENERAL APPLICATION
The THS4304 is a traditional voltage-feedback topology with wideband performance up to 3 GHz at unity gain.
Care must be taken to ensure that parasitic elements do not erode the phase margin.
Capacitance at the output and inverting input, and resistance and inductance in the feedback path, can cause
problems.
To reduce parasitic capacitance, the ground plane should be removed from under the part.
To reduce inductance in the feedback, the circuit traces should be kept as short and direct as possible. For best
performance in non-inverting unity gain (G=+1V/V), it is recommended to use a wide trace directly between the
output and inverting input.
For a gain of +2V/V, it is recommended to use a 249-Ω feedback resistor. With good layout, this should keep the
frequency response peaking to around 2 dB. This resistance is high enough to not load the output excessively,
and the part is capable of driving 100-Ω load with good performance. Higher-value resistors can be used, with
more peaking. For example, 499 Ω gives about 5 dB of peaking, and gives slightly better distortion performance
with 100-Ω load. Lower value feedback resistors can also be used to reduce peaking, but degrades the distortion
performance with heavy loads.
Power supply bypass capacitors are required for proper operation. The most critical are 0.1-µF ceramic
capacitors; these should be placed as close to the part as possible. Larger bulk capacitors can be shared with
other components in the same area as the operational amplifier.
HARMONIC DISTORTION
For best second harmonic (HD2), it is important to use a single-point ground between the power supply bypass
capacitors when using a split supply. It is also recommended to use a single ground or reference point for input
termination and gain-setting resistors (R8 and R11 in the non-inverting circuit). It is recommended to follow the
EVM layout closely in your application.
15
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
APPLICATION INFORMATION (continued)
SOT-23 versus MSOP
With light loading of 500-Ω and higher resistance, the THS4304 shows HD2 that is not dependant of package.
With heavy output loading of 100 Ω, the THS4304 in SOT-23 package shows about 6 dB better HD2
performance versus the MSOP package.
EVALUATION MODULES
The THS4304 has two evaluation modules (EVMs) available. One is for the MSOP (DGK) package and the other
for the SOT-23 (DBV) package. These provide a convenient platform for evaluating the performance of the part
and building various different circuits. The full schematics, board layout, and bill of materials (as supplied) for the
boards are shown in the following illustrations.
−V
S
GND GND +V
S
J3
J4
J6
J5
−V
S
+V
S
FB1
FB2
V
REF
R3
R6
+V
S
C5
C1
C2
C4
GND
TP1
C3
R7
R8
R9
C8
−V
S
+V
S
*
C6
+V
S
U1
C9
J2
4
3
5
R2
THS4304
R1
C7
J1
1
R10
2
*
R12
R11
−V
S
V
REF
*C6 − DGK EVM Only
*R12 − DBV EVM Only
Figure 47. EVM Full Schematic
16
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
APPLICATION INFORMATION (continued)
EVM BILL OF MATERIALS
THS4304 EVM(1)
PCB
SMD
Size
Reference
Manufacturer's
Part Number
Distributor's
Part Number
Item
Description
Designator
Quantity
1
FB1, FB2
2
(STEWARD)
HI1206N800R-00
(DIGI-KEY)
240-1010-1-ND
Bead, ferrite, 3-A, 80-Ω
1206
1206
2
3
Capacitor, 3.3-µF, Ceramic
C1, C2
2
2
(AVX) 1206YG335ZAT2A
(GARRETT)
1206YG335ZAT2A
Capacitor, 0.1-µF, Ceramic
0603
C4, C5
(AVX) 0603YC104KAT2A
(GARRETT)
0603YC104KAT2A
4
5
Open
Open
0603
0603
C3, C6(2)
2
5
R1, R3, R6,
R9, R12(3)
6
7
8
9
Resistor, 0-Ω, 1/10-W, 1%
Resistor, 49.9-Ω, 1/10-W, 1%
Resistor, 249-Ω, 1/10-W, 1%
0603
0603
0603
C7. C8, C9,
C10
4
2
2
4
(KOA) RK73Z1JTTD
(GARRETT)
RK73Z1JTTD
R2, R11
(KOA) RK73H1JLTD49R9F
(KOA) RK73H1JLTD2490F
(HH SMITH) 101
(GARRETT)
RK73H1JLTD49R9F
R7, R8
(GARRETT)
RK73H1JLTD2490F
Jack, banana recepticle, 0.25-in. di-
ameter hole
J3, J4, J5, J6
(NEWARK) 35F865
10 Test point, black
TP1
J1, J2
U1
1
2
1
(KEYSTONE) 5001
(DIGI-KEY) 5001K-ND
(NEWARK) 90F2624
11 Connector, edge, SMA PCB jack
12 Integrated Circuit, THS4304
(JOHNSON) 142-0701-801
(TI) THS4304DGK, or
(TI) THS4304DBV
13 Standoff, 4-40 HEX, 0.625-in.
Length
4
(KEYSTONE) 1808
NEWARK) 89F1934
14 Screw, Phillips, 4-40, 0.250-in.
15 Board, printed-circuit
4
1
SHR-0440-016-SN
(TI) THS4304DGK ENG A, or
(TI) THS4304DBV ENG A
(1) NOTE: All items are designated for both the DBV and DGK EVMs unless otherwise noted.
(2) C6 used on DGK EVM only.
(3) R12 used on DBV EVM only.
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THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
Figure 48. THS4304DGK EVM Layout Top and L2
Figure 49. THS4304DGK EVM Layout Bottom and L3
Figure 50. THS4304DBV EVM Layout Top and L2
Figure 51. THS4304DBV EVM Layout Bottom and L3
18
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
NON-INVERTING GAIN WITH SPLIT SUPPLY
The following schematic shows how to configure the operational amplifier for non-inverting gain with split power
supply (± 2.5V). This is how the EVM is supplied from TI. This configuration is convenient for test purposes
because most signal generators and analyzer are designed to use ground-referenced signals by default. Note
the input and output provides 50-Ω termination.
−V
S
GND GND +V
S
J3
J4
J6
J5
+V
S
−V
S
FB1
FB2
C5
0.1 mF
C1
3.3 mF
C2
3.3 mF
C4
0.1 mF
GND
C8
0
R8
R7
TP1
249 W
249 W
+V
S
U1
4
3
J2
5
R2
49.9 W
C9
1
J1
R10
0
C7
0
0
2
THS4304DBV
R11
49.9 W
−V
S
Figure 52. Non-Inverting Gain with Split Power Supply
19
THS4304
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SLOS436A–MARCH 2004–REVISED JULY 2004
INVERTING GAIN WITH SPLIT POWER SUPPLY
The following schematic shows how to configure the operational amplifier for inverting gain of 1 (–1 V/V) with
split power supply (±2.5 V). Note the input and output provides 50-Ω termination for convenient interface to
common test equipment.
−V
S
GND GND +V
S
J3
J4
J6
J5
+V
S
−V
S
FB1
FB2
C4
0.1 mF
C5
0.1 mF
C1
3.3 mF
C2
3.3 mF
R7
GND
249 W
TP1
J1
C7
0
R9
+V
S
221 W
U1
R11
61.9 W
J2
4
4
3
3
5
5
R2
49.9 W
C9
−
+
1
1
THS4304DBV
0
2
2
R1
124 W
−V
S
C8
0
Figure 53. Inverting Gain with Split Power Supply
20
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
NON-INVERTING SINGLE-SUPPLY OPERATION
The THS4304 EVM can easily be configured for single 5-V supply operation, as shown in the following
schematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken to
reference (or bias) the input signal to mid-supply.
If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input
(C7) and output (C9).
V
REF
−V
S
GND GND +V
S
R3
R6
J3
NC
J4
J6
J5
+V
S
+V
S
FB2
10 kW
10 kW
C8
R8
R7
C2
3.3 mF
C4
0.1 mF
249 W
249 W
GND
TP1
0.1 mF
+V
S
U1
5
5
4
3
3
4
J2
R2
49.9 W
C9
0
−
+
1
1
J1
C7
0
R10
0
THS4304DBV
2
2
R1
49.9 W
C5
0
V
REF
Figure 54. Non-Inverting 5-V Single-Supply Amplifier
DIFFERENTIAL ADC DRIVE AMPLIFIER
The circuit shown in Figure 54 is adapted as shown in Figure 55 to provide a high-performance differential
amplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14-bit 125-MSP ADC). For testing
purposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If the
input signal source in your application is differential and biased to mid-rail, no transformer is required.
The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two
10-kΩ resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in the
single-supply circuit of Figure 54). Applying this voltage to the one side of RG and to the positive input of the
operational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage of
the operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an input
common-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupled
from the amplifier output, via the two 1-nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 is
used to bias the ADC input to the required voltage, via the 1-kΩ resistors. Note: 100-µA common-mode current is
drawn by the ADS5500 input stage (at 125 MSPS). This causes a 100-mV shift in the input common-mode
voltage, which does not impact the performance when driving the input to –1 dB of full scale. To offset this effect,
a voltage divider from the power supply can be used to derive the input common-mode voltage reference.
Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This is
particularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provide
impedance matching and amplification of the signal.
The SFDR performance of the circuit is shown in the following graph (see Figure 56) and provides for full
performance from the ADS5500 to 40 MHz.
21
THS4304
www.ti.com
SLOS436A–MARCH 2004–REVISED JULY 2004
The differential topology employed in this circuit provides for significant suppression of the 2nd-order harmonic
distortion of the amplifiers. This, along with the superior 3rd-order harmonic distortion performance of the
amplifiers, results in the SFDR performance of the circuit (at frequencies up to 40 MHz) being set by higher-order
harmonics generated by the sampling process of the ADS5500.
The amplifier circuit (with resistor divider for bias voltage generation) requires a total of 185 mW of power from a
single 5-V power supply.
+5V
10 k W
V
(= 2.5V)
REF
mF
0.1
10 k W
R
R
F
G
V
REF
+5V
+3.3 VA +3.3 VD
THS4304
1:1
100 W
1nF
CM
V
IN
1kW
A
A
IN+
ADS 5500
D
A
49 .9 W
V
REF
+5V
From
1kW
IN−
CM
50 W
source
THS4304
CM
100 W
1nF
0.1 mF
V
REF
R
R
F
G
Figure 55. Differential ADC Drive Amplifier Circuit
90
Combined THS4304 and
ADS5500 SFDR
85
80
G = 10 dB,
−1 dBFS,
R
R
= 249 Ω,
= 115 Ω,
F
G
SNR = 69.6,
F
S =
125 MSPS
20
75
10
30
40
50
f − Frequency − MHz
Figure 56. SFDR Performance versus Frequency – THS4304 Driving ADS5500
22
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相关型号：
THS4304DGKRG4
IC OP-AMP, 5000 uV OFFSET-MAX, 830 MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MSOP-8, Operational Amplifier
TI
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