THS4500MDGNEP [TI]
增强型产品宽带低失真全差分放大器 | DGN | 8 | -55 to 125;
| 型号： | THS4500MDGNEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品宽带低失真全差分放大器 | DGN | 8 | -55 to 125 放大器 光电二极管 |
| 文件： | 总41页 (文件大小：1454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
宽带、低失真、全差动放大器
查询样品: THS4500-EP
1
特性
23
•
完全差分架构
支持国防、航空航天、和医疗应用
•
带宽：370MHz
•
受控基线
一个组装和测试场所
一个制造场所
•
•
•
•
•
•
•
•
转换速率：2800V/μs
•
互调失真 (IMD)3：30MHz 时为 -90dBc
输出侦听点 (OIP)3：30MHz 频率下为 49dBm
输出共模控制
•
•
•
•
•
支持军用（-55°C 至 125°C）温度范围
延长的产品生命周期
宽电源电压范围：5V，±5V，12V，15V
输入共模范围被位移以包括负电源轨
断电能力 (THS4500)
延长的产品变更通知
产品可追溯性
1
8
V
IN+
提供评估模块
V
IN−
2
7
V
OCM
PD
应用范围
3
4
6
5
V
V
V
S+
OUT+
S−
•
•
•
•
•
高线性模数转换器预放大器
V
无线通信接收器链
单端到差分转换
OUT−
差动线路驱动器
相关器件
器件(1)
说明
差分信号的有源滤波
THS4500/1
THS4502/3
THS4120/1
THS4130/1
THS4140/1
THS4150/1
370MHz，2800V/μs，VICR包括 VS–
370MHz，2800V/μs，中心 VICR
3.3V，100MHz，43V/μs，3.7nV/√Hz
±15V，150MHz，51V/μs，1.3nV/√Hz
±15V，160MHz，450V/μs，6.5nV/√Hz
±15V，150MHz，650V/μs，7.6nV/√Hz
(1) 偶数编号器件特有断电功能。
说明
THS4500 是一款德州仪器 (TI) 生成的高性能、全差动放大器。 特有断电功能的 THS4500 为具有非常卓越线性的
全差动放大器设定了全新的性能标准，从而支持 40MHz 上的 14 位运行。 采用带有 PowerPAD™ 封装，以实现更
小封装尺寸，提升了交流 (ac) 性能，并且改进了散热能力。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLOS832
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
10 pF
APPLICATION CIRCUIT DIAGRAM
THIRD-ORDER INTERMODULATION
DISTORTION
392 Ω
−62
−68
−74
−80
10
12
5 V
V
= 5 V
S
5 V
0.1 µF
10 µF
50 Ω
374 Ω
56.2 Ω
24.9 Ω
24.9 Ω
V
= ±5 V
+
S
−
ADC
12 Bit/80 MSps
IN
V
OCM
V
S
IN
+
−
V
ref
392 Ω
1 µF
V
+
S+
374 Ω
50 Ω
−86
−92
14
16
V
OUT
−
V
OCM
800 Ω
2.5 V
56.2 Ω
V
+
S
402 Ω
−
V
402 Ω
S−
392 Ω
392 Ω
−98
50
10
20
30
40
60
70
80
90
100
10 pF
f − Frequency − MHz
2
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TOP-SIDE
MARKING
TJ
PACKAGE
ORDERABLE PART NUMBER
VID NUMBER
Reel of 3000
Tube of 80
THS4500MDGNREP
THS4500MDGNEP
V62/13610-01XE
MSOP PowerPAD™
(DGN)
-55°C to 125°C
SJE
V62/13610-01XE-T
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
PIN ASSIGNMENTS
DGN
(TOP VIEW)
VIN–
VOCM
VS+
VIN+
PD
1
8
2
7
3
4
6
5
VS-
VOUT-
VOUT+
Copyright © 2013, Texas Instruments Incorporated
3
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
16.5 V
±VS
Supply voltage, VS
Input voltage, VI
(2)
Output current, IO
150 mA
4 V
Differential input voltage, VID
(3)
Maximum junction temperature, TJ
+150°C
Storage temperature range, Tstg
–65°C to +150°C
+300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
CDM
MM
4000 V
ESD rating:
1000 V
100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The THS4500/1 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
THERMAL INFORMATION
THS4500
THERMAL METRIC(1)
DGN
8 PINS
63.1
46.2
33.9
1.9
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
ψJB
33.6
11.9
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
±7.5
15
UNIT
V
Dual supply
±5
Supply voltage
Single supply
5
Operating junction temperature, TJ
-55
125
°C
4
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
ELECTRICAL CHARACTERISTICS: VS = ±5 V
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
G = +1, PIN = –20 dBm, RF = 392 Ω
G = +2, PIN = –30 dBm, RF = 1 kΩ
G = +5, PIN = –30 dBm, RF = 2.4 kΩ
G = +10, PIN = –30 dBm, RF = 5.1 kΩ
G > +10
370
175
70
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
ns
Small-signal bandwidth
30
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate
300
150
220
2800
0.4
PIN = –20 dBm
VP = 2 V
4 VPP Step
Rise time
2 VPP Step
Fall time
2 VPP Step
0.5
ns
Settling time to 0.01%
0.1%
VO = 4 VPP
8.3
ns
VO = 4 VPP
6.3
ns
Harmonic distortion
G = +1, VO = 2 VPP
f = 8 MHz
–82
–71
–97
–74
dBc
dBc
dBc
dBc
2nd harmonic
3rd harmonic
f = 30 MHz
f = 8 MHz
f = 30 MHz
VO= 2 VPP, fC= 30 MHz, RF = 392 Ω,
Third-order intermodulation distortion
Third-order output intercept point
–90
49
dBc
200 kHz tone spacing
fC = 30 MHz, RF = 392 Ω,
Referenced to 50 Ω
dBm
Input voltage noise
f > 1 MHz
f > 100 kHz
7
nV/√Hz
pA/√Hz
ns
Input current noise
1.7
60
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Overdrive = 5.5 V
49
dB
mV
-11
6
6.6
2
Average offset voltage drift
Input bias current
±10
±10
±40
μV/°C
μA
Average bias current drift
Input offset current
nA/°C
μA
Average offset current drift
INPUT
nA/°C
Common-mode input range
Common-mode rejection ratio
Input impedance
-5.1
70
2
V
dB
107 || 1
Ω || pF
OUTPUT
Differential output voltage swing
Differential output current drive
Output balance error
RL = 1 kΩ
RL = 20 Ω
±7.25
90
V
mA
dB
PIN = –20 dBm, f = 100 kHz
-58
0.1
Closed-loop output impedance (single-
ended)
f = 1 MHz
Ω
Copyright © 2013, Texas Instruments Incorporated
5
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RL = 400 Ω
180
92
MHz
V/μs
V/V
V/V
mV
μA
2 VPP Step
Minimum gain
0.98
-7.6
±3.4
Maximum gain
1.08
15
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
170
Input voltage range
V
Input impedance
25 || 1
kΩ || pF
V
Maximum default voltage
Minimum default voltage
POWER SUPPLY
VOCM left floating
VOCM left floating
0.10
-0.10
V
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power-supply rejection (±PSRR)
POWER-DOWN
7.5
40
V
mA
mA
dB
11
70
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
Device enabled ON above –2.9 V
Device disabled OFF below –4.3 V
-2.9
V
V
-4.3
1400
260
μA
μA
Input impedance
50 || 1
1000
800
kΩ || pF
ns
Turn-on time delay
Turn-off time delay
ns
6
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
ELECTRICAL CHARACTERISTICS: VS = 5 V
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
G = +1, PIN = –20 dBm, RF = 392 Ω
G = +2, PIN = –30 dBm, RF = 1 kΩ
G = +5, PIN = –30 dBm, RF = 2.4 kΩ
G = +10, PIN = –30 dBm, RF = 5.1 kΩ
G > +10
320
160
60
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
ns
Small-signal bandwidth
30
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate
300
180
200
1300
0.5
PIN = –20 dBm
VP = 1 V
2 VPP Step
Rise time
2 VPP Step
Fall time
2 VPP Step
0.6
ns
Settling time to 0.01%
0.1%
VO = 2 V Step
13.1
8.3
ns
VO = 2 V Step
ns
Harmonic distortion
G = +1, VO = 2 VPP
f = 8 MHz,
-80
-55
-76
-60
7
dBc
dBc
2nd harmonic
3rd harmonic
f = 30 MHz
f = 8 MHz
dBc
f = 30 MHz
dBc
Input voltage noise
f > 1 MHz
nV/√Hz
pA/√Hz
ns
Input current noise
f > 100 kHz
1.7
60
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Overdrive = 5.5 V
48
dB
mV
-11
6
8
2
Average offset voltage drift
Input bias current
±10
±10
±20
μV/°C
μA
Average bias current drift
Input offset current
nA/°C
μA
Average offset current drift
INPUT
nA/°C
Common-mode input range
Common-mode rejection ratio
Input Impedance
-0.1
65
2
V
dB
107 || 1
Ω || pF
OUTPUT
Differential output voltage swing
Output current drive
Output balance error
RL = 1 kΩ, Referenced to 2.5 V
RL = 20 Ω
±2.7
80
V
mA
dB
PIN = –20 dBm, f = 100 kHz
-58
0.1
Closed-loop output impedance (single-
ended)
f = 1 MHz
Ω
Copyright © 2013, Texas Instruments Incorporated
7
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
Applicable for –55ºC ≤ TJ ≤ +125ºC, RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
PARAMETER
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RL = 400 Ω
180
80
MHz
V/μs
V/V
V/V
mV
μA
2 VPP Step
Minimum gain
0.92
-5.6
1.3
Maximum gain
1.17
35
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
3
Input voltage range
3.7
V
Input impedance
25 || 1
kΩ || pF
V
Maximum default voltage
Minimum default voltage
POWER SUPPLY
VOCM left floating
VOCM left floating
2.75
2.25
V
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power-supply rejection (+PSRR)
POWER -DOWN
15
38
V
mA
mA
dB
10
66
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
Device enabled ON above 2.1 V
Device disabled OFF below 0.7 V
2.1
0.7
V
V
1400
140
μA
μA
Input impedance
50 || 1
1000
800
kΩ || pF
ns
Turn-on time delay
Turn-off time delay
ns
100,000,000
10,000,000
1,000,000
100,000
10,000
Wirebond Voiding Fail Mode
Electromigration Failure Mode
1,000
80
90
100
110
120
130
140
150
Continuous T (°C)
J
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) Enhanced plastic product disclaimer applies.
(4) Electromigration calculation is based on output switching 50% duty cycle at max load of 120 mA.
Figure 1. THS4500-EP Derating Chart
8
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
0.1-dB GAIN FLATNESS FREQUENCY
RESPONSE
RESPONSE
0.3
1
22
Gain = 1
Gain = 10, R = 5.1 kΩ
f
0.5
20
18
16
14
12
10
R
= 800 Ω
= −20 dBm
= ±5 V
L
0.2
0.1
0
P
V
IN
S
0
−0.5
−1
Gain = 5, R = 2.4 kΩ
f
R = 499 Ω
f
−1.5
−2
8
6
4
2
R = 392 Ω
f
Gain = 2, R = 1 kΩ
f
Gain = 1
−0.1
−2.5
−3
R
L
= 800 Ω
R = 392 Ω
f
R
P
V
= 800 Ω
= −30 dBm
= ±5 V
−0.2
−0.3
L
P
V
= −20 dBm
= ±5 V
IN
S
−3.5
−4
IN
S
0
−2
0.1
10
100
1000
0.1
1
10
100
1000
1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 2.
Figure 3.
Figure 4.
HARMONIC DISTORTION
HARMONIC DISTORTION
LARGE-SIGNAL FREQUENCY
RESPONSE
vs
vs
FREQUENCY
FREQUENCY
1
0
0
0
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
−10
−10
−20
−30
−40
−50
−60
−70
−80
−20
−30
−40
−50
−60
−70
−80
R
L
= 800 Ω
R = 800 Ω
L
R = 392 Ω
f
R = 392 Ω
f
V
V
= 1 V
= ±5 V
V
V
= 1 V
PP
= ±5 V
−1
−2
O
S
PP
O
S
Gain = 1
HD2
R
L
= 800 Ω
HD2
10
R = 392 Ω
−3
−4
f
P
V
= 10 dBm
= ±5 V
IN
S
−90
−90
HD3
HD3
−100
−100
0.1
1
100
0.1
1
10
100
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 5.
Figure 6.
Figure 7.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
OUTPUT VOLTAGE SWING
0
0
−10
−20
0
−10
−20
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
= 800 Ω
R = 392 Ω
Differential Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
= 800 Ω
R
R = 800 Ω
L
R = 392 Ω
f
L
L
−30
−40
−30
−40
R = 392 Ω
f
f
f= 8 MHz
V
V
= 2 V
= ±5 V
V
V
= 2 V
PP
= ±5 V
O
S
PP
O
S
V
= ±5 V
S
−50
−60
−70
−80
−50
−60
−70
−80
HD2
HD2
10
HD2
10
HD3
−90
−90
HD3
4
HD3
−100
−100
0
0.5
1
1.5
2
2.5
3
3.5
4.5
5
0.1
1
100
0.1
1
100
V
− Output Voltage Swing − V
f − Frequency − MHz
f − Frequency − MHz
O
Figure 8.
Figure 9.
Figure 10.
Copyright © 2013, Texas Instruments Incorporated
9
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
0
0
0
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
−10
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
R = 499 Ω
R = 392 Ω
R = 392 Ω
f
f
f
f= 8 MHz
f= 30 MHz
f= 30 MHz
V = ±5 V
S
V
= ±5 V
V
= ±5 V
S
S
HD2
HD2
HD2
HD3
HD3
3
HD3
4.5
0
0.5
1
1.5
2
2.5
3
3.5
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3.5
4
4.5
5
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
V − Output Voltage Swing − V
O
O
O
Figure 11.
Figure 12.
Figure 13.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
0
−10
−20
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
= 800 Ω
R = 1 kΩ
Single-Ended Input to
Differential Output
Gain = 2
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
= 800 Ω
R
R = 800 Ω
L
R = 1 kΩ
f
L
L
−30
−40
−50
R = 1 kΩ
f
f
V
V
= 1 V
PP
= ±5 V
V
V
= 1 V
= ±5 V
V
V
= 2 V
PP
= ±5 V
O
S
O
S
PP
O
S
HD2
−60
−70
−80
HD2
HD2
HD3
HD3
−90
HD3
−100
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 14.
Figure 15.
Figure 16.
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
FREQUENCY
0
0
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
−30
−40
−50
R = 1 kΩ
R = 1 kΩ
R = 1 kΩ
f
f
f
V
V
= 2 V
PP
= ±5 V
f= 8 MHz
f= 8 MHz
V = ±5 V
S
O
S
V
= ±5 V
S
HD2
−60
−70
−80
HD2
2.5
HD2
HD3
−90
HD3
3.5
HD3
3.5
−100
0
0.5
1
1.5
2
3
4
4.5
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0.1
1
10
100
f − Frequency − MHz
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
O
Figure 17.
Figure 18.
Figure 19.
10
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THS4500-EP
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ZHCSB54 –JUNE 2013
TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
LOAD RESISTANCE
0
0
0
Single-Ended Input to
Differential Output
Gain = 2
Differentia Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 1
−10
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
R
L
= 800 Ω
R = 800 Ω
L
V
= 2 V
PP
O
R = 1 kΩ
R = 1 kΩ
R = 392 Ω
f
f
f
f= 30 MHz
f= 8 MHz
V = ±5 V
S
f= 30 MHz
V
= ±5 V
V
= ±5 V
S
S
HD2
HD2
−60
−70
−80
HD2
HD3
HD3
3.5
HD3
3.5
−90
−100
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0
400
800
1200
1600
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
R
L
− Load Resistance − Ω
O
Figure 20.
Figure 21.
Figure 22.
THIRD-ORDER INTERMODULATION
THIRD-ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION
vs
LOAD RESISTANCE
DISTORTION
vs
POINT
vs
FREQUENCY
FREQUENCY
55
−50
0
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
Gain = 1
−10
R
V
= 392 W
F
50
45
40
−60
−70
−80
−20
−30
−40
−50
= 2 V
O
S
PP
R
L
= 800 Ω
V
= 2 V
PP
O
V
= ± 5 V
R = 392 Ω
R = 392 Ω
f
f
V
V
= 2 V
PP
= ±5 V
f= 30 MHz
O
S
V
= ±5 V
S
−60
−70
−80
HD2
35
30
−90
HD3
−90
−100
−100
10
100
0
20
40
60
80
100
120
0
400
800
1200
1600
f − Frequency − MHz
f - Frequency - MHz
R
L
− Load Resistance − Ω
Figure 23.
Figure 24.
Figure 25.
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
SETTLING TIME
SETTLING TIME
3000
1.5
0.8
0.6
0.4
0.2
0
Gain = 1
= 800 Ω
Rising Edge
Rising Edge
R
L
2500
2000
1500
1.0
0.5
R = 392 Ω
f
V
= ±5 V
S
Gain = 1
Gain = 1
= 800 Ω
R
R
= 800 W
= 499 W
R
L
L
R = 499 Ω
F
f
f = 1 MHz
= ±5 V
f= 1 MHz
0
-0.5
-1.0
V
V
= ±5 V
S
S
−0.2
−0.4
1000
500
0
Falling Edge
Falling Edge
−0.6
−0.8
-1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
5
10
15
20
0
2
4
6
8
10
12
14
t - Time - ns
t − Time − ns
V
− Differential Output Voltage Step − V
O
Figure 26.
Figure 27.
Figure 28.
Copyright © 2013, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS: ±5 V (continued)
LARGE-SIGNAL TRANSIENT
SMALL-SIGNAL TRANSIENT
RESPONSE
RESPONSE
OVERDRIVE RECOVERY
0.4
0.3
0.2
0.1
2.5
2
5
4
3
2
Gain = 4
= 800 Ω
R
L
1.5
R = 499 Ω
1.5
f
Overdrive = 4.5 V
1
1
2
1
V
= ±5 V
Gain = 1
S
Gain = 1
0.5
R
L
= 800 Ω
R
L
= 800 Ω
0.5
0
R = 499 Ω
R = 499 Ω
f
f
0
0
0
−0.5
−1
t /t = 300 ps
t /t = 300 ps
r
f
r
f
V
= ±5 V
V
= ±5 V
−0.5
S
S
−1
−0.1
−1
−2
−3
−0.2
−0.3
−0.4
−1.5
−1.5
−2
−2
−4
−5
−2.5
−100
0
100
200
300
400
500
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t − Time − µs
1
−100
0
100
200
300
400
500
t − Time − ns
t − Time − ns
Figure 29.
Figure 30.
Figure 31.
VOLTAGE AND CURRENT NOISE
REJECTION RATIOS
vs
vs
OVERDRIVE RECOVERY
FREQUENCY
FREQUENCY
200
150
100
50
90
80
70
60
50
40
30
20
10
0
100
V
= ±5 V
S
PSRR+
Source
CMMR
V
n
PSRR−
10
0
−50
I
n
Sink
R
= 800 Ω
= ±5 V
L
−100
−150
V
S
1
0.01 0.1
−10
1
10
100 1000 10 k
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0.1
1
10
100
f − Frequency − MHz
f − Frequency − kHz
Case Temperature − °C
Figure 32.
Figure 33.
Figure 34.
REJECTION RATIOS
vs
CASE TEMPERATURE
OUTPUT BALANCE ERROR
OPEN-LOOP GAIN AND PHASE
vs
vs
FREQUENCY
FREQUENCY
120
100
0
60
30
P
R
= 10 dBm
= 800 Ω
Gain
P
R
V
= −30 dBm
= 800 Ω
= ±5 V
IN
IN
−10
−20
−30
−40
−50
−60
−70
−80
CMMR
L
L
50
40
30
20
0
R = 392 Ω
V
f
S
PSRR+
= ±5 V
S
80
60
40
20
0
−30
−60
−90
Phase
−120
−150
10
0
R
= 800 Ω
= ±5 V
L
V
S
0.1
1
10
100
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
0.01
0.1
1
10
100
1000
f − Frequency − MHz
Case Temperature − °C
f − Frequency − MHz
Figure 35.
Figure 36.
Figure 37.
12
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THS4500-EP
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ZHCSB54 –JUNE 2013
TYPICAL CHARACTERISTICS: ±5 V (continued)
OPEN-LOOP GAIN
vs
INPUT BIAS AND OFFSET CURRENT
vs
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
CASE TEMPERATURE
CASE TEMPERATURE
35
30
25
20
15
10
3.4
3.3
0
58
57
56
55
54
53
52
51
50
49
V
= ±5 V
S
T = 85°C
A
I
R
V
= 800 Ω
= ±5 V
−0.01
IB−
L
S
T
A
= 25°C
−0.02
−0.03
−0.04
−0.05
3.2
3.1
I
IB+
T
A
= −40°C
3
2.9
−0.06
−0.07
−0.08
−0.09
2.8
2.7
I
OS
2.6
2.5
5
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
V
− Supply Voltage − ±V
S
Figure 38.
Figure 39.
Figure 40.
INPUT OFFSET VOLTAGE
COMMON-MODE REJECTION RATIO
OUTPUT DRIVE
vs
CASE TEMPERATURE
vs
vs
CASE TEMPERATURE
INPUT COMMON-MODE RANGE
7
200
110
V
= ±5 V
S
V
= ±5 V
V = ±5 V
S
S
100
90
80
70
60
50
40
30
20
10
Source
150
100
50
6
5
4
3
2
0
−50
1
0
Sink
−100
−150
0
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
6
Case Temperature − °C
Case Temperature − °C
Input Common-Mode Voltage Range − V
Figure 41.
Figure 42.
Figure 43.
HARMONIC DISTORTION
vs
OUTPUT OFFSET VOLTAGE AT VOCM
vs
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT COMMON-MODE VOLTAGE
OUTPUT COMMON-MODE VOLTAGE
0
600
Single-Ended and Differential
3
2
−10
Input to Differential Output
Gain = 1, V = 2 V
Gain = 1
R = 800 Ω
L
400
200
O
PP
−20
R = 392 Ω
f= 8 MHz, R = 392 Ω
f
f
−30
−40
−50
−60
V
= ±5 V
P
V
= −20 dBm
= ±5 V
S
IN
1
S
HD2-SE
0
0
HD2
-Diff
HD3-SE
HD3-Diff
−200
−70
−80
−1
−400
−600
−2
−3
−90
−100
−3.5 −2.5 −1.5 −0.5 0.5
1.5
2.5 3.5
−5 −4 −3 −2 −1
0
1
2
3
4
5
1
10
100
1000
V
− Output Common-Mode Voltage − V
OC
V
− Output Common-Mode Voltage − V
OC
f − Frequency − MHz
Figure 44.
Figure 45.
Figure 46.
Copyright © 2013, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS: ±5 V (continued)
SINGLE-ENDED OUTPUT
QUIESCENT CURRENT
IMPEDANCE IN POWER-DOWN
vs
TURN-ON AND TURN-OFF DELAY
TIME
vs
POWER-DOWN VOLTAGE
FREQUENCY
30
25
20
15
10
800
700
600
500
400
300
200
0.03
0.02
0.01
Current
0
0
−1
−2
−3
−4
Gain = 1
R
L
= 800 Ω
5
R = 392 Ω
f
P
V
= −1 dBm
= ±5 V
IN
S
0
100
0
−5
−6
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
0
0.1
1
10
100
1000
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
f − Frequency − MHz
Power-Down Voltage − V
t − Time − ms
Figure 47.
Figure 48.
Figure 49.
POWER-DOWN QUIESCENT CURRENT
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
1000
vs
SUPPLY VOLTAGE
1000
900
800
700
600
500
400
300
200
R
L
= 800 Ω
R
= 800 Ω
= ±5 V
L
900
800
700
V
S
600
500
400
300
200
100
0
100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
V
− Supply Voltage − ±V
Case Temperature − °C
S
Figure 50.
Figure 51.
14
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THS4500-EP
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ZHCSB54 –JUNE 2013
TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
0.1-dB GAIN FLATNESS FREQUENCY
RESPONSE
RESPONSE
0.2
1
0
22
Gain = 10, R = 5.1 kΩ
f
R = 499 Ω
f
20
18
16
14
12
10
0.1
0
Gain = 5, R = 2.4 kΩ
f
R = 392 Ω
f
−1
−2
−0.1
−0.2
8
6
4
2
Gain = 2, R = 1 kΩ
f
Gain = 1
= 800 Ω
−0.3
R
L
Gain = 1
R = 392 Ω
−3
−4
f
R
= 800 Ω
= −20 dBm
= 5 V
L
R
= 800 Ω
= −30 dBm
= 5 V
L
P
V
= −20 dBm
= 5 V
−0.4
−0.5
IN
S
P
V
IN
S
P
V
IN
S
0
−2
0.1
10
100
1000
0.1
1
10
100
1000
1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 52.
Figure 53.
Figure 54.
HARMONIC DISTORTION
HARMONIC DISTORTION
LARGE-SIGNAL FREQUENCY
RESPONSE
vs
vs
FREQUENCY
FREQUENCY
0
0
1
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
−10
−10
−20
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
R
L
= 800 Ω
R
L
= 800 Ω
−30
−40
R = 392 Ω
R = 392 Ω
f
f
V
V
= 1 V
= 5 V
V
V
= 1 V
= 5 V
O
S
PP
−1
O
S
PP
−50
−60
−70
−80
−2
−3
−4
HD2
HD2
Gain = 1
R
L
= 800 Ω
R = 392 Ω
f
HD3
P
V
= 10 dBm
= 5 V
HD3
IN
S
−90
−100
0.1
1
10
100
1000
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 55.
Figure 56.
Figure 57.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
OUTPUT VOLTAGE SWING
0
0
0
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−10
−20
−30
−40
−10
−20
−30
−40
−50
−60
R
= 800 Ω
R
= 800 Ω
L
L
R
= 800 Ω
L
R = 499 Ω
R = 392 Ω
f
f
R = 392 Ω
f
V
V
= 2 V
= 5 V
V
V
= 2 V
= 5 V
O
S
PP
O
S
PP
f= 8 MHz
V
= 5 V
S
−50
−60
−70
−80
HD3
HD3
HD3
−70
−80
HD2
HD2
HD2
2.5
−90
−90
−90
−100
−100
−100
0.1
1
10
100
0.1
1
10
100
0
0.5
1
1.5
2
3
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage Swing − V
O
Figure 58.
Figure 59.
Figure 60.
Copyright © 2013, Texas Instruments Incorporated
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ZHCSB54 –JUNE 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
0
−10
−20
0
−10
−20
0
−10
−20
Single-Ended Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
R
L
= 800 Ω
R
= 800 Ω
R = 800 Ω
L
L
R = 392 Ω
f = 30 MHz
−30
−40
−50
−60
−30
−40
−50
−60
−30
−40
−50
−60
R = 392 Ω
f= 8 MHz
R = 392 Ω
f= 30 MHz
V = 5 V
S
f
f
f
HD3
HD3
V
= 5 V
V
= 5 V
S
S
HD2
HD2
HD3
−70
−80
−70
−80
−70
−80
HD2
−90
−90
−90
−100
−100
−100
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
V − Output Voltage Swing − V
O
O
O
Figure 61.
Figure 62.
Figure 63.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
0
−10
−20
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−10
−20
−30
−20
−30
R
= 800 Ω
R
= 800 Ω
R = 800 Ω
L
R = 1 kΩ
f
L
L
−30
−40
−50
R = 1 kΩ
R = 1 kΩ
f
f
V
V
= 1 V
= 5 V
V
V
= 1 V
= 5 V
V
V
= 2 V
= 5 V
O
S
PP
O
S
PP
O
S
PP
−40
−40
−50
−60
−50
−60
HD2
HD3
−60
−70
−80
HD3
−70
−80
−70
HD2
−80
−90
HD2
HD3
−90
−90
−100
−100
−100
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 64.
Figure 65.
Figure 66.
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
FREQUENCY
0
0
0
Single-Ended Input to
Differential Output
Gain = 2
Differential Input to
Differential Output
Gain = 2
Differential Input to
Differential Output
Gain = 2
−10
−10
−20
10
20
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
L
= 800 Ω
R
R
= 800 W
= 1 kW
L
R = 1 kΩ
R = 1 kΩ
−30
−40
−50
−60
30
40
50
60
f
f
F
f = 8 MHz
V
V
= 2 V
= 5 V
f = 8 MHz
= 5 V
O
S
PP
V
= 5 V
V
S
S
HD3
HD3
HD3
−70
−80
70
80
HD2
HD2
2.5
HD2
−90
90
−100
100
0
0.5
1
1.5
2
3
0.1
1
10
100
0
0.5
1
1.5
2
2.5
3
f − Frequency − MHz
V
− Output Voltage Swing − V
V
- Output Voltage Swing - V
O
O
Figure 67.
Figure 68.
Figure 69.
16
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TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
LOAD RESISTANCE
0
−10
−20
0
−10
−20
−30
−40
−50
−60
−70
−80
0
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 2
Differential Input to
Differential Output
Gain = 2
10
20
V
= 2 V
PP
R
= 800 Ω
O
R
R
= 800 W
= 1 kW
L
L
R = 392 Ω
R = 1 kΩ
−30
−40
−50
−60
30
40
50
60
f
f
F
f= 30 MHz
f = 30 MHz
f = 30 MHz
= 5 V
V
= 5 V
V
= 5 V
S
V
S
S
HD2
HD3
HD2
HD3
HD2
HD3
−70
−80
70
80
−90
90
−90
−100
100
−100
0
400
800
1200
1600
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage Swing − V
R
L
− Load Resistance − Ω
V
- Output Voltage Swing - V
O
O
Figure 70.
Figure 71.
Figure 72.
THIRD-ORDER INTERMODULATION
THIRD-ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION
vs
LOAD RESISTANCE
DISTORTION
vs
POINT
vs
FREQUENCY
FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
55
−50
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Gain = 1
= 2 V
V
O
PP
50
45
40
R
F
R
L
V
= 392 W
= 800 W
= 5 V
−60
−70
−80
V
= 2 V
PP
V
= 2 V
PP
O
O
R
F
= 392 W
R = 392 Ω
f
S
f = 30 MHz
= 5 V
R
V
= 800 Ω
= 5 V
L
V
S
S
HD2
HD3
35
30
−90
−100
-100
0
400
800
1200
1600
0
20
40
60
80
100
120
10
100
R
- Load Resistance - W
f − Frequency − MHz
f - Frequency - MHz
L
Figure 73.
Figure 74.
Figure 75.
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
STEP
1400
2
0.4
0.3
0.2
Gain = 1
= 800 Ω
1.5
R
L
1200
R = 392 Ω
f
1
V
= 5 V
S
1000
800
600
400
200
0
Gain = 1
Gain = 1
R = 800 Ω
L
R = 392 Ω
f
0.5
0.1
0
R
L
= 800 Ω
R = 392 Ω
f
0
−0.5
−1
t /t = 300 ps
r
f
t /t = 300 ps
r
f
V
= 5 V
S
V
= 5 V
S
−0.1
−0.2
−0.3
−0.4
−1.5
−2
−100
0
100
200
300
400
500
0
0.5
1
1.5
2
2.5
3
−100
0
100
200
300
400
500
t − Time − ns
t − Time − ns
V
− Differential Output Voltage Step − V
O
Figure 76.
Figure 77.
Figure 78.
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TYPICAL CHARACTERISTICS: 5 V (continued)
REJECTION RATIOS
vs
REJECTION RATIOS
VOLTAGE AND CURRENT NOISE
vs
vs
FREQUENCY
FREQUENCY
CASE TEMPERATURE
90
80
70
60
50
40
30
20
10
0
100
120
100
PSRR+
CMMR
PSRR−
80
60
40
CMMR
PSRR+
V
n
PSRR−
10
I
n
20
0
R
V
= 800 Ω
= 5 V
R
V
= 800 Ω
L
L
= 5 V
S
S
1
0.01 0.1
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1
10
100 1000 10 k
0.1
1
10
100
Case Temperature − °C
f − Frequency − MHz
f − Frequency − kHz
Figure 79.
Figure 80.
Figure 81.
OUTPUT BALANCE ERROR
OPEN-LOOP GAIN AND PHASE
OPEN-LOOP GAIN
vs
vs
vs
FREQUENCY
FREQUENCY
CASE TEMPERATURE
0
60
57
56
55
54
53
52
51
50
49
48
47
46
30
R = 800 Ω
L
Gain
P
R
V
= −30 dBm
= 800 Ω
= 5 V
P
= −20 dBm
IN
IN
−10
−20
−30
−40
−50
V
= 5 V
S
R
L
= 800 Ω
L
50
40
30
20
0
R = 499 Ω
S
f
V
= 5 V
S
−30
−60
−90
Phase
−120
−150
10
0
−60
−70
−40−30−20−100 10 20 30 40 50 60 70 80 90
0.1
1
10
100
0.01
0.1
1
10
100
1000
f − Frequency − MHz
Case Temperature − °C
f − Frequency − MHz
Figure 82.
Figure 83.
Figure 84.
QUIESCENT CURRENT
vs
INPUT OFFSET VOLTAGE
vs
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
SUPPLY VOLTAGE
CASE TEMPERATURE
3.75
3.5
0
35
30
25
20
15
10
4
V
= 5 V
T
A
= 85°C
S
V
= 5 V
−0.01
−0.02
−0.03
−0.04
−0.05
−0.06
−0.07
−0.08
S
3.5
3
I
IB+
T
A
= 25°C
3.25
3
I
IB−
T
A
= −40°C
2.75
2.5
2.5
2
I
OS
2.25
1.5
2
1
0.5
0
1.75
5
0
−0.09
−0.1
1.5
1.25
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Case Temperature − °C
Case Temperature − °C
V
− Supply Voltage − ±V
S
Figure 85.
Figure 86.
Figure 87.
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TYPICAL CHARACTERISTICS: 5 V (continued)
OUTPUT DRIVE
vs
HARMONIC DISTORTION
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
vs
CASE TEMPERATURE
OUTPUT COMMON-MODE VOLTAGE
0
110
100
90
150
100
50
Single-Ended and
Differential Input
Gain = 1
V
= 5 V
S
Source
V
= 5 V
S
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
V
= 2 V
PP
O
80
R = 392 Ω
f
70
f= 8 MHz, V = 5 V
S
60
50
0
HD3-SE
and Diff
40
30
−50
20
10
−100
−150
Sink
HD2-SE
HD2-Diff
0
−10
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
1
1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
−1
0
1
2
3
4
5
V
− Output Common-Mode Voltage − V
Input Common-Mode Range − V
Case Temperature − °C
OCM
Figure 88.
Figure 89.
Figure 90.
QUIESCENT CURRENT
vs
OUTPUT OFFSET VOLTAGE
vs
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT COMMON-MODE VOLTAGE
POWER-DOWN VOLTAGE
800
25
20
4
3
V
= 5 V
S
Gain = 1
600
400
200
R
L
= 800 Ω
R = 392 Ω
f
P
V
= −20 dBm
= 5 V
IN
2
S
15
10
5
1
0
0
−200
−400
−600
−800
−1
−2
−3
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
0.1
1
10
100
1000
Power-down Voltage − V
V
− Output Common-Mode Voltage − V
OC
f − Frequency − MHz
Figure 91.
Figure 92.
Figure 93.
SINGLE-ENDED OUTPUT
POWER-DOWN QUIESCENT
CURRENT
IMPEDANCE IN POWER-DOWN
TURN-ON AND TURN-OFF DELAY
TIME
vs
vs
FREQUENCY
CASE TEMPERATURE
800
700
600
500
1100
0.03
R
L
= 800 Ω
1000
900
800
700
0.02
V
= 5 V
S
0.01
Current
0
0
600
500
400
300
200
−1
400
300
−2
−3
−4
Gain = 1
R
L
= 400 Ω
200
R = 499 Ω
f
P
V
= −1 dBm
= 5 V
IN
S
100
0
100
0
0.1
−5
−6
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1
10
100
1000
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
f − Frequency − MHz
Case Temperature − °C
t − Time − ms
Figure 94.
Figure 95.
Figure 96.
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TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1000
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
V
− Supply Voltage − V
S
Figure 97.
20
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
FULLY DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers are typically packaged in
eight-pin packages, as shown in Figure 98. The
device pins include two inputs (VIN+, VIN–), two
outputs (VOUT–, VOUT+), two power supplies (VS+, VS–),
an output common-mode control pin (VOCM), and an
optional power-down pin (PD).
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external common-
mode noise, suppression of even-order nonlinearities,
and increased dynamic range. Fully differential
amplifiers not only serve as the primary means of
providing gain to a differential signal chain, but also
provide a monolithic solution for converting single-
ended signals into differential signals for easier,
higher performance processing. The THS4500 family
of amplifiers contains products in Texas Instruments'
expanding line of high-performance, fully differential
amplifiers. Information on fully differential amplifier
fundamentals, as well as implementation specific
information, is presented in the Applications Section
of this data sheet to provide a better understanding of
the operation of the THS4500 family of devices, and
to simplify the design process for designs using these
amplifiers.
VIN-
VOCM
VS+
VIN+
PD
1
8
2
7
3
4
6
5
VS-
VOUT+
VOUT-
Figure 98. Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in
Figure 98. The functionality of a fully differential
amplifier can be imagined as two inverting amplifiers
that share a common noninverting terminal (though
the voltage is not necessarily fixed). For more
information on the basic theory of operation for fully
differential amplifiers, refer to the Texas Instruments
application note Fully Differential Amplifiers, literature
number SLOA054.
APPLICATIONS SECTION
•
•
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
•
•
•
•
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With
the VOCM Input
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the
four devices. The THS4502 and THS4503 have an
input common-mode range that is centered around
midrail, and the THS4500 and THS4501 have an
input common-mode range that is shifted to include
the negative power-supply rail. Selection of one or
the other amplifier is determined by the nature of the
application. Specifically, the THS4500 and THS4501
are designed for use in single-supply applications
where the input signal is ground-referenced, as
depicted in Figure 99. The THS4502 and THS4503
are designed for use in single-supply or split-supply
applications where the input signal is centered
between the power-supply voltages, as depicted in
Figure 100.
•
•
Saving Power with Power-Down Functionality
Linearity:
Definitions,
Terminology,
Circuit
Techniques, and Design Tradeoffs
•
•
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for
Optimal Performance
•
•
Power Dissipation and Thermal Considerations
Power Supply Decoupling Techniques and
Recommendations
•
•
Evaluation
Applications Support
Additional Reference Material
Fixtures,
Spice
Models,
and
xxx
xxx
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VIN)(1–β)–VIN–(1–β) ) 2VOCMβ
2β
R
R
F1
R
S
G1
VOUT)
+
(1)
+V
S
R
T
–VIN)(1–β) ) VIN–(1–β) ) 2VOCMβ
2β
V
S
VOUT–
+
(2)
(3)
+
-
V
OCM
VN + VIN–(1–β) ) VOUT)
β
+
-
Where:
RG
β +
R
G2
R
F2
RF ) RG
(4)
VP + VIN)(1–β) ) VOUT–β
Figure 99. Application Circuit for the THS4500
and THS4501, Featuring Single-Supply Operation
With a Ground-Reference Input Signal
NOTE: The equations denote the device inputs as VN and VP, and
the circuit inputs as VIN+ and VIN–
.
(5)
R
G
R
F
R
G1
R
F1
R
S
V
IN+
+V
S
V
P
R
T
V
V
V
S
+
OUT-
-
V
+
OCM
-
+
-
OUT+
V
OCM
+
V
-
N
-V
S
V
IN-
R
G
R
F
R
G2
R
F2
Figure 101. Diagram For Input Common-Mode
Range Equations
Figure 100. Application Circuit for the THS4500
and THS4501, Featuring Split-Supply Operation
With an Input Signal Referenced at the Midrail
Table 1 and Table 2 depict the input common-mode
range requirements for two different input scenarios,
an input referenced around the negative rail and an
input referenced around midrail. The tables highlight
the differing requirements on input common-mode
range, and illustrate the reasoning to choose either
the THS4500/1 or the THS4502/3. For signals
referenced around the negative power supply, the
THS4500/1 should be chosen because its input
common-mode range includes the negative supply
rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power-supply rails.
Equation 1 through Equation 5 are used to calculate
the required input common-mode range for a given
set of input conditions.
The equations allow calculation of the input common-
mode range requirements, given information about
the input signal, the output voltage swing, the gain,
and the output common-mode voltage. Calculating
the maximum and minimum voltage required for VN
and VP (the amplifier input nodes) determines
whether or not the input common-mode range is
violated or not. Four equations are required: two
calculate the output voltages and two calculate the
node voltages at VN and VP (note that only one of
these nodes needs calculation, because the amplifier
forces a virtual short between the two nodes).
Table 1. Negative-Rail Referenced
Gain
(V/V)
VIN+
(V)
VIN–
(V)
VIN
(VPP
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
)
1
2
4
8
–2.0 to 2.0
–1.0 to 1.0
–0.5 to 0.5
–0.25 to 0.25
0
0
0
0
4
2
2.5
2.5
2.5
2.5
4
4
4
4
0.75
0.5
1.75
1.167
0.7
1
0.3
0.5
0.167
0.389
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Table 2. Midrail Referenced
Gain
(V/V)
VIN+
(V)
VIN–
(V)
VIN
(VPP
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
)
1
2
4
8
0.5 to 4.5
1.5 to 3.5
2.0 to 3.0
2.25 to 2.75
2.5
2.5
2.5
2.5
4
2
2.5
2.5
2.5
2.5
4
4
4
4
2
3
2.16
2.3
2.83
2.7
1
0.5
2.389
2.61
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values
presented in this section provide the optimum high-
frequency performance (lowest distortion, flat
frequency response). Since the THS4500 family of
amplifiers is developed with a voltage feedback
architecture, the choice of resistor values does not
have a dominant effect on bandwidth, unlike a
current-feedback amplifier. However, resistor choices
do have second-order effects. For optimal
performance, the following feedback resistor values
are recommended. In higher gain configurations (gain
greater than two), the feedback resistor values have
much less effect on the high-frequency performance.
Example feedback and gain resistor values are given
in the section on basic design considerations
(Table 3).
R2 and R4
VOD
Gain ǒ Ǔ
VIN
R1 (Ω)
R3 (Ω)
RT (Ω)
(Ω)
1
392
499
412
523
215
665
274
681
147
698
383
487
187
634
249
649
118
681
54.9
53.6
60.4
52.3
56.2
52.3
64.9
52.3
1
2
392
2
1.3 k
1.3 k
3.32 k
1.3 k
6.81 k
5
5
10
10
R1
R2
V
V
n
-
V
out+
Amplifier loading, noise, and the flatness of the
frequency response are three design parameters that
should be considered when selecting feedback
resistors. Larger resistor values contribute more noise
and can induce peaking in the ac response in low
gain configurations; smaller resistor values can load
the amplifier more heavily, resulting in a reduction in
distortion performance. In addition, feedback resistor
values, coupled with gain requirements, determine
the value of the gain resistors and directly impact the
input impedance of the entire circuit. While there are
no strict rules about resistor selection, these trends
can provide qualitative design guidance.
+
R3
R
S
-
+
V
out-
P
V
OCM
R
T
V
S
R4
Figure 102. Diagram for Design Calculations
Equations for calculating fully differential amplifier
resistor values in order to obtain balanced operation
in the presence of a 50-Ω source impedance are
given in Equation 6 through Equation 9.
R2
R1
1
K +
R2 + R4
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
RT +
K
1–
2(1)K)
1
RS
–
Fully differential amplifiers provide designers with a
ǒ
TǓ
R3
R3 + R1 * Rs || R
(6)
(7)
great deal of flexibility in
a wide variety of
R3 ) RT || RS
R3 ) RT || RS ) R4
R1
R1 ) R2
applications. This section provides an overview of
some common circuit configurations and gives some
design guidelines. Designing the interface to an
analog-to-digital converter (ADC), driving lines
differentially, and filtering with fully differential
amplifiers are a few of the circuits that are covered.
β1 +
β2 +
VOD
VS
1–β2
RT
+ 2ǒ Ǔǒ Ǔ
β1 ) β2
RT ) RS
(8)
(9)
VOD
VIN
1–β2
+ 2ǒ Ǔ
β1 ) β2
BASIC DESIGN CONSIDERATIONS
The circuits in Figure 99 through Figure 102 are used
to highlight basic design considerations for fully
differential amplifier circuit designs.
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For more detailed information about balance in fully
differential amplifiers, see the application report, Fully
Differential Amplifiers (SLOA054), referenced at the
end of this data sheet.
voltage regardless of the load impedance present.
Terminating the output of a fully differential
amplifier with a heavy load adversely affects the
amplifier linearity.
•
Comprehend the VOCM input drive requirements.
Determine if the ADC voltage reference can
provide the required amount of current to move
VOCM to the desired value. A buffer may be
needed.
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can
act as an antenna. A large decoupling capacitor
on this node eliminates this problem.
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
The THS4500 family of amplifiers are designed
specifically to interface to today's highest-
performance ADCs. This section highlights the key
concerns when interfacing to an ADC and provides
example interface circuits.
•
•
There are several key design concerns when
interfacing to an analog-to-digital converter:
Know the input common-mode range. If the input
signal is referenced around the negative power-
supply rail (for example, around ground on a
•
Terminate the input source properly. In high-
frequency receiver chains, the source that feeds
the fully differential amplifier requires a specific
load impedance (that is, 50 Ω).
single
5
V
supply), then the THS4500/1
accommodates the input signal. If the input signal
is referenced around midrail, choose the
THS4502/3 for the best operation.
•
Design a symmetric printed circuit board (PCB)
layout. Even-order distortion products are heavily
influenced by layout, and careful attention to a
symmetric layout minimizes these distortion
products.
•
Packaging makes
a
difference at higher
frequencies. If possible, choose the smaller,
thermally-enhanced MSOP package for the best
performance. As
temperatures provide better performance. If
possible, use thermally-enhanced package,
a
rule, lower junction
•
Minimize inductance in power-supply decoupling
traces and components. Poor power-supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power-supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the
current loop.
a
even if the power dissipation is relatively small
compared to the maximum power dissipation
rating to achieve the best results.
Understand the effect of the load impedance seen
by the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level
of intermodulation distortion performance.
•
•
•
Use separate analog and digital power supplies
and grounds. Noise (bounce) in the power
supplies (created by digital switching currents) can
couple directly into the signal path, and power-
supply noise can create higher distortion products
as well.
Use care when filtering. While an RC low-pass
filter may be desirable on the output of the
amplifier to filter broadband noise, the excess
loading can negatively impact the amplifier
linearity. Filtering in the feedback path does not
have this effect.
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at
the output of the data converter. Two representative
circuits shown below highlight single-supply operation
and split supply operation, respectively. Specific
feedback resistor, gain resistor, and feedback
capacitor values are not shown, as these values
depend on the frequency of interest. Information on
calculating these values can be found in the
applications material above.
•
•
AC-coupling allows easier circuit design. If dc-
coupling is required, be aware of the excess
power dissipation that can occur due to level-
shifting the output through the output common-
mode voltage control.
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop
fully differential amplifiers drive a specific output
24
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
C
C
F
G
R
R
F
R
G
S
15 V
R
S
R
G
R
C
S
R
F
T
R
R
ISO
V
S
+
5 V
-
V
OCM
V
R
T
S
R
L
V
DD
THS4500/2
5 V
+
-
10 mF 0.1 mF
0.1 mF
R
R
ISO
ISO
V
C
S
+
IN
-
ADS5410
12-Bit/80 MSPS
IN
V
OCM
+
R
F
= 26 V
PP
-
OD
CM
R
G
1 mF
THS4503
ISO
C
G
10 mF 0.1 mF
5
V
R
G
0.1 mF
R
F
Figure 105. Fully Differential Line Driver With
High Output Swing
C
F
Figure 103. Using the THS4503 With the ADS5410
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
C
F
Similar to single-ended counterparts, fully differential
amplifiers have the ability to couple filtering
functionality with voltage gain. Numerous filter
topologies can be based on fully differential
amplifiers. Several of these are outlined in the
application report A Differential Circuit Collection
(literature number SLOA064), referenced at the end
of this data sheet. The circuit below depicts a simple,
two-pole, low-pass filter applicable to many different
types of systems. The first pole is set by the resistors
and capacitors in the feedback paths, and the second
pole is set by the isolation resistors and the capacitor
across the outputs of the isolation resistors.
R
S
R
G
R
F
5 V
V
R
T
S
5 V
10 mF 0.1 mF
R
ISO
+
ADS5421
-
IN
14-Bit/40 MSPS
V
OCM
+
IN
-
CM
1 mF
THS4501
R
ISO
R
G
R
F
C
F
0.1 mF
C
F1
Figure 104. Using the THS4501 With the ADS5421
FULLY DIFFERENTIAL LINE DRIVERS
R
G1
R
F1
R
S
R
R
ISO
R
T
V
S
+
-
V
C
O
+
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers.
-
R
G2
ISO
The high power-supply voltage rating (16.5
V
R
F2
absolute maximum) allows operation on a single 12-V
or a single 15-V supply. The high supply voltage,
coupled with the ability to provide differential outputs,
enables the ability to drive 26 VPP into reasonably
heavy loads (250 Ω or greater). The circuit in
Figure 105 illustrates the THS4500 family of devices
used as high-speed line drivers. For line driver
applications, close attention must be paid to thermal
design constraints because of the typically high level
of power dissipation.
C
F2
Figure 106. A Two-Pole, Low-Pass Filter Design
Using a Fully Differential Amplifier With Poles
Located at: P1 = (2πRFCF)–1 in Hz and
P2 = (4πRISOC)–1 in Hz
Often, filters like these are used to eliminate
broadband noise and out-of-band distortion products
in signal acquisition systems. It should be noted that
the increased load placed on the output of the
amplifier by the second low-pass filter has
a
Copyright © 2013, Texas Instruments Incorporated
25
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
detrimental effect on the distortion performance. The
preferred method of filtering is to use the feedback
network, as the typically smaller capacitances
required at these points in the circuit do not load the
amplifier nearly as heavily in the passband.
frequency noise that could couple into the signal path
through the VOCM circuitry.
A 0.1-μF or 1-μF
capacitance is a reasonable value for eliminating a
great deal of broadband interference, but additional,
tuned decoupling capacitors should be considered if a
specific source of electromagnetic or radio frequency
interference is present elsewhere in the system.
Information on the ac performance (bandwidth, slew
rate) of the VOCM circuitry is included in the
ELECTRICAL CHARACTERISTICS and TYPICAL
CHARACTERISTICS sections.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a
critical function to the fully differential amplifier; it
accepts an input voltage and reproduces that input
voltage as the output common-mode voltage. In other
words, the VOCM input provides the ability to level-shift
the outputs to any voltage inside the output voltage
swing of the amplifier.
Since the VOCM pin provides the ability to set an
output common-mode voltage, the ability for
increased power dissipation exists. While this
possibility does not pose a performance problem for
the amplifier, it can cause additional power
dissipation of which the system designer should be
aware. The circuit shown in Figure 108 demonstrates
an example of this phenomenon. For a device
operating on a single 5-V supply with an input signal
referenced around ground and an output common-
mode voltage of 2.5 V, a dc potential exists between
the outputs and the inputs of the device. The amplifier
sources current into the feedback network in order to
provide the circuit with the proper operating point.
While there are no serious effects on the circuit
performance, the extra power dissipation may need to
be included in the system power budget.
A description of the input circuitry of the VOCM pin is
shown in Figure 107 to facilitate an easier
understanding of the VOCM interface requirements.
The VOCM pin has two 50-kΩ resistors between the
power supply rails to set the default output common-
mode voltage to midrail. A voltage applied to the
VOCM pin alters the output common-mode voltage as
long as the source has the ability to provide enough
current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the VOCM equivalent
circuit diagram. Current drive is especially important
when using the reference voltage of an analog-to-
digital converter to drive VOCM. Output current drive
capabilities differ from part to part, so a voltage buffer
may be necessary in some applications.
V
OCM
I
1
=
R
F1
+R + R || R
G1 S T
DC Current Path to Ground
V
S+
R
G1
R
F1
R
S
R = 50 kW
2.5-V DC
5 V
2 V
- V - V
S+ S-
R
T
OCM
V
S
I
IN
=
V
OCM
R
+
-
R
L
V
OCM
= 2.5 V
I
IN
+
R = 50 kW
-
V
S-
2.5-V DC
R
G2
R
F2
DC Current Path to Ground
Figure 107. Equivalent Input Circuit for VOCM
V
OCM
I
2
=
R
+ R
G2
F2
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal.
As shown in Figure 107, the VOCM input has a high
impedance associated with it, dictated by the two 50-
kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and
any associated PCB traces to act as an antenna. For
this reason, a decoupling capacitor is recommended
on this node for the sole purpose of filtering any high-
Figure 108. Depiction of DC Power Dissipation
Caused By Output Level-Shifting in a DC-Coupled
Circuit
26
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
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ZHCSB54 –JUNE 2013
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
etc.). Use of the intercept point, rather than strictly the
intermodulation distortion, allows for simpler system-
level calculations. Intercept points, like noise figures,
can be easily cascaded back and forth through a
signal chain to determine the overall receiver chain
The THS4500 family of fully differential amplifiers
contains devices that come with and without the
power-down option. Even-numbered devices have
power-down capability, which is described in detail
here.
intermodulation
distortion
performance.
The
relationship between intermodulation distortion and
intercept point is depicted in Figure 109 and
Figure 110.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (that is, an internal pull-up resistor is present),
putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
enable threshold voltage, the device is on. Below the
disable threshold voltage, the device is off. Behavior
between these threshold voltages is not specified.
P
O
P
O
∆f = f − f1
c
c
∆f = f2 − f
c
c
IMD = P − P
O
3
S
P
P
S
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors.
S
f − 3∆f f1
f
c
f2
f + 3∆f
c
c
f − Frequency − MHz
Figure 109. 2-Tone and 3rd-Order
Intermodulation Products
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
P
OUT
(dBm)
1X
OIP
3
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The
THS4500
family
of
devices
features
P
O
unprecedented distortion performance for monolithic
fully differential amplifiers. This section focuses on
the fundamentals of distortion, circuit techniques for
reducing nonlinearity, and methods for equating
distortion of fully differential amplifiers to desired
linearity specifications in RF receiver chains.
IMD
IIP
3
P
IN
3
(dBm)
3X
Amplifiers are generally thought of as linear devices.
In other words, the output of an amplifier is a linearly
scaled version of the input signal applied to it. In
reality, however, amplifier transfer functions are
P
S
nonlinear. Minimizing amplifier nonlinearity is
primary design goal in many applications.
a
Figure 110. Graphical Representation of 2-Tone
and 3rd-Order Intercept Point
Intercept points are specifications that have long
been used as key design criteria in the RF
communications world as
a
metric for the
intermodulation distortion performance of a device in
the signal chain (for example, amplifiers, mixers,
Copyright © 2013, Texas Instruments Incorporated
27
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
Due to the intercept point ease-of-use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related
design decisions. Traditionally, these systems use
primarily class-A, single-ended RF amplifiers as gain
blocks. These RF amplifiers are typically designed to
operate in a 50-Ω environment, just like the rest of
the receiver chain. Since intercept points are given in
dBm, this implies an associated impedance (50 Ω).
60
55
Normalized to 200 Ω
Normalized to 50 Ω
50
45
40
35
30
OIP R = 800 Ω
3
L
Gain = 1
R = 392 Ω
25
f
However, with a fully differential amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to the outputs regardless of the impedance present, it
is important to comprehend this feature when
evaluating the intercept point of a fully differential
amplifier. The THS4500 series of devices yields
optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of
an analog-to-digital converter over its input frequency
band. As a result, terminating the input of the ADC to
V
= ± 5 V
S
20
15
Tone Spacing = 200 kHz
0
10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
Figure 111. Equivalent 3rd-Order Intercept Point
for the THS4500
Comparing specifications between different device
types becomes easier when a common impedance
level is assumed. For this reason, the intercept points
on the THS4500 family of devices are reported
normalized to a 50-Ω load impedance.
50
Ω
can actually be detrimental to system
performance.
This discontinuity between open-loop, class-A
amplifiers and closed-loop, class-AB amplifiers
becomes apparent when comparing the intercept
points of the two types of devices. Equation 10 gives
the definition of an intercept point, relative to the
intermodulation distortion.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is
analogous to noise analysis in single-ended
amplifiers; the same concepts apply. Figure 112
shows a generic circuit diagram consisting of a
voltage source, a termination resistor, two gain
setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the
relevant noise sources. From this circuit, the noise
factor (F) and noise figure (NF) are calculated. The
figures indicate the appropriate scaling factor for each
of the noise sources in two different cases. The first
case includes the termination resistor, and the
second, simplified case assumes that the voltage
source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier
input noise power (NA) can be calculated by summing
each individual noise source with its scaling factor.
The noise delivered to the amplifier by the source (NI)
and input noise power are used to calculate the noise
factor and noise figure as shown in Equation 23
through Equation 27.
Ť
Ť
IMD3
2
ǒ Ǔwhere
OIP3 + PO )
(10)
V2Pdiff
P + 10 logǒ Ǔ
O
2RL 0.001
NOTE: P is the output power of a single tone, R is the
o
L
differentialload resistance, and V
is the differential
P(diff)
peak voltage for a single tone.
(11)
As can be seen in the equations, when a higher
impedance is used, the same level of intermodulation
distortion performance results in a lower intercept
point. Therefore, it is important to understand the
impedance seen by the output of the fully differential
amplifier when selecting a minimum intercept point.
Figure 111 shows the relationship between the strict
definition of an intercept point with a normalized, or
equivalent, intercept point for the THS4500.
28
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
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ZHCSB54 –JUNE 2013
e
g
e
f
R
g
R
n
f
N
i
N
A
Scaling Factors for Individual Noise Sources
Asseming No Termination Resistance is Used
(that is, RT is Open)
S
i
e
N : Fully Differential Amplifier; termination = 2R
A
g
N
i
N
S
o
Noise
Source
Scale Factor
R
s
+
2
o
R
fully-diff
amp
−
t
i
ni
Rg Rg
N
ȡ
ȣ
Ȥ
o
)
2
(e )
ni
e
s
R
ȧ
R ȧ
f
s
Rg )
Ȣ
2
e
t
(18)
(19)
(20)
2
(i )
ni
2
i
ii
R
g
2
e
g
e
f
2
(i )
ii
R
g
R
g
R
f
2
Rg
ǒ Ǔ
2
4kTR
f
Rf
(21)
(22)
2
ȣ
ȧ
Figure 112. Noise Sources in a Fully Differential
Amplifier Circuit
Rg
ȡ
2
4kTR
R
ȧ
g
s
ȢR )
Ȥ
g
2
Scaling Factors for Individual Noise Sources
Assuming a Finite Value Termination Resistor
Input Noise With a Termination Resistor
N : Fully Differential Amplifier
A
2
Noise
Source
ȡ
ȣ
Scale Factor
2RtRg
2
ȧ
ȧ
ȧ
ȧ
Ȥ
Rt)2Rg
Ni + 4kTRs
ȡ
ȣ
ȧ
Rg
RsRt
2RtRg
Rg
R )
ȧ s
)
ȧ
R
ȧ
Rt)2Rg
2
(e )
ni
f
Rg )
ǒ
Ǔ
2 Rs)Rt
Ȣ
(23)
(12)
(13)
(14)
2
R
2
(i )
ni
g
Input Noise Assuming No Termination Resistor
2
2
R
2
(i )
ii
g
2RG
Ni = 4kTRS
RS + 2RG
2
2RsRG
ȡ
(24)
ȣ
Rs)2Rg
Noise Factor and Noise Figure Calculations
NA = S(Noise Source ´ Scale Factor)
4kTR
t
ȧ
ȧ
2RsRg
Rt )
(25)
Ȣ
R )2R Ȥ
s
g
(15)
(16)
NA
F = 1 +
NI
2
Rg
ǒ Ǔ
2
4kTR
(26)
(27)
f
Rf
NF + 10 log (F)
2
ȡ
Rg
ȣ
ȧ
RsRt
4kTR
2
g
ȧR )
g
ǒ
Ǔ
2 Rs)Rt
(17)
Copyright © 2013, Texas Instruments Incorporated
29
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
PRINTED CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
pole and/or a zero below 400 MHz that can affect
circuit operation. Keep resistor values as low as
possible,
consistent
with
load
driving
considerations.
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to PCB layout parasitic and external
component types.
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils, or 1.27
mm to 2.54 mm) should be used, preferably with
ground and power planes opened up around
them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (less
than 4 pF) may not need an RS since the
THS4500 family is nominally compensated to
operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded
phase margin). If a long trace is required, and the
6-dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout
techniques).
Recommendations that optimize performance include:
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance,
a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
•
Minimize the distance (< 0.25”, 6.35 mm) from the
power-supply pins to high frequency 0.1-μF
decoupling capacitors. At the device pins, the
ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 μF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PCB. The primary goal is to
minimize the impedance seen in the differential-
current return paths.
•
A 50-Ω environment is normally not necessary
onboard, and in fact,
a higher impedance
environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined based onboard
material and trace dimensions, a matching series
resistor into the trace from the output of the
THS4500 family is used as well as a terminating
shunt resistor at the input of the destination
device.
•
Careful selection and placement of external
components
preserve
the
high-frequency
performance of the THS4500 family. Resistors
should be a very low reactance type. Surface-
mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep the
leads and PCB trace length as short as possible.
Never use wirewound type resistors in a high-
frequency application. Since the output pin and
inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed close
to the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or surface-
mount resistors have approximately 0.2 pF in
shunt with the resistor. For resistor values greater
than 2.0 kΩ, this parasitic capacitance can add a
•
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device: this
total effective impedance should be set to match
the trace impedance. If the 6-dB attenuation of a
doubly-terminated
unacceptable,
terminated at the source end only. Treat the trace
as capacitive load in this case. This
transmission
long trace can be series-
line
is
a
a
configuration does not preserve signal integrity as
well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation due to the voltage
divider formed by the series output into the
terminating impedance.
Socketing a high-speed part such as the THS4500
family is not recommended. The additional lead
length and pin-to-pin capacitance introduced by
the socket can create an extremely troublesome
parasitic network that can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
•
30
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
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ZHCSB54 –JUNE 2013
the THS4500 family parts directly onto the board.
0.205
0.060
PowerPAD DESIGN CONSIDERATIONS
0.017
The THS4500 family is available in a thermally-
enhanced PowerPAD set of packages. These
packages are constructed using a downset leadframe
upon which the die is mounted [see Figure 113(a)
and Figure 113(b)]. This arrangement results in the
lead frame being exposed as a thermal pad on the
underside of the package [see Figure 113(c)].
Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be
achieved by providing a good thermal path away from
the thermal pad.
Pin 1
0.013
0.030
0.075
0.025 0.094
0.035
0.040
0.010
vias
Top View
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
Figure 114. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 114. There should be etch for
the leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils (0.33 mm) in
diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These holes help dissipate the heat
generated by the THS4500 family IC. These
additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad.
They can be larger because they are not in the
thermal pad area to be soldered so that wicking
is not a problem.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
4. Connect all holes to the internal ground plane.
Figure 113. Views of PowerPAD, Thermally-
Enhanced Package
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This transfer slowing makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
complete
connection
around
the
entire
circumference of the plated-through hole.
Copyright © 2013, Texas Instruments Incorporated
31
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
Maximum power dissipation levels are depicted in
Figure 115 for the two packages. The data for the
DGN package assumes a board layout that follows
the PowerPAD layout guidelines referenced above
and detailed in the PowerPAD application notes in
the Additional Reference Material section at the end
of the data sheet.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
3.5
8-Pin DGN Package
3
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard surface-
mount component. This process results in a part
that is properly installed.
2.5
2
8-Pin D Package
1.5
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
1
0.5
0
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
−40
−20
0
20
40
60
80
T
− Ambient Temperature − °C
A
θ
θ
Τ
= 170°C/W for 8-Pin SOIC (D)
= 58.4°C/W for 8-Pin MSOP (DGN)
= 150°C, No Airflow
JA
JA
J
exceeded. For best performance, design for
a
maximum junction temperature of +125°C. Between
+125°C and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade.
Figure 115. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this consideration is difficult to quantify
because the signal pattern is inconsistent; an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power
dissipation for a given package can be calculated
using the following formula.
TMAX - TA
PDmax
=
q
JA
Where:
PDmax is the maximum power dissipation in the
amplifier (W).
TMAX is the absolute maximum junction
temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however,
the load capacitance should be isolated by two
isolation resistors in series with the output. The
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
to begin the optimization process. Larger isolation
resistors decrease the amount of peaking in the
frequency response induced by the capacitive load,
but this decreased peaking comes at the expense ofa
larger voltage drop across the resistors, increasing
the output swing requirements of the system.
ambient air (°C/W).
(28)
For systems where heat dissipation is more critical,
the THS4500 family of devices is offered in an
MSOP-8 package with PowerPAD. The thermal
coefficient for the MSOP PowerPAD package is
substantially improved over the traditional SOIC.
32
Copyright © 2013, Texas Instruments Incorporated
THS4500-EP
www.ti.com.cn
ZHCSB54 –JUNE 2013
obtained by ordering through the THS4500 or
THS4501 product folder on the Texas Instruments
web site, www.ti.com, or through your local Texas
Instruments sales representative. A schematic for the
evaluation board is shown in Figure 117 with the
default component values. Unpopulated footprints are
shown to provide insight into design flexibility.
R
F
V
S
R
G
R
S
R
R
ISO
+
-
V
S
C
L
R
T
+
-
ISO
-V
S
Riso = 10 - 25 W
C4
C0805
R
F
R4
R
G
R0805
PD
V
S
U1
J2
J3
J1
C5
C0805
THS450X
4
J2
J3
3
C1
C0805
R6
R2
7
1
8
_
R0805
Figure 116. Use of Isolation Resistors With a
Capacitive Load
R0805
R0805
C7
C0805
R0805
R1
C2
R1206
C0805
+
5
R3
6
R7
2
PwrPad
C6
C0805
-V
S
V
OCM
R5 R0805
C3
POWER-SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
C0805
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance.
J2
J4
R8
4
5
3
1
R0805
R9
R0805
R11
R1206
J3
R0805
6
R9
T1
Figure 117. Simplified Schematic of the
Evaluation Board
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
practice is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the THS4500 family of devices is
available through either the Texas Instruments web
site (www.ti.com) or as one model on a disk from the
Texas Instruments Product Information Center (1-
800-548-6132). The PIC is also available for design
assistance and detailed product information at this
number. These models do a good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths.
4. Recommended
values
for
power-supply
decoupling include 10-μF and 0.1-μF capacitors
for each supply. A 1000-pF capacitor can be
used across the supplies as well for extremely
high frequency return currents, but often is not
required.
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, an evaluation board
has been developed for the THS4500 family of fully
differential amplifiers. The evaluation board can be
Copyright © 2013, Texas Instruments Incorporated
33
THS4500-EP
ZHCSB54 –JUNE 2013
www.ti.com.cn
ADDITIONAL REFERENCE MATERIAL
•
•
•
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
PowerPAD Thermally-Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number
SLOA054D.
•
•
•
•
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and
Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature
Number SLOA064.
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments
Literature Number SLOA072.
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog
Applications Journal, July 2001.
34
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS4500MDGNEP
THS4500MDGNREP
V62/13610-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
HVSSOP
HVSSOP
DGN
DGN
DGN
DGN
8
8
8
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
SJE
SJE
SJE
SJE
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
V62/13610-01XE-T
80
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.57
1.28
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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