THS4511HKT/EM [TI]
RAD-TOLERANT CLASS V, WIDEBAND, FULLY DIFFERENTIAL AMPLIFIER;
| 型号： | THS4511HKT/EM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | RAD-TOLERANT CLASS V, WIDEBAND, FULLY DIFFERENTIAL AMPLIFIER 放大器 |
| 文件： | 总25页 (文件大小：914K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4511–SP
www.ti.com
SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
RAD-TOLERANT CLASS V, WIDEBAND, FULLY DIFFERENTIAL AMPLIFIER
1
FEATURES
DESCRIPTION/ORDERING INFORMATION
•
Fully Differential Architecture
•
Common-Mode Input Range Includes Negative
Rail
The THS4511 is
amplifier designed
a
fully differential operational
for single-supply
5
V
data-acquisition systems. It has very low noise at
2 nV/√Hz, and extremely low harmonic distortion of
–76 dBc HD2 and –88 dBc HD3 at 70 MHz with
2 Vpp, G = 14 dB, and 100 Ω load. Slew rate is very
high at 5100 V/μs and with settling time of 5.5 ns to
1% (2 V step) it is ideal for pulsed applications. It is
designed for minimum gain of 6 dB.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Minimum Gain of 2 V/V (6 dB)
Bandwidth: 1.1 GHz (Gain = 6 dB)
Slew Rate: 5100 V/μs
1% Settling Time: 5.5 ns
HD2: –76 dBc at 70 MHz
HD3: –88 dBc at 70 MHz
To allow for dc coupling to ADCs, its unique output
common-mode control circuit maintains the output
common-mode voltage within 5 mV offset (typical)
from the set voltage, when set within ±0.5 V of
mid-supply. The common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source.
OIP2: 84 dBm at 70 MHz
OIP3: 42 dBm at 70 MHz
Input Voltage Noise: 2 nV/√Hz (f > 10 MHz)
Noise Figure: 21.8 dB (50 Ω System, G = 6 dB)
Output Common-Mode Control
5 V Power Supply Current: 39.2 mA
Power-Down Capability: 0.65 mA
Rad-Tolerant: 150 kRad (Si) TID
QML-V Qualified, SMD 5962-07222
The THS4511 is a high-performance amplifier that
has been optimized for use in 5 V single-supply data
acquisition systems. The output has been optimized
for best performance with its common-mode voltages
set to mid-supply, and the input has been optimized
for performance over a wide range of common-mode
APPLICATIONS
input voltages. High performance at
a
low
power-supply voltage enables single-supply 5 V
data-acquisition systems while minimizing component
count.
•
•
•
•
•
5 V Data-Acquisition Systems
High Linearity ADC Amplifier
Wireless Communication
Medical Imaging
The THS4511 is offered in a 16-pin ceramic flatpack
package (W), and is characterized for operation over
the full military temperature range from –55°C to
125°C.
Test and Measurement
RELATED PRODUCTS
Video Buffer, Single Ended to Differential
MINIMUM
GAIN
COMMON-MODE
RANGE OF INPUT(1)
DEVICE
Video Source
THS4511-SP 6 dB
THS4513-SP 6 dB
–0.3 V to 2.3 V
0.75 V to 4.25 V
R
= 75 W
V
175 W
348 W
S
IN
V
= 5 V
S+
130 W
V
Signal
(1) Assumes a 5 V single-ended power supply
R
R
O
O
-
VOD
THS4511
175 W
+
V
= 2.5 V
CM
V
75 W
130 W
S-
348 W
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
THS4511–SP
www.ti.com
SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION(1)
PACKAGED DEVICES
TEMPERATURE
CERAMIC FLATPACK
W (16)(2)
SYMBOL
–55°C to 125°C
5962-0722201VFA
5962-0722201VFA
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VS– to VS+
Supply voltage
6 V
VI
Input voltage
±VS
4 V
VID
IO
Differential input voltage
Output current
200 mA
Continuous power dissipation
Maximum junction temperature(2)
Operating free-air temperature range
Storage temperature range
HBM
See Dissipation Rating Table
150°C
TJ
TA
–55°C to 125°C
–65°C to 150°C
2000 V
Tstg
ESD ratings
CDM
MM
1500 V
100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
DISSIPATION RATINGS TABLE
POWER RATING
PACKAGE
θJC
θJA
TA ≤ 25°C
TA = 125°C
W (16)
14.7°C/W
189°C/W
661 mW
132 mW
2
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SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
DEVICE INFORMATION
W PACKAGE
TOP VIEW
VS–
VS–
VS–
VS–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
PD
VIN–
VIN+
VOUT+
VOUT–
CM
VS+
CM
VS+
VS+
VS+
TERMINAL FUNCTIONS
TERMINAL
(W PACKAGE)
DESCRIPTION
NO. NAME
3
4
5
NC
No internal connection
VIN–
VOUT+
CM
Inverting amplifier input
Non-inverting amplifier output
Common-mode voltage input
Positive amplifier power supply input
Inverting amplifier output
6, 11
7, 8, 9, 10
VS+
12
13
14
VOUT–
VIN+
PD
Non-inverting amplifier input
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation
Negative amplifier power supply input
1, 2, 15, 16 VS–
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SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS; VS+ – VS– = 5 V (Unchanged after 150 kRad):
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 14 dB, CM = open, VOD = 2 Vpp, RF = 348 Ω, RL = 200 Ω
Differential, TA = 25°C, Single-Ended Input, Differential Output, Input Referenced to Ground, and Output Referenced to
Mid-Supply
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
G = 6 dB, VO = 100 mVpp
1.1
1.0
720
3
GHz
Small-Signal Bandwidth
G = 10 dB, VO = 100 mVpp
G = 14 dB, VO = 100 mVpp
G = 10 dB
MHz
GHz
Gain-Bandwidth Product
G = 10 dB, VO = 2 Vpp
G = 14 dB, VO = 2 Vpp
G = 6 dB, VO = 2 Vpp
65
Bandwidth for 0.1 dB flatness
MHz
115
1.1
5100
0.5
0.5
5.5
–106
–90
–87
–108
–106
–83
–83
–75
–83
–74
84
Large-Signal Bandwidth
Slew Rate (Differential)
Rise Time
GHz
V/μs
ns
VO = 2 V Step
Fall Time
ns
Settling Time to 1%
ns
f = 10 MHz, RL = 100 Ω
f = 50 MHz, RL = 100 Ω
f = 100 MHz, RL = 100 Ω
f = 10 MHz, RL = 100 Ω
f = 50 MHz, RL = 100 Ω
f = 100 MHz, RL = 100 Ω
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
dBc
fC = 50 MHz
fC = 100 MHz
fC = 50 MHz
fC = 100 MHz
fC = 50 MHz
fC = 100 MHz
fC = 50 MHz
fC = 100 MHz
2nd Order Intermodulation Distortion
3rd Order Intermodulation Distortion
2nd Order Output Intercept Point
3rd Order Output Intercept Point
200 kHz tone spacing,
RL = 100 Ω
dBc
77
200 kHz tone spacing,
RL = 100 Ω
dBm
42
38
Noise Figure
50 Ω system, 10 MHz
f > 10 MHz
21.8
2
dB
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
nV/√Hz
pA/√Hz
f > 10 MHz
1.5
Open-Loop Voltage Gain (AOL
)
63
1
dB
mV
TA = 25°C
4
Input Offset Voltage
TA = –55°C to 125°C
5.5
Average Offset Voltage Drift
Input Bias Current
2.3
8
µV/°C
μA
TA = 25°C
15.5
20
TA = –55°C to 125°C
Average Bias Current Drift
Input Offset Current
20
nA/°C
μA
TA = 25°C
0.5
3.6
7
TA = –55°C to 125°C
Average Offset Current Drift
7
nA/°C
4
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SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS; VS+ – VS– = 5 V (Unchanged after 150 kRad): (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 14 dB, CM = open, VOD = 2 Vpp, RF = 348 Ω, RL = 200 Ω
Differential, TA = 25°C, Single-Ended Input, Differential Output, Input Referenced to Ground, and Output Referenced to
Mid-Supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
Common-Mode Input Range High
Common-Mode Input Range Low
Common-Mode Rejection Ratio
Differential Input Impedance
Common-Mode Input Impedance
OUTPUT
2.3
–0.3
V
dB
80
18.2 || 0.5
4.0 || 1.5
MΩ || pF
TA = 25°C
3.7
3.5
3.8
1.2
5.2
Maximum Output Voltage High
Minimum Output Voltage Low
Differential Output Voltage Swing
TA = –55°C to 125°C
TA = 25°C
V
Each output with 100 Ω to
mid-supply
1.3
1.5
TA = –55°C to 125°C
TA = 25°C
4.8
4.0
V
TA = –55°C to 125°C
RL = 10 Ω
Differential Output Current Drive
Output Balance Error
96
–52
0.3
mA
dB
Ω
VO = 100 mV, f = 1 MHz
f = 1 MHz
Closed-Loop Output Impedance
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth
Slew Rate
250
MHz
V/μs
V/V
mV
110
Gain
1
5
Output Common-Mode Offset from CM input
CM Input Bias Current
1.5 V < CM < 3.5 V
1.5 V < CM < 3.5 V
±40
μA
CM Input Voltage Range
CM Input Impedance
1.25 to 3.75
32 || 2.8
2.5
V
kΩ || pF
V
CM Default Voltage
CM pins floating
POWER SUPPLY
Specified Operating Voltage
Maximum Quiescent Current
3.75(1)
5
5.25
42.5
44
V
TA = 25°C
39.2
TA = –55°C to 125°C
TA = 25°C
mA
dB
Minimum Quiescent Current
35.9
34
39.2
90
TA = –55°C to 125°C
To differential output
Referenced to Vs–
Device assured on above 2.1 V
Device assured off below 0.7 V
TA = 25°C
Power Supply Rejection (±PSRR)
POWER DOWN
Enable Voltage Threshold
Disable Voltage Threshold
> 2.1
< 0.7
0.65
V
0.9
1.2
Powerdown Quiescent Current
mA
TA = –55°C to 125°C
PD = VS–
Input Bias Current
Input Impedance
100
50 || 2
55
μA
kΩ || pF
ns
Turn-On Time Delay
Turn-Off Time Delay
Measured to output on
Measured to output off
10
μs
(1) See the Application Information section of this data sheet for device operation with full supply voltages less than 5 V.
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SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 14 dB, CM = open, VOD = 2 Vpp, RF = 348 Ω, RL = 200 Ω
Differential, Single-Ended Input, Input Referenced to Ground and Output Referenced to Mid-Rail
G = 6 dB, VOD = 100 mVPP
G = 10 dB, VOD = 100 mVPP
G = 14 dB, VOD = 100 mVPP
G = 6 dB, VOD = 2 VPP
G = 10 dB, VOD = 2 VPP
G = 14 dB, VOD = 2 VPP
HD2, G = 14 dB, VOD = 2 VPP
HD3, G = 14 dB, VOD = 2 VPP
HD2, G = 14 dB
Figure 1
Figure 2
Small-Signal Frequency
Response
Figure 3
Figure 4
Large Signal Frequency
Response
Figure 5
Figure 6
vs Frequency
Figure 7
vs Frequency
Figure 8
Harmonic
Distortion
vs Output Voltage
vs Output Voltage
vs Frequency
Figure 9
HD3, G = 14 dB
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
IMD2, G = 14 dB
Intermodulation
Distortion
IMD3, G = 14 dB
vs Frequency
OIP2
vs Frequency
Output Intercept Point
OIP3
vs Frequency
Transition Rate
vs Output Voltage
Transient Response
Rejection Ratios
vs Frequency
Overdrive Recovery
Output Voltage Swing
Turn-Off Time
vs Load Resistance
Turn-On Time
Input Offset Voltage
Input Referred Noise
Noise Figure
vs Input Common-Mode Voltage
vs Frequency
vs Frequency
Quiescent Current
Output Balance Error
CM Input Bias Current
Differential Output Offset Voltage
Output Common-Mode Offset
vs Supply Voltage
vs Frequency
vs CM Input Voltage
vs CM Input Voltage
vs CM Input Voltage
6
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SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
SMALL-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
10
9
8
7
6
5
4
3
2
1
0
12
11
10
9
G = 6 dB
= 100 mVpp
G = 10 dB
R
= 1 kΩ
V
V
OD
= 100 mVpp
L
OD
R
L
= 1 kΩ
R
= 500 Ω
R = 500 Ω
L
L
R
= 200 Ω
= 100 Ω
8
L
7
R
L
= 100 Ω
6
R
L
5
R
L
= 200 Ω
4
10
10
10
100
1k
10k
10k
10k
10
10
10
100
1k
10k
10k
10k
f − Frequency − MHz
f − Frequency − MHz
Figure 1.
Figure 2.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
12
10
8
15
14
13
12
11
10
9
G = 6 dB
V
OD
= 2 Vpp
R
= 1 kΩ
L
R
= 1 kΩ
L
R
= 500 Ω
L
6
R
L
= 500 Ω
R
L
= 200 Ω
= 100 Ω
R
= 100 Ω
L
4
R
L
2
R
L
= 200 Ω
G = 14 dB
= 100 mVpp
V
OD
8
0
100
1k
100
1k
f − Frequency − MHz
f − Frequency − MHz
Figure 3.
Figure 4.
LARGE-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
12
11
10
9
15
14
13
12
11
10
9
G = 10 dB
V
OD
= 2 Vpp
R
= 1 kΩ
L
R
L
= 1 kΩ
R
L
= 500 Ω
R = 500 Ω
L
8
R
L
= 100 Ω
R
= 100 Ω
L
7
6
R
= 200 Ω
L
5
R
L
= 200 Ω
G = 14 dB
= 2 Vpp
V
OD
4
8
100
1k
100
1k
f − Frequency − MHz
f − Frequency − MHz
Figure 5.
Figure 6.
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SLOS538A–SEPTEMBER 2007–REVISED OCTOBER 2007
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−40
−40
−50
G = 14 dB
G = 14 dB
V = 2 Vpp
OD
V
OD
= 2 Vpp
−50
−60
R
L
= 200 Ω
R
L
= 1 kΩ
−60
R
L
= 200 Ω
R
L
= 1 kΩ
−70
−70
−80
−80
−90
−90
R
L
= 499 Ω
R
L
= 499 Ω
R = 100 Ω
L
−100
−110
−120
−100
−110
−120
R
L
= 100 Ω
1
10
100
1
10
100
f − Frequency − MHz
f − Frequency − MHz
Figure 7.
Figure 8.
HD2 vs OUTPUT VOLTAGE
HD3 vs OUTPUT VOLTAGE
−60
−70
−40
−50
G = 14 dB
G = 14 dB
f = 100 MHz
−60
f = 100 MHz
f = 50 MHz
−80
−70
f = 50 MHz
−90
−80
−90
−100
−110
−120
f = 10 MHz
−100
−110
−120
f = 10 MHz
3.5 4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
0
0.5
1.0
1.5
2.0
2.5
3.0
V
O
− Output Voltage − Vpp
V
O
− Output Voltage − Vpp
Figure 9.
Figure 10.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−40
−50
−60
−70
−80
−90
−100
−40
−50
−60
−70
−80
−90
−100
V
= 2 Vpp Envelope
V
= 2 Vpp Envelope
OD
OD
200 kHz Tone Spacing
200 kHz Tone Spacing
R
L
= 100 Ω
R
= 100 Ω
L
R
L
= 1 kΩ
R
L
= 1 kΩ
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
Figure 11.
Figure 12.
8
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OIP2 vs FREQUENCY
OIP3 vs FREQUENCY
100
90
80
70
60
50
45
40
35
30
25
20
V
= 2 Vpp Envelope
V
OD
= 2 Vpp Envelope
OD
50
40
200 kHz Tone Spacing
= 100 Ω
200 kHz Tone Spacing
R = 100 Ω
L
R
L
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
Figure 13.
Figure 14.
TRANSITION RATE vs OUTPUT VOLTAGE
TRANSIENT RESPONSE
1.5
1.0
6000
5000
4000
3000
2000
1000
0
R
L
= 200 Ω
Falling
0.5
Rising
G = 6 dB
0.0
R
L
= 200 Ω
V
OD
= 2 V
PP
−0.5
−1.0
−1.5
0
10 20 30 40 50 60 70 80 90 100
t − Time − ns
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
OD
− Differential Output Voltage − Vpp
Figure 15.
Figure 16.
REJECTION RATIOS vs FREQUENCY
OVERDRIVE RECOVERY
100
90
80
70
60
50
40
30
20
4
2
PSRR+
Input
1.5
2
0
1
Output
0.5
CMRR
0
−0.5
−1
−2
−4
−1.5
10
0
−2
0.1
0.01
10
100
1000
1
t − Time − 100 ns/div
f − Frequency − MHz
Figure 17.
Figure 18.
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OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
TURN-OFF TIME
3.2
6.4
6
7
3
2.8
2.6
5.6
5.2
4.8
4.4
4
6
5
4
3
2
1
0
Output
2.4
2.2
2
1.8
3.6
3.2
2.8
2.4
2
PD Input
1.6
1.4
1.2
1
1.6
0.8
0.6
0.4
0.2
0
1.2
0.8
0.4
0
0
500
1000
1500
2000
t - Time - (2.5 ms/div)
R
L
− Load Resistance − Ω
Figure 19.
Figure 20.
INPUT OFFSET VOLTAGE
vs
INPUT COMMON-MODE VOLTAGE
TURN-ON TIME
10
9
3
6.4
6
PD Input
2.8
2.6
5.6
5.2
2.4
8
7
4.8
4.4
2.2
2
Output
1.8
1.6
4
3.6
3.2
6
5
4
3
1.4
1.2
1
2.8
2.4
0.8
0.6
0.4
0.2
2
1.6
1.2
0.8
0.4
0
2
1
0
0
-0.2
-0.5
0
0.5
1
1.5
2
2.5
3
t - Time - (2.5 ms/div)
V
- Commom-Mode Input Voltage - V
IC
Figure 21.
Figure 22.
INPUT REFERRED NOISE vs FREQUENCY
NOISE FIGURE vs FREQUENCY
1000
100
10
25
50-W System
G = 6 dB
24
23
22
21
20
Input Current Noise
Input Voltage Noise
1
0
10
100
1k
10k
100k
1M
10M
0
20
40
60
80
100 120 140 160 180 200
f - Frequency - Hz
f - Frequency - MHz
Figure 23.
Figure 24.
10
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QUIESCENT CURRENT
vs SUPPLY VOLTAGE
OUTPUT BALANCE ERROR
vs FREQUENCY
44
42
-20
-25
-30
-35
= 25oC
VOD = 500 mVPP
T
A
T
= 85oC
A
40
38
36
-40
-45
T
= -40oC
A
34
32
30
-50
-55
-60
28
3.75
4
4.25
4.5
4.75
5
5.25
100k
1M
10M
100M
10G
f - Frequency - Hz
V
- Supply Voltage - V
S
Figure 25.
Figure 26.
CM INPUT BIAS CURRENT
vs CM INPUT VOLTAGE
DIFFERENTIAL OUTPUT OFFSET VOLTAGE
vs CM INPUT VOLTAGE
5
4
3
2
200
100
0
-100
-200
1
0
-1
-300
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
- Common-Mode Input Voltage - V
IC
V
- Common-Mode Input Voltage - V
IC
Figure 27.
Figure 28.
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OUTPUT COMMON-MODE OFFSET
vs CM INPUT VOLTAGE
50
40
30
20
10
0
-10
-20
-30
-40
-50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
- Common-Mode Input Voltage - V
IC
Figure 29.
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TEST CIRCUITS
The output is probed using a high-impedance
differential probe across the 100 Ω resistor. The gain
is referred to the amplifier output by adding back the
6 dB loss due to the voltage divider on the output.
The THS4511 is tested with the following test circuits.
For simplicity, the power supply decoupling is not
shown – see the layout in the application information
section for recommendations. Depending on the test
conditions, component values are changed per the
following tables, or as otherwise noted. The signal
generators used are ac coupled 50 Ω sources, and a
0.22 μF capacitor and a 49.9 Ω resistor to ground are
inserted across RIT on the alternate input to balance
the circuit.
V
IN
R
F
R
G
From
50 W
Source
5 V
R
R
IT
49.9 W
49.9 W
Output Measured
Here With High-
Impedance
100 W
THS4511
CM
R
G
Differential Probe
0.22 mF
49.9 W
Open
0.22 mF
IT
Table 1. Gain Component Values
R
F
GAIN
6 dB
RF
RG
RIT
Figure 30. Frequency Response Test Circuit
348 Ω
348 Ω
348 Ω
348 Ω
165 Ω
100 Ω
56.2 Ω
16.5 Ω
61.9 Ω
69.8 Ω
88.7 Ω
287 Ω
10 dB
14 dB
20 dB
Distortion
The circuit shown in Figure 31 is used to measure
harmonic distortion and intermodulation distortion of
the amplifier.
Note: The gain setting includes 50 Ω source
impedance. Components are chosen to achieve
gain and 50 Ω input termination.
A signal generator is used as the signal source, and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω and
to maintain the proper gain. To balance the amplifier,
a 0.22 μF capacitor and 49.9 Ω resistor to ground are
inserted across RIT on the alternate input.
Table 2. Load Component Values
RL
RO
ROT
Atten
6 dB
100 Ω
200 Ω
499 Ω
1k Ω
25 Ω
open
86.6 Ω
237 Ω
487 Ω
69.8 Ω
56.2 Ω
52.3 Ω
16.8 dB
25.5 dB
31.8 dB
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
Note: The total load includes 50 Ω termination by
the test equipment. Components are chosen to
achieve load and 50 Ω line termination through a
1:1 transformer.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1 MHz.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column Atten in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output as shown in
Figure 31, the signal will see slightly more loss, and
these numbers will be approximate.
V
IN
R
R
F
G
From
50 W
Source
5 V
R
R
IT
V
OUT
R
R
O
Frequency Response
1:1
To 50 W
Test
Equipment
R
OT
THS4511
CM
R
IT
The circuit shown in Figure 30 is used to measure the
frequency response of the circuit.
G
O
0.22 mF
49.9 W
Open
A network analyzer is used as the signal source and
as the measurement device. The output impedance
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22 μF
capacitor and 49.9 Ω resistor to ground are inserted
across RIT on the alternate input.
0.22 mF
R
F
Figure 31. Distortion Test Circuit
Slew Rate, Transient Response, Settling Time,
Output Impedance, Overdrive, Output Voltage,
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and Turn-On/Off Time
RG
RIT
RF
The circuit shown in Figure 32 is used to measure
slew rate, transient response, settling time, output
impedance, overdrive recovery, output voltage swing,
and turn-on/turn-off times of the amplifier. For output
impedance, the signal is injected at VOUT with VIN left
open, and the drop across the 49.9 Ω resistor is used
to calculate the impedance seen looking into the
amplifier’s output.
0.22 mF
49.9 W
5 V
49.9 W
To
VOUT–
50 W
Test
Equipment
THS4511
CM
RG
RIT
49.9 W
VOUT+
0.22 mF
49.9 W
RCM
VIN From
50 W
source
RCMT
RF
V
IN
From
50 W
Source
R
R
F
G
Figure 33. CM Input Test Circuit
5 V
R
R
IT
49.9 W
49.9 W
CMRR and PSRR
V
V
OUT+
To 50 W
Test
Equipment
THS4511
CM
R
G
The circuit shown in Figure 34 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being
performed.
OUT-
0.22 mF
49.9 W
Open
0.22 mF
IT
R
F
348 W
V
S+
Figure 32. SR, Transient Response, Settling Time,
ZO, Overdrive Recovery, VOUT Swing, and
Turn-on/off Test Circuit
5 V
PSRR+
V
IN
49.9 W
49.9 W
Output
Measured
Here
With High-
Impedance
Differential
Probe
From
50 W
Source
100 W
100 W
CMRR
PSRR-
THS4511
CM
100 W
CM Input
Open
0.22 mF
V
S-
69.8 W
The circuit shown in Figure 33 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single-ended
348 W
Figure 34. CMRR and PSRR Test Circuit
at VOUT+ or VOUT– with the input injected at VIN, RCM
=
0 Ω and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
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APPLICATION INFORMATION
R
R
F
G
Single-Ended
Input
APPLICATIONS
Differential
Output
5 V
The following circuits show application information for
the THS4511. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. For
more detail on the use and operation of fully
differential operational amplifiers, refer to application
report Fully-Differential Amplifiers (SLOA054) .
V
+
–
OUT–
THS4511
R
G
+
–
V
OUT+
Differential Input to Differential Output Amplifier
The THS4511 is
a fully differential operational
R
F
amplifier, and can be used to amplify differential input
signals to differential output signals. A basic block
diagram of the circuit is shown in Figure 35 (CM input
not shown). The gain of the circuit is set by RF
divided by RG.
Figure 36. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
R
F
The input common-mode voltage of a fully differential
operational amplifier is the voltage at the (+) and (–)
input pins of the operational amplifier.
Differential
Output
Differential
Input
5 V
R
It is important to not violate the input common-mode
voltage range (VICR) of the operational amplifier.
Assuming the operational amplifier is in linear
operation, the voltage across the input pins is only a
few millivolts at most. Finding the voltage at one input
pin determines the input common-mode voltage of
the operational amplifier.
G
G
V
V
V
IN+
OUT–
+
THS4511
–
R
+
–
V
IN–
OUT+
Treating the negative input as a summing node, the
voltage is given by Equation 1:
R
F
æ
ö
÷
÷
ø
æ
ö
÷
÷
ø
RG
RF
Figure 35. Differential Input to Differential Ouput
Amplifier
ç
ç
VIC = VOUT+
´
+ VIN-
´
ç
ç
RG + RF
RG + RF
è
è
(1)
To determine the VICR of the operational amplifier, the
voltage at the negative input is evaluated at the
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
extremes of VOUT+
.
As the gain of the operational amplifier increases, the
input common-mode voltage becomes closer and
closer to the input common-mode voltage of the
source.
Single-Ended Input to Differential Output
Amplifier
The THS4511 can be used to amplify and convert
single-ended input signals to differential output
signals. A basic block diagram of the circuit is shown
in Figure 36 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
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Setting the Output Common-Mode Voltage
operational amplifier. Note RS and RIT are added to
the alternate input from the signal input to balance
the amplifier. One resistor that is equal to the
combined value RI = RG + RS||RIT can be placed at
the alternate input.
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 5 mV offset (typical) from the set
voltage, when set within 0.5 V of mid-supply. If left
unconnected, the common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source. Figure 37 is
representative of the CM input. The internal CM
circuit has about 700 MHz of –3 dB bandwidth, which
is required for best performance, but it is intended to
be a dc-bias input pin. Bypass capacitors are
recommended on this pin to reduce noise at the
output. The external current required to overdrive the
internal resistor divider is given by Equation 2:
RS
RF
RG
V
= 3.75 V to 5 V
RIT
S+
RPD
VSignal
RO
RO
VOUT-
VOUT+
THS4511
RG
CM
RS
RIT
VS–
RPD
VCM
RF
Figure 38. THS4511 DC Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
To Set VIC
2VCM - (VS+ - VS- )
50 kW
IEXT
=
(2)
where VCM is the voltage applied to the CM pin, and
VS+ ranges from 3.75 V to 5 V, and VS- is 0 V
(ground).
Note that in Figure 38, the source is referenced to
ground as is the input termination resistor RIT. The
proper value of resistance to add can be calculated
from Equation 3:
V
S+
1
R
=
P D
50 kΩ
I
é
ê
ê
ê
ù
ú
ú
ú
EXT
1
1 .6
S +
1
To Internal
CM Circuit
-
CM
V
R
R
I
F
- 1 .6
ê
ë
ú
û
2
50 kΩ
(3)
where RI = RG + RS||RIT.
V
S–
VS+ is the power-supply voltage, RF is the feedback
resistance, RG is the gain-setting resistance, RS is the
signal source resistance, and RIT is the termination
resistance.
Figure 37. CM Input Circuit
Device Operation with Single Power Supplies
Less than 5 V
Table 3 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, a dc-coupled
50 Ω source impedance, and setting the output
common-mode voltage to mid-supply.
The THS4511 is optimized to work in systems using
5 V single supplies, and the characterization data
presented in this data sheet was taken with 5 V
single-supply inputs. For ac-coupled systems or
dc-coupled systems operating with supplies less than
5 V and greater than 3.75 V, the amplifier input
common-mode range is maximized by adding
pull-down resistors at the device inputs. The
pull-down resistors provide additional loading at the
input, and lower the common-mode voltage that is fed
back into the device input through resistor RF.
Figure 38 shows the circuit configuration for this
mode of operation where RPD is added to the
dc-coupled circuit to avoid violating the VICR of the
Table 3. RPD Values for Various Gains,
VS+ = 3.75 V, DC-coupled Signal Source
Gain
6 dB
RF
RG
RIT
RPD
348 Ω
348 Ω
348 Ω
348 Ω
169 Ω
102 Ω
61.9 Ω
40.2 Ω
64.9 Ω
78.7 Ω
115 Ω
221 Ω
80.6 Ω
90.9 Ω
90.9 Ω
77.6 Ω
10 dB
14 dB
20 dB
If the signal originates from an ac-coupled 50 Ω
source (see Figure 39), the equivalent dc-source
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resistance is an open circuit, and RI = RG + RIT.
Table 4 is a modification of Table 1 to add the proper
Video Source
= 75 W
R
V
175 W
348 W
S
IN
values with RPD assuming VS+
= 3.75 V, an
ac-coupled 50 Ω source impedance, and setting the
output common-mode voltage to mid-supply.
V
= 5 V
S+
130 W
V
Signal
R
R
O
O
-
Table 4. RPD Values for Various Gains,
VS+ = 3.75 V, AC-Coupled Signal Source
VOD
THS4511
175 W
+
V
= 2.5 V
CM
Gain
6 dB
RF
RG
RIT
RPD
V
75 W
130 W
S-
348 Ω
348 Ω
348 Ω
348 Ω
169 Ω
102 Ω
61.9 Ω
40.2 Ω
64.9 Ω
78.7 Ω
115 Ω
221 Ω
86.6 Ω
110 Ω
158 Ω
226 Ω
10 dB
14 dB
20 dB
348 W
Figure 40. Single-Supply Video Buffer, Gain = 2
0.8
0.6
0.4
C
RS
RG
RF
V
= 3.75 V to 5 V
R
RPD
S+
IT
VSignal
RO
RO
VOUT-
VOUT+
THS4511
0.2
0
RG
C
CM
VS-
R
RPD
RS
IT
-0.2
-0.4
RF
Figure 39. THS4511 AC Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
to Set VIC
0
5
10
15
20
t - Time - ms
Figure 41. Y' Signal With 3-Level Sync and Video
Signal
Video Buffer
Figure 40 shows a possible application of the
THS4511 as a DC-coupled video buffer with a gain
of 2. Figure 41 shows a plot of the Y' signal
originating from a HDTV 720p video system. The
input signal includes a tri-level sync (minimum level at
–0.3 V) and the portion of a video signal with
maximum amplitude of 0.7 V. Although the buffer
draws its power from a 5 V single-ended power
supply, internal level shifters allow the buffer to
support input signals, which are as much as –0.3 V
below ground. This allows maximum design flexibility
while maintaining a minimum parts count. Figure 42
shows the differential output of the buffer. Note that
the DC-coupled amplifier can introduce a DC offset
on a signal applied at its input.
1.5
1
0.5
0
-0.5
-1
0
5
10
15
20
t - Time - ms
Figure 42. Video Buffer Differential Output Signal
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THS4511 + ADS5500 Combined Performance
THS4511 + ADS5424 Combined Performance
The THS4511 is designed to be a high-performance
drive amplifier for high-performance data converters
like the ADS5500 14 bit 125 MSPS ADC. Figure 43
shows a circuit combining the two devices. The
THS4511 amplifier circuit provides 10 dB of gain and
converts the single-ended input signal to a differential
output signal. The default common-mode output of
the THS4511 (2.5 V) is not compatible with the
required common-mode input of the ADS5500
(1.55 V), so dc-blocking capicitors are added (0.22
µF). Note that a biasing circuit (not shown in
Figure 43) is needed to provide the required
common-mode, dc-input for the ADS5500. The 100 Ω
resistors and 2.7 pF capacitor between the THS4511
outputs and ADS5500 inputs, along with the input
capacitance of the ADS5500, limit the bandwidth of
the signal to 115 MHz (–3 dB). For testing, a signal
generator is used for the signal source. The
generator is an ac-coupled 50 Ω source. A band-pass
filter is inserted in series with the input to reduce
harmonics and noise from the signal source. Input
termination is accomplished via the 69.8 Ω resistor
and 0.22 μF capacitor to ground in conjunction with
the input impedance of the amplifier circuit. A 0.22 μF
capacitor and 49.9 Ω resistor are inserted to ground
across the 69.8 Ω resistor and 0.22 μF capacitor on
the alternate input to balance the circuit. Gain is a
function of the source impedance, termination, and
348 Ω feedback resistor. See Table 1 for component
values to set proper 50 Ω termination for other
common gains.
Figure 44 shows the THS4511 driving the ADS5424
ADC.
The THS4511 amplifier provides 10 dB of gain,
converts the single-ended input to differential, and
sets the proper input common-mode voltage to the
ADS5424. Input termination and circuit testing is the
same as described above for the THS4511 +
ADS5500 circuit.
The 225 Ω resistors and 2.7 pF capacitor between
the THS4511 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100MHz (–3dB).
When the THS4511 is operated from a single power
supply with VS+ = 5 V and VS- = ground, the 2.5 V
output common-mode voltage is compatable with the
recommended value of the ADS5424 input
common-mode voltage (2.4 V).
VIN
100 W
348 W
From
50 W
source
5 V
69.8 W
14 bit,
105 MSPS
225 W
225 W
AIN+
2.7pF
ADS5424
AIN–
THS4511
CM
100 W
VBG
49.9 W
0.22 mF
69.8 W
49.9 W
0.1 mF
0.1 mF
348 W
Figure 44. THS4511 + ADS5424 Circuit
VIN
100 W
348 W
From
50 W
source
5 V
69.8 W
14 bit,
125 MSPS
0.22 mF 100 W
AIN +
THS4511
CM
ADS5500
2.7 pF
100 W
AIN -
CM
0.22 mF 100 W
49.9 W
69.8 W
0.22 mF
0.1 mF
348 W
Figure 43. THS4511 + ADS5500 Circuit
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Layout Recommendations
5. Two 10 μF and two 0.1 μF power-supply
decoupling capacitors should be placed as near
the power-supply pins as possible.
It is recommended to follow the layout of the external
components near the amplifier, ground plane
construction, and power routing of the EVM as
closely as possible. General guidelines are:
6. Two 0.1 μF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
1. Signal routing should be direct and as short as
possible into and out of the operational amplifier
circuit.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a solid
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
and L3.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
4. An output resistor is recommended on each
output, as near the output pin as possible.
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THS4511 EVM
Figure 45 is the THS4511 EVAL1 EVM schematic for the plastic QFN (RGT) package. Layers 1 through 4 of the
PCB are shown in Figure 46, and Table 5 is the bill of material for the EVM as supplied from TI. The same layout
recommendations should be followed for the THS4511 ceramic flatpack devices. Contact your TI representative
for availability of the THS4511 EVM.
GND
J5
V
S+
J6
TP1
VCC
J8
R5
10 mF
10 mF
0.1 mF
0.1 mF
348 W
R1
56.2 W
VCC
8
C3
C5
C12
C13
R9
6
5
J1
7
R3
open
12
PD
J3
C15
3
340 W
R12
R7
T1
2
V
V
-
O+
6
1
R11
69.8 W
86.6 W
R8
49.9 W
U1
0.22 mF
11
+
5
4
O-
PwrPad 10
VCC
J2
R4
4
3
86.6 W
Vocm
9
XFMR_ADT1-1WT
340 W
15 13
14 16
R2
56.2 W
R10
open
C1
open
R6
J7
C8
open
C7
open
348 W
TP3
TP2
C2
open
C14
0.1 mF
C11
0.1 mF
Figure 45. THS4511 EVAL1 EVM Schematic
Figure 46. THS4511 EVAL1 EVM Layer 1 Through 4
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Table 5. THS4511RGT EVM Bill of Materials
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER(1)
ITEM
DESCRIPTION
1
2
CAP, 10.0 μF, Ceramic, X5R, 6.3V
CAP, 0.1 μF, Ceramic, X5R, 10V
CAP, 0.22 μF, Ceramic, X5R, 6.3V
OPEN
0805 C3, C5
2
4
1
6
2
1
(AVX) 08056D106KAT2A
(AVX) 0402ZD104KAT2A
(AVX) 04026D224KAT2A
0402 C11, C12, C13, C14
0402 C15
3
4
0402 C1, C2, C7, C8, C9, C10
0402 R9, R10
0402 R12
5
OPEN
6
Resistor, 49.9 Ω, 1/16W, 1%
Resistor, 56.2 Ω, 1/16W, 1%
Resistor, 69.8 Ω, 1/16W, 1%
Resistor, 86.6 Ω, 1/16W, 1%
Resistor, 340 Ω, 1/16W, 1%
Resistor, 348 Ω, 1/16W, 1%
Resistor, 0 Ω, 5%
(KOA) RK73H1ETTP49R9F
(KOA) RK73H1ETTP56R2F
(KOA) RK73H1ETTP69R8F
(KOA) RK73H1ETTP86R6F
(KOA) RK73H1ETTP3400F
(KOA) RK73H1ETTP3480F
(KOA) RK73Z2ATTD
7
0402 R1, R2
0402 R11
8
3
2
2
2
2
1
2
9
0402 R7, R8
0402 R3, R4
0402 R5, R6
0805 C4, C6
T1
10
11
12
13
Transformer, RF
(MINI-CIRCUITS) ADT1-1WT
Jack, banana receptance, 0.25" diameter
hole
14
J5, J6
(HH SMITH) 101
15
16
17
18
19
20
21
OPEN
J1, J7, J8
J2, J3
3
2
3
1
4
4
1
Connector, edge, SMA PCB Jack
Test point, Red
(JOHNSON) 142-0701-801
(KEYSTONE) 5000
(TI) THS4511RGT
TP1, TP2, TP3
U1
IC, THS4511
Standoff, 4-40 HEX, 0.625" length
SCREW, PHILLIPS, 4-40, 0.250"
Printed circuit board
(KEYSTONE) 1808
SHR-0440-016-SN
(TI) EDGE# 6475513
(1) The manufacturer's part numbers were used for test purposes only.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the following table.
Input Range, VS+ to VS-
Input Range, VI
3.0 V to 6.0 V
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS-
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS-
Output Range, VO
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): THS4511–SP
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2021
PACKAGING INFORMATION
Orderable Device
5962-0722201VFA
THS4511HKT/EM
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-55 to 125
25 to 25
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
CFP
CFP
HKT
16
16
1
Non-RoHS
& Green
Call TI
N / A for Pkg Type
N / A for Pkg Type
5962-0722201VF
A
THS4511M
ACTIVE
HKT
1
RoHS & Green
Call TI
THS4511HKT/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4511-SP :
Catalog : THS4511
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
HKT0016A
CFP - 2.13 mm max height
S
C
A
L
E
0
.
7
0
0
CERAMIC DUAL FLATPACK
7.442
7.137
B
A
14X 1.27
16
1
10.414
9.652
2X 8.89
8
9
0.482
16X
0.382
0.2
C A
B
0.177
0.097
C
2.13 MAX
5.36
5.06
0.432
0.254
25.400
24.384
(5.21)
9
8
(10.03)
1
16
PIN 1 ID
4221021/B 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. Lid and cavity are electrically isolated
4. The terminals are gold plated.
5. Falls within MIL-STD-1835 CDFP-F11A.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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