THS4531A_16 [TI]
Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier;
| 型号： | THS4531A_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier |
| 文件： | 总50页 (文件大小：1485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4531A
www.ti.com
SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
Ultra Low Power, Rail-to-Rail Output, Fully-Differential Amplifier
Check for Samples: THS4531A
1
FEATURES
DESCRIPTION
The THS4531A is a low-power, fully-differential op
amp with input common-mode range below the
negative rail and rail-to-rail output. The device is
designed for low-power data acquisition systems and
high density applications where power consumption
and dissipation is critical.
•
Ultra Low Power:
–
–
–
Voltage: 2.5 V to 5.5 V
Current: 250 µA
Power-Down Mode: 0.5 µA (typ)
•
•
•
•
•
•
Fully-Differential Architecture
Bandwidth: 36 MHz
The device features accurate output common-mode
control that allows for dc coupling when driving
analog-to-digital converters (ADCs). This control,
coupled with the input common-mode range below
the negative rail and rail-to-rail output, allows for easy
interface from single-ended ground-referenced signal
sources to successive-approximation registers
(SARs), and delta-sigma (ΔΣ) ADCs using only
single-supply 2.5-V to 5-V power. The THS4531A is
also a valuable tool for general-purpose, low-power
differential signal conditioning applications.
Slew Rate: 200 V/µs
THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
High DC Accuracy:
–
–
–
VOS: ±100 µV
VOS Drift: ±3 µV/˚C (–40°C to +125°C)
AOL: 114 dB
•
•
•
Rail-to-Rail Output (RRO)
Negative Rail Input (NRI)
Output Common-Mode Control
The THS4531A is characterized for operation over
the extended industrial temperature range from
–40°C to +125°C. The following package options are
available:
APPLICATIONS
•
•
8-pin SOIC (MSOP) and VSSOP (D and DGK)
10-pin WQFN (RUN)
•
•
Low-Power SAR, ΔΣ ADC Driver
Low Power, High Performance:
0
−10
−20
−30
−40
VS = 5 V
G = 1 V/V
VOUT = 1 VRMS
RF = 2 kΩ
–
–
Differential to Differential Amplifier
Single-Ended to Differential Amplifier
RL = 600 Ω
•
•
Low-Power, Wide-Bandwidth Differential Driver
−50
−60
−70
−80
Low-Power, Wide-Bandwidth Differential
Signal Conditioning
−90
•
High Channel Count and Power Dense
Systems
−100
−110
−120
−130
−140
0
5k
10k
15k
20k
24k
Frequency (Hz)
G071
Figure 1. 1-kHz FFT Plot on Audio Analyzer
Table 1. Related Products
THD (dBc) at 100
DEVICE
BW (MHz)
IQ (mA)
kHz
VN (nV/√Hz)
RAIL-TO-RAIL
THS4521
THS4520
THS4121
THS4131
145
570
100
150
1.14
15.3
16
–120
–114
–79
4.6
2
Out
Out
5.4
1.3
In/Out
No
16
–107
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
THS4531A
SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
CHANNEL
COUNT
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
1
1
1
1
1
1
T4531A
T4531A
531A
THS4531AID
THS4531AIDR
Rails, 75
SOIC-8
VSSOP-8
WQFN-10
D
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Tape and reel, 2500
Rails, 80
THS4531AIDGK
THS4531AIDGKR
THS4531AIRUNT
THS4531AIRUNR
THS4531A
DGK
RUN
531A
Tape and reel, 2500
Tape and reel, 250
Tape and reel, 3000
531A
531A
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
VALUE
UNITS
Supply voltage, VS– to VS+
5.5
Input/output voltage, VIN±, VOUT±, and VOCM pins
Differential input voltage, VID
(VS–) – 0.7 to (VS+) + 0.7
V
V
1
Continuous output current, IO
50
mA
mA
Continuous input current, Ii
0.75
Continuous power dissipation
See Thermal Information
Maximum junction temperature, TJ
Operating free-air temperature range, TA
Storage temperature range, Tstg
150
–40 to +125
–65 to +150
3
°C
°C
°C
kV
Electrostatic
discharge (ESD)
ratings:
Human body model (HBM)
Charge device model (CDM)
500
V
THERMAL INFORMATION
THS4531A THS4531A THS4531A
VSSOP
SOIC
(P)
WQFN
(RUN)
THERMAL METRIC(1)
(MSOP)
(DGK)
UNITS
8 PINS
133
78
8 PINS
198
84
10 PINS
163
66
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
73
120
19
113
17
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
26
ψJB
73
118
N/A
113
N/A
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
ELECTRICAL CHARACTERISTICS: VS = 2.7 V
Test conditions at TA = 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
LEVEL
PARAMETER
AC PERFORMANCE
CONDITIONS
MIN
TYP
MAX UNITS
VOUT = 100 mVPP, G = 1
34
16
VOUT = 100 mVPP, G = 2
VOUT = 100 mVPP, G = 5
VOUT = 100 mVPP, G = 10
VOUT = 100 mVPP, G = 10
VOUT = 2 VPP, G = 1
Small-signal bandwidth
MHz
6
2.7
Gain-bandwidth product
27
MHz
MHz
MHz
V/µs
ns
Large-signal bandwidth
34
Bandwidth for 0.1-dB flatness
Slew rate, rise/fall, 25% to 75%
Rise/fall time, 10% to 90%
Settling time to 1%, rise/fall
Settling time to 0.1%, rise/fall
Settling time to 0.01%, rise/fall
Overshoot/undershoot, rise/fall
VOUT = 2 VPP, G = 1
12
190/320
5.2/6.1
25/20
60/60
150/110
1/1
VOUT = 2-V step
ns
ns
%
f = 1 kHz, VOUT = 1 VRMS
f = 10 kHz
–122
–127
–59
C
2nd-order harmonic distortion
3rd-order harmonic distortion
dBc
f = 1 MHz
f = 1 kHz, VOUT = 1 VRMS
f = 10 kHz
–130
–135
–70
dBc
dBc
f = 1 MHz
2nd-order intermodulation distortion
3rd-order intermodulation distortion
Input voltage noise
–83
f = 1 MHz, 200-kHz tone spacing,
VOUT envelope = 2 VPP
–81
f = 1 kHz
10
nV/√Hz
Hz
Voltage noise 1/f corner frequency
Input current noise
45
f = 100 kHz
0.25
6.5
pA/√Hz
kHz
ns
Current noise 1/f corner frequency
Overdrive recovery time
Overdrive = 0.5 V
65
Output balance error
VOUT = 100 mV, f = 1 MHz
f = 1 MHz (differential)
–65
dB
Closed-loop output impedance
2.5
Ω
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
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ELECTRICAL CHARACTERISTICS: VS = 2.7 V (continued)
Test conditions at TA = 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
LEVEL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
DC PERFORMANCE
Open-loop voltage gain (AOL
)
100
113
dB
A
A
TA = +25°C
±100
±400
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = +25°C
±715
µV
Input-referred offset voltage
±855
B
±1300
±7
±2
±2
Input offset voltage drift(1)
Input bias current
±7 µV/°C
±9
B
A
B
±3
200
250
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = +25°C
275
nA
286
305
0.45
0.45
0.45
±5
0.55
Input bias current drift(1)
Input offset current
0.55 nA/°C
0.55
B
A
B
±50
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
±55
nA
±57
±60
±0.03
±0.03
±0.03
±0.1
Input offset current drift(1)
±0.1 nA/°C
±0.1
B
INPUT
TA = +25°C, CMRR > 87 dB
VS– – 0.2
VS– – 0.2
VS–
A
B
A
B
A
C
C
Common-mode input low
V
TA = –40°C to +125°C, CMRR > 87 dB
TA = +25°C, CMRR > 87 dB
VS–
VS+ – 1.2 VS+ – 1.1
VS+ – 1.2 VS+ – 1.1
Common-mode input high
V
dB
TA = –40°C to +125°C, CMRR > 87 dB
Common-mode rejection ratio
Input impedance common-mode
Input impedance differential mode
OUTPUT
90
116
200 || 1.2
200 || 1
kΩ || pF
TA = +25°C
VS–
0.06
+
VS–
0.2
+
A
B
A
B
Single-ended output voltage: low
Single-ended output voltage: high
V
V
TA = –40°C to +125°C
TA = +25°C
VS–
0.06
+
VS–
0.2
+
VS+ – 0.2
VS+ – 0.2
VS+
0.11
–
TA = –40°C to +125°C
VS+
–
0.11
Output saturation voltage: high/low
Linear output current drive
110/60
±22
mV
mA
C
A
B
TA = +25°C
±15
±15
TA = –40°C to +125°C
(1) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
4
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
ELECTRICAL CHARACTERISTICS: VS = 2.7 V (continued)
Test conditions at TA = 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
LEVEL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
POWER SUPPLY
Specified operating voltage
2.5
5.5
330
370
V
B
A
B
A
TA = +25°C, PD = VS+
230
270
108
Quiescent operating current/ch
µA
dB
TA = –40°C to +125°C, PD = VS+
Power-supply rejection (PSRR)
POWER DOWN
87
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
Power-down quiescent current
Turn-on time delay
Specified on above 2.1 V
Specified off below 0.7 V
PD = VS– + 0.5 V
2.1
V
A
A
A
A
0.7
50
0.5
500
2
nA
µA
PD = VS– + 0.5 V
Time from PD = high to VOUT = 90% of final
650
value, RL= 200 Ω
ns
C
Time from PD = low to VOUT = 10% of original
value, RL= 200 Ω
Turn-off time delay
20
OUTPUT COMMON-MODE VOLTAGE CONTROL (VOCM
)
Small-signal bandwidth
Slew rate
VOCM input = 100 mVPP
23
14
MHz
V/µs
V/V
C
C
A
A
VOCM input = 1 VSTEP
Gain
0.99
0.8
0.996
±1
1.01
±5
Common-mode offset voltage
Offset = output common-mode voltage – VOCM
input voltage
mV
VOCM input bias current
VOCM input voltage range
VOCM = (VS+ – VS–)/2
±20
±100
1.75
nA
V
A
A
0.75 to
1.9
VOCM input impedance
100 || 1.6
±3
kΩ || pF
C
A
Default voltage offset from
(VS+ – VS–)/2
Offset = output common-mode voltage –
(VS+ – VS–)/2
±10
mV
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ELECTRICAL CHARACTERISTICS: VS = 5 V
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
LEVEL
PARAMETER
AC PERFORMANCE
CONDITIONS
MIN
TYP
MAX UNITS
VOUT = 100 mVPP, G = 1
36
17
VOUT = 100 mVPP, G = 2
VOUT = 100 mVPP, G = 5
VOUT = 100 mVPP, G = 10
VOUT = 100 mVPP, G = 10
VOUT = 2 VPP, G = 1
Small-signal bandwidth
MHz
6
2.7
Gain-bandwidth product
27
MHz
MHz
MHz
V/µs
ns
Large-signal bandwidth
36
Bandwidth for 0.1-dB flatness
Slew rate, rise/fall, 25% to 75%
Rise/fall time, 10% to 90%
Settling time to 1%, rise/fall
Settling time to 0.1%, rise/fall
Settling time to 0.01%, rise/fall
Overshoot/undershoot, rise/fall
VOUT = 2 VPP, G = 1
15
220/390
4.6/5.6
25/20
60/60
150/110
1/1
ns
VOUT = 2 VStep
ns
ns
%
f = 1 kHz, VOUT = 1 VRMS
f = 10 kHz
–122
–128
–60
C
2nd-order harmonic distortion
3rd-order harmonic distortion
dBc
f = 1 MHz
f = 1 kHz, VOUT = 1 VRMS
f = 10 kHz
–130
–137
–71
dBc
dBc
f = 1 MHz
2nd-order intermodulation distortion
3rd-order intermodulation distortion
Input voltage noise
–85
f = 1 MHz, 200-kHz tone spacing,
VOUT envelope = 2 VPP
–83
f = 1 kHz
10
nV/√Hz
Hz
Voltage noise 1/f corner frequency
Input current noise
45
f = 100 kHz
0.25
6.5
pA/√Hz
kHz
ns
Current noise 1/f corner frequency
Overdrive recovery time
Overdrive = 0.5 V
65
Output balance error
VOUT = 100 mV, f = 1 MHz
f = 1 MHz (differential)
–67
dB
Closed-loop output impedance
2.5
Ω
6
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
LEVEL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
DC PERFORMANCE
Open-loop voltage gain (AOL
)
100
114
dB
A
A
TA = +25°C
±100
±400
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = +25°C
±715
µV
Input-referred offset voltage
±855
B
±1300
±7
±2
±2
Input offset voltage drift(1)
Input bias current
±7 µV/°C
±9
B
A
B
±3
200
250
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = +25°C
279
nA
292
315
0.5
0.5
0.5
±5
0.65
Input bias current drift(1)
Input offset current
0.65 nA/°C
0.65
B
A
B
±50
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
±55
nA
±57
±60
±0.03
±0.03
±0.03
±0.1
Input offset current drift(1)
±0.1 nA/°C
±0.1
B
INPUT
TA = +25°C, CMRR > 87 dB
VS– – 0.2
VS– – 0.2
VS–
A
B
A
B
A
C
C
Common-mode input: low
V
TA = –40°C to +125°C, CMRR > 87 dB
TA = +25°C, CMRR > 87 dB
VS–
VS+ – 1.2 VS+ –1.1
VS+ – 1.2 VS+ –1.1
Common-mode input: high
V
dB
TA = –40°C to +125°C, CMRR > 87 dB
Common-mode rejection ratio
Input impedance common-mode
Input impedance differential mode
OUTPUT
90
116
200 || 1.2
200 || 1
kΩ || pF
TA = +25°C
VS– + 0.1 VS– + 0.2
VS– + 0.1 VS– + 0.2
A
B
A
Linear output voltage: low
TA = –40°C to +125°C
TA = +25°C
VS+ – 0.25
VS+ – 0.25
VS+
–
V
0.12
Linear output voltage: high
TA = –40°C to +125°C
VS+
–
B
0.12
Output saturation voltage: high/low
Linear output current drive
120/100
±25
mV
mA
C
A
B
TA = +25°C
±15
±15
TA = –40°C to +125°C
(1) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
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ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
TEST
LEVEL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
POWER SUPPLY
Specified operating voltage
2.5
5.5
350
390
V
B
A
B
A
TA = 25°C, PD = VS+
250
290
108
Quiescent operating current/ch
µA
dB
TA = –40°C to 125°C, PD = VS+
Power-supply rejection (PSRR)
POWER DOWN
87
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
Power-down quiescent current
Turn-on time delay
Specified on above 2.1 V
Specified off below 0.7 V
PD = VS– + 0.5 V
2.1
A
A
A
A
V
0.7
50
0.5
500
2
nA
µA
PD = VS– + 0.5 V
Time from PD = high to VOUT = 90% of final
600
value, RL= 200 Ω
ns
C
Time from PD = low to VOUT = 10% of
original value, RL= 200 Ω
Turn-off time delay
15
OUTPUT COMMON-MODE VOLTAGE CONTROL (VOCM
)
Small-signal bandwidth
Slew rate
VOCM input = 100 mVPP
24
15
MHz
V/µs
V/V
C
C
A
A
VOCM input = 1 VSTEP
Gain
0.99
0.95
0.996
±1
1.01
±5
Common-mode offset voltage
Offset = output common-mode voltage –
VOCM input voltage
mV
VOCM input bias current
VOCM input voltage range
VOCM = (VS+ – VS–)/2
±20
±120
4.0
nA
V
A
A
0.75 to
4.15
VOCM input impedance
65 || 0.86
±3
kΩ || pF
C
A
Default voltage offset from
(VS+ – VS–)/2
Offset = output common-mode voltage –
(VS+ – VS–)/2
±10
mV
8
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
DEVICE INFORMATION
PIN CONFIGURATIONS
THS4531A
SOIC-8 (D), VSSOP-8 (DGK) PACKAGE (TOP VIEW)
THS4531A
WQFN-10 (RUN) PACKAGE (TOP VIEW)
VS+
VIN-
VOCM
VS+
VIN+
8
7
1
2
3
4
10
VOUT-
VOUT+
9
8
7
6
1
2
3
4
PD
VS-
NC
NC
PD
6
5
VOCM
VIN-
VOUT+
VOUT-
VIN+
5
VS-
PIN FUNCTIONS
NUMBER
NAME
DESCRIPTION
THS4531A D, DGK PACKAGE
1
2
3
4
5
6
7
8
VIN–
VOCM
VS+
Inverted (negative) output feedback
Common-mode voltage input
Amplifier positive power-supply input
Noninverted amplifier output
Inverted amplifier output
VOUT+
VOUT–
VS–
Amplifier negative power-supply input. Note VS– tied together on multichannel devices.
PD
Power-down, PD = logic low = low power mode, PD = logic high = normal operation (PIN MUST BE DRIVEN)
VIN+
Noninverted amplifier input
THS4531A RUN PACKAGE
1
2, 8
3
VOUT–
NC
Inverted amplifier output
No internal connection
PD
Power-down, PD = logic low = low power mode, PD = logic high = normal operation (PIN MUST BE DRIVEN)
4
VIN+
VS–
Noninverted amplifier input
5
Amplifier negative power-supply input. Note VS– tied together on multichannel devices.
Inverting amplifier input
6
VIN–
VOCM
VOUT+
VS+
7
Common-mode voltage input
9
Noninverted amplifier output
10
Amplifier positive power-supply input
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TABLE OF GRAPHS
Description
VS = 2.7 V
Figure 2
VS = 5 V
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Small-signal frequency response
Large-signal frequency response
Figure 3
Large- and small- signal pulse response
Single-ended slew rate vs VOUT step
Differential slew rate vs VOUT step
Figure 4
Figure 5
Figure 6
Overdrive recovery
Figure 7
10-kHz FFT on audio analyzer
Figure 8
Harmonic distortion vs Frequency
Figure 9
Harmonic distortion vs Output voltage at 1 MHz
Harmonic distortion vs Gain at 1 MHz
Harmonic distortion vs Load at 1 MHz
Harmonic distortion vs VOCM at 1 MHz
Two-tone, 2nd and 3rd order intermodulation distortion vs Frequency
Single-ended output voltage swing vs Load resistance
Single-ended output saturation voltage vs Load current
Main amplifier differential output impedance vs Frequency
Frequncy response vs CLOAD
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
RO vs CLOAD
Rejection ratio vs Frequency
Turn-on time
Turn-off time
Input-referred voltage noise and current noise spectral density
Main amplifier differential open-loop gain and phase vs Frequency
Output balance error vs Frequency
VOCM small signal frequency response
VOCM large and small signal pulse response
VOCM input impedance vs frequency
Count vs input offset current
Count vs input offset current temperature drift
Input offset current vs temperature
Count vs input offset voltage
Count vs input offset voltage temperature drift
Input offset voltage vs temperature
10
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS: VS = 2.7V
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0V, CM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
21
18
15
12
9
21
18
15
12
9
G = 1 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
6
6
3
3
0
0
−3
−6
−9
−12
−15
−18
−21
−3
−6
−9
−12
−15
−18
−21
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
VOUT = 100 mVpp
100k
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
G001
G002
Figure 2.
Figure 3.
SINGLE-ENDED SLEW RATE
vs
LARGE- and SMALL-SIGNAL PULSE RESPONSE
VOUT STEP
1.5
400
350
300
250
200
150
100
50
VS = 2.7 V
VS = 2.7 V
0.5-V Step
2-V Step
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
1
0.5
0
−0.5
−1
Rising
Falling
−1.5
0
0
20
40
60
80
100
0
0.5
1
1.5
2
2.5
Time (ns)
Differential VOUT (V)
G003
G004
Figure 4.
Figure 5.
DIFFERENTIAL SLEW RATE
vs
VOUT STEP
OVERDRIVE RECOVERY
2
4
250
200
150
100
50
VIN
VOUT
VS = 2.7 V
1.5
1
3
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
2
0.5
0
1
0
−0.5
−1
−1
−2
−3
−4
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
RL = 2 kΩ
−1.5
−2
Rising
Falling
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
0
1
2
3
4
5
6
G005
Differential VOUT (V)
G053
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS: VS = 2.7V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0V, CM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.
HARMONIC DISTORTION
vs
10-kHz FFT ON AUDIO ANALYZER
FREQUENCY
10
0
−20
−30
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 100 kΩ
VOUT = 4 Vpp
VS = 2.7 V
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
Second Harmonic
Third Harmonic
0
1
0
5k
10k
15k
20k
24k
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G006
G007
Figure 8.
Figure 9.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE at 1 MHz
HARMONIC DISTORTION
vs
GAIN at 1 MHz
−10
−20
−30
−40
−50
−60
−70
−80
−40
−45
−50
−55
−60
−65
−70
−75
−80
VS = 2.7 V
RF = 2 kΩ
RL = 2 kΩ
Second Harmonic
Third Harmonic
VOUT = 2 Vpp
VS = 2.7 V
f = 1 MHz
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
f = 1 MHz
Second Harmonic
Third Harmonic
2
3
4
0
2
4
6
8
10
Gain (V/V)
VOUT (Vpp
)
G008
G009
Figure 10.
Figure 11.
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
LOAD at 1 MHz
VOCM at 1 MHz
0
−10
−20
−30
−40
−50
−60
−70
−80
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
VS = 2.7 V
VS = 2.7 V
Second Harmonic
Third Harmonic
Second Harmonic
Third Harmonic
G = 1 V/V
RF = 2 kΩ
VOUT = 2 Vpp
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
f = 1 MHz
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
0.5
1
1.5
2
Load (Ω)
VOCM (V)
G010
G011
Figure 12.
Figure 13.
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS: VS = 2.7V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0V, CM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.
SINGLE-ENDED OUTPUT VOLTAGE SWING
TWO-TONE, 2nd and 3rdORDER INTERMODULATION
vs
DISTORTION vs FREQUENCY
LOAD RESISTANCE
−10
−20
−30
−40
−50
−60
−70
−80
−90
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
2.5
2
VOUT MAX
VOUT MIN
VOUT = 2 Vpp Envelope
1.5
1
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
0.5
0
Second Intermodulation
Third Intermodulation
1
10
50
100
1k
10k
Frequency (MHz)
Load Resistance (Ω)
G012
G013
Figure 14.
Figure 15.
SINGLE-ENDED OUTPUT SATURATION VOLTAGE
vs
MAIN AMPLIFIER DIFFERENTIAL OUTPUT IMPEDANCE
vs
LOAD CURRENT
FREQUENCY
1
100
VSAT High
VS = 2.7 V
VSAT Low
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
0.8
10
1
0.6
0.4
0.2
0
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
0.1
0.01
0.1
1
10
30
10k
100k
1M
10M
40M
Differential Load Current (mA)
Frequency (Hz)
G014
G015
Figure 16.
Figure 17.
FREQUENCY RESPONSE
RO
vs
vs
CLOAD
CLOAD
3
0
200
100
−3
VS = 2.7 V, G = 1 V/V
RF = 2 kΩ, RL = 2 kΩ
VOUT = 100 mVpp
−6
−9
10
CL = 0 pF,RO = 0 Ω
−12
−15
−18
−21
CL = 15 pF,RO = 200 Ω
CL = 39 pF,RO = 100 Ω
CL = 120 pF,RO = 50 Ω
CL = 470 pF,RO = 20 Ω
CL = 1200 pF,RO = 12 Ω
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
1
100k
1M
10M
100M
1
10
100
1k 2k
Frequency (Hz)
CLOAD (pF)
G016
G017
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS: VS = 2.7V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0V, CM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.
REJECTION RATIO
vs
FREQUENCY
TURN-ON TIME
3
2
1
0
1.5
1
−20
−30
−40
−50
−60
−70
−80
−90
−100
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
0.5
0
Power Down
VOUT
CMRR
PSRR
0
200
400
600
800
1000
100k
1M
10M
30M
Time (ns)
G019
Frequency (Hz)
G018
Figure 20.
Figure 21.
INPUT-REFERRED VOLTAGE NOISE
and
TURN-OFF TIME
CURRENT NOISE SPECTRAL DENSITY
3
2
1
0
1.5
1
100
10
1
100
10
1
Power Down
VOUT
Voltage Noise
Current Noise
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
0.5
0
0.1
0.1
0
10
20
30
40
50
10
100
1k
10k
100k
1M
Time (ns)
Frequency (Hz)
G020
G021
Figure 22.
Figure 23.
MAIN AMPLIFIER DIFFERENTIAL
OPEN-LOOP GAIN and PHASE
vs
OUTPUT BALANCE ERROR
vs
FREQUENCY
FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
0
−30
−40
−50
−60
−70
−80
Magnitude
Phase
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
−45
−90
−135
−180
10
100
1k
10k
100k
1M
10M
100M
100k
1M
10M
30M
Frequency (Hz)
G022
Frequency (Hz)
G023
Figure 24.
Figure 25.
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS: VS = 2.7V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0V, CM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.
VOCM SMALL-SIGNAL FREQUENCY RESPONSE
VOCM LARGE- and SMALL SIGNAL PULSE RESPONSE
3
0
2
1.8
1.6
1.4
1.2
1
−3
−6
−9
−12
−15
−18
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
0.2-V Step
1-V Step
0.8
0.6
100k
1M
Frequency (Hz)
10M
50M
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
G024
G025
Figure 26.
Figure 27.
VOCM INPUT IMPEDANCE
vs
INPUT OFFSET CURRENT
HISTOGRAM
FREQUENCY
200k
100k
600
500
400
300
200
100
0
VS = 2.7 V
THS4531AID
VS = 2.7 V
TA =25°C
10k
1k
100
100k
1M
Frequency (Hz)
10M
50M
G026
Input Offset Current (nA)
G055
Figure 28.
Figure 29.
INPUT OFFSET CURRENT
vs
INPUT OFFSET CURRENT TEMP DRIFT
HISTOGRAM
TEMPERATURE
50
40
12
10
8
THS4531AID
VS = 2.7 V
0°C to +70°C
THS4531AID
VS = 2.7 V
−40°C to +85°C
−40°C to +125°C
30
20
10
0
6
−10
−20
−30
−40
−50
4
2
0
−50
−25
0
25
50
75
100
125
Temperature (°C)
G057
Input Offset Current Temperature Drift (pA/°C)
G056
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: VS = 2.7V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0V, CM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.
INPUT OFFSET VOLTAGE
HISTOGRAM
INPUT OFFSET VOLTAGE TEMP DRIFT
HISTOGRAM
600
500
400
300
200
100
0
10
8
THS4531AID
0°C to +70°C
THS4531AID
VS = 2.7 V
VS = 2.7 V
TA = 25°C
−40°C to +85°C
−40C to +125C
6
4
2
0
Input Offset Voltage (µV)
Input Offset Voltage Temperature Drift (µV/°C)
G058
G059
Figure 32.
Figure 33.
INPUT OFFSET VOLTAGE
vs
TEMPERATURE
1000
800
THS4531AID
VS = 2.7 V
600
400
200
0
−200
−400
−600
−800
−1000
−50
−25
0
25
50
75
100
125
Temperature (°C)
G060
Figure 34.
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SLOS823A –DECEMBER 2012–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS: VS = 5V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
21
18
15
12
9
21
18
15
12
9
G = 1 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
6
6
3
3
0
0
−3
−6
−9
−12
−15
−18
−21
−3
−6
−9
−12
−15
−18
−21
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
VOUT = 100 mVpp
100k
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
G027
G028
Figure 35.
Figure 36.
SINGLE-ENDED SLEW RATE
vs
LARGE- and SMALL-SIGNAL PULSE RESPONSE
VOUT STEP
1.5
600
500
400
300
200
100
0
VS = 5 V
VS = 5 V
0.5-V Step
2-V Step
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
1
0.5
0
−0.5
−1
Rising
Falling
−1.5
0
20
40
60
80
100
0
1
2
3
4
5
Time (ns)
Differential VOUT (V)
G029
G030
Figure 37.
Figure 38.
DIFFERENTIAL SLEW RATE
vs
VOUT STEP
OVERDRIVE RECOVERY
3
6
250
200
150
100
50
VIN
VOUT
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
2
1
4
2
0
0
−1
−2
−3
−2
−4
−6
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
Rising
Falling
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
0
1
2
3
4
5
6
7
8
G031
Differential VOUT (V)
G054
Figure 39.
Figure 40.
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TYPICAL CHARACTERISTICS: VS = 5V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
HARMONIC DISTORTION
vs
10-kHz FFT ON AUDIO ANALYZER
FREQUENCY
10
0
−20
−30
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 100 kΩ
VOUT = 8 Vpp
VS = 5 V
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
Second Harmonic
Third Harmonic
0
1
0
5k
10k
15k
20k
24k
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
G032
G033
Figure 41.
Figure 42.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE at 1 MHz
HARMONIC DISTORTION
vs
GAIN at 1 MHz
−30
−40
−50
−60
−70
−80
−40
−45
−50
−55
−60
−65
−70
−75
−80
VS = 5 V
VS = 5 V
RF = 2 kΩ
RL = 2 kΩ
Second Harmonic
Third Harmonic
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
f = 1 MHz
Second Harmonic
Third Harmonic
2
3
4
5
6
7
8
0
2
4
6
8
10
Gain (V/V)
VOUT (Vpp
)
G034
G035
Figure 43.
Figure 44.
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
LOAD at 1 MHz
VOCM at 1 MHz
0
−10
−20
−30
−40
−50
−60
−70
−80
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
VS = 5 V
VS = 5 V
Second Harmonic
Third Harmonic
Second Harminc
Third Harmonic
G = 1 V/V
RF = 2 kΩ
VOUT = 2 Vpp
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
f = 1 MHz
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Load (Ω)
VOCM (V)
G036
G037
Figure 45.
Figure 46.
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TYPICAL CHARACTERISTICS: VS = 5V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
SINGLE-ENDED OUTPUT VOLTAGE SWING
TWO-TONE, 2nd and 3rdORDER INTERMODULATION
vs
DISTORTION vs FREQUENCY
LOAD RESISTANCE
−10
−20
−30
−40
−50
−60
−70
−80
−90
5
4.5
4
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT MAX
VOUT MIN
3.5
3
VOUT = 2 Vpp Envelope
2.5
2
VS = 5 V
G = 2 V/V
RF = 2 kΩ
1.5
1
Second Intermodulation
Third Intermodulation
0.5
0
1
10
50
100
1k
10k
Frequency (MHz)
Load Resistance (Ω)
G038
G039
Figure 47.
Figure 48.
SINGLE-ENDED OUTPUT SATURATION VOLTAGE
MAIN AMPLIFIER DIFFERENTIAL OUTPUT IMPEDANCE
vs
vs
LOAD CURRENT
FREQUENCY
1.2
100
VSAT High
VSAT Low
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
1
0.8
0.6
0.4
0.2
0
10
1
VS = 5 V
G = 2 V/V
RF = 2 kΩ
0.1
0.01
0.1
1
10
30
10k
100k
1M
10M
40M
Differential Load Current (mA)
Frequency (Hz)
G040
G041
Figure 49.
Figure 50.
FREQUENCY RESPONSE
RO
vs
vs
CLOAD
CLOAD
3
0
200
100
−3
VS = 5 V, G = 1 V/V
RF = 2 kΩ, RL = 2 kΩ
VOUT = 100 mVpp
−6
−9
10
CL = 0 pF,RO = 0 Ω
−12
−15
−18
−21
CL = 15 pF,RO = 200 Ω
CL = 39 pF,RO = 100 Ω
CL = 120 pF,RO = 50 Ω
CL = 470 pF,RO = 20 Ω
CL = 1200 pF,RO = 12 Ω
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
1
100k
1M
10M
100M
1
10
100
1k 2k
Frequency (Hz)
CLOAD (pF)
G042
G043
Figure 51.
Figure 52.
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TYPICAL CHARACTERISTICS: VS = 5V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
REJECTION RATIO
vs
FREQUENCY
TURN-ON TIME
5
4
3
2
1
0
2.5
2
−20
−30
−40
−50
−60
−70
−80
−90
−100
VS = 5 V
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
Power Down
VOUT
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
1.5
1
0.5
0
CMRR
PSRR
0
200
400
600
800
1000
100k
1M
10M
30M
Time (ns)
G045
Frequency (Hz)
G044
Figure 53.
Figure 54.
INPUT-REFERRED VOLTAGE NOISE
and
TURN-OFF TIME
CURRENT NOISE SPECTRAL DENSITY
5
4
3
2
1
0
2.5
2
100
10
1
100
10
1
Power Down
VOUT
Voltage Noise
Current Noise
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
1.5
1
0.5
0
0.1
0.1
0
10
20
30
40
50
10
100
1k
10k
100k
1M
Time (ns)
Frequency (Hz)
G046
G047
Figure 55.
Figure 56.
MAIN AMPLIFIER DIFFERENTIAL
OPEN-LOOP GAIN and PHASE
vs
OUTPUT BALANCE ERROR
vs
FREQUENCY
FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
0
−30
−40
−50
−60
−70
−80
Magnitude
Phase
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
−45
−90
−135
−180
10
100
1k
10k
100k
1M
10M
100M
100k
1M
10M
30M
Frequency (Hz)
G048
Frequency (Hz)
G049
Figure 57.
Figure 58.
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TYPICAL CHARACTERISTICS: VS = 5V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
VOCM SMALL-SIGNAL FREQUENCY RESPONSE
VOCM LARGE- and SMALL SIGNAL PULSE RESPONSE
3
0
3.2
3
2.8
2.6
2.4
−3
−6
−9
0.2-V Step
1-V Step
−12
−15
−18
2.2
2
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
1.8
100k
1M
Frequency (Hz)
10M
50M
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
G050
G051
Figure 59.
Figure 60.
VOCM INPUT IMPEDANCE
vs
INPUT OFFSET CURRENT
HISTOGRAM
FREQUENCY
100k
10k
1k
600
500
400
300
200
100
0
VS = 5 V
THS4531AID
VS = 5 V, 25°C
100
100k
1M
Frequency (Hz)
10M
50M
G052
Input Offset Current (nA)
G061
Figure 61.
Figure 62.
INPUT OFFSET CURRENT
vs
INPUT OFFSET CURRENT TEMP DRIFT
HISTOGRAM
TEMPERATURE
50
40
14
12
10
8
THS4531AID
VS = 5 V
0°C to +70°C
THS4531AID
VS = 5 V
−40°C to +85°C
−40°C to +125°C
30
20
10
0
6
−10
−20
−30
−40
−50
4
2
0
−50
−25
0
25
50
75
100
125
Temperature (°C)
G063
Input Offset Current Temperature Drift (pA/C)
G062
Figure 63.
Figure 64.
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TYPICAL CHARACTERISTICS: VS = 5V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0V, VOCM = open, VOUT = 2Vpp, RF = 2kΩ, RL = 2kΩ Differential, G =
1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°Cunless otherwise noted.
INPUT OFFSET VOLTAGE
HISTOGRAM
INPUT OFFSET VOLTAGE TEMP DRIFT
HISTOGRAM
600
500
400
300
200
100
0
10
8
THS4531AID
0°C to +70°C
THS4531AID
VS = 5 V
VS = 5 V
TA = 25°C
−40°C to +85°C
−40°C to +125°C
6
4
2
0
Input Offset Voltage (µV)
Input Offset Voltage Temperature Drift (µV/°C)
G064
G065
Figure 65.
Figure 66.
INPUT OFFSET VOLTAGE
vs
TEMPERATURE
1000
800
THS4531AID
VS = 5 V
600
400
200
0
−200
−400
−600
−800
−1000
−50
−25
0
25
50
75
100
125
Temperature (°C)
G066
Figure 67.
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APPLICATION INFORMATION
TYPICAL CHARACTERISTICS TEST CIRCUITS
Figure 68 shows the general test circuit built on the EVM that was used for testing the THS4531A. For simplicity,
power supply decoupling is not shown – please see layout in the applications section for recommendations.
Depending on the test conditions, component values are changed per Table 2 and Table 3, or as otherwise
noted. Some of the signal generators used are ac coupled 50Ω sources and a 0.22µF cap and 49.9Ω resistor to
ground are inserted across RIT on the un-driven or alternate input as shown to balance the circuit. Split-power
supply is used to ease the interface to common lab test equipment, but if properly biased, the amplifier can be
operated single-supply as described in the applications section with no impact on performance. For most of the
tests, the devices are tested with single ended input and a transformer on the output to convert the differential
output to single ended because common lab test equipment have single ended inputs and outputs. Performance
is the same or better with differential input and differential output.
VIN+
RG
RF
RO
Input From 50-ꢁ
Test Equipment
PD
RIT
VS+
VOUTœ
1:1
Output to 50-ꢁ
Test Equipment
+
0.22 ꢀF
VOCM
THS4531A
VOUT+
ROT
œ
0.22 ꢀF
RG
VSœ
VINœ
RO
No Connection
RF
RIT
0.22 ꢀF
49.9 ꢁ
Installed to Balance
Amplifier
Figure 68. General Test Circuit
Table 2. Gain Component Values for Single-Ended Input(1)
GAIN
1 V/V
2 V/V
5 V/V
10 V/V
RF
RG
2kΩ
RIT
2kΩ
2kΩ
2kΩ
2kΩ
51.1Ω
52.3Ω
53.6Ω
57.6Ω
1kΩ
392Ω
187kΩ
(1) Note components are chosen to achieve gain and 50Ω input termination. Resistor values shown are closest standard values so gains
are approximate.
Table 3. Load Component Values For 1:1 Differential to Single-Ended Output Transformer(1)
RL
RO
ROT
ATTEN
6
100Ω
200Ω
499Ω
1kΩ
25Ω
open
86.6Ω
237Ω
487Ω
976Ω
69.8Ω
56.2Ω
52.3Ω
51.1Ω
16.8
25.5
31.8
37.9
2kΩ
(1) Note the total load includes 50Ω termination by the test equipment. Components are chosen to achieve load and 50Ω line termination
through a 1:1 transformer. Resistor values shown are closest standard values so loads are approximate.
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Due to the voltage divider on the output formed by the load component values, the amplifier’s output is
attenuated. The column “Atten” in Table 3 shows the attenuation expected from the resistor divider. When using
a transformer at the output as shown in Figure 68, the signal will see slightly more loss due to transformer and
line loss, and these numbers will be approximate. The standard output load used for most tests is 2kΩ with
associated 37.9dB of loss.
Frequency Response, and Output Impedance
The circuit shown in Figure 68 is used to measure the frequency response of the amplifier.
A network analyzer is used as the signal source and the measurement device. The output impedance of the
network analyzer is 50Ω and is DC coupled. RIT and RG are chosen to impedance match to 50Ω and maintain
the proper gain. To balance the amplifier, a 49.9Ω resistor to ground is inserted across RIT on the alternate input.
The output is routed to the input of the network analyzer via 50Ω coax. For 2k load, 37.9dB is added to the
measurement to refer back to the amplifier’s output per Table 3.
For output impedance, the signal is injected at VOUT with VIN left open. The voltage drop across the 2x RO
resistors is measured with a high impedance differential probe and used to calculate the impedance seen looking
into the amplifier’s output.
Distortion
At 1MHz and above, the circuit shown in Figure 68 is used to measure harmonic, intermodulation distortion, and
output impedance of the amplifier.
A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output
impedance of the signal generator is 50Ω and is AC coupled. RIT and RG are chosen to impedance match to 50Ω
and maintain the proper gain. To balance the amplifier, a 0.22µF cap and 49.9Ω resistor to ground is inserted
across RIT on the alternate input. A low-pass filter is inserted in series with the input to reduce harmonics
generated at the signal source. The level of the fundamental is measured and then a high-pass filter is inserted
at the output to reduce the fundamental so it does not generate distortion in the input of the spectrum analyzer.
Distortion in the audio band is measured using an audio analyzer. Refer to audio measurement section for detail.
Slew Rate, Transient Response, Settling Time, Overdrive, Output Voltage, and Turn-On/Off Time
The circuit shown in Figure 69 is used to measure slew rate, transient response, settling time, overdrive
recovery, and output voltage swing. Turn on and turn off times are measured with 50Ω input termination on the
PD input, by replacing the 0.22µF capacitor with 49.9Ω resistor.
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VIN+
VOUTœ
RG
RF
RO
Output to
Input From 50-ꢁ
Test Equipment
Test Equipment
PD
RIT
VS+
+
0.22 ꢀF
VOCM
THS4531A
œ
0.22 ꢀF
VSœ
VINœ
VOUT+
RG
RO
Output to
Test Equipment
No Connection
RF
RIT
0.22 ꢀF
49.9 ꢁ
Installed to Balance
Amplifier
Figure 69. Slew Rate, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, and Turn-
on/off Test Circuit
Common-Mode and Power Supply Rejection
The circuit shown in Figure 70 is used to measure the CMRR. The signal from the network analyzer is applied
common-mode to the input.
VIN+
RG
RF
RO
Input From 50-ꢁ
Test Equipment
VS+
VOUTœ
+
Measure With
Diff Probe
VOCM
THS4531A
VOUT+
ROT
œ
0.22 ꢀF
VSœ
VINœ
RG
RO
No Connection
RF
Cal Diff Probe
RIT
Figure 70. CMRR Test Circuit
Figure 71 is used to measure the PSRR of VS+ and VS-. The power supply is applied to the network analyzer’s
DC offset input. For both CMRR and PSRR, the output is probed using a high impedance differential probe
across ROT
.
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Power
Supply
Network
Analyzer
Cal Diff Probe
RO
VIN+
RG
RF
VS+
No Connection
RIT
VOUTœ
+
Measure With
Diff Probe
VOCM
THS4531A
VOUT+
RO
ROT
œ
0.22 ꢀF
VSœ
VINœ
RG
No Connection
RF
RIT
Figure 71. PSRR Test Circuit
VOCM Input
The circuit shown in Figure 72 is used to measure the transient response, frequency response and input
impedance of the VOCM input. For these tests, the cal point is across the 49.9Ω VOCM termination resistor.
Transient response and frequency response are measured with RCM = 0Ω and using a high impedance
differential probe at the summing junction of the two RO resistors, with respect to ground. The input impedance is
measured using a high impedance differential probe at the VOCM pin and the drop across RCM is used to calculate
the impedance seen looking into the amplifier’s VOCM input.
VIN+
RG
RF
RO
No Connection
RIT
For BW
Measure With
Diff Probe Here
VS+
VOUTœ
VOCM
RCM
+
From Network
Analyzer
VOCM
-
THS4531A
VOUT+
For ZIN
Measure With
Diff Probe Here
VINœ
49.9 ꢀ
VSœ
Cal Diff Probe
RG
RO
No Connection
RF
RIT
NC
Figure 72. VOCM Input Test Circuit
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Balance Error
The circuit shown in Figure 73 is used to measure the balance error of the main differential amplifier. A network
analyzer is used as the signal source and the measurement device. The output impedance of the network
analyzer is 50Ω and is DC coupled. RIT and RG are chosen to impedance match to 50Ω and maintain the proper
gain. To balance the amplifier, a 49.9Ω resistor to ground is inserted across RIT on the alternate input. The output
is measured using a high impedance differential probe at the summing junction of the two RO resistors, with
respect to ground.
VIN+
RG
RF
RO
Input From 50-ꢁ
Test Equipment
RIT
VS+
VOUTœ
Cal Diff Probe
Measure With
Diff Probe Here
+
VOCM
THS4531A
VOUT+
œ
0.22 ꢀF
VSœ
VIN-
RG
RO
No Connection
RF
RIT
49.9 ꢁ
Installed to Balance
Amplifier
Figure 73. Balance Error Test Circuit
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APPLICATION CIRCUITS
The following circuits show application information for the THS4531A. For simplicity, power supply decoupling
capacitors are not shown in these diagrams – please see the EVM and Layout Recommendations section for
recommendations. For more detail on the use and operation of fully differential op amps refer to application
report “Fully-Differential Amplifiers” SLOA054D.
Differential Input to Differential Output Amplifier
The THS4531A is a fully differential op amp and can be used to amplify differential input signals to differential
output signals. A basic block diagram of the circuit is shown in Figure 74 (VOCM and PD inputs not shown). The
gain of the circuit is set by RF divided by RG.
RG
RF
VIN+
VOUTœ
Differential
Input
Differential
Output
VS+
+
THS4531A
œ
VSœ
RF
RG
VINœ
VOUT+
Figure 74. Differential Input to Differential Output Amplifier
Single-Ended Input to Differential Output Amplifier
The THS4531A can also be used to amplify and convert single-ended input signals to differential output signals.
A basic block diagram of the circuit is shown in Figure 75 (VOCM and PD inputs not shown). The gain of the
circuit is again set by RF divided by RG.
RG
RF
VIN+
VOUTœ
Single-Ended
Input
Differential
Output
VS+
+
THS4531A
œ
VSœ
RF
RG
VOUT+
Figure 75. Single-Ended Input to Differential Output Amplifier
Differential Input to Single-Ended Output Amplifier
Fully differential op amps like the THS4531A are not recommended for differential to single-ended conversion.
This application is best performed with an instrumentation amplifier or with a standard op amp configured as a
classic differential amplifier. See application section of the OPA835 data sheet (SLOS713).
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Input Common-Mode Voltage Range
The input common-model voltage of a fully differential op amp is the voltage at the “+ and –“ input pins of the op
amp.
It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is
in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one
input pin will determine the input common-mode voltage of the op amp.
Treating the negative input as a summing node, the voltage is given by:
æ
ç
è
ö
÷
ø
æ
ö
÷
ø
RG
RF
V
´
+ V
´
ç
OUT+
IN-
RG + RF
RG + RF
è
(1)
To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+
.
As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input
common-mode voltage of the source.
Setting the Output Common-Mode Voltage
The output common-model voltage is set by the voltage at the VOCM pin and the internal circuit works to maintain
the output common-mode voltage as close as possible to this voltage. If left unconnected, the output common-
mode is set to mid-supply by internal circuitry, which may be over-driven from an external source. Figure 76 is
representative of the VOCM input. The internal VOCM circuit has about 24MHz of -3dB bandwidth, which is required
for best performance, but it is intended to be a DC bias input pin. Bypass capacitors are recommended on this
pin to reduce noise. The external current required to overdrive the internal resistor divider is given approximately
by the formula:
2VOCM - V - VS-
(
60kΩ
)
S+
IEXT
=
(2)
where VOCM is the voltage applied to the VOCM pin.
VS+
IEXT
Internal
60 kΩ
60 kΩ
VOCM Circuit
VOCM
VS–
Figure 76. Simplified VOCM Input Circuit
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Power Down
The power down pin is internally connected to a CMOS stage which must be driven to a minimum of 2.1V to
ensure proper high logic.
VS+
Internal
PD Circuit
PD
VSœ
Figure 77. Simplified Power Down Internal Circuit
If 1.8V logic is used to drive the pin, a shoot through current of up to 100µA may develop in the digital logic
causing the overall quiescent current to exceed the 2uA of maximum disabled quiescent current specified in the
electrical characteristics.
In order to properly interface to 1.8V logic with minimal increase in additional current draw, a logic-level translator
like the SN74AVC1T45 can be used.
Alternatively, the same function may be achieved using a diode and pull up resistor shown below.
3V
V
S+
1.8V
ꢀController
THS4531A
RPU
D
PD
Figure 78. THS4531A Power Down Interface to 1.8V Logic Microcontroller
The voltage seen at the power down pin will be a function of the supply voltage, input logic level, and diode drop.
As long as the diode is forward biased, the power down voltage will be determined by:
VPD = VL +Vf
(3)
Where VL is the logic level voltage and Vf is the forward voltage drop across the diode.
This means for 1.8V logic, the forward voltage of the diode should be greater than 0.3V but less than 0.7V in
order to keep the power down logic level above 2.1V and less than 0.7V respectively.
For example, if we select 1N914 as the diode with a forward voltage of approximately 0.4V, the translated logic
voltages will be 0.4V for disabled operation and 2.2V for enabled operation.
The additional current draw can be determined by:
VCC - (VL +Vf )
=
RPU
iPD
(4)
This equation shows that larger values of RPU result in a smaller additional current. A reasonable value of RPU
may be 500kΩ where we can expect to see an additional current draw of 5.2µA while the device is in operation
and 1.6µA when disabled.
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Single-Supply Operation
To facilitate testing with common lab equipment, the THS4531A EVM is built to allow for split-supply operation
and most of the data presented in this data sheet was taken with split-supply power inputs. But the device is
designed for use with single-supply power operation and can easily be used with single-supply power without
degrading the performance. The only requirement is to bias the device properly and the specifications in this data
sheet are given for single supply operation.
Low Power Applications and the Effects of Resistor Values on Bandwidth
The THS4531A is designed for the nominal value of RF to be 2 kΩ. This gives excellent distortion performance,
maximum bandwidth, best flatness, and best pulse response. It also loads the amplifier. For example; in gain of 1
with RF = RG = 2 kΩ, RG to ground, and VOUT+ = 4V, 1mA of current will flow through the feedback path to
ground. In low power applications, it is desirable to reduce this current by increasing the gain setting resistors
values. Using larger value gain resistors has two primary side effects (other than lower power) due to their
interaction with the device and PCB parasitic capacitance:
1. Lowers the bandwidth.
2. Lowers the phase margin
(a) This will cause peaking in the frequency response.
(b) And will cause over shoot and ringing in the pulse response.
Figure 79 shows the small signal frequency response for gain of 1 with RF and RG equal to 2kΩ, 10kΩ, and
100kΩ. The test was done with RL = 2kΩ. Due to loading effects of RL, lower values may reduce the peaking, but
higher values will not have a significant effect.
As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in
frequency response is synonymous with overshoot and ringing in pulse response).
9
VOUT = 100 mVPP
6
3
0
−3
−6
−9
−12
RF = 2 kΩ
RF = 10 kΩ
RF = 100 kΩ
−15
−18
−21
100k
1M
10M
100M
Frequency (Hz)
G067
Figure 79. THS4531A Frequency Response with Various Gain Setting Resistor Values
Driving Capacitive Loads
The THS4531A is designed for a nominal capacitive load of 2pF (differentially). When driving capacitive loads
greater than this, it is recommended to use small resisters (RO) in series with the output as close to the device as
possible. Without RO, capacitance on the output will interact with the output impedance of the amplifier causing
phase shift in the loop gain of the amplifier that will reduce the phase margin resulting in:
1. Peaking in the frequency response.
2. Overshoot, undershoot, and ringing in the time domain response with a pulse or square-wave signal.
3. May lead to instability or oscillation.
Inserting RO will compensate the phase shift and restore the phase margin, but it will also limit bandwidth. The
circuit shown in Figure 69 is used to test for best RO versus capacitive loads, CL, with a capacitance placed
differential across the VOUT+ and VOUT-along with 2kΩ load resistor, and the output is measure with a differential
probe. Figure 80 shows the optimum values of RO versus capacitive loads, CL, and Figure 81 shows the
frequency response with various values. Performance is the same on both 2.7V and 5V supply.
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200
100
10
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
1
1
10
100
CLOAD (pF)
1k 2k
G068
Figure 80. Recommended Series Output Resistor vs Capacitive Load for Flat Frequency Response
3
0
VS = 2.7 V
G = 1 V/V
−3
RF = 2 kΩ
RL = 2 kΩ
−6
VOUT = 100 mVpp
−9
CL = 0 pF,RO = 0 Ω
−12
CL = 15 pF,RO = 200 Ω
CL = 39 pF,RO = 100 Ω
CL = 120 pF,RO = 50 Ω
−15
CL = 470 pF,RO = 20 Ω
CL = 1200 pF,RO = 12 Ω
−18
−21
100k
1M
10M
100M
Frequency (Hz)
G069
Figure 81. Frequency Response for Various RO and CL Values
Audio Performance
The THS4531A provides excellent audio performance with very low quiescent power. To show performance in
the audio band, the device was tested with an audio analyzer. THD+N and FFT tests were run at 1Vrms output
voltage. Performance is the same on both 2.7V and 5V supply. Figure 82 is the test circuit used, and Figure 83
and Figure 84 show performance of the analyzer. In the FFT plot the harmonic spurs are at the testing limit of the
analyzer, which means the THS4531A is actually much better than can be directly measured. Because the
THS4531A distortion performance cannot be directly measured in the audio band it is estimated from
measurement in high noise gain configuration correlated with simulation.
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RG
RF
10
VINœ
VOUTœ
100 pF
VS+
+
VOCM
From Analyzer
THS4531A
To Analyzer
œ
0.22 ꢀF
RG
10
VIN+
VOUT+
RF
100 pF
Figure 82. THS4531A Audio Analyzer Test Circuit
−95
VS = 5 V
G = 1 V/V
VOUT = 1 VRMS
No Weighting
A−Weighting
−97
−99
RF = 2 kΩ
RL = 600 Ω
−101
−103
−105
−107
−109
−111
−113
−115
0
5k
10k
15k
20k
24k
Frequency (Hz)
G070
Figure 83. THD+N on Audio Analyzer, 10 Hz to 24 kHz
0
−10
−20
−30
−40
VS = 5 V
G = 1 V/V
VOUT = 1 VRMS
RF = 2 kΩ
RL = 600 Ω
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
0
5k
10k
15k
20k
24k
Frequency (Hz)
G071
Figure 84. 1kHz FFT Plot on Audio Analyzer
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Audio On/Off Pop Performance
The THS4531A is tested to show on and off pop performance by connecting a speaker between the differential
outputs and switching on and off the power supply, and also by using the power down function of the THS4531A.
Testing was done with and without tones. During these tests no audible pop could be heard.
With no input tone, Figure 85 shows the voltage waveforms when switching power on to the THS4531A and
Figure 86 shows voltage waveforms when turning power off. The transients during power on and off show no
audible pop should be heard.
5
4
3
2
1
0
2.5
2
VS = 5 V
1.5
1
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
Power Supply
0.5
0
VOUT
VOUT
+
−
0
50m
100m
150m
200m
Time (s)
G072
Figure 85. Power Supply Turn On Pop Performance
5
4
3
2
1
0
2.5
2
Power Supply
VOUT
VOUT
+
−
VS = 5 V
1.5
1
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
0.5
0
0
50m
100m
150m
200m
Time (s)
G073
Figure 86. Power Supply Turn Off Pop Performance
With no input tone, Figure 87 shows the voltage waveforms using the PD pin to enable and disable the
THS4531A. The transients during power on and off show no audible pop should be heard.
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5
4
3
2
1
0
2.5
Power Down
VOUT
+
VOUT
−
2
VS = 5 V
1.5
1
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
0.5
0
0
50m
100m
150m
200m
Time (s)
G074
Figure 87. PD Enable Pop Performance
AUDIO ADC DRIVER PERFORMANCE: THS4531A AND PCM4204 COMBINED PERFORMANCE
To show achievable performance with a high performance audio ADC, the THS4531A is tested as the drive
amplifier for the PCM4204. The PCM4204 is a high-performance, four-channel analog-to-digital (A/D) converter
designed for professional and broadcast audio applications. The PCM4204 architecture utilizes a 1-bit delta-
sigma modulator per channel incorporating an advanced dither scheme for improved dynamic performance, and
supports PCM output data. The PCM4204 provides flexible serial port interface and many other advanced
features. Please refer to its data sheet for more information.
The PCM4204 EVM is used to test the audio performance of the THS4531A as a drive amplifier. The standard
PCM4204 EVM is provided with 4x OPA1632 fully differential amplifiers, which use the same pin out as the
THS4531A. For testing, one of these amplifiers is replaced with a THS4531A device in same package (MSOP),
gain changed to 1V/V, and power supply changed to single supply +5V. Figure 88 shows the circuit. With single
supply +5V supply the output common-mode of the THS4531A defaults to +2.5V as required at the input of the
PCM4204. So the resistor connecting the VOCM input of the THS4531A to the input common-mode drive from the
PCM4204 is optional and no performance change was noted with it connected or removed. The EVM power
connections were modified by connecting positive supply inputs, +15V, +5VA and +5VD, to a +5V external power
supply (EXT +3.3 was not used) and connecting -15V and all ground inputs to ground on the external power
supply so only one external +5V supply was needed to power all devices on the EVM.
2 kꢀ
1 nF
2 kꢀ
40.2 ꢀ
VINœ
100 pF
2.7 nF
5V
VOUTœ
To Analyzer
+
VOCM
From Analyzer
THS4531A
VOUT+
PCM4204
œ
0.22 ꢁF
1 nF
2 kꢀ
40.2 ꢀ
VIN+
100 pF
2 kꢀ
Figure 88. THS4531A and PCM4204 Test Circuit
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An audio analyzer is used to provide an analog audio input to the EVM and the PCM formatted digital output is
read by the digital input on the analyzer. Data was taken at fS = 96kHz, and audio output uses PCM format.
Other data rates and formats are expected to show similar performance in line with that shown in the data sheet.
Figure 89 shows the THD+N vs Frequency with no weighting and Figure 90 shows an FFT with 1kHz input tone.
Input signal to the PCM4204 for these tests is -0.5dBFS. Table 4 summarizes results of testing using the
THS4531A + PCM4204 versus typical Data Sheet performance, and show it make an excellent drive amplifier for
this ADC.
−95
−97
−99
−101
−103
−105
−107
−109
−111
−113
−115
20
100
1k
10k 20k
Frequency (Hz)
G075
Figure 89. THS4531A + PCM4204 THD+N vs Frequency with No Weighting
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
20
100
1k
10k
24k
Frequency (Hz)
G076
Figure 90. THS4531A + PCM4204 1kHz FFT
Table 4. 1kHz AC Analysis: Test Circuit versus PCM4204 Data Sheet Typical Specifications (fS = 96kSPS)
CONFIGURATION
THS4531A + PCM4204
PCM4204 Data Sheet (typ)
TONE
1kHz
1kHz
THD + N
-106 dB
-103 dB
SAR ADC PERFORMANCE
THS4531A and ADS8321 Combined Performance
To show achievable performance with a high performance SAR ADC, the THS4531A is tested as the drive
amplifier for the ADS8321. The ADS8321 is a 16-bit, SAR ADC that offers excellent AC and DC performance,
with ultra-low power and small size. The circuit shown in Figure 91 is used to test the performance. Data was
taken using the ADS8321 at 100kSPS with input frequency of 10 kHz and signal levels 0.5 dB below full scale.
The FFT plot of the spectral performance is in Figure 92. A summary of the FFT analysis results are in Table 5
along with ADS8321 typical data sheet performance at fS = 100kSPS. Please refer to its data sheet for more
information.
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The standard ADS8321 EVM and THS4531A EVM are modified to implement the schematic in Figure 91 and
used to test the performance of the THS4531A as a drive amplifier. With single supply +5V supply the output
common-mode of the THS4531A defaults to +2.5V as required at the input of the ADS8321 so the VOCM input of
the THS4531A simply bypassed to GND with 0.22µF capacitor. The summary of results of the FFT analysis
versus typical data sheet performance shown in Table 5 show the THS4531A will make an excellent drive
amplifier for this ADC.
2 kꢀ
2 kꢀ
121 ꢀ
No Input
VINœ
100 pF
220 pF
2.2 nF
5V
49.9 ꢀ
VOUTœ
To Data
Analysis
+
VOCM
THS4531A
VOUT+
ADS8321
œ
0.22 ꢁF
2 kꢀ
Single-Ended
Signal from
Generator and
10 kHz BPF
2 kꢀ
121 ꢀ
VIN+
100 pF
220 pF
49.9 ꢀ
Figure 91. THS4531A and ADS8321 Test Circuit
0
−10
−20
−30
−40
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = −0.5 dBFS
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
0
10k
20k
30k
40k
50k
Frequency (Hz)
G078
Figure 92. THS4531A + ADS8321 1kHz FFT
Table 5. 10kHz FFT Analysis Summary
CONFIGURATION
THS4531A + ADS8321
ADS8321 Data Sheet (typ)
TONE
10kHz
10kHz
SIGNAL
-0.5 dBFS
-0.5 dBFS
SNR
THD
SINAD
87 dBc
84 dBc
SFDR
87 dBc
87 dBc
-96 dBc
-86 dBc
100 dBc
86 dBc
THS4531A and ADS7945 Combined Performance
To show achievable performance with a high performance SAR ADC, the THS4531A is tested as the drive
amplifier for the ADS7945. The ADS7945 is a 14-bit, SAR ADC that offers excellent AC and DC performance,
with low power and small size. The circuit shown in Figure 93 is used to test the performance. Data was taken
using the ADS7945 at 2MSPS with input frequency of 10 kHz and signal level 0.5 dB below full scale. The FFT
plot of the spectral performance is in Figure 94. A summary of the FFT analysis results are in Table 6 along with
ADS7945 typical data sheet performance at fS = 2MSPS. Please refer to its data sheet for more information.
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The standard ADS7945 EVM and THS4531A EVM are modified to implement the schematic in Figure 93 and
used to test the performance of the THS4531A as a drive amplifier. With single supply +5V supply the output
common-mode of the THS4531A defaults to +2.5V as required at the input of the ADS7945 so the VOCM input of
the THS4531A simply bypassed to GND with 0.22µF capacitor. The summary of results of the FFT analysis
versus typical data sheet performance shown in Table 6 show the THS4531A will make an excellent drive
amplifier for this ADC.
2 kꢀ
2 kꢀ
40.2 ꢀ
VINœ
100 pF
5 V
VOUTœ
To Data
Analysis
Differential
Signal from
Generator and
10 kHz BPF
+
VOCM
THS4531A 1 nF
ADS7945
œ
0.22 ꢁF
2 kꢀ
VOUT+
2 kꢀ
40.2 ꢀ
VIN+
100 pF
Figure 93. THS4531A and ADS7945 Test Circuit
0
−10
−20
−30
−40
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = −0.5 dBFS
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
1k
10k
100k
Frequency (Hz)
1M
G077
Figure 94. THS4531A and ADS7945 Test Circuit
Table 6. 10kHz FFT Analysis Summary
CONFIGURATION
TONE
10kHz
10kHz
SIGNAL
-0.5 dBFS
-0.5 dBFS
SNR
THD
SFDR
96 dBc
94 dBc
THS4531A + ADS7945
83 dBc
84 dBc
-93 dBc
-92 dBc
ADS7945 Data Sheet (typ)
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EVM AND LAYOUT RECOMMENDATIONS
The THS4531A EVM (SLOU356) should be used as a reference when designing the circuit board. It is
recommended to follow the EVM layout of the external components near to the amplifier, ground plane
construction, and power routing as closely as possible. General guidelines are:
1. Signal routing should be direct and as short as possible into and out of the op amp.
2. The feedback path should be short and direct avoiding vias if possible.
3. Ground or power planes should be removed from directly under the amplifier’s input and output pins.
4. A series output resistor is recommended to be placed as near to the output pin as possible. See Figure 80
“Recommended Series Output Resistor vs. Capacitive Load” for recommended values given expected
capacitive load of design.
5. A 2.2µF power supply decoupling capacitor should be placed within 2 inches of the device and can be
shared with other op amps. For split supply, a capacitor is required for both supplies.
6. A 0.1µF power supply decoupling capacitor should be placed as near to the power supply pins as possible.
Preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
7. The PD pin uses TTL logic levels referenced to the negative supply voltage (VS-). When not used it should
tied to the positive supply to enable the amplifier. When used, it must be actively driven high or low and
should not be left in an indeterminate logic state. A bypass capacitor is not required, but can be used for
robustness in noisy environments.
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REVISION HISTORY
Changes from Original (December 2012) to Revision A
Page
•
Changed graph title from "VOS OVER TEMPERATURE" to "SMALL-SIGNAL FREQUENCY RESPONSE" ..................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2013
PACKAGING INFORMATION
Orderable Device
THS4531AID
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125 T4531A
-40 to 125
THS4531AIDGK
THS4531AIDGKR
THS4531AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
DGK
D
80
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
8
2500
2500
3000
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125 T4531A
-40 to 125 531A
-40 to 125 531A
THS4531AIRUNR
THS4531AIRUNT
QFN
RUN
RUN
10
10
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4531AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
THS4531AIDR
D
8
2500
Pack Materials-Page 2
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