THS4567 [TI]
具有 VICM 和 VOCM 控制的 220MHz CMOS 输入全差分放大器;
| 型号： | THS4567 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 VICM 和 VOCM 控制的 220MHz CMOS 输入全差分放大器 放大器 信息通信管理 |
| 文件： | 总33页 (文件大小：1629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4567
SBOSA51 – DECEMBER 2020
THS4567 220 MHz, High Input Impedance, Fully Differential Amplifier with
Independent Input and Output Common-Mode Control
1 Features
3 Description
•
•
•
•
•
•
•
•
•
Gain Bandwidth Product (GBWP): 220 MHz
Slew Rate: 500 V/µs
Bandwidth: 42 MHz (G = 10 V/V)
Voltage Noise: 4.2 nV/√ Hz
Supply Current (IQ): 2 mA
IQ : 28 µA (Shutdown)
The THS4567 device is a novel fully-differential
amplifier (FDA) that includes independent input
common-mode (VICM) and output-common mode
(VOCM) control. Standard FDAs only possess output
common-mode control. The THS4567 is
a
decompensated amplifier with a minimum stable gain
of 10 V/V.
Rail-to-Rail Output (RRO)
The THS4567 operates as
a
fully differential
High Impedance CMOS Inputs
Independent Input and Output Common-Mode
Control
transimpedance amplifier (TIA) and analog-to-digital
converter (ADC) driver in a single integrated stage.
The VICM loop decouples the reverse bias across the
photodiode(PD) from the amplifiers input and output
swing compliance ranges thereby allowing the
designer to maximize the PD reverse bias and
minimize the PD capacitance. The VICM loop can be
disabled which then allows the THS4567 to operate
as a standard FDA.
•
Disable Input Common-Mode Loop to Use as a
Standard Fully Differential Amplifier (FDA)
Single-Supply Range: 3.3 V to 5.5 V
Split-Supply Range: ±1.65 V to ±2.75 V
Operating Temperature Range: -40°C to 125°C
•
•
•
2 Applications
•
•
•
•
•
Absolute Optical Encoder
AC Drive Position Feedback
Linear Motor Position Sensor
Clinical Pulse Oximeter
The VOCM loop sets the differential output common-
mode voltage and is typically set at the subsequent
ADC stage common-mode reference voltage.
Device Information (1)
Optical Coherence Tomography
PART NUMBER
PACKAGE
BODY SIZE (NOM)
THS4567
WQFN (10)
2.00 mm × 2.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
3
VBIAS
0.8 pF
0
1 Mꢀ
3.3 ꢀ
5 V
-3
0.1 …F
+
VOCM = 2.5 V
œ
-6
VICM = 1.5 V
1 nF
ADC
+
œ
0.1 …F
0.1 …F
G = 7 V/V
G = 10 V/V
-9
G = 40 V/V
G = 100 V/V
-12
3.3 ꢀ
1 Mꢀ
0.8 pF
1M
10M
Frequency (Hz)
100M
D201
VBIAS
Small-Signal Frequency Response vs Gain
Single-Stage Differential-Input to Differential-
Output, TIA and ADC Driver for Optical Encoders
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4567
SBOSA51 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics: Differential TIA Mode,
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 20
8.3 Differential TIA with 0-V Biased Photodiode.............24
8.4 Differential AC Coupled TIA......................................25
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Documentation Support.......................................... 27
11.2 Receiving Notification of Documentation Updates..27
11.3 Support Resources................................................. 27
11.4 Trademarks............................................................. 27
11.5 Electrostatic Discharge Caution..............................27
11.6 Glossary..................................................................27
12 Mechanical, Packaging, and Orderable
ICM loop enabled ......................................................... 5
6.6 Electrical Characteristics: FDA operation, ICM
loop disabled ................................................................ 6
6.7 Typical Characteristics: (VS+) – (VS–) = 5 V................ 9
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2020
*
Initial Release
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5 Pin Configuration and Functions
VS+
10
9
1
2
3
4
OUTœ
ICM_EN
AMP_EN
IN+
OUT+
VICM
VOCM
IN-
8
7
6
5
Not to scale
VSœ
Figure 5-1. RUN Package
10-Pin WQFN
Top View
Table 5-1. Pin Functions
NAME
PIN NO.
I/O
DESCRIPTION
AMP_EN
3
I
Amplifier enable. HIGH (Default) = normal operation; LOW = power-off mode.
Input common-mode loop enable. HIGH (Default) = ICM loop enabled (TIA mode); ICM loop
disabled (FDA mode).
ICM_EN
2
I
IN+
4
6
9
1
I
Noninverting (positive) amplifier input (VIN+ = voltage measured at pin 4).
Inverting (negative) amplifier input (VIN– = voltage measured at pin 6).
Noninverting (positive) amplifier output (VOUT+ = voltage measured at pin 9).
Inverting (negative) amplifier output (VOUT– = voltage measured at pin 1).
IN–
I
OUT+
OUT–
O
O
Input common-mode voltage input (VICM = voltage applied at pin 8, VICM = voltage
measured at pin 8).
VICM
8
7
I
I
Output common-mode voltage input (VOCM = voltage applied at pin 7, VOCM = average
output voltage).
VOCM
VS+
VS–
10
5
–
–
Positive power-supply input (VS+ = voltage applied at pin 10).
Negative power-supply input (VS– = voltage applied at pin 5).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.75
UNIT
V
VS
Total supply voltage (VS+ – VS-)
Input, output, enable and common-mode pin voltage range
Differential input pin voltage
Continuous input current
(VS–) – 0.5
(VS+) + 0.5
±1
V
V
IIN
±10
mA
mA
°C
°C
°C
IOUT
TJ
Continuous output current(2)
±20
Junction temperature
150
TA
Operating free-air temperature
Storage temperature
–40
–65
125
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Long-term continuous output current for electromigration limits.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
MIN
3.3
NOM
MAX
5.5
UNIT
V
VS
TA
Total supply voltage
5
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
THS4567
THERMAL METRIC(1)
RUN (WQFN)
10 PINS
118
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
70.6
57.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.7
ΨJB
57.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: Differential TIA Mode, ICM loop enabled
VS+ = 2.5 V, VS– = –2.5 V, VOCM = Open, VICM = Open, RF = 1 MΩ, CF = 0.4 pF, CIN = 10 pF (on each input pin), AMP_EN
= 2.5 V, ICM loop enabled (ICM_EN = 2.5 V) and TA = 25℃. (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (ICM LOOP)
Differential-transimpedance gain
bandwidth product
GBWP
VOUT = 100 mVPP
220
MHz
MHz
Input Common-Mode control loop
small-signal bandwidth
VOUT = 100 mVPP
5
0.02
0.35
f = 100 kHz, ICM loop disabled
f= 100 kHz, output current of ICM loop,
ICM_CTL (3) < 750 nA
f= 100 kHz, Output current of ICM
loop, ICM_CTL (3) < 2.8 µA
0.5
0.65
1.1
iN
Input differential current noise
pA/√Hz
f= 100 kHz, Output current of ICM
loop, ICM_CTL (3) < 5.5 µA
f= 100 kHz, Output current of ICM
loop, ICM_CTL (3) < 17 µA
f= 100 kHz, Output current of ICM
loop, ICM_CTL (3) < 55 µA
1.9
DC PERFORMANCE (ICM LOOP)
VICM pin open (voltage measured at
pin 8)
VICM(1)
VICM pin default voltage above VS–
1.4
1.4
1.55
1.75
1.75
V
Default input common-mode voltage
above VS–
(1)
VICM
VICM pin open, VICM = (VIN+ + VIN–)/2
TA = –40°C to +125°C, VICM pin open
ICM_CTL variation = 5 µA to 20 µA
1.55
160
2.8
V
ΔVICM/ΔTA
Input common-mode voltage drift
µV/°C
ΔVICM
/
Input common-mode voltage vs.
ICM_CTL current (2) (3)
2
3.6 mV/µA
µV/°C
ΔICM_CTL
TA = –40°C to +125°C, VICM pin driven
to midsupply
ΔVICM/ΔTA
Input common-mode voltage offset drift
22
VICM pin driven to midsupply,
VIN_OS
Input common-mode offset error
VICM pin DC input resistance
VICM input high
–25
±2.5
200
25
mV
kΩ
V
ICM_CTL = 0(2), VIN_OS = (VICM – VICM)
VICM pin driven to midsupply
≤ ±20-mV shift from midsupply offset,
ICM_CTL ≤ 100 µA
VS+ – 1.5 VS+ – 1.3
≤ ±20-mV shift from midsupply offset,
ICM_CTL ≤ 100 µA
VICM input low
VS– + 0.8 VS– + 1
0.5%
V
Input common-mode control current
offset mismatch between inputs
ICM_OS = ΔI(CM_CTL, IN+/IN–)/Average
ICM_CTL, ICM_CTL = 10 µA
ICM_OS
(1) VICM refers to the common-mode or average voltage at the FDA inputs (IN+ and IN–). When the input common-mode (ICM) control
function is enabled (ICM_EN = HIGH), the device generates matched source/sink control currents to drive the input pins towards the
VICM pin reference voltage. Therefore VICM represents the voltage at pin 8, while VICM represents the average input voltage.
(2) ICM_CTL refers to the magnitude of the matched source/sink control currents generated by the ICM loop at the device IIN+ and IIN– pins.
(3) A positive ICM_CTL current is defined as a sinking (pull-down) current, generated by the ICM control loop to balance the total currents
(external common-mode + feedback) that flow into the FDA input pins.
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6.6 Electrical Characteristics: FDA operation, ICM loop disabled
VS+ = 2.5 V, VS– = –2.5 V, VOCM = Open, VICM = Open, RF = 5 kΩ, Gain = 10 V/V, ICM loop disabled (ICM_EN = –2.5 V),
RL = 1 kΩ and TA = 25°C. (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
GBWP
Small-signal bandwidth
Large-signal bandwidth
Gain bandwidth product
Slew rate
VOUT (2) = 100 mVPP
43
28
MHz
MHz
MHz
V/µs
ns
VOUT (2) = 8 VPP
220
500
8
VOUT = 8V Step, 20% ↔ 80%
VOUT = 100 mVPP, 10% ↔ 90%
tR, tF
Rise and fall time
0.1% settling time
0.001% settling time
65
VOUT = 8V Step
ns
175
–115
–105
–118
–108
4.2
f= 100 kHz, VOUT = 2 VPP
f= 100 kHz, VOUT = 8 VPP
f= 100 kHz, VOUT = 2 VPP
f= 100 kHz, VOUT = 8 VPP
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
eN
iN
Input differential voltage noise
Input current noise, each input
nV/√Hz
fA/√Hz
10
f = 100 kHz
Closed-loop differential output
impedance
ZOUT
0.2
Ω
DC PERFORMANCE
AOL
VOS
Open-loop gain
Input-referred offset voltage
104
–10
117
0.2
1
dB
mV
VOS = (VIN+ – VIN–
)
10
ΔVOS/ΔTA Input-referred offset voltage drift
TA = –40°C to +125°C
Noninverting and inverting inputs
(IBN – IBI)
µV/°C
pA
IBN, IBI
IOS
Input bias current
Input offset current
20
±20
pA
INPUT
Differential input resistance
Effective shunt resistance between inputs
1
1
GΩ
Effective shunt resistance to AC GND at
each input
Common-mode input resistance
Effective shunt capacitance between
inputs
Differential input capacitance
Common-mode input capacitance
Common-mode rejection ratio
0.6
0.9
pF
dB
V
Effective shunt capacitance to AC GND at
each input
CMRR = (ΔVCM/ΔVOS). Inputs shifted
±500 mV around midsupply
CMRR
CMIR+
70
80
VS+
–
TA = 25°C, AOL > 90 dB
VS+ – 1.6
1.85
Common-mode input high
Common-mode input low
VS+
–
TA = –40°C to +125°C, AOL > 90 dB
1.65
TA = 25°C, AOL > 90 dB
VS– + 0.2 VS– – 0.2
VS– – 0.1
CMIR–
V
TA = –40°C to +125°C, AOL > 90 dB
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6.6 Electrical Characteristics: FDA operation, ICM loop disabled (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = Open, VICM = Open, RF = 5 kΩ, Gain = 10 V/V, ICM loop disabled (ICM_EN = –2.5 V),
RL = 1 kΩ and TA = 25°C. (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL= 20 kΩ, TA = 25°C, input driven
to ±VS/Gain
VS –
0.125
VS
0.075
–
Output voltage range to either supply
Output voltage range to either supply
Output voltage range to either supply
Output voltage range to either supply
Output voltage range to either supply
V
V
V
V
V
RL= 20 kΩ, TA = 25°C,
VOS shift < 150 µV from default offset
VS –
0.175
VS
0.125
–
RL= 20 kΩ, TA = –40°C to +125°C,
VOS shift < 150 µV from default offset
VS
0.175
–
RL= 1 kΩ, TA = 25°C,
VOS shift < 150 µV from default offset
VS – 0.25 VS – 0.2
VS – 0.25
RL= 1 kΩ, TA = –40°C to +125°C,
VOS shift < 150 µV from default offset
OUTPUT COMMON-MODE (VOCM) CONTROL
VOCM(3) pin driven ± 0.5 mV around
midsupply
Output common-mode loop SSBW
5
4.5
80
MHz
MHz
dB
VOCM pin driven ± 0.5 V around
midsupply
Output common-mode loop LSBW
ΔVOUT
DC output balance (2) (3)
/ΔVOCM
VOCM = ±1 V
ΔVOCM
Output common-mode gain (3)
/ΔVOCM
VOCM pin driven ±1 V around midsupply
VOCM pin driven to midsupply
0.99
1
100
1.01
V/V
nA
Input DC bias current of VOCM pin
Input impedance of VOCM pin
VOCM pin driven ± 0.5 mV around
midsupply
200||1
kΩ || pF
VOCM input pin voltage offset from
mid-supply (4)
VOCM pin open
–8
–2
±2.5
–22
4
mV
mV
Output common-mode voltage offset
from midsupply
VOCM_OS
VOCM pin open
–30
30
ΔVOCM_OS Output common-mode voltage offset
TA = –40°C to +125°C, VOCM pin open
VOCM pin driven to midsupply
µV/°C
mV
/TA
drift
Output common-mode voltage offset
from midsupply
VOCM_OS
–25
±1.5
25
ΔVOCM_OS Output common-mode voltage offset
TA = –40°C to +125°C, VOCM pin driven
to midsupply
–18
0.9
1
µV/°C
/TA
drift
VOCM input headroom to VS+
≤ ±10 mV shift from VOCM_OS
1
1
V
V
V
V
TA = –40°C to +125°C, ≤ ±10 mV shift
from VOCM_OS
VOCM input headroom to VS+
VOCM input headroom from VS–
VOCM input headroom from VS–
≤ ±10 mV shift from VOCM_OS
0.9
1
TA = –40°C to +125°C, ≤ ±10 mV shift
from VOCM_OS
ΔVOCM_OS
/ΔVS+
Positive power-supply rejection ratio
Negative power-supply rejection ratio
76
80
VOCM = 0 V (driven)
dB
ΔVOCM_OS
/ΔVS–
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6.6 Electrical Characteristics: FDA operation, ICM loop disabled (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = Open, VICM = Open, RF = 5 kΩ, Gain = 10 V/V, ICM loop disabled (ICM_EN = –2.5 V),
RL = 1 kΩ and TA = 25°C. (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
IQ
Quiescent current
TA = 25°C
1.4
1.5
10
70
90
1.9
2
2.5
2.7
40
mA
mA
µA
dB
dB
IQ
Quiescent current
VICM loop enabled
AMP_EN = VS–
VOCM is driven
VOCM is driven
IQ
Disabled quiescent current
Power-supply rejection ratio to VS+
Power-supply rejection ratio to VS–
28
94
110
+PSRR
–PSRR
POWER DOWN
Enable voltage (Amplifier ON above
this voltage)
VIH
VIL
IIH
VS+ – 0.7 VS+ – 0.5
AMP_EN and ICM_EN
V
Disable voltage threshold (Amplifier
OFF below this voltage)
VS+ – 2 VS+ – 1.8
AMP_EN and ICM_EN driven to (VS+) –
0.25 V
Control pin HIGH Input bias current
3.5
7
µA
External pull-down current required to
switch ON→OFF (1)
175
µA
µA
µs
µs
IIL
Control pin LOW Input bias current
Turn-ON time delay (Main amplifier)
Turn-OFF time delay (Main amplifier)
AMP_EN and ICM_EN driven to VS–
–5
–1.1
1.5
Time to VOUT stabilized within 1% of the
final value
tAMP_ON
tAMP_OFF
Time to supply current ≤ 100 μA
0.9
(1) Leaving the AMP_EN pin floating is not recommended. When using a pull-up resistor ensure that the necessary bias current can be
supplied.
(2) VOUT is the differential output voltage, (VOUT– – VOUT+).
(3) VOCM refers to the voltage measured at pin 7. VOCM = [(VOUT+ + VOUT–)/2] refers to the average output voltage.
(4) The offset between the voltage measured at the VOCM pin and the midsupply voltage.
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
3
3
0
0
-3
-3
-6
-6
VOUT = 100 mVPP
VOUT = 1 VPP
VOUT = 5 VPP
VOUT = 8 VPP
G = 7 V/V
-9
-9
G = 10 V/V
G = 40 V/V
G = 100 V/V
-12
-12
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D200
D201
VOUT = 100 mVPP
Figure 6-2. Frequency Response vs VOUT
Figure 6-1. Small-Signal Frequency Response vs Gain
3
1
0.5
0
0
-3
-6
-0.5
-1
-1.5
-2
CL = 10 pF, RISO = 0 W
CL = 47 pF, RISO = 13 W
-9
CL = 100 pF, RISO = 13 W
-2.5
-3
CL = 470 pF, RISO = 8 W
CL = 1 nF, RISO = 5.6 W
-12
1k
10k
100k
Frequency (Hz)
1M
10M
1M
10M
Frequency (Hz)
100M
D206
D205
VOUT = 8 VPP
Figure 6-4. Large-Signal Frequency Response Flatness
Figure 6-3. Small-Signal Frequency Response vs CL
1000
10
Differential Noise
Common-mode Noise
100
10
1
1
0.1
0.1
100
1k
10k 100k
Frequency (Hz)
1M
10M
1
10
100
D207
Input Common-Mode Current (Each Input) (mA)
D220
f = 100 kHz, ICM loop enabled
Figure 6-5. Input Referred Voltage Noise vs Frequency
Figure 6-6. Input Referred Current Noise vs ICM_CTL
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
-60
-70
-50
-60
HD2, VOUT = 2 VPP
HD3, VOUT = 2 VPP
HD2, VOUT = 8 VPP
HD3, VOUT = 8 VPP
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-80
-70
-90
-80
-100
-110
-120
-130
-140
-90
-100
-110
-120
-130
100
1k
10k
Frequency (Hz)
100k
1M
1
2
3
4
5
6
Output Voltage (VPP
7
8
9
)
D208
D209
Figure 6-7. Harmonic Distortion vs Frequency
Figure 6-8. Harmonic Distortion vs VOUT
-20
-30
-50
-60
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-40
-70
-50
-60
-80
-70
-90
-80
-100
-110
-120
-130
-90
-100
-110
-120
-130
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
100
1k
2k
-1.5
-1
-0.5
0
0.5
Output Common-Mode Voltage (V)
1
1.5
Load Resistance (W)
D210
D211
VOUT = 8 VPP
VOUT = 8 VPP
Figure 6-9. Harmonic Distortion vs RL
Figure 6-10. Harmonic Distortion vs VOCM
-30
-40
-40
-50
-60
-70
-80
-90
-50
-60
-70
-80
HD2, ICM_CTL = 5 mA
-90
HD3, ICM_CTL = 5 mA
HD2, ICM_CTL = 25 mA
HD3, ICM_CTL = 25 mA
HD2, ICM_CTL = 100 mA
HD3, ICM_CTL = 100 mA
-100
-110
-120
IMD3
IMD2
100k
1M
Frequency (Hz)
10M
1
10
Center Frequency (MHz)
D212
D224
VOUT = 8 VPP; Differential input to differential output; ICM Loop
Enabled
VOUT = 2 VPP (each tone), Tone separation from center
frequency = 100 kHz
Figure 6-11. Harmonic Distortion vs ICM_CTL
Figure 6-12. Intermodulation Distortion vs Frequency
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
60
5
4
Input
Output
Input
Output
40
3
2
20
1
0
0
-1
-2
-3
-4
-5
-20
-40
-60
Time (100 ns/div.)
Time (100 ns/div.)
D213
D214
tR/tF = 8 ns
Slew rate (rising and falling) = 500 V/µs
Figure 6-13. Small-Signal Transient Response
Figure 6-14. Large-Signal Transient Response
120
100
80
30
100
10
1
AOL Magnitude (dB)
AOL Phase (è)
0
-30
60
-60
40
-90
20
-120
-150
-180
-210
0
-20
-40
0.1
10k
100k
1M
Frequency (Hz)
10M
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M
D215
D223
G = 1 V/V, VOUT = 2 VPP, with VOCM adjusted
Figure 6-16. Closed-Loop Output Impedance vs Frequency
Figure 6-15. Open-Loop Gain
120
110
100
90
140
120
100
80
80
70
60
60
50
PSRR+
PSRR-
40
40
1k
10k
100k 1M
Frequency (Hz)
10M
100M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D222
D221
Figure 6-18. Common-Mode Rejection Ratio vs Frequency
Figure 6-17. Power-Supply Rejection Ratio vs Frequency
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
10k
100k
1M
Frequency (Hz)
10M
10k
100k
1M
Frequency (Hz)
10M
D218
D219
VOCM pin driven with 100 mVPP signal. Average output
voltage measured.
VICM pin driven with 100 mVPP signal. Average input voltage
measured.
Figure 6-19. VOCM Loop Small-Signal Frequency Response
Figure 6-20. VICM Loop Small-Signal Frequency Response
2.2
2.3
2.2
2.1
2
2.1
2
1.9
1.8
1.7
1.6
1.9
1.8
1.7
1.6
3
3.5
4
Total Supply Voltage (V)
4.5
5
5.5
6
-50
-25
0
25
50
75
100
125
Ambient Temperature (èC)
D170
D171
3 Typical Units
Typical Unit
Figure 6-21. Quiescent Current vs Total Supply Voltage
Figure 6-22. Quiescent Current vs Ambient Temperature
150
125
100
75
25
20
15
10
5
50
25
0
-25
-50
-75
-100
0
-5
-50
-25
0
25
50
75
100
125
-2.5
-2
-1.5
-1
-0.5
0
0.5
Input Common-Mode Voltage (V)
1
1.5
Ambient Temperature (èC)
D102
D110
VOS normalized at 25°C
3 Typical Units
Figure 6-23. Offset Voltage vs Ambient Temperature
Figure 6-24. Input Bias Current vs Input Common-Mode Voltage
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
1.5
0.5
0.25
0
1
0.5
0
-0.5
-1
-0.25
TA = -40èC
TA = 25èC
TA = 125èC
-1.5
-0.5
-2.5
-2
-1.5
Input Common-Mode Voltage (V)
-1
-0.5
0
0.5
1
1.5
-2.5
-2
-1.5
Input Common-Mode Voltage (V)
-1
-0.5
0
0.5
1
1.5
D103
D104
3 Typical Units
3 Typical Units
Figure 6-25. Offset Voltage vs Input Common-Mode Voltage
Figure 6-26. Offset Voltage vs Input Common-Mode Voltage vs
Ambient Temperature
2
1.5
1
2
TA = -40èC
TA = 25èC
TA = 125èC
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-5
-4
-3
-2
Differential Output Voltage (V)
-1
0
1
2
3
4
5
-5
-4
-3
-2
Differential Output Voltage (V)
-1
0
1
2
3
4
5
D107
D108
3 Typical Units, RL = 20 kΩ
Typical Unit, RL = 20 kΩ
Figure 6-27. Offset Voltage vs Differential Output Voltage
Figure 6-28. Offset Voltage vs Differential Output Voltage vs
Ambient Temperature
2
1.5
1
2
TA = -40èC
TA = 25èC
TA = 125èC
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-5
-4
-3
-2
Differential Output Voltage (V)
-1
0
1
2
3
4
5
-5
-4
-3
-2
Differential Output Voltage (V)
-1
0
1
2
3
4
5
D111
D112
3 Typical Units, RL = 1 kΩ
Typical Unit, RL = 1 kΩ
Figure 6-29. Offset Voltage vs Differential Output Voltage
Figure 6-30. Offset Voltage vs Differential Output Voltage vs
Ambient Temperature
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
ê5
ê4.5
ê4
ê5
ê4.5
ê4
ê3.5
ê3
ê3.5
ê3
ê2.5
ê2
ê2.5
ê2
ê1.5
ê1
ê1.5
ê1
TA = -40èC
TA = 25èC
TA = 125èC
ê0.5
0
ê0.5
0
0
10
20 30
Differential Output Current (mA)
40
50
0
10
20
30
Differential Output Current (mA)
40
50
60
D120
D121
3 Typical Units
Typical Unit
Figure 6-31. Differential Output Voltage vs Load Current
Figure 6-32. Differential Output Voltage vs Load Current vs
Ambient Temperature
-0.75
-0.78
-0.81
-0.84
-0.87
-0.9
-0.75
-0.78
-0.81
-0.84
-0.87
-0.9
-0.93
-0.96
-0.99
TA = -40èC
-0.93
TA = 25èC
TA = 125èC
-0.96
-20
0
20
Input Common-Mode Current, ICM_CTL (mA)
40
60
80
100
-20
0
20
Input Common-Mode Current, ICM_CTL (mA)
40
60
80
100
D125
D126
VICM pin floating, 3 Typical Units
VICM pin floating, Typical Unit
Figure 6-33. Average input Voltage vs Input Common-Mode
Current
Figure 6-34. Average Input Voltage vs Input Common-Mode
Current vs Ambient Temperature
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-1
-1
ICM_CTL = 5 mA
TA = -40èC
-1.5
-1.5
ICM_CTL = 20 mA
TA = 25èC
ICM_CTL = 50 mA
TA = 125èC
-2
-2
-2
-1.5
-1
-0.5
VICM Set Voltage (V)
0
0.5
1
1.5
-2
-1.5
-1
-0.5
VICM Set Voltage (V)
0
0.5
1
1.5
D127
D128
Typical Unit
ICM_CTL = 20 µA, Typical Unit
Figure 6-35. Average Input Voltage vs VICM Set Voltage
Figure 6-36. Average Input Voltage vs VICM Set Voltage vs
Ambient Temperature
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6.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
VS+ = 2.5 V, VS– = –2.5 V, VOCM = open, VICM = open, RF = 5 kΩ, G = 10 V/V, ICM loop disabled, RL = 1 kΩ, single-ended
input, differential output, and input and output referenced to midsupply and TA ≈ 25°C, 1 (unless otherwise noted).
10
8
10
8
6
6
4
4
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
-50
-25
0
25
50
75
100
125
-2
-1.5
-1
-0.5
0
0.5
1
Output Common-Mode Voltage Set (V)
1.5
2
Ambient Temperature (èC)
D116
D115
VOCM = 0 V, 3 Typical Units
VOCM offset = (VOCM - VOCM), 3 Typical Units
Figure 6-38. Output Common-Mode Offset Voltage vs Ambient
Temperature
Figure 6-37. Output Common-Mode Offset Voltage vs Output
Common-Mode Set Voltage
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7 Detailed Description
7.1 Overview
The THS4567 device is a unique fully differential amplifier that features an input common-mode control loop in
addition to the output common-mode control loop typically found in all fully differential amplifiers. The THS4567
device has a high impedance CMOS input stage with a very low input bias current. The independent input and
output common-mode control along with the high impedance CMOS inputs make the THS4567 device an ideal
high-gain, low-noise, fully-differential transimpedance amplifier.
The input common-mode loop of the THS4567 device may be disabled by setting the ICM_EN pin below its
turnoff threshold voltage, turning it into a standard fully differential amplifier with output common-mode control
only. The THS4567 device operates over a wide power supply voltage range from 3.3 V to 5.5 V, which makes
this device an excellent choice for driving differential ADCs and buffering DAC outputs.
This device features a low-power mode with a unique active pullup resistor that improves EMI reliability of the
shutdown pin when left floating. The AMP_EN and ICM_EN pins draw very little bias current when the logic
voltage is outside the switching threshold region. Within the switching threshold region, the bias current
increases, especially close to the transition region. The increased bias current prevents the logic from
inadvertently switching in the presence of EMI.
7.2 Functional Block Diagram
VS+
OUT+
œ
INœ
6 kꢀ
6 kꢀ
High-AOL
Differential I/O
Amplifier
+
×1
œ
IN+
+
OUTœ
×1
VS+
VS+
œ
400 kꢀ
VICM
Error
8 ꢁA
Amplifier
+
œ
VICM
VOCM
Error
Amplifier
+
181 kꢀ
VOCM
VSœ
CMOS
Buffer
400 kꢀ
ICM_EN
AMP_EN
VSœ
CMOS
Buffer
Copyright © 2017, Texas Instruments Incorporated
VSœ
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7.3 Feature Description
The THS4567 architecture features three main building blocks:
1. A high open loop gain differential I/O main amplifier.
2. An output common-mode control error amplifier that sets the common-mode of the differential outputs of the
main amplifier.
3. An input common-mode control error amplifier that sets the common-mode of the differential inputs of the
main amplifier, independent of the output common-mode.
7.3.1 Main Amplifier
The main differential I/O amplifier has a wide gain bandwidth product of 220 MHz and is stable in gain
configurations > 10 V/V. Figure 6-15 shows the open-loop response of the main amplifier. The main amplifier has
a high-impedance CMOS input stage with very low input bias currents, which makes it ideal for use in high-gain
transimpedance systems or as a voltage amplifier with large feedback and gain resistors.
7.3.2 Output Common-Mode Control
The output common-mode loop works by sensing the average voltage between the two outputs of the main
amplifier through the two 6-kΩ resistors internal resistors in Section 7.2 and comparing it against the voltage at
the VOCM pin. The VOCM error amplifier then adjusts the internal bias of the main amplifier to minimize the
error voltage between its input pins. The voltage at the VOCM node defaults to midsupply through the two 400-
kΩ internal bias string resistors between VS+ and VS–. When using the VOCM at its default voltage, connect an
external capacitor to the VOCM pin to bypass the noise from the internal 400-kΩ resistors. When the amplifier is
disabled, the default midsupply bias string is disabled to save power. The THS4567 device output common-
mode can also be set by driving the VOCM pin externally through a low output impedance source. Ensure that
the source is capable of driving the input impedance of the VOCM pin.
7.3.3 Input Common-Mode Control
The THS4567 device features a unique input common-mode control error amplifier that sets the input common-
mode voltage independent of the output common-mode voltage. The VICM error amplifier works by sensing the
average voltage at the main amplifiers inputs and then sourcing or sinking an equal amount of current into both
the input nodes of the main amplifier to maintain the input common-mode voltage equal to voltage at the VICM
pin. If the VICM pin is left floating, its input voltage defaults to 1.5-V above VS–. This voltage is set by the
combination of the 8-µA current source and the 181-kΩ resistor shown in Section 7.2. When using the VICM at
its default voltage, connect an external capacitor to the VICM pin to bypass the noise from the internal 181-kΩ
resistor. The VICM voltage can be set to an arbitrary value by driving the VICM pin externally through a low
output impedance source. The input common-mode control loop can be disabled by setting ICM_EN pin low.
With the input common-mode loop disabled the THS4567 device behaves like a standard fully-differential
amplifier (FDA).
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
For proper shutdown mode operation, the amplifier enable (AMP_EN) pin must be asserted to the desired
voltage. An internal pullup resistor is provided on the AMP_EN pin so that if the pin is floated, then the device
defaults to an ON state. For applications that require the device to be constantly powered on when the supplies
are present, tie the AMP_EN pin to the positive supply voltage (VS+).
The disable operation is referenced from the positive supply. For an OFF state condition, the disable control pin
must be 2 V below the positive supply.
7.4.2 Differential Transimpedance Amplifier Mode
The primary use case of the input common-mode control loop is in differential transimpedance amplifier
applications where two photodiodes are excited by a differential input. Any ambient light that is incident on both
photodiodes will produce a DC offset current which is subsequently rejected by the input common-mode loop.
The input common-mode loop enables the use of very high feedback resistors to amplify the differential
photodiode current while simultaneously rejecting common-mode currents. Disabling the input common-mode
loop allows the common-mode current to flow through the feedback resistors thereby reducing the effective
output swing for the differential signal component. The THS4567 device can reject sourcing or sinking
photodiode currents.
The high impedance CMOS inputs of the THS4567 device minimizes the amplifiers input current noise enabling
the use of very high transimpedance gains (>100 kΩ), while the low input voltage noise maximizes the system
signal-to-noise ratio (SNR). The high gain bandwidth product of the THS4567 device allows it be used as a
single-stage differential transimpedance amplifier while driving a high performance ADC driver.
7.4.3 Fully Differential Amplifier (FDA) Mode
With the input common-mode loop disabled, the THS4567 device behaves like a standard FDA. It can convert a
single-ended input signal to a differential output or a differential input to a differential output with independent
output common-mode control. For a detailed understanding of FDA operation check out the training video.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Noise Analysis
To simplify the noise calculation of an FDA configured as a TIA, split the circuit into two identical halves and treat
each half as an independent op amp circuit. The noise of an op amp configured as a TIA is shown in
Transimpedance Considerations for High-Speed Amplifiers and is repeated in Equation 1. The equivalent noise
circuit is shown in Figure 8-1. The amplifiers voltage noise eNOP in Figure 8-1 is the specified input-referred
voltage noise of the THS4567 (eN) divided by 1.414. This method enables us to analyze the FDA as two identical
and uncorrelated halves. The total noise of the FDA is the total noise of each half multiplied by 1.414.
√4kTRF
RF
CF
ib
œ
CPD
+
eNOP
Figure 8-1. Transimpedance Amplifier Noise Analysis Circuit
To minimize the total noise of a TIA the circuit designer should:
1. Minimize the current noise of the op amp (ib). Since the THS4567 device has CMOS inputs its current noise
contribution can be ignored.
2. Maximize the transimpedance gain (RF).
3. Minimize the amplifiers voltage noise (eN). The THS4567 possesses a class leading 4.2 nV/ Hz of broadband
voltage noise while consuming less than 2.5 mA of quiescent current.
4. Minimize the photodiode capacitance (CPD).
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The capacitance of a photodiode can be minimized by increasing its reverse bias. The THS4567 input and
output common-mode can be independently controlled. The independent control feature allows the circuit
designer to set photodiode's anode close to the negative supply voltage while tying its cathode close to the
positive supply voltage to maximize the reverse bias across the photodiode. The output common-mode is then
set to match the next stage ADCs input common-mode range. In a standard op amp TIA, the input common-
mode is biased close to the positive supply to maximize the output swing of the amplifier. This bias configuration
limits the reverse bias across the photodiode thereby increasing its input capacitance. The THS4567 device is
optimized to reduce total system noise by optimizing the noise source from each contributing source in Equation
1.
2
2
»
…
…
ÿ
Ÿ
≈
’
4kT
en
(
en ∂2
p
∂ F ∂Cs
3
)
2
∆
∆
÷
÷
iEQ = ib +
+
+
/ 2
RF
RF
Ÿ
⁄
«
◊
(1)
where
•
•
•
•
•
•
ib = current noise of the THS4567 device
4kT = 16 × 10–21J at 290 degrees Kelvin
RF = feedback resistor
eN = voltage noise of the THS4567 device
CS = total input capacitance from the THS4567, photodiode and any PCB parasitics
F = noise integration frequency limit
8.2 Typical Application
The primary use case for the THS4567 input common-mode loop is in differential transimpedance applications
that have a large common-mode offset due to ambient light. In this section we compare the performance of the
THS4567 device with the input common-mode loop enabled (TIA mode) as shown in Figure 8-2 versus a
differential TIA implementation built using two discrete op amp channels (OPA mode) as shown in Figure 8-3.
VBIAS
CF
RF
IPD+
RFILT
–0.25 V
–
+
10-VPP Differential SAR
ADC Input
VOCM = 2.5 V
VICM = 1 V
CFILT
–
+
VBIAS
5.25 V
RFILT
’
RF'
CF'
IPD–
Figure 8-2. THS4567 with Integrated Differential TIA + ADC Driver
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VBIAS
CF
RF
IPD+
R1
R2
–0.25 V
RFILT
–
+
–0.25 V
+
–
5.25 V
5.25 V
10-VPP Differential SAR
ADC Input
5 V
CFILT
VOCM = 2.5 V
THS4561
–
+
+
–
5.25 V
RFILT
’
VBIAS
R2'
R1'
–0.25 V
RF'
CF'
IPD–
Figure 8-3. Discrete Differential Op Amp TIA + 2nd Stage ADC Driver
8.2.1 Design Requirements
The requirements for this application are:
•
•
•
•
•
•
Supply voltage: 5.5 V
ADC full-scale range: 10 VPP differential
ADC input common-mode voltage: 2.5 V
Ambient light current offset (DC): 10 µA
Single-sided signal current: 5 µAPP (each photodiode). Differential signal current = 10 µAPP
Input signal frequency: 100 kHz
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8.2.2 Detailed Design Procedure (THS4567 in TIA Mode)
The output current from each photodiode is shown in Figure 8-4. A detailed procedure on how to set the various
bias voltages and select the optimal value of transimpedance gain follows.
•
Set VS+ = 5.25 V and VS– = –0.25 V to allow the THS4567 to swing 10 VPP (differential) without introducing
distortion due to limited headroom.
•
•
•
Set ICM_EN = logic high to enable the THS4567 TIA mode of operation.
Set VOCM to 2.5 V to match the ADC input common-mode range.
With the photodiodes (PDs) configured with a cathode bias as shown in Figure 8-2 both PDs will source
current when light is incident on them. To maximize the reverse bias across the PD, VBIAS is typically set to
the amplifiers positive supply voltage or the highest available positive supply voltage.
The maximum output current from the PD is the sum of the ambient light current and the maximum signal
current.
•
•
•
ITOTAL = IAMBIENT + ISIGNAL = 10 µA + 5 µA = 15 µA
(2)
In the TIA mode, VICM is set to its minimum input common-mode compliance limit (1.25 V) to maximize the
reverse bias across the PDs thereby reducing the PD capacitance.
Reverse bias across the photodiodes = (5.25 V - 1.25 V) = 4 V
(3)
In the TIA mode, the ICM loop cancels the common-mode input current due to ambient light (10 µA) at the
amplifier's input pin and only the differential signal current flows through the feedback resistors RF and RF'.
The maximum TIA gain is therefore the ratio of the maximum differential output swing and the maximum
differential signal current as shown in Equation 4.
Maximum TIA gain = (10 VPP/ 10 µA) = 1 MΩ
(4)
•
Once the feedback resistor value is set, select the value of feedback capacitance as described in
Transimpedance Considerations for High-Speed Amplifiers.
20
IPD+
IPD-
17.5
15
Signal
Current
12.5
10
7.5
5
Ambient
Light
2.5
0
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
Figure 8-4. Photodiode Differential Output Current
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8.2.2.1 OPA Mode Configuration
The OPA mode configuration is shown in Figure 8-3. This configuration results in a reverse bias of (5.25 V - 5 V
= 0.25 V) across the PD thereby greatly increasing the PD capacitance compared to the TIA mode.
In the OPA mode there is no input common-mode current cancellation so the maximum value of feedback
resistance (RF, RF') is the ratio of the maximum single-ended output swing and the maximum single-ended input
current as shown in Equation 5.
Maximum TIA gain = (5 V/15 µA) = 333.33 kΩ
(5)
The total differential swing is 333.33 kΩ × 10 µAPP = 3.33 V. To maximize the ADC gain range a subsequent
amplifier gain stage is needed. The second gain stage which is typically implemented with a standard FDA like
the THS4561 will also adjust the output common-mode to match the ADCs input common-mode compliance
range.
As the level of ambient light increases relative to the differential signal from the PD, the maximum gain
configuration in the OPA mode will decrease while it stays constant for the THS4567 TIA mode.
8.2.3 Application Curves
Figure 8-5 shows the output of the THS4567 device in TIA mode. The output common-mode is centered on
VOCM = 2.5 V and the differential output of 10 VPP maximizes the subsequent ADCs entire common-mode
range.
Figure 8-6 shows the output of the first stage transimpedance amplifier setup shown in Figure 8-3. The output
common-mode is centered on 0.83 V. The offset in the common-mode is caused by the offset due to the ambient
light. More importantly the differential output swing is only 3.33 V. To maximize the ADC dynamic range the
subsequent THS4561 differential amplifier stage is configured in a signal gain of 3 V/V. The THS4561 device will
also perform a level shift to center the output common-mode to 2.5 V.
7.5
4.5
VOUT-
VOUT+
VOUT-
VOUT+
5
3
2.5
0
1.5
0
-1.5
-2.5
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
D500
Figure 8-6. Output of the 1st Stage Discrete Op
Amp Transimpedance Amplifier (OPA Mode)
Figure 8-5. Output of THS4567 (TIA Mode)
The noise performance of the THS4567 device (half-circuit) is then compared against the noise of the OPA607
and the OPA365 in OPA mode. Using Equation 1 we can estimate the total input referred spot noise for the
THS4567 device. Transimpedance Considerations for High-Speed Amplifiers is used to estimate the noise of the
OPA607 and OPA365 transimpedance amplifier stage in OPA mode.
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A PD capacitance of 5 pF is assumed. In a real world system the PD capacitance will be higher in OPA mode
because of the lower reverse bias across the PD. The calculated noise results are shown in Table 8-1 where the
benefit of the THS4567 device can clearly be seen. The spot noise has been normalized to the closed loop
bandwidth. The OPA mode architecture would require a second gain stage to maximize the ADCs input full scale
range. The second stage would increase the power consumption and degrade the noise.
Table 8-1. Noise Comparison
Amplifier Specification
Photodiode Capacitance (pF)
Amplifier Input Capacitance (pF)
Amplifier Voltage Noise (nV/√ Hz)
TIA Gain (kΩ)
THS4567
OPA607
5
OPA365
5
5
1
17
8
4.2
1000
2.4
0.2
3.8
4.5
333.33
1
333.33
1.4
Closed Loop Bandwidth (MHz)
Input-Referred Spot Noise (pA/√ Hz)
0.39
0.36
8.3 Differential TIA with 0-V Biased Photodiode
The circuit in Figure 8-7 can be used for a differential TIA with 0-V reverse bias across the photodiode. The
VICM loop should be disabled in this configuration since the loop can only source or sink DC current. Any DC
current generated by the photodiode in the configuration shown will be differential in nature.
CF
RF
VS–
IPD+
–
+
–
VICM
(disabled)
VOCM = 2.5 V
+
IPD–
VS+
RF'
CF'
Figure 8-7. Differential TIA with 0-V Biased Photodiode
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8.4 Differential AC Coupled TIA
The circuit in Figure 8-8 can be used as a differential AC-coupled TIA with variable reverse bias across the
photodiode. Since no DC current flows in the feedback network due to the AC coupling the VICM loop can be
disabled.
CF
+VBIAS
RF
VS–
IPD+
–
+
–
VICM
(disabled)
VOCM = 2.5 V
+
IPD–
VS+
RF'
–VBIAS
CF'
Figure 8-8. Differential AC Coupled TIA
9 Power Supply Recommendations
The THS4567 device is principally intended to operate with a nominal single-supply voltage of 3.3 V to 5.5 V.
Split (or bipolar) supplies can be used with the THS4567 device, as long as the total value across the device
remains less than 5.5 V. A low power-supply source impedance must be maintained across frequency so use
multiple bypass capacitors in parallel. Place the bypass capacitors as close to the supply pins as possible. Place
the smallest capacitor (< 10 nF) on the same side of the PCB as the THS4567 device. Larger capacitors (> 1 µF)
can be placed further away and shared among different devices in the system.
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations
Similar to all high-speed devices, best system performance is achieved with close attention to board layout.
General high-speed signal path layout suggestions include:
•
•
Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, both ground and power planes must be opened up around the capacitive sensitive input and output
device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue
and less of a stability issue.
Good high-frequency decoupling capacitors (0.01 µF) are required to a ground plane at the device power
pins. Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device
power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
Differential signal routing over any appreciable distance must use microstrip layout techniques with matched
impedance traces.
•
•
The THS4567 outputs are sensitive to capacitive loading. Isolate the output of the THS4567 from any
capacitive load by placing series isolation resistors close to the amplifiers output pins.
10.2 Layout Example
Place bypass capacitors close to VDD
and GND pins on the same side as
DUT. Use multiple vias to connect to
power and GND planes
GND
Optional noise bypass capacitors on
VICM and VOCM inputs. Capacitors
placed on bottom of PCB through vias
VS+
Series isolation resistors on each
differential output to isolate device
outputs from PCB capacitance
OUT+
VICM
VOCM
IN-
OUT–
ICM_EN
AMP_EN
Place feedback elements
close to DUT
IN+
VS–
Place photodiodes close to device inputs
to minimize parasitic capacitance
GND
VS+
VS+
Figure 10-1. Example Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments,RUN_FDA_4567 EVM user's guide
Texas Instruments, Fully-Differential Amplifiers application note
Texas Instruments, Fully Differential Amplifiers TI Precision Labs
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS4567IRUNR
ACTIVE
QFN
RUN
10
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SN67
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RUN 10
2 X 2, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228249/A
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PACKAGE OUTLINE
RUN0010A
WQFN - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
5
(0.2) TYP
4
6
SYMM
2X 1.5
6X 0.5
9
1
0.3
0.2
10X
10
PIN 1 ID
0.1
C A B
0.6
10X
0.05
0.4
4220470/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
SEE SOLDER MASK
DETAIL
10X (0.7)
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220470/A 05/2020
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
10X (0.7)
10
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4220470/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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