THS4631DE4 [TI]
高速 FET 输入运算放大器 | D | 8 | -40 to 85;
| 型号： | THS4631DE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高速 FET 输入运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 |
| 文件： | 总27页 (文件大小：1287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DGN−8
D−8
DDA−8
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
HIGH-VOLTAGE, HIGH SLEW RATE, WIDEBAND
FET-INPUT OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
•
High Bandwidth:
The THS4631 is a high-speed, FET-input operational
amplifier designed for applications requiring wideband
operation, high-input impedance, and high-power
– 325 MHz in Unity Gain
– 210 MHz Gain Bandwidth Product
High Slew Rate:
supply voltages. By providing
a 210-MHz gain
•
bandwidth product, ±15-V supply operation, and
100-pA input bias current, the THS4631 is capable of
simultaneous wideband transimpedance gain and
large output signal swing. The fast 1000 V/µs slew
rate allows for fast settling times and good harmonic
distortion at high frequencies. Low current and volt-
age noise allow amplification of extremely low-level
input signals while still maintaining a large sig-
nal-to-noise ratio.
– 900 V/µs (G = 2)
– 1000 V/µs (G = 5)
•
•
•
•
•
•
•
•
Low Distortion of –76 dB, SFDR at 5 MHz
Maximum Input Bias Current: 100 pA
Input Voltage Noise: 7 nV/√Hz
Maximum Input Offset Voltage: 500 µV at 25°C
Low Offset Drift: 2.5 µV/°C
Input Impedance: 109 || 3.9 pF
Wide Supply Range: ± 5 V to ± 15 V
High Output Current: 95 mA
The characteristics of the THS4631 make it ideally
suited for use as a wideband photodiode amplifier.
Photodiode output current is a prime candidate for
transimpedance amplification as shown below. Other
potential applications include test and measurement
systems requiring high-input impedance, ADC and
DAC buffering, high-speed integration, and active
filtering.
APPLICATIONS
•
•
•
•
•
•
•
Wideband Photodiode Amplifier
High-Speed Transimpedance Gain Stage
Test and Measurement Systems
Current-DAC Output Buffer
Active Filtering
The THS4631 is offered in an 8-pin SOIC (D), and
the 8-pin SOIC (DDA) and MSOP (DGN) with
PowerPAD™ package.
Related FET Input Amplifier Products
High-Speed Signal Integrator
High-Impedance Buffer
SLEW
RATE
(V/µS)
VOLTAGE
NOISE
(nV/√Hz)
VS
(V)
GBWP
(MHz)
MINIMUM
GAIN
DEVICE
OPA656
OPA657
OPA627
THS4601
±5
±5
230
1600
16
290
700
55
7
1
7
1
1
Photodiode Circuit
4.8
4.5
5.4
C
R
F
±15
±15
180
100
F
_
+
λ
R
L
−V
(Bias)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNITS
VS
VI
Supply voltage, VS– to VS+
33 V
Input voltage
±VS
(2)
IO
Output current
150 mA
Continuous power dissipation
Maximum junction temperature(2)
Operating free-air temperature, continues operation, long-term reliability(2)
Storage temperature range
See Dissipation Rating Table
TJ
150°C
125°C
TA
Tstg
65°C to 150°C
300°C
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
HBM
CDM
MM
1000 V
ESD ratings:
1500 V
100 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS
POWER RATING(1) (TJ =125°C)
PACKAGE
θJC (°C/W)
θJA (°C/W)
T
A ≤ 25°C
TA = 85°C
0.47 W
D (8)(2)
DDA (8)
DGN (8)
38.3
9.2
95
1.1 W
45.8
58.4
2.3 W
0.98 W
4.7
2.14 W
1.11 W
(1) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance.
(2) This data was taken using the JEDEC standard High-K test PCB.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
±5
MAX
±15
30
UNITS
V
Dual Supply
VS
TA
Supply Voltage
Single Supply
10
Operating free-air temperature
-40
85
°C
2
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
PACKAGE / ORDERING INFORMATION
PACKAGE DEVICES(1)
THS4631D
PACKAGE TYPE SOIC – 8
TRANSPORT MEDIA, QUANTITY
Rails, 75
SOIC – 8
THS4631DR
Tape and Reel, 2500
Rails, 75
THS4631DDA
THS4631DDAR
THS4631DGN
THS4631DGNR
SOIC-PP – 8(2)
MSOP-PP – 8(2)
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) PowerPad™ is electrically isolated from all other pins. Connection of the PowerPAD to the PCB ground plane is recommended because
the ground plane is typically the largest copper area on a PCB. However, connection of the PowerPAD to VS- up to VS+ is allowed if
desired.
PIN ASSIGNMENTS
THS4631
TOP VIEW
D, DDA, AND DGN
NC
NC
1
2
3
4
8
7
6
5
V
IN−
V
IN+
V
V
S+
OUT−
V
S−
NC
NC = No Internal Connection
3
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 499 Ω, RL = 1 kΩ, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
–40°C to
85°C
MIN/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = 1, RF = 0 Ω, VO = 200 mVPP
G = 2, RF = 499 Ω, VO = 200 mVPP
G = 5, RF = 499 Ω, VO = 200 mVPP
G = 10, RF = 499 Ω, VO = 200 mVPP
G > 20
325
105
55
Small signal bandwidth, -3 dB
MHz
25
Gain bandwidth product
0.1 dB bandwidth flatness
Large-signal bandwidth
210
38
MHz
MHz
MHz
G = 2, RF = 499 Ω, CF = 8.2 pF
G = 2, RF = 499 Ω, VO = 2 VPP
G = 2, RF = 499 Ω, VO = 2-V step
G = 2, RF = 499 Ω, VO = 10-V step
G = 5, RF = 499 Ω, VO = 10-V step
2-V step
105
550
900
1000
5
Slew rate
V/µs
Rise and fall time
ns
ns
0.1%, G = -1, VO = 2-V step, CF = 4.7 pF
0.01%, G = -1, VO = 2-V step, CF = 4.7 pF
40
Settling time
190
HARMONIC DISTORTION
Second harmonic distortion
RL = 100 Ω
-65
-76
-62
-94
7
dBc
dBc
G = 2,
VO = 2 VPP
f = 5 MHz
RL = 1 k Ω
RL = 100 Ω
RL = 1 kΩ
,
Third harmonic distortion
Input voltage noise
f > 10 kHz
f > 10 kHz
nV/√Hz
fA/√Hz
Input current noise
20
DC PERFORMANCE
Open-loop gain
RL = 1 kΩ
80
260
±2.5
50
70
65
65
dB
µV
Min
Max
Max
Max
Max
Input offset voltage(1)
Average offset voltage drift(1)
Input bias current
500
±10
100
100
1600
±12
2000
±12
VCM = 0 V
25°C to 85°C
µV/°C
pA
1500
700
2000
1000
VCM = 0 V
Input offset current
25
pA
INPUT CHARACTERISTICS
-12.5 to
11.5
Common-mode input range
-13 to 12
-12 to 11
80
-9 to 11
80
V
Min
Min
Common-mode rejection ratio
Differential input resistance
VCM = 10 V
95
86
dB
109 || 3.9
109 || 3.9
Ω || pF
Ω || pF
Common-mode input resistance
OUTPUT CHARACTERISTICS
RL = 100 Ω
RL = 1 kΩ
±11
±13.5
98
±10
±13
90
±9.5
±12.8
85
±9.5
±12.8
80
Output voltage swing
V
Min
Static output current (sourcing)
Static output current (sinking)
Closed loop output impedance
POWER SUPPLY
RL = 20 Ω
mA
mA
Ω
Min
Min
RL = 20 Ω
95
85
80
80
G = 1, f = 1 MHz
0.1
±15
±5
±16.5
±4
±16.5
±4
±16.5
±4
V
Max
Min
Max
Min
Min
Min
Specified operating voltage
V
Maximum quiescent current
Minimum quiescent current
11.5
11.5
95
13
14
14
mA
mA
dB
dB
10
9
9
Power supply rejection (PSRR +)
Power supply rejection (PSRR –)
VS+ = 15.5 V to 14.5 V, VS– = 15 V
VS+ = 15 V, VS– = -15.5 V to -14..5 V
85
80
80
95
85
80
80
(1) Input offset voltage is 100% tested at 25°C. It is specified by characterization and simulation over the listed temperature range.
4
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
+15 V
Test Data
Mesurement Point
50 Ω Source
+
953 Ω
50 Ω Test
Equipment
THS4631
_
49.9 Ω
49.9 Ω
−15 V
R
G
R
F
499 Ω
499 Ω
C
F
SMALL SIGNAL FREQUENCY
RESPONSE
SMALL SIGNAL FREQUENCY
RESPONSE
0.1-dB FLATNESS
10
9
6.3
6.2
6.1
50
40
30
20
10
V
= 200 mV
PP
O
V
= 200 mV
PP
O
C
= 0 pF
F
G = 100, R = 11.3 kΩ, R = 115 Ω
F
G
C
= 5.6 pF
F
8
7
C
F
= 8.2 pF
6
G = 10, R = 499 Ω,
F
6
5.9
5.8
R
= 54.9 Ω
G
5
C
= 8.2 pF
105 MHz
G = 5, R = 499 Ω,
F
F
R
= 124 Ω
G
4
105 MHz
G = 2, R = 499 Ω,
F
38 MHz
3
2
R
= 499 Ω
G
G = 1, R = 0 Ω
F
G = 2, R = 499 Ω,
0
F
5.7
5.6
R
G
= 499 Ω
1
0
−10
100 k
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
FREQUENCY RESPONSE
vs
SMALL SIGNAL FREQUENCY
RESPONSE
LARGE SIGNAL FREQUENCY
RESPONSE
CAPACiTIVE LOAD
4
2
8
7
6
5
4
3
2
1
0
5
4
3
2
1
R
= 50 Ω,
G = 1,
V
= 200 mV
PP
ISO
C
L
O
V
= 5 V
PP
O
= 10 pF
R
R
= 0 Ω,
F
L
C
= 0 pF
= 1 kΩ
F
C
= 2.2 pF
F
0
V
= 0.5 V
O
PP
R
= 30 Ω,
= 56 pF
ISO
C
L
−2
−4
−6
105 MHz
R
C
= 20 Ω,
ISO
= 100 pF
0
V
= 2 V
O
PP
102 MHz
L
−1
C
F
= 5.2 pF
+15 V
50 Ω
Source
−2
−3
−4
−5
R
ISO
THS4631
G = −1, R = 499 Ω,
F
R
L
R
G
= 499 Ω
C
L
−8
−15 V
0 Ω
−10
100 k
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
10 M
100 M
1 G
1 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4.
Figure 5.
Figure 6.
5
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
SECOND ORDER
HARMONIC DISTORTION
vs
THIRD ORDER
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
FREQUENCY
FREQUENCY
−30
−40
−50
−60
−70
−80
−90
-50
-55
-60
-65
-70
-75
-80
-85
-90
-30
-40
-50
-60
-70
-80
-90
G = 2,
Gain = 2
Gain = 2
HD2, R = 100 W
L
R
F
= 499 W,
R
C
V
= 499 Ω,
R
C
V
= 499 W
F
F
O
F
C
F
= 8.2 pF,
= 8.2 pF
= 2 V
PP
= 8.2 pF
F
f = 4 MHz
= 2 V
HD3, R = 100 W
L
O
PP
R
L
= 100 W
R
L
= 100 Ω
HD2, R = 1 kW
L
R = 1 kW
L
HD3, R = 1 kW
L
R
= 1 kΩ
L
-100
-95
-100
-1 10
1 M
10 M
100 M
0
0.5
1
1.5
2
2.5
3
3.5
4
1 M
10 M
100 M
V
- Output Voltage Swing - V
f − Frequency − Hz
O
f - Frequency - Hz
PP
Figure 7.
Figure 8.
Figure 9.
SLEW RATE
vs
OUTPUT VOLTAGE
OPEN-LOOP GAIN
vs
TEMPERATURE
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
90
80
70
60
50
40
30
20
10
0
50
25
1200
1000
800
82
81
80
79
78
77
76
75
74
G = 5,
R
R
= 499 Ω,
F
G
= 124 Ω
0
−25
−50
−75
600
−100
−125
−150
400
200
0
−175
−200
73
72
−10
1 k 10 k 100 k 1 M 10 M 100 M
1 G
0
2
4
6
8
10
12
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
f − Frequency − Hz
V
− Output Voltage − V
T − Case Temperature − °C
C
O
PP
Figure 10.
Figure 11.
Figure 12.
INPUT VOLTAGE
vs
FREQUENCY
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT BIAS CURRENT
vs
TEMPERATURE
12
11.5
11
800
100
T
A
= 85°C
700
600
500
400
300
200
T
A
= 25°C
10.5
10
10
T
= −40°C
A
9.5
9
100
0
1
10
−40−30−20
−10 0 10 20 30 40 50 60 70 80 90
100
1 k
10 k
100 k
0
2
4
6
8
10 12 14 16
V
− Supply Voltage − + V
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
S
Figure 13.
Figure 14.
Figure 15.
6
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
INPUT OFFSET CURRENT
INPUT OFFSET VOLTAGE
OUTPUT VOLTAGE
vs
TEMPERATURE
vs
vs
TEMPERATURE
TEMPERATURE
300
200
250
225
200
175
150
125
100
75
13.55
Referred to 25°C
V
+
O
13.5
13.45
13.4
DDA Package
100
0
D Package
13.35
13.3
−100
V
−
O
50
−200
−300
13.25
13.2
25
0
DGN Package
25
35
45
55
65
75
85
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
T
C
− Case Temperature − °C
Figure 16.
Figure 17.
Figure 18.
STATIC OUTPUT DRIVE CURRENT
vs
SMALL SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
TEMPERATURE
100
125
100
75
1.2
Source
1
0.8
0.6
0.4
0.2
98
96
94
92
90
88
50
Sink
25
0
0
−0.2
−0.4
−0.6
−0.8
−1
−25
Gain = 2,
−50
−75
Gain = 2,
C
= 8.2 pF,
F
C
= 8.2 pF,
V = 100 mV
PP,
F
I
L
V = 1 V
PP,
R
= 1 kΩ
I
R
L
= 1 kΩ
86
84
−100
−125
−1.2
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
T
C
− Case Temperature − °C
t − Time− ns
t − Time − ns
Figure 19.
Figure 20.
Figure 21.
LARGE SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
7
12
10
8
2.5
20 V
10 V
PP
PP
2
5
1.5
6
3
1
4
0.5
2
1
0
0
−0.5
−1
-1
-2
Gain = 5,
-4
-3
Gain = 2,
R
= 499 W,
Gain = 5,
F
L
-6
C
= 8.2 pF,
F
R = 499 W,
F
−1.5
−2
R
= 1 kW
V = 2 V
PP,
I
-8
-5
R = 1 kW
L
R
= 1 kΩ
L
-10
-7
−2.5
-12
0
20 40 60 80 100 120 140 160 180
0
20 40 60 80 100 120 140 160 180
t - Time - ns
0
25
50
75 100 125 150
t - Time - ns
t − Time− ns
Figure 22.
Figure 23.
Figure 24.
7
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA = 25°C, G = 2, RF = 499 Ω, RL = 1 kΩ, Unless otherwise noted.
SETTLING TIME
SETTLING TIME
OVERDRIVE RECOVERY
1.5
1.25
1
3
4
3
2
1
20
15
10
5
Input
Gain = 5,
2.5
Rising
Rising
R
R
= 499 Ω,
F
G
= 124 Ω
2
1.5
0.75
0.5
1
0.5
0.25
G = −1,
= 4.7 pF
G = −1,
= 4.7 pF
C
F
C
F
0
0
0
−0.5
−1
0
−0.25
−0.5
−1
−5
Output
−2
−3
−4
−10
−15
−20
−1.5
−2
−0.75
−1
Falling
Falling
−2.5
−3
−1.25
−1.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
t − Time − ms
t − Time − ns
t − Time − ns
Figure 25.
Figure 26.
Figure 27.
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
REJECTION RATIO
vs
OVERDRIVE RECOVERY
FREQUENCY
20
4
100
90
80
70
60
50
40
30
20
100
Input
90
80
70
60
50
40
30
20
10
0
3
2
15
10
CMRR
Output
5
0
1
PSRR+
PSRR−
0
−5
−1
−10
−2
Gain = 5,
= 499 Ω,
= 124 Ω
R
R
F
G
−15
−20
−3
−4
10
0
−0.05
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35
100 k
10 k
1 M
10 M
100 M
−15
−10
−5
0
5
10
15
t − Time − ms
V
− Input Common-Mode Range − V
f − Frequency − Hz
ICR
Figure 28.
Figure 29.
Figure 30.
OUTPUT IMPEDANCE
vs
FREQUENCY
100
10
1
0.1
0.01
100 k
1 M
100 M
1 G
10 M
f − Frequency − Hz
Figure 31.
8
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
APPLICATION INFORMATION
The large gain-bandwidth product of the THS4631
provides the capability for simultaneously achieving
both high-transimpedance gain, wide bandwidth, high
slw rate, and low noise. In addition, the high-power
supply rails provide the potential for a very wide
dynamic range at the output, allowing for the use of
input sources which possess wide dynamic range.
The combination of these characteristics makes the
THS4631 a design option for systems that require
transimpedance amplification of wideband, low-level
input signals. A standard transimpedance circuit is
shown in Figure 32.
INTRODUCTION
The THS4631 is a high-speed, FET-input operational
amplifier. The combination of: high gain bandwidth
product of 210 MHz, high slew rate of 1000 V/µs, and
trimmed dc precision makes the device an excellent
design option for a wide variety of applications,
including test and measurement, optical monitoring,
transimpedance gain circuits, and high-impedance
buffers. The applications section of the data sheet
discusses these particular applications in addition to
general information about the device and its features
Photodiode Circuit
TRANSIMPEDANCE FUNDAMENTALS
C
F
F
FET-input
amplifiers
are
often
used
in
transimpedance applications because of their ex-
tremely high input impedance. A transimpedance
block accepts a current as an input and converts this
current to a voltage at the output. The high-input
impedance associated with FET-input amplifiers
minimizes errors in this process caused by the input
bias currents, IIB, of the amplifier.
R
_
+
λ
R
L
−V
(Bias)
DESIGNING THE TRANSIMPEDANCE
CIRCUIT
Figure 32. Wideband Photodiode Transimpedance
Amplifier
Typically, design of a transimpedance circuit is driven
by the characteristics of the current source that
provides the input to the gain block. A photodiode is
the most common example of a capacitive current
source that interfaces with a transimpedance gain
block. Continuing with the photodiode example, the
system designer traditionally chooses a photodiode
based on two opposing criteria: speed and sensitivity.
Faster photodiodes cause a need for faster gain
stages, and more sensitive photodiodes require
higher gains in order to develop appreciable signal
levels at the output of the gain stage.
As indicated, the current source typically sets the
requirements for gain, speed, and dynamic range of
the amplifier. For a given amplifier and source combi-
nation, achievable performance is dictated by the
following parameters: the amplifier gain-bandwidth
product, the amplifier input capacitance, the source
capacitance, the transimpedance gain, the amplifier
slew rate, and the amplifier output swing. From this
information, the optimal performance of
a
transimpedance circuit using a given amplifier is
determined. Optimal is defined here as providing the
required transimpedance gain with a maximized flat
frequency response.
These parameters affect the design of the
transimpedance circuit in a few ways. First, the speed
of the photodiode signal determines the required
bandwidth of the gain circuit. Second, the required
gain, based on the sensitivity of the photodiode, limits
the bandwidth of the circuit. Third, the larger capaci-
tance associated with a more sensitive signal source
also detracts from the achievable speed of the gain
block. The dynamic range of the input signal also
places requirements on the amplifier dynamic range.
Knowledge of the source output current levels,
coupled with a desired voltage swing on the output,
dictates the value of the feedback resistor, RF. The
transfer function from input to output is VOUT = IINRF.
For the circuit shown in Figure 32, all but one of the
design parameters is known; the feedback capacitor
(CF) must be determined. Proper selection of the
feedback capacitor prevents an unstable design,
controls pulse response characteristics, provides
maximized flat transimpedance bandwidth, and limits
broadband integrated noise. The maximized flat fre-
quency response results with CF calculated as shown
in Equation 1, where CF is the feedback capacitor, RF
is the feedback resistor, CS is the total source
capacitance (including amplifier input capacitance
and parasitic capacitance at the inverting node), and
GBP is the gain-bandwidth product of the amplifier in
hertz.
9
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
2
4C
1
1
S
A
OL
) Ǹǒ Ǔ
Gain
)
p R GBP
p R GBP
p R GB P
F
F
F
−20 dB/
Decade
C
+
20 dB/Decade
Rate-of-Closure
F
2
(1)
Once the optimal feedback capacitor has been selec-
ted, the transimpedance bandwidth can be calculated
with Equation 2.
Noise Gain
GBP
GBP
F
+
Ǹ
20 dB/
Decade
*3dB
ǒ
Ǔ
2p RF CS ) CF
(2)
0
f
+
_
C
I(CM)
Zero
Pole
C
I(DIFF)
Figure 34. Transimpedance Circuit Bode Plot
R
C
F
C
P
The performance of the THS4631 has been
measured for a variety of transimpedance gains with
a variety of source capacitances. The achievable
bandwidths of the various circuit configurations are
summarized numerically in Table 1. The frequency
responses are presented in Figure 35, Figure 36, and
Figure 37.
I(
DIODE)
C
D
F
C
S
= C
+ C
+ C + C
I(DIFF) P D
I(CM)
A. The total source capacitance is the sum of
several distinct capacitances.
Note that the feedback capacitances do not corre-
spond exactly with the values predicted by the
equation. They have been tuned to account for the
parasitic capacitance of the feedback resistor
(typically 0.2 pF for 0805 surface mount devices) as
well as the additional capacitance associated with the
PC board. The equation should be used as a starting
point for the design, with final values for CF optimized
in the laboratory.
Figure 33. Transimpedance Analysis Circuit
Where:
CI(CM) is the common-mode input capacitance.
CI(DIFF) is the differential input capacitance.
CD is the diode capacitance.
CP is the parasitic capacitance at the inverting
node.
Table 1. Transimpedance Performance Summary
for Various Configurations
The feedback capacitor provides a pole in the noise
gain of the circuit, counteracting the zero in the noise
gain caused by the source capacitance. The pole is
set such that the noise gain achieves a 20-dB per
decade rate-of-closure with the open-loop gain re-
sponse of the amplifier, resulting in a stable circuit.
As indicated, the formula given provides the feedback
capacitance for maximized flat bandwidth. Reduction
in the value of the feedback capacitor can increase
the signal bandwidth, but this occurs at the expense
of peaking in the ac response.
SOURCE
CAPACITANCE
(PF)
TRANS-
IMPEDANCE
GAIN (Ω)
FEEDBACK
CAPACITANCE
(PF)
-3 dB
FREQUENCY
(MHZ)
18
18
10 k
100 k
1 M
2
0.5
0
15.8
3
18
1.2
8.4
2.1
0.52
5.5
1.4
0.37
47
10 k
100 k
1 M
2.2
0.7
0.2
3
47
47
100
100
100
10 k
100 k
1 M
1
0.2
10
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
10-kΩ TRANSIMPEDANCE RESPONSES
current as an input rather than a voltage. Also, the
capacitance of the current source has a direct effect
on the frequency response. A simple interface circuit
can be used to emulate a capacitive current source
85
80
75
C
C
= 18 PF
= 2 PF
S
F
with
a
network analyzer. With this circuit,
C
C
= 47 PF
= 2.2 PF
S
transimpedance bandwidth measurements are simpli-
fied, making amplifier evaluation easier and faster.
F
C
C
= 100 PF
= 3 PF
S
I
O
Network Analizer
F
C2
70
65
I
50 W
50 W
O
1
V
R
R
= ±15 V
= 1 k
= 10 k
S
(s) +
L
F
C1
C2
V
ǒ1 )
Ǔ
S
R
S
2RS
C1
V
S
10 k
100 k
1 M
10 M
1 G
(Above the Pole Frequency)
f − Frequency − Hz
Figure 35.
A. The interface network creates a capacitive,
constant current source from network
100-kΩ TRANSIMPEDANCE RESPONSES
a
105
analyzer and properly terminates the net-
work analyzer at high frequencies.
C
C
= 18 PF
= 0.5 PF
S
F
Figure 38. Emulating a Capacitive Current Source
With a Network Analyzer
100
95
C
C
= 47 PF
= 0.7 PF
S
F
The transconductance transfer function of the
C
= 100 PF
= 1 PF
interface circuit is:
S
C
F
s
90
85
V
R
R
= ±15 V
= 1 k
= 100 k
C1
C2
S
ǒ1)
Ǔ
2RS
I
L
O
(s) +
F
1
V
s ) 2 R
S
ǒ
Ǔ
C1)C2
10 k
100 k
1 M
10 M
1 G
S
(3)
f − Frequency − Hz
The transfer function contains a zero at dc and a pole
Figure 36.
1
(
)
2 RS C1 ) C2
at:
. The transconductance is constant
1-MΩ TRANSIMPEDANCE RESPONSES
125
1
C
C
= 18 PF
= 0 PF
S
C1
F
ǒ1 ) C2Ǔ
2 RS
120
115
at:
, above the pole frequency, provid-
ing a controllable ac-current source. This circuit also
properly terminates the network analyzer with 50 Ω at
high frequencies. The second requirement for this
current source is to provide the desired output im-
pedance, emulating the output impedance of a
photodiode or other current source. The output im-
pedance of this circuit is given by:
C
C
= 47 PF
= 0.2 PF
S
F
110
105
C
C
= 100 PF
= 0.2 PF
S
F
V
R
R
= ±15 V
= 1 k
= 1 M
S
100
95
L
F
1
ȱs )
ȳ
ȧ
10 k
100 k
1 M
10 M
ǒ
Ǔ
2RS C1)C2
C1 ) C2
Z (s) +
f − Frequency − Hz
ȧ
O
C1 C2
1
Figure 37.
ǒ
Ǔ
s s ) 2 R
C1
S
(4)
Assuming C1 >> C2, the equation reduces to:
MEASURING TRANSIMPEDANCE
BANDWIDTH
1
ZO
[
sC2
, giving the appearance of a capacitive
source at a higher frequency.
While there is no substitute for measuring the per-
formance of a particular circuit under the exact
conditions that are used in the application, the com-
plete system environment often makes measure-
ments harder. For transimpedance circuits, it is diffi-
cult to measure the frequency response with tradition-
al laboratory equipment because the circuit requires a
Capacitor values should be chosen to satisfy two
requirements. First, C2 represents the anticipated
capacitance of the true source. Second C1 is chosen
such
that
the
corner
frequency
of
the
transconductance network is much less than the
transimpedance bandwidth of the circuit. Choosing
11
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
this corner frequency properly leads to more accurate
measurements of the transimpedance bandwidth. If
the interface circuit corner frequency is too close to
the bandwidth of the circuit, determining the power
level in the flatband is difficult. A decade or more of
flat bandwidth provides a good basis for determining
the proper transimpedance bandwidth.
R
F2
R
+ R
1 )
ǒ Ǔ
EQ
F1
R
F3
(5)
C
F
R
F3
R
F2
R
F1
ALTERNATIVE TRANSIMPEDANCE
CONFIGURATIONS
_
+
λ
Other transimpedance configurations are possible.
Three possibilities are shown below.
R
L
The first configuration is a slight modification of the
basic transimpedance circuit. By splitting the
feedback resistor, the feedback capacitor value be-
comes more manageable and easier to control. This
type of compensation scheme is useful when the
feedback capacitor required in the basic configuration
becomes so small that the parasitic effects of the
board and components begin to dominate the total
feedback capacitance. By reducing the resistance
across the capacitor, the capacitor value can be
increased. This mitigates the dominance of the para-
sitic effects.
−V
(Bias)
A.
A
resistive T-network enables high
transimpedance gain with reasonable re-
sistor values.
Figure 40. Alternative Transimpedance
Configuration 2
The third configuration uses a capacitive T-network to
achieve fine control of the compensation capacitance.
The capacitor CF3 can be used to tune the total
effective feedback capacitance to a fine degree. This
circuit behaves
the same as
the basic
C
F
transimpedance configuration, with the effective CF
given by Equation 6.
R
F2
R
F1
C
F3
1
1
+
1 )
ǒ Ǔ
_
+
λ
C
C
C
FEQ
F1
F2
(6)
R
L
C
F3
−V
(Bias)
C
F1
C
F2
A. Splitting the feedback resistor enables use
of a larger, more manageable feedback
capacitor.
R
F
_
+
Figure 39. Alternative Transimpedance
Configuration 1
λ
R
L
The second configuration uses a resistive T-network
to achieve high transimpedance gains using relatively
small resistor values. This topology can be useful
when the desired transimpedance gain exceeds the
value of available resistors. The transimpedance gain
is given by Equation 5.
−V
(Bias)
A. A capacitive T-network enables fine control
of the effective feedback capacitance using
relatively large capacitor values.
Figure 41. Alternative Transimpedance
Configuration 3
12
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
SUMMARY OF KEY DECISIONS IN
TRANSIMPEDANCE DESIGN
feedback resistors this large or anticipate using an
external compensation scheme to stabilize the circuit.
Using a simple capacitor in parallel with the feedback
resistor makes the amplifier more stable as shown in
the Typical Characteristics graphs.
The following is a simplified process for basic
transimpedance circuit design. This process gives a
start to the design process, though it does ignore
some aspects that may be critical to the circuit.
NOISE ANALYSIS
STEP 1:
Determine the capacitance of the
source.
High slew rate, unity gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate
at the expense of a higher input noise voltage. The
7 nV/√Hz input voltage noise for the THS4631 is,
however, much lower than comparable amplifiers
while achieving high slew rates. The input-referred
voltage noise, and the input-referred current noise
term, combine to give low output noise under a wide
variety of operating conditions. Figure 42 shows the
amplifier noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
be noise voltage or current density terms in either
nV/√Hz or fA/√Hz.
STEP 2:
Calculate the total source capacitance,
including the amplifier input capaci-
tance, CI(CM) and CI(DIFF)
.
STEP 3:
STEP 4:
Determine the magnitude of the poss-
ible current output from the source,
including the minimum signal current
anticipated and maximum signal current
anticipated.
Choose a feedback resistor value such
that the input current levels create the
desired output signal voltages, and
ensure that the output voltages can
accommodate the dynamic range of the
input signal.
E
NI
+
_
E
O
R
S
I
BN
STEP 5:
STEP 6:
STEP 7:
Calculate the optimum feedback capaci-
tance using Equation 1.
E
RF
E
RS
4kTR
R
I
S
f
Calculate the bandwidth given the
resulting component values.
R
g
4kT
4kTR
f
BI
R
g
Evaluate the circuit to determine if all
design goals are satisfied.
4kT = 1.6E−20J
at 290K
SELECTION OF FEEDBACK RESISTORS
Figure 42. Noise Analysis Model
Feedback resistor selection can have a significant
effect on the performance of the THS4631 in a given
application, especially in configurations with low
closed-loop gain. If the amplifier is configured for
unity gain, the output should be directly connected to
the inverting input. Any resistance between these two
points interacts with the input capacitance of the
amplifier and causes an additional pole in the fre-
quency response. For nonunity gain configurations,
low resistances are desirable for flat frequency re-
sponse. However, care must be taken not to load the
amplifier too heavily with the feedback network if
large output signals are expected. In most cases, a
trade off is made between the frequency response
characteristics and the loading of the amplifier. For a
gain of 2, a 499-Ω feedback resistor is a suitable
operating point from both perspectives. If resistor
values are chosen too large, the THS4631 is subject
to oscillation problems. For example, an inverting
amplifier configuration with a 5-kΩ gain resistor and a
5-kΩ feedback resistor develops an oscillation due to
the interaction of the large resistors with the input
capacitance. In low gain configurations, avoid
The total output noise voltage can be computed as
the square root of all square output noise voltage
contributors. Equation 7 shows the general form for
the output noise voltage using the terms shown in
Figure 42.
2
2
ǒ
SǓ2 Ǔ2
ǒ
) 4kTRS NG ) IBIRf ) 4kTRfNG
+ Ǹǒ
Ǔ
EO
ENI ) IBN
R
(7)
Dividing this expression by the noise gain [NG = (1+
Rf/Rg)] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 8:
2
IBIRf
4kTRf
NG
2
ǒ
SǓ2
) 4kTRS )
Ǹ
ǒ Ǔ )
NG
EN +
ENI ) IBN
R
(8)
Using high resistor values can dominate the total
equivalent input-referred noise. Using 3-kΩ
a
source-resistance (RS) value adds a voltage noise
term of approximately 7 nV/√Hz. This is equivalent to
the amplifier voltage noise term. Using higher resistor
13
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
values dominate the noise of the system. Although
the THS4631 JFET input stage is ideal for
high-source impedance because of the low-bias cur-
rents, the system noise and bandwidth is limited by a
high-source (RS) impedance.
formance of the THS4631. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
Again, keep their leads and PC board trace
length as short as possible. Never use wirebound
type resistors in a high frequency application.
Since the output pin and inverting input pins are
the most sensitive to parasitic capacitance,
always position the feedback and series output
resistors, if any, as close as possible to the
inverting input pins and output pins. Other net-
work components, such as input termination re-
sistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time con-
stants that can degrade performance. Good axial
metal-film or surface-mount resistors have ap-
proximately 0.2 pF in shunt with the resistor. For
resistor values > 2.0 kΩ, this parasitic capaci-
tance can add a pole and/or a zero that can
effect circuit operation. Keep resistor values as
low as possible, consistent with load driving
considerations.
SLEW RATE PERFORMANCE WITH VARYING
INPUT STEP AMPLITUDE AND RISE/FALL
TIME
Some FET input amplifiers exhibit the peculiar
behavior of having a larger slew rate when presented
with smaller input voltage steps and slower edge
rates due to a change in bias conditions in the input
stage of the amplifier under these circumstances.
This phenomena is most commonly seen when FET
input amplifiers are used as voltage followers. As this
behavior is typically undesirable, the THS4631 has
been designed to avoid these issues. Larger ampli-
tudes lead to higher slew rates, as would be antici-
pated, and fast edges do not degrade the slew rate of
the device. The high slew rate of the THS4631 allows
improved SFDR and THD performance, especially
noticeable above 5 MHz.
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS4631 is nominally compen-
sated to operate with a 2-pF parasitic load.
Higher parasitic capacitive loads without an RS
are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrin-
sic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is not necessary onboard, and
in fact, a higher impedance environment im-
proves distortion as shown in the distortion ver-
sus load plots. With a characteristic board trace
impedance based on board material and trace
dimensions, a matching series resistor into the
trace from the output of the THS4631 is used as
well as a terminating shunt resistor at the input of
the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective im-
pedance should be set to match the trace im-
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4631 requires careful
attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
•
Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
de-coupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the de-coupling
capacitors. The power supply connections should
always be de-coupled with these capacitors.
Larger (6.8 µF or more) tantalum de-coupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
•
Careful selection and placement of external
components preserve the high frequency per-
14
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
pedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case. This does not preserve signal integrity
or a doubly-terminated line. If the input im-
pedance of the destination device is low, there is
some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
•
Socketing a high-speed part like the THS4631 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket
creates a troublesome parasitic network which
makes it almost impossible to achieve a smooth,
stable frequency response. Best results are ob-
tained by soldering the THS4631 part directly
onto the board.
0.035
0.040
0.010
vias
Top View
Figure 44. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD DESIGN CONSIDERATIONS
The THS4631 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 43 (a) and Figure 43
(b)]. This arrangement results in the lead frame being
exposed as a thermal pad on the underside of the
package [see Figure 43 (c)]. Because this thermal
pad has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad
0.300
0.100
0.035
0.026
0.010
Pin 1
0.030
0.060
0.060
0.140
0.050
0.176
The PowerPAD package allows for both assembly
and thermal management in one manufacturing oper-
ation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
0.035
0.080
0.010
vias
All Units in Inches
Top View
Figure 45. DDA PowerPAD PCB Etch and Via
Pattern
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the mechanical methods of
heatsinking.
PowerPAD PCB LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern is shown in
Figure 44 and Figure 45. There should be etch
for the leads and for the thermal pad.
DIE
2. Place the recommended number of holes in the
area of the thermal pad. These holes should be
10 mils in diameter. Keep them small so that
solder wicking through the holes is not a problem
during reflow.
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS4631 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal pad. They can be larger because
Figure 43. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
15
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
T
T
A
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
max
P
+
D max
q
JA
(9)
4. Connect all holes to the internal ground plane.
Although the PowerPAD is electrically isolated
from all pins and the active circuitry, connection
to the ground plane is recommended. This is due
to the fact that ground planes on most PCBs are
typically the targets copper area. Offering the
best thermal path heat to flow out of the device.
where:
PDmax is the maximum power dissipation in the
amplifier (W).
Tmax is the absolute maximum junction tempera-
ture (°C).
TA is the ambient temperature (°C).
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. There-
fore, the holes under the THS4631 PowerPAD
package should make their connection to the
internal ground plane with a complete connection
around the entire circumference of the
plated-through hole.
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/W).
NOTE:
For systems where heat dissipation is more
critical, the THS4631 is offered in an 8-pin MSOP
with PowerPAD package and an 8-pin SOIC with
PowerPAD package with better thermal perform-
ance. The thermal coefficient for the PowerPAD
packages are substantially improved over the
traditional SOIC. Maximum power dissipation
levels are depicted in Figure 46 for the available
packages. The data for the PowerPAD packages
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its via holes exposed. The bottom-side
solder mask should cover the via holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
assume
a
board layout that follows the
PowerPAD layout guidelines referenced above
and detailed in the PowerPAD application note
number SLMA002. Figure 46 also illustrates the
effect of not soldering the PowerPAD to a PCB.
The thermal impedance increases substantially
which may cause serious heat and performance
issues. Be sure to always solder the PowerPAD
to the PCB for optimum performance.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard sur-
face-mount component. This results in a part that
is properly installed.
4
T
J
= 125°C
3.5
3
θJ = 58.4°C/W
A
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
2.5
2
θJ = 98°C/W
A
To maintain maximum output capabilities, the
THS4631 does not incorporate automatic thermal
shutoff protection. The designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction tempera-
ture of 150°C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur,
but the performance of the amplifier begins to de-
grade. The thermal characteristics of the device are
dictated by the package and the PC board. Maximum
power dissipation for a given package can be calcu-
lated using Equation 9.
1.5
1
0.5
0
θJ = 158°C/W
A
−40
−20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
Figure 46. Maximum Power Dissipation
vs. Ambient Temperature
16
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
Results are with no air flow and PCB size = 3" x 3 "
θJA
= 58.4°C/W for the 8-pin MSOP with
PowerPAD (DGN).
θJA = 98°C/W for the 8-pin SOIC high-K test PCB
(D).
θJA
= 158°C/W for the 8-pin MSOP with
PowerPAD, without solder.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power dissi-
pation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem
DESIGN TOOLS EVALUATION FIXTURE,
SPICE MODELS, AND APPLICATIONS
SUPPORT
Texas Instruments is committed to providing its cus-
tomers with the highest quality of applications sup-
port. To support this goal an evaluation board has
been developed for the THS4631 operational ampli-
fier. The board is easy to use, allowing for straightfor-
ward evaluation of the device. The evaluation board
can be ordered through the Texas Instruments web
site, www.ti.com, or through your local Texas Instru-
ments sales representative. The board layers are
provided in Figure 47, Figure 48, and Figure 49. The
bill of materials for the evaluation board is provided in
Table 2.
Figure 48. EVM Layers 2 and 3, Ground
Figure 49. EVM Bottom Layer
Figure 47. EVM Top Layer
17
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
BILL OF MATERIALS
Table 2. THS4631DDA EVM
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QUANTITY
MANUFACTURER'S
PART NUMBER(1)
ITEM
DESCRIPTION
1
4
CAP, 2.2 µF, CERAMIC, X5R, 25 V
CAP, 0.1µF, CERAMIC, X7R, 50 V
OPEN
1206
0805
0805
0805
0805
1206
1206
1206
1206
C3, C6
C1, C2
R4, Z4, Z6
Z2
2
2
3
1
2
2
1
1
1
3
(AVX) 12063D225KAT2A
(AVX) 08055C104KAT2A
6
7
RESISTOR, 0 OHM, 1/8 W
RESISTOR, 499 OHM, 1/8 W, 1%
OPEN
(KOA) RK73Z2ATTD
R3, Z5
R8, Z9
R1
(KOA) RK73H2ATTD4990F
8
9
RESISTOR, 0 OHM, 1/4 W
RESISTOR, 49.9 OHM, 1/4 W, 1%
RESISTOR, 953 OHM, 1/4 W, 1%
CONNECTOR, SMA PCB JACK
(KOA) RK73Z2BLTD
10
11
13
R2
(KOA) RK73H2BLTD49R9F
(KOA) RK73H2BLTD9530F
(JOHNSON) 142-0701-801
Z3
J1, J2, J3
JACK, BANANA RECEPTANCE, 0.25"
DIA. HOLE
14
15
J4, J5, J6
3
(SPC) 813
TEST POINT, BLACK
TP1, TP2
TP3
2
1
4
4
1
1
(KEYSTONE) 5001
(KEYSTONE) 5000
(KEYSTONE) 1808
SHR-0440-016-SN
(TI) THS4631DDA
TEST POINT, RED
16
17
18
19
STANDOFF, 4-40 HEX, 0.625" LENGTH
SCREW, PHILLIPS, 4-40, .250"
IC, THS4631
U1
BOARD, PRINTED CIRCUIT
(TI) EDGE # 6467873 Rev.A
(1) The manufacturer's part numbers are used for test purposes only.
EVM
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic
capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4631 is
available through either the Texas Instruments web site (www.ti.com). These models help in predicting
small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types
in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the
model file itself.
18
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
Figure 50. THS4631 EVM Schematic
19
THS4631
www.ti.com
SLOS451A–DECEMBER 2004–REVISED MARCH 2005
ADDITIONAL REFERENCE MATERIAL
•
•
•
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
Noise Analysis of FET Transimpedance Amplifiers, application bulletin, Texas Instruments Literature Number
SBOA060.
•
•
Tame Photodiodes With Op Amp Bootstrap, application bulletin, Texas Instruments Literature Number
SBBA002.
Designing Photodiode Amplifier Circuits With OPA128, application bulletin, Texas Instruments Literature
Number SBOA061.
•
•
Photodiode Monitoring With Op Amps, application bulletin, Texas Instruments Literature Number SBOA035.
Comparison of Noise Performance Between a FET Transimpedance Amplifier and a Switched Integrator,
Application Bulletin, Texas Instruments Literature Number SBOA034.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
Input Range, VS+ to VS–
Input Range, VI
10 V to 30 V
10 V to 30 V NOT TO EXCEED VS+ or VS–
10 V to 30 V NOT TO EXCEED VS+ or VS–
Output Range, VO
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
20
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2005
PACKAGING INFORMATION
Orderable Device
THS4631D
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
THS4631DDA
SO
Power
PAD
DDA
DDA
DGN
DGN
DGN
DGN
8
75
TBD
CU SNPB
Level-1-235C-UNLIM
THS4631DDAR
THS4631DGN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
Power
PAD
8
8
8
8
8
2500
TBD
CU SNPB
Level-1-235C-UNLIM
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4631DGNG4
THS4631DGNR
THS4631DGNRG4
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4631DR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
THS4631DRG4
SOIC
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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