THS5651IDWR [TI]
10-Bit, 100MSPS, CommsDAC, Diff. Scalable Current Outputs between 2mA to 20mA 28-SOIC -40 to 85;
| 型号： | THS5651IDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-Bit, 100MSPS, CommsDAC, Diff. Scalable Current Outputs between 2mA to 20mA 28-SOIC -40 to 85 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
SOIC (DW) OR TSSOP (PW) PACKAGE
(TOP VIEW)
Member of the Pin-Compatible
CommsDAC Product Family
100 MSPS Update Rate
10-Bit Resolution
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
NC
NC
CLK
DV
DGND
2
DD
3
Superior Spurious Free Dynamic Range
Performance (SFDR) to Nyquist at 20 MHz
Output: 61 dBc
4
MODE
5
AV
DD
6
COMP2
IOUT1
IOUT2
AGND
COMP1
BIASJ
EXTIO
EXTLO
SLEEP
1 ns Setup/Hold Time
7
8
Differential Scalable Current Outputs: 2 mA
to 20 mA
9
10
11
12
13
14
On-Chip 1.2-V Reference
3 V and 5 V CMOS-Compatible Digital
Interface
Straight Binary or Twos Complement Input
Power Dissipation: 175 mW at 5 V, Sleep
Mode: 25 mW at 5 V
NC – No internal connection
Package: 28-Pin SOIC and TSSOP
The THS5651 is a 10-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data
transmission in wired and wireless communication systems. The 10-bit DAC is a member of the CommsDAC
series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin
compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package and
pinout. The THS5651 offers superior ac and dc performance while supporting update rates up to 100 MSPS.
The THS5651 operates from an analog supply of 4.5 V to 5.5 V. Its inherent low power dissipation of 175 mW
ensures that the device is well suited for portable and low power applications. Lowering the full-scale current
output reduces the power dissipation without significantly degrading performance. The device features a
SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power
consumption for system needs.
The THS5651 is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A
current-source-array architecture combined with simultaneous switching shows excellent dynamic
performance. On-chip edge-triggered input latches and a 1.2 V temperature compensated bandgap reference
provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS
logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The
THS5651 supports both a straight binary and twos complement input word format, enabling flexible interfacing
with digital signal processors.
The THS5651 provides a nominal full-scale differential output current of 20 mA and >300 kΩ output impedance,
supporting both single-ended and differential applications. The output current can be directly fed to the load
(e.g., external resistor load or transformer), with no additional external output buffer required. An accurate
on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA,
withnosignificantdegradationofperformance. Thisreducespowerconsumptionandprovides20dBgainrange
control capabilities. Alternatively, an external reference voltage and control amplifier may be applied in
applications using a multiplying DAC. The output voltage compliance range is 1.25 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CommsDAC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
description (continued)
The THS5651 is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation
over the industrial temperature range of –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
28-TSSOP
(PW)
28-SOIC
(DW)
–40°C to 85°C
THS5651IPW
THS5651IDW
functional block diagram
AV
DD
C
1
SLEEP
COMP1
0.1 µF
0.1 µF
COMP2
EXTLO
EXTIO
1.2 V
REF
IOUT1
1 nF
–
+
R
R
Output
Current
Switches
50 Ω
LOAD
LOAD
Current
Source
Array
C
EXT
BIASJ
Control
AMP
0.1 µF
I
IOUT2
BIAS
R
BIAS
2 kΩ
DV
DD
50 Ω
Logic
D[9:0]
Control
MODE
CLK
DGND
AGND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
AV
NO.
20
I
I
Analog ground return for the internal analog circuitry
Positive analog supply voltage (4.5 V to 5.5 V)
Full-scale output current bias
24
DD
BIASJ
CLK
18
O
I
28
External clock input. Input data latched on rising edge of the clock.
Compensation and decoupling node, requires a 0.1 µF capacitor to AV
Internal bias node, requires a 0.1 µF decoupling capacitor to AGND.
Data bits 0 through 9.
COMP1
COMP2
D[9:0]
19
I
.
DD
23
I
[1:10]
I
D9 is most significant data bit (MSB), D0 is least significant data bit (LSB).
Digital ground return for the internal digital logic circuitry
Positive digital supply voltage (3 V to 5.5 V)
DGND
26
27
17
I
I
DV
DD
EXTIO
I/O Used as external reference input when internal reference is disabled (i.e., EXTLO = AV ). Used as internal
DD
reference output when EXTLO = AGND, requires a 0.1 µF decoupling capacitor to AGND when used as reference
output
EXTLO
IOUT1
IOUT2
MODE
16
22
21
25
O
O
O
I
Internal reference ground. Connect to AV to disable the internal reference source
DD
DAC current output. Full scale when all input bits are set 1
Complementary DAC current output. Full scale when all input bits are 0
Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See
timing diagram.
NC
[11:14]
15
N
I
No connection
SLEEP
Asynchronous hardware power down input. Active High. Internal pulldown. Requires 5 µs to power down but 3 ms
to power up.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, AV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
DD
DD
DV
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.5 V
Supply voltage range, AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V to 6.5 V
DD
DD
CLK, SLEEP, MODE (see Note 2) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV
Digital input D9–D0 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV
IOUT1, IOUT2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to AV
COMP1, COMP2 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV
EXTIO, BIASJ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
DD
DD
EXTLO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Operating free-air temperature range, T : THS5651I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Measured with respect to AGND.
2. Measured with respect to DGND.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
electrical characteristics over recommended operating free-air temperature range, AV
= 5 V,
DD
DV
= 5 V, IOUT = 20 mA (unless otherwise noted)
DD
FS
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
Bits
†
DC accuracy
INL
Integral nonlinearity
–1
±0.5
±0.25
1
LSB
LSB
T
A
= –40°C to 85°C
DNL
Differential nonlinearity
–0.5
0.5
Monotonicity
Analog output
Monotonic
Offset error
0.02
2.3
%FSR
%FSR
Without internal reference
With internal reference
Gain error
1.3
‡
Full scale output current
2
20
mA
V
Output compliance range
Output resistance
AV
DD
= 5 V, IOUT
FS
= 20 mA
–1
1.25
300
5
kΩ
pF
Output capacitance
Reference output
Reference voltage
1.18
0.1
1.22
100
1.32
1.25
V
§
Reference output current
nA
Reference input
V
Input voltage range
Input resistance
V
EXTIO
1
1.3
MΩ
MHz
pF
¶
Small signal bandwidth
Input capacitance
Without C
COMP1
100
Temperature coefficients
Offset drift
0
±40
Without internal reference
With internal reference
ppm of
FSR/°C
Gain drift
±120
±35
Reference voltage drift
Power supply
AV
Analog supply voltage
Digital supply voltage
Analog supply current
4.5
3
5
5.5
5.5
30
5
V
DD
DV
V
DD
AVDD
DVDD
25
3
mA
mA
mA
I
I
Sleep mode supply current
Sleep mode
#
Digital supply current
5
6
||
Power dissipation
AV
DD
= 5 V, DV
= 5 V, IOUT
FS
= 20 mA
175
±0.4
mW
%FSR/V
°C
DD
AV
DD
Power supply rejection ratio
DV
±0.025
DD
Operating range
–40
85
†
‡
§
¶
#
||
Measured at IOUT1 in virtual ground configuration.
Nominal full-scale current IOUT equals 32X the IBIAS current.
Use an external buffer amplifier with high impedance input to drive any external load.
Reference bandwidth is a function of external cap at COMP1 pin and signal level.
FS
Measured at f
Measured for 50 Ω R
= 50 MSPS and f
= 1 MHz.
CLK
OUT
at IOUT1 and IOUT2, f
= 50 MSPS and f
= 20 MHz.
OUT
LOAD
CLK
Specifications subject to change
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
electrical characteristics over recommended operating free-air temperature range, AV
= 5 V,
DD
DV
= 5 V, IOUT = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load
DD
FS
(unless otherwise noted)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog output
DV
DV
= 4.5 V to 5.5 V
100
67
DD
DD
f
Maximum output update rate
MSPS
CLK
= 3 V to 3.6 V
†
t
t
Output settling time to 0.1%
35
1
ns
ns
s(DAC)
Output propagation delay
pd
‡
GE
Glitch energy
Worst case LSB transition (code 511 – code 512)
5
pV–s
ns
†
t
t
Output rise time 10% to 90%
1
r(IOUT)
†
Output fall time 90% to 10%
Output noise
1
ns
f(IOUT)
IOUT
IOUT
= 20 mA
= 2 mA
15
10
FS
pA/√HZ
FS
AC linearity
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 25 MSPS, f
= 50 MSPS, f
= 50 MSPS, f
= 1 MHz, T = 25°C
–72
–72
–70
–70
75
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
OUT
OUT
OUT
A
= 1 MHz, T = –40°C to 85°C
–64
A
THD
Total harmonic distortion
dBc
= 2 MHz, T = 25°C
A
= 100 MSPS, f
OUT
= 2 MHz, T = 25°C
A
= 25 MSPS, f
= 50 MSPS, f
= 50 MSPS, f
= 50 MSPS, f
= 50 MSPS, f
= 50 MSPS, f
= 1 MHz, T = 25°C
A
OUT
OUT
OUT
OUT
OUT
OUT
= 1 MHz, T = –40°C to 85°C
66
A
= 1 MHz, T = 25°C
74
73
65
61
66
53
53
82
81
78
A
dBc
= 2.51 MHz, T = 25°C
A
Spurious free dynamic range to
Nyquist
= 5.02 MHz, T = 25°C
A
= 20.2 MHz, T = 25°C
A
SFDR
= 100 MSPS, f
= 100 MSPS, f
= 100 MSPS, f
= 5.04 MHz, T = 25°C
dBc
dBc
dBc
OUT
OUT
OUT
A
= 20.2 MHz, T = 25°C
A
= 40.4 MHz, T = 25°C
A
= 50 MSPS, f
= 50 MSPS, f
= 1 MHz, T = 25°C,1 MHz span
OUT
A
Spurious free dynamic range
within a window
= 5.02 MHz, 2 MHz span
dBc
OUT
= 100 MSPS, f
= 5.04 MHz, 4 MHz span
OUT
†
‡
Measured single ended into 50 Ω load at IOUT1.
Single-ended output IOUT1, 50 Ω doubly terminated load.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
electrical characteristics over recommended operating free-air temperature range, AV
= 5 V,
DD
DV
= 5 V, IOUT = 20 mA (unless otherwise noted)
DD
FS
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Interface
DV
DV
DV
DV
DV
DV
= 5 V
3.5
2.1
5
3.3
0
DD
DD
DD
DD
DD
DD
V
High-level input voltage
V
V
IH
IL
= 3.3 V
= 5 V
1.3
0.9
10
10
5
V
Low-level input voltage
= 3.3 V
0
I
I
High-level input current
Low-level input current
Input capacitance
= 3 V to 5.5 V
= 3 V to 5.5 V
–10
–10
1
µA
µA
pF
IH
IL
Timing
t
t
t
t
Input setup time
1
1
4
ns
ns
ns
clk
su(D)
Input hold time
h(D)
Input latch pulse high time
Digital delay time
w(LPH)
d(D)
1
Specifications subject to change
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
†
TYPICAL CHARACTERISTICS
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 0 dBFS
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 5 MSPS
90
84
78
72
66
60
54
48
84
78
72
66
60
54
0 dBFS
fCLK = 5 MSPS
–6 dBFS
–12 dBFS
fCLK = 25 MSPS
fCLK = 50 MSPS
fCLK = 70 MSPS
fCLK = 100 MSPS
0
10
20
30
40
50
0
0.5
1.0
1.5
2.0
2.5
Fout – MHz
Fout – MHz
Figure 1
Figure 2
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 25 MSPS
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 50 MSPS
78
72
66
60
54
48
78
72
66
60
54
48
–6 dBFS
–12 dBFS
–6 dBFS
0 dBFS
0 dBFS
–12 dBFS
0
2
4
6
8
10
12
0
5
10
15
20
25
Fout – MHz
Fout – MHz
Figure 3
Figure 4
† AV
= DV
= 5 V, IOUT
= 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, T = 25°C (unless otherwise
DD
noted.)
DD
FS
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
†
TYPICAL CHARACTERISTICS
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 70 MSPS
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 100 MSPS
78
72
66
60
54
48
78
72
66
60
54
48
–6 dBFS
–12 dBFS
–6 dBFS
–12 dBFS
0 dBFS
0 dBFS
0
10
20
30
40
0
10
20
30
40
50
Fout – MHz
Fout – MHz
Figure 5
Figure 6
SPURIOUS FREE DYNAMIC RANGE
vs
SPURIOUS FREE DYNAMIC RANGE
vs
AOUT AT FOUT = FCLOCK/5
AOUT AT FOUT = FCLOCK/11
78
72
66
60
54
48
78
72
66
60
54
48
2.27 MHz @ 25 MSPS
4.55 MHz @ 50 MSPS
5 MHz @ 25 MSPS
10 MHz @ 50 MSPS
6.36 MHz @ 70 MSPS
9.1 MHz @ 100 MSPS
20 MHz @ 100 MSPS
14 MHz @ 70 MSPS
–27 –24 –21 –18 –15 –12 –9 –6 –3
0
–27 –24 –21 –18 –15 –12 –9 –6 –3
0
Aout – dBFS
Aout – dBFS
Figure 7
Figure 8
† AV
= DV
= 5 V, IOUT
= 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, T = 25°C (unless otherwise
DD
noted.)
DD
FS
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
†
TYPICAL CHARACTERISTICS
DUAL TONE SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
CLOCK FREQUENCY AT FOUT = 2 MHZ
vs
AOUT AT FOUT = FCLOCK/7
78
–66
–72
–78
–84
3.38/3.63 MHz @ 25 MSPS
0.675/0.725 MHz @ 5 MSPS
72
6.75/7.25 MHz @ 50 MSPS
2nd Harmonic
3rd Harmonic
66
60
13.5/14.5 MHz
@ 100 MSPS
4th Harmonic
54
9.67/10.43 MHz
@ 70 MSPS
48
–30 –27 –24 –21 –18 –15 –12 –9 –6 –3
0
0
20
40
60
80
100
120
Aout – dBFS
Fclock – MSPS
Figure 9
Figure 10
SPURIOUS FREE DYNAMIC RANGE
vs
FULL-SCALE OUTPUT CURRENT
SPURIOUS FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY AT 100 MSPS
78
78
72
66
60
54
48
Fclock = 100 MSPS
Fout = 2.5 MHz
72
66
60
54
48
Differential @ –6 dBFS
Fout = 10 MHz
Fout = 40 MHz
Differential @ 0 dBFS
Single-ended @ –6 dBFS
Single-ended
@ 0 dBFS
Fout = 28.6 MHz
2
4
6
8
10 12 14 16 18 20
IoutFS – mA
0
5
10 15 20 25 30 35 40 45 50
Fout – MHz
Figure 11
Figure 12
† AV
= DV
= 5 V, IOUT
= 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, T = 25°C (unless otherwise
DD
DD
FS
A
noted.)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
†
TYPICAL CHARACTERISTICS
SPURIOUS FREE DYNAMIC RANGE
vs
TEMPERATURE AT 70 MSPS
78
72
66
60
54
48
Fout = 2 MHz
Fout = 10 MHz
Fout = 25 MHz
–40
–20
0
20
40
60
80
T
A
– °C
Figure 13
INTEGRAL NONLINEARITY
0.1
–0.0
–0.1
–0.2
–0.3
0
128
256
384
512
640
768
896
1024
Code
Figure 14
† AV
= DV
= 5 V, IOUT
= 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, T = 25°C (unless otherwise
DD
noted.)
DD
FS
A
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
†
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
0.2
0.1
0.0
–0.1
–0.2
0
128
256
384
512
640
768
896
1024
Code
Figure 15
SINGLE-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
Fout = 5 MHz at
Fclock = 50 MSPS
–70
–80
–90
–100
0
5
10
15
20
25
Frequency – MHz
Figure 16
SINGLE-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
Fout = 10 MHz at
Fclock = 100 MSPS
–100
0
10
20
30
40
50
Frequency – MHz
Figure 17
† AV
= DV
= 5 V, IOUT
= 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, T = 25°C (unless otherwise
FS A
DD
noted.)
DD
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
†
TYPICAL CHARACTERISTICS
DUAL-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Fclock = 100 MSPS
Fout1 = 13.2 MHz,
Fout2 = 14.2 MHz
0
10
20
30
40
50
Frequency – MHz
Figure 18
FOUR-TONE OUTPUT SPECTRUM
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Fclock = 50 MSPS
Fout1 = 6.25 MHz,
Fout2 = 6.75 MHz,
Fout3 = 7.25 MHz,
Fout4 = 7.75 MHz
0
5
10
15
20
25
Frequency – MHz
Figure 19
† AV
= DV
= 5 V, IOUT
= 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, T = 25°C (unless otherwise
DD
noted.)
DD
FS
A
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
The THS5651 architecture is based on current steering, combining high update rates with low power
consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are
capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current
of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents
thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc
offsets, even order distortion components, and increase signal output power by a factor of two. Major
advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic
performance. The DAC’s high output impedance of >300 kΩ and fast switching result in excellent dynamic
linearity (spurious free dynamic range SFDR).
The full-scale output current is set using an external resistor R
voltage reference source (1.2 V) and control amplifier. The current I
internally to provide a full-scale output current equal to 32 times I
from 20 mA down to 2 mA.
in combination with an on-chip bandgap
BIAS
through resistor R
. The full-scale current can be adjusted
is mirrored
BIAS
BIAS
BIAS
data interface and timing
The THS5651 comprises separate analog and digital supplies, i.e. AV
and DV . The digital supply voltage
DD
DD
can be set from 5.5 V down to 3 V, thus enabling flexible interfacing with external logic. The THS5651 provides
two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary
input data word format, whereas mode 1 (mode pin connected to DV ) sets a twos complement input
DD
configuration.
Figure 20 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge
of the input clock. The THS5651 provides for minimum setup and hold times (> 1 ns), allowing for noncritical
external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be
chosenarbitrarilyunderthetimingconstraintslistedinthedigitalspecificationstable. However, a50%dutycycle
will give optimum dynamic performance. Figure 21 shows a schematic of the equivalent digital inputs of the
THS5651, valid for pins D9–D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic thresholds
of DV /2 ±20%. Since the THS5651 is capable of being updated up to 100 MSPS, the quality of the clock and
DD
data input signals are important in achieving the optimum performance. The drivers of the digital data interface
circuitry should be specified to meet the minimum setup and hold times of the THS5651, as well as its required
min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above
conditions will result in the lowest data feed-through and noise. Additionally, operating the THS5651 with
reduced logic swings and a corresponding digital supply (DV ) will reduce data feed-through. Note that the
DD
update rate is limited to 67 MSPS for a digital supply voltage DV
of 3 V to 3.6 V.
DD
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
D[9:0]
Valid Data
t
s(DAC)
t
pd
0.1%
50%
DAC
90%
10%
Output
0.1%
r(IOUT)
(IOUT1 or
IOUT2)
t
t
h(D)
t
su(D)
t
d(D)
1/f
CLK
CLK
50%
50%
50%
50%
50%
50%
t
w(LPH)
Figure 20. Timing Diagram
Table 1. Input Interface Modes
MODE 0
MODE 1
MODE PIN CONNECTED TO
DV
FUNCTION/MODE
MODE PIN CONNECTED TO
DGND
DD
Input code format
Binary
Twos complement
DV
DD
External
Digital in
Internal
Digital in
Figure 21. Digital Equivalent Input
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
DAC transfer function
The THS5651 delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the
binaryinputwordhasthedecimalrepresentation1023. Formode1, theMSBisinverted(twoscomplementinput
format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0,
straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1
IOUT
IOUT2
FS
where IOUT is the full-scale output current. The output currents can be expressed as:
FS
CODE
1024
IOUT1
IOUT
FS
(1023 CODE)
1024
IOUT2
IOUT
FS
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads R or a transformer with equivalent input load resistance R . This would translate into
LOAD
LOAD
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
CODE
1024
VOUT1
VOUT2
IOUT1
IOUT2
R
R
IOUT
R
LOAD
LOAD
FS
(1023–CODE)
1024
IOUT
R
LOAD
LOAD
FS
The differential output voltage VOUT
can thus be expressed as:
DIFF
(2CODE–1023)
VOUT
VOUT1–VOUT2
IOUT
R
DIFF
FS
LOAD
1024
The latter equation shows that applying the differential output will result in doubling of the signal power delivered
to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and
IOUT2, which would lead to increased signal distortion.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
reference operation
The THS5651 comprises a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor R
. The bias current I
through resistor
BIAS
BIAS
R
is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current
BIAS
equals 32 times this bias current. The full-scale output current IOUT can thus be expressed as:
FS
32
V
EXTIO
BIAS
IOUT
32
I
BIAS
FS
R
where V
is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage
EXTIO
of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
C
of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference
EXT
can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference
can be disabled and overridden by an external reference by connecting EXTLO to AV . Capacitor C
hence be omitted. Terminal EXTIO thus serves as either input or output node.
may
DD
EXT
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R
or changing
BIAS
the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal
1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak
internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal
1 nF load, as shown in Figure 22. This provides the user with more flexibility and higher bandwidths, which are
specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to
AGND or left disconnected when an external control amplifier is used.
EXT Reference
Voltage
External
Control AMP
–
THS4041
+
AGND
SLEEP
1 nF
AV
DD
COMP1
AV
DD
AVDD
1.2 V
REF
Current Source Array
EXTLO
EXTIO
BIASJ
–
REF AMP
+
Internal
Control AMP
R
EXT
IOUT1 or IOUT2
Figure 22. Bypassing the Internal Reference and Control Amplifier
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
analog current outputs
Figure 23 shows a simplified schematic of the current source array output with corresponding switches.
Differential PMOS switches direct the current of each individual PMOS current source to either the positive
output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined
by the stack of the current sources and differential switches, and is typically >300 kΩ in parallel with an output
capacitance of 5 pF.
OutputnodesIOUT1andIOUT2haveanegativecompliancevoltageof–1V, determinedbytheCMOSprocess.
Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5651 device. The
positive output compliance depends on the full-scale output current IOUT and positive supply voltage AV
.
FS
DD
The positive output compliance equals 1.25 V for AV
= 5 V and IOUT = 20 mA. Exceeding the positive
DD
FS
compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion
performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1
and IOUT2 does not exceed 0.5 V (e.g. when applying a 50 Ω doubly terminated load for 20 mA full-scale output
current). Applications requiring the THS5651 output (i.e., OUT1 and/or OUT2) to extend its output compliance
should size R
accordingly.
LOAD
AV
DD
Current
Sources
Switches
IOUT1
IOUT2
Current Source Array
R
R
LOAD
LOAD
Figure 23. Equivalent Analog Current Output
Figure 24(a) shows the typical differential output configuration with two external matched resistor loads. The
nominalresistorloadof50Ω willgiveadifferentialoutputswingof2V whenapplyinga20mAfull-scaleoutput
PP
current. The output impedance of the THS5651 depends slightly on the output voltage at nodes IOUT1 and
IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 24(b) should be chosen.
In this I–V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The
complementary output should be connected to ground to provide a dc current path for the current sources
switchedto IOUT2. Note that the INL/DNL specifications for the THS5651 are measured with IOUT1 maintained
at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current determine the
valueofthefeedbackresistorR . CapacitorC filtersthesteepedgesoftheTHS5651currentoutput, thereby
FB
FB
reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate on
a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be selected if a
single-ended unipolar output is desirable.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
C
FB
R
FB
50 Ω
+)
100 Ω
–
+
IOUT1
IOUT2
IOUT1
IOUT2
+)
VOUT
–)
VOUT
–)
THS4001
THS4011
50 Ω
(a)
(b)
Figure 24. Differential and Single-Ended Output Configuration
The THS5651 can be easily configured to drive a doubly terminated 50 Ω cable. Figure 25(a) shows the
single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of
25 Ω. Node IOUT2 should be connected to ground or terminated with a resistor of 25 Ω. Differential-to-single
conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as
shown in Figure 25(b). This configuration provides maximum rejection of common-mode noise sources and
even order distortion components, thereby doubling the power to the output. The center tap on the primary side
of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the
ac performance of the THS5651 is optimum and specified using this differential transformer coupled output,
limiting the voltage swing at IOUT1 and IOUT2 to ±0.5 V.
50 Ω
1:1
50 Ω
VOUT
VOUT
IOUT1
IOUT2
IOUT1
IOUT2
100 Ω
50 Ω
50 Ω
50 Ω
25 Ω
(a)
(b)
Figure 25. Driving a Doubly Terminated 50 Ω Cable
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
sleep mode
The THS5651 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode
is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the THS5651 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal
capacitor value of 0.1 µF power down takes less than 5 µs, and approximately 3 ms to power backup. The
SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 22.
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
offset error
Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0.
gain error
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D or SINAD)
S/N+D or SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in
decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
output compliance range
The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the
output stage or breakdown may occur.
settling time
The time required for the output to settle within a specified error band.
glitch energy
The time integral of the analog value of the glitch transient.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
offset drift
The change in offset error versus temperature from the ambient temperature (T = 25°C) in ppm of full-scale
A
range per °C.
gain drift
The change in gain error versus temperature from the ambient temperature (T = 25°C) in ppm of full-scale
A
range per °C.
reference voltage drift
The change in reference voltage error versus temperature from the ambient temperature (T = 25°C) in ppm
A
of full-scale range per °C.
THS5651 evaluation board
An evaluation module (EVM) board for the THS5651 digital-to-analog converter is available for evaluation. This
board allows the user the flexibility to operate the THS5651 in various configurations. Possible output
configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs.
The digital inputs are designed to interface with the TMS320 C5000 or C6000 family of DSPs or to be driven
directly from various pattern generators with the onboard option to add a resistor network for proper load
termination.
See the THS56x1 Evaluation Module User’s Guide for more details (SLAU032).
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-Bit, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
•
21
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
Figure 27. Board Layout, Layer 1
Figure 28. Board Layout, Layer 2
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
Figure 29. Board Layout, Layer 3
Figure 30. Board Layout, Layer 4
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
Figure 31. Board Layout, Layer 5
Table 2. Bill of Materials
QTY
3
REF. DES
C1, C22, C31
PART NUMBER
1206ZC105KAT2A
DESCRIPTION
MFG.
Ceranucm 1 µF, 10 V, X7R, 10%
6.3 V, 4.7 µF, tantalum
AVX
4
C18, C19, C28, C35
C15, C24, C4
C25, C32
ECSTOJY475
ECSTOJY106
Panasonic
Panasonic
3
6.3 V, 10 µF, tantalum
0
Ceramic, not installed, 50 V, X7R, 10%
Ceramic, 0.01 µF, 50 V, X7R, 10%
Ceramic, 0.1 µF, 50 V, X7R, 10%
6
C14, C2, C20, C26, C29, C33 12065C103KAT2A
AVX
AVX
17
C10, C11, C12, C13, C16,
C17, C21, C23, C27, C3, C30,
C34, C5, C6, C7, C8, C9
12065C104KAT2A
2
4
1
1
D1, D2
AND/AND5GA or equivalent
27-43-037447
GREEN LED, 1206 size SM chip LED
Fair-Rite SM beads #27-037447
34-Pin header for IDC
FB1, FB2, FB3, FB4
FairRite
Samtec
Lumberg
J1
J2
TSW-117-07-L-D or equivalent
KRMZ2 or equivalent
2 Terminal screw connector,
2TERM_CON
1
1
3
0
3
1
4
J3
TSW-112-07-L-S or equivalent
KRMZ3 or equivalent
142-0701-206 or equivalent
142-0701-206 or equivalent
DO1608C-472
Single row 12-pin header
Samtec
J4
3 Terminal screw connector
Lumberg
J5, J6, J7
J8, J9
PCB Mount SMA jack, SMA_PCB_MT
PCB Mount SMA jack, not installed
DO1608C-series, DS1608C-472
1206 Chip resistor, 1.5K, 1/4 W, 1%
Johnson Components
Johnson Components
Coil Craft
L1, L2, L3
R1
1206
R10, R11, R4, R5
CTS/CTS766-163-(R)330-G-TR 8 Element isolated resistor pack, 33 Ω
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
APPLICATION INFORMATION
Table 2. Bill of Materials (Continued)
QTY
4
REF. DES
R12, R19, R7, R9
PART NUMBER
DESCRIPTION
MFG.
1206
1206
1206 Chip resistor, 33 Ω, 1/4 W, 1%
1206 Chip resistor, 0 Ω, 1/4 W, 1%
4 mm SM Pot, 5K
5
R13, R17. R2, R21, R8
1
R14
3214W-1-502 E or equivalent
Bourns
1
R15
1206
1206 Chip resistor, 2.94K, 1/4 W, 1%
1206 Chip resistor, 3K, 1/4 W, 1%
1206 Chip resistor, 49.94K, 1/4 W, 1%
1206 Chip resistor, 10K, 1/4 W, 1%
1206 Chip resistor, 10K, 1/4 W, 1%
1206 Chip resistor, 100K, 1/4 W, 1%
1206 Chip resistor, TBD, 1/4 W, 1%
1206 Chip resistor, 750K, 1/4 W, 1%
RF Transformer, T1-1T-KK81
1
R16
1206
3
R18, R24, R29
1206
3
R20, R3, R6
1206
1
R22
1206
1
R23
1206
1
R25
1206
4
R26, R27, R28, R30
1206
1
T1
T1-1T-KK81
SN74LVT245BDW
MiniCircuits
TI
2
U1, U2
Octal bus transceiver, 3-state,
SN74LVT245B
1
1
U3
U4
SN74AHCT1G00DBVR/
SN74AHC1G00DBVR
Single gate NAND, SN74AHC1G00
TI
TI
SN74AHCT1G32DBVR/
SN74AHCC1G32DBVR
Single 2 input positive or gate,
SN74AHC1G32
THS5641
THS5641IDW
DAC, 2.7–5.5 V, 8 Bit, 125 MHz
DAC, 2.7–5.5 V, 10 Bit, 125 MHz
DAC, 2.7–5.5 V, 12 Bit, 125 MHz
DAC, 2.7–5.5 V, 14 Bit, 125 MHz
Quad AND gate
TI
TI
TI
TI
TI
TI
THS5651
THS5651IDW
THS5661
THS5661IDW
THS5671
THS5647IDW
1
1
0
SN74ALVC08
LT1004D
SN74ALVC08D
LT1004CD-1-2/LT1004ID-1-2
AD1580BRT
Precision 1.2 V reference
NOT INSTALLED
Precision voltage reference, not
installed
1
4
3
2
THS3001
W2
THS3001CD/THS2001ID
THS3001 high-speed op amp
TI
TSW-102-07-L-S or equivalent
TSW-102-07-L-S or equivalent
TSW-102-07-L-S or equivalent
2 position jumper_.1’’ spacing, W2
3 position jumper_.1’’ spacing, W3
Samtec
Samtec
Samtec
W3
2X3_JUMPER
6-Pin header dual row, 0.025×0.1,
2X3_JUMPER
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/C 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
27
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IMPORTANT NOTICE
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