THS6052CDDA [TI]
暂无描述;
| 型号： | THS6052CDDA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 驱动器 |
| 文件： | 总33页 (文件大小：509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
D
D
Remote Terminal ADSL Line Driver
– Ideal for Both Full Rate ADSL and G.Lite
– Compatible With 1:1 Transformer Ratio
D
High Speed
– 120 MHz (–3 dB, G=1, ±12 V, R = 25 Ω)
– 1200 V/µs Slew Rate (G = 4, ±12 V)
L
Low 2.1 pA/√Hz Noninverting Current Noise
– Reduces Noise Feedback Through
Hybrid Into Downstream Channel
D
D
D
D
D
Low Distortion, Single-Ended, G = 4
– –79 dBc (250 kHz, 2 V , 100-Ω load)
pp
Low Power Shutdown (THS6043)
– 300-µA Total Standby Current
D
D
Wide Supply Voltage Range ±5 V to ±15 V
– Ideal for ±12-V Operation
Thermal Shutdown and Short-Circuit
Protection
Wide Output Swing
– 43-Vpp Differential Output Voltage,
Standard SOIC, SOIC PowerPAD and
TSSOP PowerPAD Package
R = 200 Ω, ±12-V Supply
L
D
High Output Current
– 350 mA (typ)
Evaluation Module Available
THS6043
SOIC (D) AND
TSSOP PowerPAD (PWP) PACKAGE
(TOP VIEW)
THS6042
SOIC (D) AND
SOIC PowerPAD (DDA) PACKAGE
(TOP VIEW)
D1 OUT
D1 IN–
D1 IN+
V
CC+
1
2
3
4
5
6
7
14
D1 OUT
D1 IN–
D1 IN+
V
CC+
1
2
3
4
8
7
6
5
13 D2 OUT
12 D2 IN–
11 D2 IN+
D2 OUT
D2 IN–
D2 IN+
V
CC–
N/C
V
CC–
10
9
N/C
GND
N/C
SHUTDOWN
N/C
8
description
The THS6042/3 is a high-speed line driver ideal for driving signals from the remote terminal to the central office
in asymmetrical digital subscriber line (ADSL) applications. It can operate from a ±12-V supply voltage while
drawing only 8.2 mA of supply current per channel. It offers low –79 dBc total harmonic distortion driving a 100-Ω
load (2 Vpp). The THS6042/3 offers a high 43-Vpp differential output swing across a 200-Ω load from a ±12-V
supply. The THS6043 features a low-power shutdown mode, consuming only 300 µA quiescent current per
channel. The THS6042/3 is packaged in standard SOIC, SOIC PowerPAD, and TSSOP PowerPAD packages.
+12 V
THS6042
RELATED PRODUCTS
Driver 1
50 Ω
+
_
V +
I
1:1
DEVICE
DESCRIPTION
750 Ω
175-mA, ±12 ADSL CPE line driver
THS6052/3
THS6092/3
OPA2677
THS6062
15.7 dBm
Delivered
to Telephone
Line
275-mA, +12 V ADSL CPE line driver
100 Ω
THS6042
Driver 2
380-mA, +12 V ADSL CPE line driver
±15 V to ± 5 V Low noise ADSL receiver
±6 V to 5 V Low noise ADSL receiver
210 Ω
50 Ω
+
_
V –
I
0.68 µF
OPA2822
750 Ω
–12 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
AVAILABLE OPTIONS
PACKAGED DEVICE
SOIC-8 PowerPAD SOIC-14
EVALUATION
MODULES
T
A
SOIC-8
(D)
TSSOP-14
(PWP)
(DDA)
(D)
THS6042EVM
THS6043EVM
0°C to 70°C
THS6042CD
THS6042ID
THS6042CDDA
THS6042IDDA
THS6043CD
THS6043ID
THS6043CPWP
THS6043IPWP
–40°C to 85°C
—
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
CC–
CC+
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V
CC
Output current (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mA
Differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 4 V
Maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Total power dissipation at (or below) 25°C free-air temperature . . . . . . . . . . . See Dissipation Ratings Table
Operating free-air temperature, T : Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature, T : Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 125°C
stg
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The THS6042 and THS6043 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected
toathermallydissipatingplaneforproperpowerdissipation. Failuretodosomayresultinexceedingthemaximumjunctiontemperature
which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD
thermally enhanced package.
DISSIPATION RATING TABLE
T
= 25°C
A
PACKAGE
θ
θ
T = 150°C
J
POWER RATING
JA
JC
‡
‡
‡
‡
‡
‡
D-8
DDA
D-14
PWP
95°C/W
45.8°C/W
66.6°C/W
38.3°C/W
9.2°C/W
26.9°C/W
1.32 W
2.73 W
1.88 W
37.5°C/W
1.4°C/W
3.3 W
‡
This data was taken using the JEDEC proposed high-K test PCB. For the JEDEC low-K test
PCB, the Θ is168°C/W for the D–8 package and 122.3°C/W for the D–14 package.
JA
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
recommended operating conditions
MIN NOM
MAX
±15
30
UNIT
Dual supply
Single supply
C-suffix
±5
10
Supply voltage, V
to V
V
CC+
CC–
0
70
Operating free-air temperature, T
°C
A
I-suffix
–40
85
electrical characteristics over recommended operating free-air temperature range, T = 25°C,
A
V
= ±12 V, R
= 750 Ω, R = 100 Ω (unless otherwise noted)
CC
(FEEDBACK)
L
dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
120
95
MAX
UNIT
G = 1, R = 560 Ω
F
R
R
R
= 25 Ω
= 100 Ω
= 25 Ω
G = 2, R = 500 Ω
V
CC
= ±6 V, ±12 V
= ±6 V, ±12 V
L
L
L
F
Small-signal bandwidth
BW
G = 4, R = 390 Ω
75
MHz
F
(–3 dB)
G = 4, R = 390 Ω
100
65
F
V
CC
G = 8, R = 280 Ω
F
V
CC
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±12 V
= ±6 V
1000
900
600
1400
1200
G = 2, R = 390 Ω,
F
V
= 5 V
O
pp
SR
Slew rate (see Note 2)
V/µs
= ±15 V
= ±12 V
G = 4, R = 750 Ω,
F
V
O
= 12 V
pp
R
= 100 Ω
L
G = 4, R = 750 Ω,
F
V
CC
= ±6 V
600
V
O
= 5 V
pp
NOTE 2: Slew rate is defined from the 25% to the 75% output levels.
noise/distortion performance
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
–79
UNIT
V
O(pp)
= 2 V
= 16 V
= 2 V
= 7 V
G = 4,
R
= 100 Ω,
L
Total harmonic distortion
(single-ended configuration)
(R = 390 Ω)
V
CC
= ±12 V, f = 250 kHz
V
V
V
–75
O(pp)
O(pp)
O(pp)
THD
dBc
–72
G = 4,
R
= 25 Ω,
= ±6 V, f = 250 kHz
L
F
V
V
CC
–68
V
n
Input voltage noise
+Input
= ±6 V, ±12 V
f = 10 kHz
2.2
2.1
11
nV/√Hz
pA/√Hz
CC
I
n
Input current noise
V
CC
= ±6 V, ±12 V, ±15 V
f = 10 kHz
–Input
f = 250 kHz ,
= 430 Ω,
V
R
= ±6 V, ±12 V,
= 100 Ω
CC
L
–71
–65
R
F
Crosstalk
V
O
= 2 Vpp, G = 4
dBc
f = 250 kHz ,
= 390 Ω,
V
CC
= ±6 V, ±12 V,
R
R = 25 Ω
L
F
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
electrical characteristics over recommended operating free-air temperature range, T = 25°C,
A
V
= ±12 V, R
= 750 Ω, R = 100 Ω (unless otherwise noted) (continued)
CC
(FEEDBACK) L
dc performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
16
21
5
UNIT
T
A
= 25°C
9.5
Input offset voltage
T
= full range
= 25°C
A
mV
T
A
1
V
V
V
= ±6 V, ±12 V
OS
CC
Differential offset voltage
Offset drift
T
= full range
= full range
= 25°C
7
A
T
A
20
µV/°C
T
A
3.5
10
12
5
– Input bias current
T
= full range
= 25°C
A
T
A
1
3.5
1
I
IB
+ Input bias current
= ±6 V, ±12 V
µA
CC
T
= full range
= 25°C
6
A
T
A
10
12
Differential input bias current
Open-loop transimpedance
T
A
= full range
Z
OL
R
= 1 kΩ
V = ±6 V, ±12 V
CC
MΩ
L
input characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
= 25°C
±9.6 ±10.1
±9.5
A
V
V
V
= ±12 V
CC
T
A
= full range
= 25°C
V
ICR
Input common-mode voltage range
V
T
A
±3.7
±3.6
59
±4.2
= ±6V
CC
CC
T
A
= full range
= 25°C
T
A
68
CMRR Common-mode rejection ratio
= ±6 V, ±12 V
V
T
A
= full range
55
+ Input
1.5
15
2
MΩ
Ω
R
C
Input resistance
I
i
– Input
Input capacitance
pF
output characteristics
PARAMETER
TEST CONDITIONS
MIN
±7.5
±4.1
TYP
±9.1
±4.6
MAX
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= ±12 V
= ±6 V
R
R
= 25 Ω
L
L
Single ended
100-mV overdrive
V
O
Output voltage swing
V
= ±12 V
= ±6 V
±10.3 ±10.8
= 100 Ω
±4.5
300
230
±4.9
350
260
400
15
R
R
R
= 25 Ω,
= 10 Ω,
= 0 Ω,
= ± 12 V
= ±6 V
L
L
L
I
I
Output current
mA
O
Short-circuit current
Output resistance
= ±12 V
mA
OS
r
Open loop
Ω
o
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
electrical characteristics over recommended operating free-air temperature range, T = 25°C,
A
V
= ±12 V, R
= 750 Ω, R = 100 Ω (unless otherwise noted) (continued)
CC
(FEEDBACK) L
power supply
PARAMETER
TEST CONDITIONS
MIN
±4.5
9
TYP
MAX
±16.5
33
UNIT
Dual supply
V
CC
Operating range
V
Single supply
T
= 25°C
8.2
7.4
10.5
11.5
9.5
A
V
CC
V
CC
V
CC
V
CC
= ±12 V
= ±6 V
= ±12 V
= ±6 V
T
A
= full range
= 25°C
Quiescent current (each driver)
Power supply rejection ratio
I
mA
dB
CC
T
A
T
A
= full range
= 25°C
10.5
T
A
–65
–62
–62
–60
–72
–69
T
A
= full range
= 25°C
PSRR
T
A
T
A
= full range
shutdown characteristics (THS6043 only)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= ±6 V, ±12 V, GND = 0 V
CC
V
V
Shutdown pin voltage for power up
Shutdown pin voltage for power down
0.8
V
IL(SHDN)
(GND Pin as Reference)
V
= ±6 V, ±12 V, GND = 0 V
CC
(GND pin as reference)
2
V
IH(SHDN)
I
t
t
I
I
Total quiescent current when in shutdown state
Disable time (see Note 3)
V
CC
V
CC
V
CC
V
CC
V
CC
= ±6 V, ±12 V
= ±12 V
0.3
0.5
0.2
40
0.7
mA
µs
CC(SHDN)
DIS
Enable time (see Note 3)
= ±12 V
µs
EN
Shutdown pin input bias current for power up
Shutdown pin input bias current for power down
= ±6 V, ±12 V
= ±6 V, ±12 V V
100
100
µA
µA
IL(SHDN)
= 3.3 V
50
IH(SHDN)
(SHDN)
NOTE 3: Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has
reached half of its final value.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Small and large signal output
Harmonic distortion
vs Frequency
1 – 6
7, 8, 9
13, 14, 15
vs Output voltage
vs Frequency
10, 11, 12,
16, 17, 18
V
I
Voltage noise and current noise
Quiescent current
vs Frequency
19
20
21
22
23
24
25
n, n
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Output current
V
V
V
Positive output voltage headroom
Negative output voltage headroom
Output voltage headroom
O
z
Closed loop output impedance
Quiescent current in shutdown mode
vs Frequency
o
vs Free-air temperature
Input offset voltage and
differential input offset voltage
V
IO
vs Free-air temperature
26
I
Input bias current
vs Free-air temperature
vs Frequency
27
28
IB
CMRR Common-mode rejection ratio
Crosstalk
vs Frequency
29
SR
Slew rate
vs Output voltage step
30
Shutdown response
31
Transimpedance and phase
Overdrive recovery
vs Frequency
32
33, 34
35, 36
Small and large signal pulse response
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
SMALL AND LARGE SIGNAL OUTPUT
SMALL AND LARGE SIGNAL OUTPUT
vs
vs
FREQUENCY
FREQUENCY
24
18
24
18
V
= 8 V
O
O
PP
PP
PP
V
= 8 V
= 2 V
O
O
PP
PP
V
= ±12 V
CC
G = 4
R = 750 Ω
V
= ±12 V
CC
G = 4
R = 390 Ω
12
6
12
6
f
f
R
= 100 Ω
V
= 2 V
L
R = 100 Ω
L
V
0
–6
0
–6
V
= 0.5 V
O
V
= 0.5 V
PP
O
–12
–12
V
O
= 0.125 V
100 K
PP
V
O
= 0.125 V
100 K
PP
–18
–24
–18
–24
10 K
10 M
100 M
1 M
1 G
10 K
10 M
100 M
1 M
1 G
f – Frequency – Hz
f – Frequency – Hz
Figure 1
Figure 2
SMALL AND LARGE SIGNAL OUTPUT
SMALL AND LARGE SIGNAL OUTPUT
vs
vs
FREQUENCY
FREQUENCY
30
24
30
24
V
= 16 V
O
PP
PP
PP
V
= 16 V
O
PP
PP
V
= ±12 V
CC
G = 8
R = 280 Ω
V
= ±12 V
CC
G = 8
R = 750 Ω
18
12
18
12
f
f
R
= 100 Ω
V
= 4 V
L
R = 100 Ω
L
O
V
= 4 V
O
6
0
6
0
V
= 1 V
O
V
= 1 V
PP
O
–6
–6
V
O
= 0.25 V
100 K
PP
V
O
= 0.25 V
100 K
PP
–12
–18
–12
–18
10 K
10 M
100 M
1 M
1 G
10 K
10 M
100 M
1 M
1 G
f – Frequency – Hz
f – Frequency – Hz
Figure 3
Figure 4
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
SMALL AND LARGE SIGNAL OUTPUT
SMALL AND LARGE SIGNAL OUTPUT
vs
vs
FREQUENCY
FREQUENCY
24
18
24
18
V
= 8 V
= 2 V
O
O
PP
PP
V
= 8 V
= 2 V
O
O
PP
PP
V
= ±6 V
CC
G = 4
R = 750 Ω
V
= ±6 V
CC
G = 4
R = 390 Ω
12
6
12
6
f
f
R
= 25 Ω
V
L
R = 25 Ω
L
V
0
–6
0
–6
V
O
= 0.5 V
PP
V
O
= 0.5 V
PP
–12
–12
V
O
= 0.125 V
100 K
PP
V
O
= 0.125 V
100 K
PP
–18
–24
–18
–24
10 K
10 M
100 M
1 M
1 G
10 K
10 M
100 M
1 M
1 G
f – Frequency – Hz
f – Frequency – Hz
Figure 5
Figure 6
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
–70
–75
–80
–85
–90
–95
–100
–70
–75
–80
–85
–90
–95
–100
2nd Order
2nd Order
V
= ±10 V
CC
Gain = 4
= 100 Ω
V
= ±15 V
CC
Gain = 4
= 100 Ω
R
L
R
L
R = 390 Ω
f = 250 KHz
f
R = 390 Ω
f = 250 KHz
f
3rd Order
3rd Order
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
V
O
– Output Voltage – V
V
O
– Output Voltage – V
PP
PP
Figure 7
Figure 8
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
FREQUENCY
–70
–75
–80
–30
–40
–50
–60
–70
–80
V
= ±5.4 V
CC
Gain = 4
= 100 Ω
V
= ±15 V
CC
Gain = 4
= 100 Ω
R
2nd Order
L
R
L
2nd Order
R = 390 Ω
f = 250 KHz
f
R = 390 Ω
f
V
O
= 2 V
PP
–85
–90
3rd Order
–95
–90
3rd Order
5
–100
–100
0
1
2
3
4
6
7
100 k
1 M
10 M
100 M
V
O
– Output Voltage – V
f – Frequency – Hz
PP
Figure 9
Figure 10
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
V
= ±10 V
V
= ±5.4 V
CC
Gain = 4
= 100 Ω
CC
Gain = 4
= 100 Ω
R
R
L
L
2nd Order
2nd Order
R = 390 Ω
R = 390 Ω
f
f
V
O
= 2 V
PP
V
O
= 2 V
PP
3rd Order
3rd Order
–90
–90
–100
–100
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
f – Frequency – Hz
f – Frequency – Hz
Figure 11
Figure 12
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
–70
–75
–80
–85
–90
–70
–75
–80
–85
–90
2nd Order
2nd Order
V
= ±10 V
CC
Gain = 4
= 25 Ω
V
= ±15 V
CC
Gain = 4
= 25 Ω
R
L
R = 390 Ω
f = 250 KHz
f
R
L
R = 390 Ω
f = 250 KHz
f
3rd Order
3rd Order
–95
–95
–100
–100
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
V
O
– Output Voltage – V
PP
V
O
– Output Voltage – V
PP
Figure 13
Figure 14
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
FREQUENCY
–70
–75
–80
–85
–90
–30
–40
–50
–60
–70
–80
2nd Order
2nd Order
V
= ±5.4 V
CC
Gain = 4
= 25 Ω
R
L
R = 390 Ω
f = 250 KHz
f
3rd Order
3rd Order
V
= ±15 V
CC
Gain = 4
= 25 Ω
R
L
–95
R = 390 Ω
f
–90
V
O
= 2 V
PP
–100
–100
0
1
2
3
4
5
6
7
100 k
1 M
10 M
100 M
f – Frequency – Hz
V
O
– Output Voltage – V
PP
Figure 15
Figure 16
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
2nd Order
2nd Order
3rd Order
3rd Order
V
= ±10 V
CC
Gain = 4
= 25 Ω
V
= ±5.4 V
CC
Gain = 4
R = 25 Ω
L
R
L
R = 390 Ω
f
O
R = 390 Ω
f
–90
–90
V
= 2 V
PP
V
= 2 V
O PP
–100
–100
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
f – Frequency – Hz
f – Frequency – Hz
Figure 17
Figure 18
VOLTAGE NOISE AND CURRENT NOISE
QUIESCENT CURRENT
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
100
10
V
T
= ±5 V to ±15 V
= 25°C
CC
A
Per Amplifier
9.5
9
V
CC
= ±12 V
8.5
IN–
8
10
7.5
V
CC
= ±6 V
IN+
7
6.5
V
n
6
1
10
5.5
100
1 k
10 k
100 k
–40
–20
0
20
40
60
80
100
f – Frequency – Hz
T
A
– Free-Air Temperature – °C
Figure 19
Figure 20
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
POSITIVE OUTPUT VOLTAGE HEADROOM
NEGATIVE OUTPUT VOLTAGE HEADROOM
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.35
1.3
–1.05
–1.1
(+V
CC
– V )
O
(–V
CC
– V )
O
V
= ±6 V, R = 25 Ω
L
CC
V
CC
= ±6 V, R = 100 Ω
L
1.25
1.2
–1.15
–1.2
V
CC
= ±12 V, R = 100 Ω
L
V
CC
= ±12 V, R = 100 Ω
L
1.15
V
CC
= ±6 V, R = 100 Ω
–1.25
L
V
CC
= ±6 V, R = 25 Ω
L
1.1
–1.3
1.05
–1.35
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 21
Figure 22
OUTPUT VOLTAGE HEADROOM
CLOSED LOOP OUTPUT IMPEDANCE
vs
vs
OUTPUT CURRENT
FREQUENCY
100
10
4
| V
| – | V
|
O
V
R
= ± 5 V to ± 15 V
CC
= ±12 V and ±6 V
CC
= 100 Ω
V
CC
L
R = 750 Ω
3.5
f
Gain = 8
3
2.5
2
Gain = 4
1
Gain = 2
0.1
1.5
1
0.01
0
100
I
200
300
400
500
100 K
1 M
10 M
f – Frequency – Hz
100 M
1 G
– Output Current – | mA |
O
Figure 23
Figure 24
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE AND
DIFFERENTIAL INPUT OFFSET VOLTAGE
vs
QUIESCENT CURRENT IN SHUTDOWN MODE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.5
0.4
0.3
0.2
0.1
0
0.4
0.35
0.3
12
11
10
Both Amplifiers
V
= ± 6 V to ± 12 V
CC
V
CC
= ± 12 V
V
= ± 6 V
CC
0.25
9
V
OS
0.2
8
7
Differential V
OS
0.15
–40
–20
0
20
40
60
80
100
–40
–20
0
T
20
40
60
80
100
T
A
– Free-Air Temperature – °C
– Temperature – °C
A
Figure 25
Figure 26
COMMON-MODE REJECTION RATIO
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
vs
FREQUENCY
80
5
Gain = 2
R = 1 kΩ
f
V
CC
= ±6 V to ± 12 V
4.5
4
V
R
= +12 V
= 100 Ω
CC
L
70
60
50
40
30
20
I
IB–
3.5
3
V
R
= +6 V
= 25 Ω
CC
L
2.5
2
1.5
1
I
IB+
0.5
0
10 k
100 k
1 M
10 M
100 M
–40
–20
0
20
40
60
80
100
f – Frequency – Hz
T
A
– Temperature – °C
Figure 27
Figure 28
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
SLEW RATE
vs
OUTPUT VOLTAGE STEP
CROSSTALK
vs
FREQUENCY
1800
1600
1400
1200
1000
800
0
–10
–20
V
= ±6 V to ±12 V
Gain = 4
= 100 Ω
R = 750 Ω
f
CC
Gain = 4
V
CC
= ±15 V
R
L
R = 390 Ω
f
R
= 25 Ω
L
–30
–40
–50
V
CC
= ±12 V
R = 430 Ω
f
L
R
= 100 Ω
V
CC
= ±6 V
600
–60
–70
400
200
0
–80
–90
0
2
4
6
8
10
12
14
16
100 k
1 M
10 M
100 M
Output Voltage Step – V
f – Frequency – Hz
Figure 29
Figure 30
TRANSIMPEDANCE AND PHASE
vs
FREQUENCY
SHUTDOWN RESPONSE
7
6
140
3
1
45
V
R
= ±5 V to ±15 V
CC
= 1 kΩ
L
V
(SHDN)
120
100
80
0
5
–1
–3
–5
–7
Transimpedance
–45
4
3
–90
Phase
2
60
–135
Gain = 8
+12 V
1
–9
V
CC
R = 750 Ω
V
O
40
20
–180
–225
f
–11
0
R
= 100 Ω
L
–13
–1
12
16
20
0
4
8
1 K
10 K
100 K
f – Frequency – Hz
1 M
10 M 100 M
1 G
t – Time – µs
Figure 31
Figure 32
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
OVERDRIVE RECOVERY
OVERDRIVE RECOVERY
16
12
8
2
16
12
8
2
V
I
Gain = 8
= ±12 V
Gain = –8
V
CC
R = 750 Ω
1.5
V
= ±12 V
CC
R = 750 Ω
1.5
f
L
R
= 100 Ω
f
R
= 100 Ω
1
L
1
V
I
V
O
0.5
0
4
0
4
0
0.5
0
–4
–8
–0.5
–1
–4
–8
–0.5
–1
V
O
–1.5
–2
–12
–16
–1.5
–2
–12
–16
0
40
80
120
160
200
t – Time – ns
0
40
80
120
160
200
t – Time – ns
Figure 33
Figure 34
SMALL AND LARGE SIGNAL PULSE RESPONSE
SMALL AND LARGE SIGNAL PULSE RESPONSE
0.6
6
4
2
6
4
2
0.6
0.4
0.2
Large Signal
Gain = –8
= ±12 V
Gain = 8
= ±12 V
V
V
CC
R = 750 Ω
CC
R = 750 Ω
f
0.4
0.2
f
R
= 100 Ω
R
= 100 Ω
Small Signal
L
L
0
0
0
0
–2
–2
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
Small Signal
–4
–6
–4
–6
Large Signal
120
0
40
80
160
200
0
40
80
120
160
200
t – Time – ns
t – Time – ns
Figure 35
Figure 36
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
The THS6042/3 contain two independent operational amplifiers. These amplifiers are current feedback
topology amplifiers made for high-speed operation. They have been specifically designed to deliver the full
power requirements of ADSL and therefore can deliver output currents of at least 230 mA at full output voltage.
The THS6042/3 are fabricated using the Texas Instruments 30-V complementary bipolar process, HVBiCOM.
This process provides excellent isolation and high slew rates that result in the device’s excellent crosstalk and
extremely low distortion.
ADSL
The THS6042/3 were primarily designed as line drivers for ADSL (asymmetrical digital subscriber line). The
driver output stage has been sized to provide full ADSL power levels of 13 dBm onto the telephone lines.
Although actual driver output peak voltages and currents vary with each particular ADSL application, the
THS6042/3 are specified for a minimum full output current of 230 mA at ±6 V and 300 mA at the full output
voltage of ±12 V. This performance meets the demanding needs of ADSL at the client side end of the telephone
line. A typical ADSL schematic is shown in Figure 37.
The ADSL transmit band consists of 255 separate carrier frequencies each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as
low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or creates intermodulation products that interfere with other ADSL carrier frequencies.
The THS6042/3 have been specifically designed for ultra low distortion by careful circuit implementation and
by taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figures 7 – 15. In the differential driver configuration, the second order
harmonics tend to cancel out. Thus, the dominant total harmonic distortion (THD) is primarily due to the third
order harmonics. Additionally, distortion should be reduced as the feedback resistance drops. This is because
the bandwidth of the amplifier increases, which allows the amplifier to react faster to any nonlinearities in the
closed-loop system. Another significant point is the fact that distortion decreases as the impedance load
increases. This is because the output resistance of the amplifier becomes less significant as compared to the
output load resistance.
Even though the THS6042/3 are designed to drive ADSL signals that have a maximum bandwidth of 1.1 MHz,
reactive loading from the transformer can cause some serious issues. Most transformers have a resonance
peak typically occurring from 20 MHz up to 150 MHz depending on the manufacturer and construction
technique. This resonance peak can cause some serious issues with the line driver amplifier such as small
high-frequency oscillations, increased current consumption, and/or ringing. Although the series termination
resistor helps isolate the transformer’s resonance from the line-driver amplifier, additional means may be
necessary to eliminate the effects of a reactive load. The simplest way is to add a snubber network, also known
as a zoebel network, in parallel with the transformer as shown by R
and C
in Figure 36. At high
(SNUB)
(SNUB)
frequencies, where the transformer’s impedance becomes very high at its resonance frequency (ex: 1 kΩ @
100 MHz), the snubber provides a resistive load to the circuit. The value for R should initially be set to
(SNUB)
the impedance presented by the transformer within its pass-band. An example of this would be to use a 100-Ω
resistor for a 1:1 transformer or a 25-Ω resistor for a 1:2 transformer. The value for C should be chosen
(SNUB)
such that the –3 dB frequency is about 5 times less than the resonance frequency. For example,if the resonance
frequencyisat100MHz, theimpedanceofC shouldbeequaltoR at20MHz. Thisleadstoavalue
(SNUB)
(SNUB)
of C
= 1 / (2 π f R
), or approximately 82 pF. This should only be used as a starting point. The final
(SNUB)
(SNUB)
values will be dictated by actual circuit testing.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
ADSL (continued)
One problem in the ADSL CPE area is noise. It is imperative that signals received off the telephone line have
as high a signal-to-noise ratio (SNR) as possible. This is because of the numerous sources of interference on
the line. The best way to accomplish this high SNR is to have a low-noise receiver such as the THS6062 or
OPA2822 on the front-end. Even if the receiver has very low noise characteristics, noise could be dominated
by the line driver amplifier. The THS6042/3 were primarily designed to circumvent this issue.
The ADSL standard, ANSI T1.413, stipulates a noise power spectral density of –140 dBm/Hz, which is
equivalent to 31.6 nV/√Hz for a 100-Ω system. Although many amplifiers can reach this level of performance,
actual ADSL system testing has indicated that the noise power spectral density may be required to have ≤ –150
dBm/Hz, or ≤ 10 nV/√Hz. With a transformer ratio of 1:2, this number reduces to less than 5 nV/√Hz. The
THS6042/3, with an equivalent input noise of 2.2 nV/√Hz, is an excellent choice for this application. Coupled
with a low 2.1 pA/√Hz noninverting current noise, a very low 11 pA/√Hz inverting current noise, and low value
resistors, the THS6042/3 ensures that the received signal SNR is as high as possible.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
ADSL (continued)
+12 V
+
0.1 µF
THS6042
Driver 1
10 µF
50 Ω
+
_
V +
I
R
C
(SNUB)
1:1
750 Ω
Telephone Line
100 Ω
(SNUB)
1 µF
210 Ω
499 Ω
+12 V
1 kΩ
THS6042
Driver 2
0.1 µF
0.68 µF
499 Ω
50 Ω
+
_
V –
I
–
V
O+
+
THS6062
Receiver 1
750 Ω
10 µF
499 Ω
0.1 µF
+
–12 V
1 kΩ
499 Ω
–
V
O–
+
THS6062
Receiver 2
–12 V
0.1 µF
Figure 37. THS6042 ADSL Application With 1:1 Transformer Ratio
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise
model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input, while VFB amplifiers usually only specify one noise current parameter. The noise model is shown
in Figure 38. This model includes all of the noise sources as follows:
•
•
•
•
e = Amplifier internal voltage noise (nV/√Hz)
n
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
e
= Thermal voltage noise associated with each resistor (e = 4 kTR )
Rx x
Rx
e
Rs
e
n
R
Noiseless
S
+
_
e
ni
e
no
IN+
e
Rf
R
F
e
Rg
IN–
R
G
Figure 38. Noise Model
The total equivalent input noise density (e ) is calculated by using the following equation:
ni
2
) ǒIN ) RSǓ2
ǒ
Ǔ
) 4 kTR ) 4 kTǒR GǓ
2
Ǹ
ǒ Ǔ
) ǒIN– R G Ǔ
e
+
e
ø R
ø R
n
s
ni
F
F
Where:
–23
k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
R || R = Parallel resistance of R and R
F
G
F
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the
ni
overall amplifier gain (A ).
V
R
F
+ e ǒ1 ) Ǔ(Noninverting Case)
e
+ e
A
no
ni
R
G
ni
V
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel
G
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares
S
n
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
2
ȱ e ȳ
ni
NF + 10log
ȧ ȧ
2
ǒe
Ǔ
Ȳ ȴ
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
ȱ
ȳ
2ȣ
2
ȡ
) ǒIN ) R
Ǔ
S
ǒe Ǔ
ȧ
ȧ
n
ȧ
ȧ
ȧ
ȧ
Ȣ
ꢀ
ȧ
ȧ
ȧ
ȧ
NF + 10logȧ1 )
4 kTR
S
ȧ
Ȳ
ȴ
Figure 39 shows the noise figure graph for the THS6042/3.
16
f = 10 kHz
= 25°C
T
A
14
12
10
8
6
4
2
0
10
100
1 k
10 k
R
– Source Resistance – Ω
S
Figure 39. Noise Figure vs Source Resistance
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
device protection features
The THS6042/3 have two built-in features that protect the devices against improper operation. The first
protection mechanism is output current limiting. Should the output become shorted to ground, the output current
is automatically limited to the value given in the data sheet. While this protects the output against excessive
current, the device internal power dissipation increases due to the high current and large voltage drop across
the output transistors. Continuous output shorts are not recommended and could damage the device.
The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above
approximately 180_C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown
circuit automatically turns the device back on.
thermal information – PowerPAD
The THS6042/3 are available packaged in thermally-enhanced PowerPAD packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 40(a) and Figure 40(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 40(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. This
is discussed in more detail in the PCB design considerations section of this document.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 40. Views of Thermally Enhanced PWP Package
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
PCB design considerations
Proper PCB design techniques in two areas are important to assure proper operation of the THS6042/3. These
areas are high-speed layout techniques and thermal-management techniques. Because the devices are
high-speed parts, the following guidelines are recommended.
D
Ground plane – It is essential that a ground plane be used on the board to provide all components with a
low inductive ground connection. Although a ground connection directly to a terminal of the THS6042/3 is
not necessarily required, it is highly recommended that the thermal pad of the package be tied to ground.
This serves two functions. It provides a low inductive ground to the device substrate to minimize internal
crosstalk and it provides the path for heat removal.
D
Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This
isespeciallytrueinthenoninvertingconfiguration. AnexampleofthiscanbeseeninFigure41, whichshows
what happens when a 2.2-pF capacitor is added to the inverting input terminal in the noninverting
configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of
the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While
the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is
because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in
the noninverting configuration. This can be seen in Figure 42, where a 22-pF capacitor adds only 0.9 dB
of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor
decreases. While this can initally appear to be a faster and better system, overshoot and ringing are more
likely to occur under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input
node should always be performed for stable operation.
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
6
4
2
1
V
= ±12 V
C = 22 pF
i
CC
Gain = 1
C = 2.2 pF
i
R
= 50 Ω
= 0.1 V
L
V
O
0
2
0
V
= ±12 V
CC
Gain = –1
–1
R
= 50 Ω
= 0.1 V
L
V
O
–2
–3
–4
–5
–6
–7
C = 0 pF
i
(Stray C Only)
–2
C = 0 pF
(Stray C Only)
i
–4
–6
–8
C in
750 Ω
750 Ω
R
g
–
+
V
O
V
–
+
I
V
I
V
O
50 Ω
C in
50 Ω
50 Ω
R
= 50 Ω
L
–10
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f – Frequency – Hz
f – Frequency – Hz
Figure 41
Figure 42
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
PCB design considerations (continued)
D
D
Proper power supply decoupling – Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the
supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible
tothesupplyterminal. Asthisdistanceincreases, theinductanceintheconnectingetchmakesthecapacitor
less effective. The designer should strive for distances of less than 0.1 inches between the device power
terminal and the ceramic capacitors.
Differential power supply decoupling – The THS6042/3 were designed for driving low-impedance
differential signals. The 50-Ω load which each amplifier drives causes large amounts of currents to flow from
amplifier to amplifier. Power supply decoupling for differential current signals must be accounted for to
ensure low distortion of the THS6042/3. By simply connecting a 0.1-µF to 1-µF ceramic capacitor from the
+V
pin to the –V
pin, differential current loops will be minimized (see Figure 37). This will help keep
CC
CC
the THS6042/3 operating at peak performance.
Because of its power dissipation, proper thermal management of the THS6042/3 is required. Even though the
THS6042 and THS6043 PowerPADs are different, the general methodology is the same. Although there are
many ways to properly heatsink these devices, the following steps illustrate one recommended approach for
a multilayer PCB with an internal ground plane. Refer to Figure 43 for the following steps.
Thermal pad area (0.15 x 0.17) with 6 vias
(Via diameter = 13 mils)
Figure 43. THS6043 PowerPAD PCB Etch and Via Pattern – Minimum Requirements
1. Place 6 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept small
so that solder wicking through the holes is not a problem during reflow.
2. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This will
help dissipate the heat generated from the THS6042/3. These additional vias may be larger than the 13 mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered, therefore, wicking is generally not a problem.
3. Connect all holes to the internal ground plane.
4. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Webconnectionshaveahighthermalresistanceconnectionthatisusefulforslowingtheheat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS6042/3 package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated through hole.
5. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with
its 6 holes. The bottom-side solder mask should cover the 6 holes of the thermal pad area. This eliminates
the solder from being pulled away from the thermal pad area during the reflow process.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
PCB design considerations (continued)
6. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.
7. Withthesepreparatorystepsinplace, theTHS6042/3issimplyplacedinpositionandrunthroughthesolder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
The actual thermal performance achieved with the THS6042/3 in their PowerPAD packages depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ , is about 95°C/W for the SOIC–8 (D) package, 45.8°C/W for the DDA
JA
package, 66.6°C/W for the SOIC–14 (D) package, and 37.5°C/W for the PWP package. Although the maximum
recommended junction temperature (T ) is listed as 150°C, performance at this elevated temperature will suffer.
J
To ensure optimal performance, the junction temperature should be kept below 125°C. Above this temperature,
distortion will tend to increase. Figure 44 shows the recommended power dissipation with a junction
temperature of 125°C. If no solder is used to connect the PowerPAD to the PCB, the θ
will increase
JA
dramatically with a vast reduction in power dissipation capability. For a given θ and a maximum junction
JA
temperature, the power dissipation is calculated by the following formula:
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
= Power dissipation of THS6042/3 (watts)
= Maximum junction temperature allowed in the design (125°C recommended)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case (D–8 =38.3°C/W, DDA = 9.2°C/W,
D–14 = 26.9°C/W, PWP = 1.4°C/W)
= Thermal coefficient from case to ambient
JC
CA
5
PWP
T
J
= 125 °C
θ
= 37.5 °C/W
JA
DDA
4
3
2
1
θ
= 45.8 °C/W
JA
D-14
= 66.6 °C/W
θ
JA
D-8
θ
= 95 °C/W
JA
0
–40
–20
0
20
40
60
80
100
T – Free-Air Temperature – °C
a
NOTE: Results are with no air flow and PCB size = 3”× 3”
2 oz. trace and copper pad with solder unless otherwise noted.
Figure 44. Maximum Power Dissipation vs Free-Air Temperature
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
PCB design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multiamplifier devices. Because these devices have linear output stages (Class-AB), most
of the heat dissipation is at low output voltages with high output currents. Figure 45 and Figure 46 show this
effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient
temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is
considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure
may result. When using V
= ±6 V, there is generally not a heat problem, even with SOIC packages.
CC
However, when using V
= ±12 V, the SOIC package is severely limited in the amount of heat it can dissipate.
CC
The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD
devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane
to fully use the heat dissipation properties of the PowerPAD. The standard SOIC package, on the other hand,
is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θ decreases and the heat dissipation capability increases. The currents and voltages shown in these
JA
graphs are for the total package.
MAXIMUM RMS OUTPUT CURRENT
MAXIMUM RMS OUTPUT CURRENT
vs
vs
RMS OUTPUT VOLTAGE (DUE TO THERMAL LIMITS)
RMS OUTPUT VOLTAGE (DUE TO THERMAL LIMITS)
1000
1000
Both Channels
J
A
V
= ±6 V
V
= ±12 V
Both Channels
J
A
CC
CC
T
T
= 150°C
= 50°C
T
T
= 150°C
= 50°C
Maximum Output
Current Limit Line
Maximum Output
Current Limit Line
PWP
= 37.5°C/W
θ
JA
DDA
= 45.8°C/W
JA
θ
PWP
θ
= 37.5°C/W
JA
DDA
JA
100
100
θ
= 45.8°C/W
SO-14 Package
= 67°C/W
θ
SO-14 Package
= 67°C/W
JA
High-K Test PCB
θ
JA
High-K Test PCB
SO-8 Package
= 95°C/W
θ
JA
High-K Test PCB
Safe
Operating
Area
SO-8 Package
= 95°C/W
θ
JA
High-K Test PCB
10
10
0
1
2
3
4
5
6
0
2
4
6
8
10
12
V
O
– RMS Output Voltage – V
V
O
– RMS Output Voltage – V
Figure 45
Figure 46
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
recommended feedback and gain resistor values
As with all current feedback amplifiers, the bandwidth of the THS6042/3 is an inversely proportional function
of the value of the feedback resistor. This can be seen from Figures 1 to 6. The recommended resistors for the
optimum frequency response are shown in Table 1. These should be used as a starting point and once optimum
values are found, 1% tolerance resistors should be used to maintain frequency response characteristics.
Because there is a finite amount of output resistance of the operational amplifier, load resistance can play a
major part in frequency response. This is especially true with these drivers, which tend to drive low-impedance
loads. This can be seen in Figures 1–6. As the load resistance increases, the output resistance of the amplifier
becomes less dominant at high frequencies. To compensate for this, the feedback resistor may need to be
changed. For most applications, a feedback resistor value of 750 Ω is recommended, which is a good
compromise between bandwidth and phase margin that yields a very stable amplifier.
Table 1. Recommended Feedback (R ) Values for Optimum Frequency Response
f
R
= 25 Ω
R = 100 Ω
L
L
GAIN
V
= ±6 V
V
= ±12 V
V
= ±6 V
CC
620 Ω
V
= ±12 V
CC
680 Ω
CC
560 Ω
CC
510 Ω
1
2, –1
4
470 Ω
270 Ω
200 Ω
430 Ω
240 Ω
200 Ω
430 Ω
270 Ω
200 Ω
390 Ω
240 Ω
200 Ω
8
Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the
bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback
amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value
of the gain resistor to increase or decrease the overall amplifier gain.
Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and may increase the distortion. Decreasing the feedback resistance too low may
increase the bandwidth, but an increase in the load on the output may cause distortion to increase instead of
decreasing. It is also important to know that decreasing load impedance increases total harmonic distortion
(THD). Typically, the third order harmonic distortion increases more than the second order harmonic distortion.
This is illustrated in Figure 10 to 12 and Figures 16 to 18.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
shutdown control
The THS6043 is essentially the same amplifier as the THS6042. The only difference is the added flexibility of
a shutdown circuit. When the shutdown pin signal is low, the THS6043 is active. But, when a shutdown pin is
high (≥2 V), the THS6043 is turned off. The shutdown logic is not latched and should always have a signal
applied to it. To help ensure a fixed logic state, an internal 50 kΩ resistor to GND is utilized. An external resistor,
such as a 3.3 kΩ, to GND may be added to help improve noise immunity within harsh environments. If no
external resistor is utilized and SHDN pin is left unconnected, the THS6043 defaults to a power-on state. A
simplified circuit can be seen in Figure 47.
+V
CC
To Internal
Bias Circuitry
Control
SHDN
50 kΩ
GND
GND
–V
CC
Figure 47. Simplified THS6043 Shutdown Control Circuit
One aspect of the shutdown feature, which is often over-looked, is that the amplifier does not have a largeoutput
impedance while in shutdown mode. This is due to the R and R resistors. This effect is true for any amplifier
F
G
connected as an amplifier with gains >1. The internal circuitry may be powered down and in a high-impedance
state, buttheresistorsarealwaysthere. Thisallowsthesignaltoflowthroughtheseresistorsandintotheground
connection. Figure 48 shows the results of the output impedance with no feedback resistor and a typically
configured amplifier.
1000
V
CC
= ±5 V to ±15 V
Open Loop
100
10
1
0.1
Gain = –8
R
= 750 Ω
F
0.01
10 K
100 K
1 M
10 M
100 M
1 G
f – Frequency – Hz
Figure 48. Output Impedance In Shutdown Mode
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6042/3 has been internally compensated to maximize its bandwidth
and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on
the output decreases the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 5 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 49. Keep in mind that stray capacitance on the output is also considered
capacitive loading, whether or not it is there on purpose. A minimum value of 5 Ω should work well for most
applications. In ADSL systems, setting the series resistor value to 12.4 Ω both isolates any capacitance loading
and provides the proper line impedance matching at the source end.
750 Ω
100 Ω
_
12.4 Ω
Output
+
C
+ C
L
Input
(Stray)
Figure 49. Driving a Capacitive Load
general configurations
A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6042/3,
like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors
directly from the output to the inverting input is not recommended. This is because, at high frequencies, a
capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when
using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily
implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an
RC-filter at the noninverting terminal of the operational-amplifier (see Figure 50).
R
R
F
G
V
R
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
1 ) sR1C1
–
I
G
V
O
+
V
I
1
f
+
R1
–3dB
2pR1C1
C1
Figure 50. Single-Pole Low-Pass Filter
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
APPLICATION INFORMATION
general configurations (continued)
If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because
oftheirhighslew-ratesandhighbandwidths, CFBamplifierscancreateveryaccuratesignalsandhelpminimize
distortion. An example is shown in Figure 51.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 –
)
(
R
Q
G
Figure 51. 2-Pole Low-Pass Sallen-Key Filter
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–ā8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
MECHANICAL DATA
DDA (S–PDSO–G8)
Power PADt PLASTIC SMALL-OUTLINE
0,49
0,35
M
0,10
1,27
8
5
Thermal Pad
(See Note D)
0,20 NOM
3,99
3,81
6,20
5,84
Gage Plane
0,25
1
4
4,98
4,80
0°–8°
0,89
0,41
1,68 MAX
Seating Plane
0,10
1,55
1,40
0,13
0,03
4202561/A 02/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
PowerPAD is a trademark of Texas Instruments.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS6042, THS6043
350 mA, ±12 V ADSL CPE LINE DRIVERS
SLOS264G – MARCH 2000 – REVISED DECEMBER 2001
MECHANICAL INFORMATION
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明