THS6301 [TI]
单端口、G.Fast 106MHz、212MHz CPE DSL 线路驱动器放大器;
| 型号： | THS6301 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单端口、G.Fast 106MHz、212MHz CPE DSL 线路驱动器放大器 放大器 驱动 驱动器 |
| 文件： | 总34页 (文件大小：1813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
THS6301 G.Fast DSL 线路驱动器放大器（具有带宽和功率调节功能） 特
性
1 特性
3 说明
1
•
•
•
支持 G.Fast 106MHz、212MHz DSL 应用
THS6301 是一款采用单通道电流反馈架构的差分线路
驱动器，支持 G.Fast 和不同数字用户线路 (DSL) 家庭
网关系统。该器件支持
支持传统 VDSL 和 ADSL2+ 应用
适合 G.Fast 和传统应用的高 MTPR （线路功率 =
8dBm）：
106MHz 和 212MHz G.Fast 数字用户线路配置文件，
使用本地离散多音调制 (DMT) 信号。THS6301 可在
8dBm 线路功率下以 212 MHz 的频率发挥高线性特
性。
–
–
–
–
–
ADSL2+ = 69dB
VDSL-17a = 73dB
VDSL-30a = 69dB
G.Fast 106MHz = 62dB
G.Fast 212MHz = 55dB
该器件的独特架构可以最大限度地降低静态电流，同时
仍可提供极高的线性特性。对于并不需要该放大器全部
性能的线路驱动模式，该器件的内在偏置设置可提供节
能效果。为了进一步提高灵活性并节省更多电力，可以
通过连接到一个器件引脚的外部偏置电阻器来调节总静
态电流。此外，该器件还 具备 两种线路端接模式，以
便在非常低的功耗下保持阻抗匹配。
•
•
•
•
•
多种电源模式可适应不同外形
可通过外部电阻器调节偏置电流
低功耗线路端接模式：10.2mA
掉电模式
12V 技术支持高功率输出
2 应用
该器件还可用作固定增益差分放大器，可以扩展带宽和
功率以适应不同应用的 需求。
•
•
•
•
G.Fast 和传统 DSL 线路驱动器
通用宽带线路驱动器
PLC 驱动器
该器件采用 16 引脚 4 x 4mm VQFN 封装。
器件信息(1)
DAC 输出放大器
器件型号
THS6301
封装
VQFN (16)
封装尺寸（标称值）
4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
MTPR G.Fast 212 MHz
（偏置 10，PAR = 15 dB，1/64 丢失音）
多音功率比 (MTPR) 图形
（G.Fast，212MHz，8dBm）
-40
Digital Interface
12 V
Line Power = 4 dBm
-42.5
Line Power = 8 dBm
-45
-47.5
-50
B1
B2
VS+
-52.5
-55
-57.5
-60
RSERIES
+
IN+
1:n
OUT+
OUT-
œ
-62.5
-65
Differential
to Line
Differential
Input
RL
-67.5
-70
RSERIES
œ
IN-
+
-72.5
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
Frequency (Hz)
D020
VSœ
Bias Adjust
IADJ
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS877
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 19
7.5 Programming .......................................................... 19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
Power Supply Recommendations...................... 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 9
6.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 文档支持................................................................ 26
11.2 接收文档更新通知 ................................................. 26
11.3 社区资源................................................................ 26
11.4 商标....................................................................... 26
11.5 静电放电警告......................................................... 26
11.6 术语表 ................................................................... 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2018) to Revision A
Page
•
已发布至生产 .......................................................................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
THS6301
www.ti.com.cn
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
RSA Package
16-Pin VQFN
Top View
IADJ
IN+
INœ
NC
1
2
3
4
12
11
10
9
NC
VS+
VSœ
NC
Thermal
Pad
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
B1
NO.
16
7
I
I
Most significant bit (MSB), logic level referenced to VS–
Least significant bit (LSB), logic level referenced to VS–
Bias current reference pin
B2
IADJ
IN–
1
—
I
3
Negative input
IN+
NC
2
I
Positive input
4
—
No internal connection to device (VS– recommended)
5, 8, 9, 12,
13, 14
NC
—
Not connected
OUT–
OUT+
VS–
6
O
O
Negative output
15
10
11
Positive output
—
—
Negative supply voltage connection
Positive supply voltage connection
VS+
The thermal pad is connected to pin 4 via a downbond connection.
The pad must be at the same potential as pin 4.
Thermal pad
—
Copyright © 2018, Texas Instruments Incorporated
3
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
13.2
5.5
10
UNIT
Supply voltage(2)
Digital inputs to GND
Analog inputs to GND
Differential analog inputs
Continuous power dissipation
Tstg
VS pin to GND (all modes)
B1, B2
V
V
V
V
–0.3
2
VIN+, VIN–
(VIN+ – VIN–)
–6
6
See Thermal Information
Storage temperature
Junction temperature
–65
150
150
°C
°C
TJ
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Supply bypass capacitor type, value and location relative to the device are critical to prevent damage to the device when the device is
turned on. See Power Supply Recommendations.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, allpins(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
11.4
±5.7
–40
–40
NOM
12
MAX
12.6
±6.3
85
UNIT
VS
Supply voltage
V
±6
TA
TJ
Ambient temperature
Junction temperature
°C
°C
125
6.4 Thermal Information
THS6301
THERMAL METRIC(1)
RSA (VQFN)
UNIT
16 PINS
39
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
38.8
18
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1
ΨJB
17.9
7.7
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
THS6301
www.ti.com.cn
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
6.5 Electrical Characteristics
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ = 100 pF, drive mode 5 (B1B2 = 01,
G.Fast mid power)(1) and output power measured at input of transformer (1:1) with no assumed transformer insertion losses
(unless otherwise noted)
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(2)
VOUT = 1 VPP, drive mode 1 (0Z, ADSL2+)
500
565
C
C
VOUT = 1 VPP, drive mode 2 (Z1, VDSL low power)
VOUT = 1 VPP, drive mode 3 (11, G.Fast low power
and VDSL mid power)
635
C
SSBW
Small-signal bandwidth
MHz
VOUT = 1 VPP, drive mode 4 (1Z, VDSL high power)
VOUT = 1 VPP, drive mode 5 (01, G.Fast mid power)
VOUT = 1 VPP, drive mode 6 (10, G.Fast high power)
VOUT = 15 VPP, drive mode 1 (0Z, ADSL2+)
540
670
618
160
200
C
C
C
C
C
VOUT = 15 VPP, drive mode 2 (Z1, VDSL low power)
VOUT = 15 VPP, drive mode 3 (11, G.Fast low power
and VDSL mid power)
260
C
LSBW
Large-signal bandwidth
MHz
VOUT = 15 VPP, drive mode 4 (1Z, VDSL high power)
VOUT = 15 VPP, drive mode 5 (01, G.Fast mid power)
270
275
C
C
VOUT = 15 VPP, drive mode 6 (10, G.Fast high
power)
300
C
Drive mode 1 (0Z), 10%-90% 15-VPP pulse
Drive mode 2 (Z1), 10%-90% 15-VPP pulse
Drive mode 3 (11), 10%-90% 15-VPP pulse
Drive mode 4 (1Z), 10%-90% 15-VPP pulse
Drive mode 5 (01), 10%-90% 15-VPP pulse
Drive mode 6 (10), 10%-90% 15-VPP pulse
Drive mode 1 (0Z), 10%-90% 15-VPP pulse
Drive mode 2 (Z1), 10%-90% 15-VPP pulse
Drive mode 3 (11), 10%-90% 15-VPP pulse
Drive mode 4 (1Z), 10%-90% 15-VPP pulse
Drive mode 5 (01), 10%-90% 15-VPP pulse
Drive mode 6 (10), 10%-90% 15-VPP pulse
f > 1 MHz, drive mode 1 (0Z)
3200
4000
6400
7100
8200
10500
2500
3200
4400
5400
6500
8000
4.3
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Slew rate down
V/µs
V/µs
SR
Slew rate up
f > 1 MHz, drive mode 2 (Z1)
3.9
f > 1 MHz, drive mode 3 (11)
3.9
Input-referred voltage
noise
en
nV/√Hz
f > 1 MHz, drive mode 4 (1Z)
3.9
f > 1 MHz, drive mode 5 (01)
3.7
f > 1 MHz, drive mode 6 (10)
3.5
Line-termination modes, referred to RSERIES
Power-down mode, referred to RSERIES
–154
–166
dBm/Hz
Line-termination mode 00, output referred
(f > 1 MHz)
5.6
6
C
C
C
Noise floor, line
termination mode
Line-termination mode Z0, output referred
(f > 1 MHz)
nV/√Hz
Power-down mode, output referred
(f > 1 MHz)
1.6
(1) See Table 1 for the different Bias Modes of the device
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by
characterization and simulation. (C) Typical value only for information. (D) Simulated value only for information
Copyright © 2018, Texas Instruments Incorporated
5
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ = 100 pF, drive mode 5 (B1B2 = 01,
G.Fast mid power)(1) and output power measured at input of transformer (1:1) with no assumed transformer insertion losses
(unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(2)
Line power = 8 dBm, f ≤ 552 kHz, PAR = 15 dB
Line power = 8 dBm, f ≤ 1.104 MHz, PAR = 15 dB
Line power = 8 dBm, f ≤ 2.208 MHz, PAR = 15 dB
67
69
67
C
C
C
ADSL2+ MTPR(3)
dB
Line power = 8 dBm, f ≤ 14 MHz,
PAR = 15 dB, bias = 11
73
71.5
69
C
C
C
C
C
C
D
C
C
D
VDSL2-17a MTPR(3)
dB
Line power = 8 dBm, f ≤ 17.6 MHz,
PAR = 15 dB, bias = 11
Line power = 8 dBm, f ≤ 30 MHz,
PAR = 15 dB, bias = 11
VDSL2-30a MTPR(3)
VDSL2-35b MTPR(3)
dB
dB
Line power = 8 dBm, f ≤ 35 MHz,
PAR = 15 dB, bias = 11
66
Line power = 4 dBm, f ≤ 106 MHz,
PAR = 15 dB, bias 01
68
dB
dB
Line power = 8 dBm, f ≤ 106 MHz,
PAR = 15 dB, bias 10
G.Fast 106-MHz
MTPR(3)
62
Line-termination mode, line power = 8 dBm,
PAR = 15 dB
60
Line power = 4 dBm, f ≤ 212 MHz,
PAR = 15 dB, bias 10
63
Line power = 8 dBm, f ≤ 212 MHz,
PAR = 15 dB, bias 10
G.Fast 212-MHz
MTPR(3)
55
dB
Line-termination mode, line power = 4 dBm,
PAR = 15 dB
50
Drive mode 6 (10, G.Fast high power), f = 100 kHz
Drive mode 6 (10, G.Fast high power), f = 50 MHz
Drive mode 6 (10, G.Fast high power), f = 106 MHz
Drive mode 6 (10, G.Fast high power), f = 212 MHz
Power-down bias mode
1.2
1.7
D
D
D
D
D
D
2.8
Differential output
impedance
Ω
5.3
2400
1.3
Line-termination modes
DC PERFORMANCE
AV
Differential gain
At dc, no load, all modes
8.3
–100
18
8.6
8.9
V/V
mV
VPP
A
A
A
Differential output offset
Output swing
100
Differential, at dc, 200-Ω load at amplifier output
Differential input
resistance
RIN-DIFF
RIN-SE
8
4
10
5
12
6
kΩ
kΩ
A
A
Single-ended input
resistance
(3) ADSL2+, VDSL2-17a and VDSL2-30a profiles are specified with 1-in-4 missing tones; VDSL2-35b and G.Fast profiles are specified with
1-in-64 missing tones
6
Copyright © 2018, Texas Instruments Incorporated
THS6301
www.ti.com.cn
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
Electrical Characteristics (continued)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ = 100 pF, drive mode 5 (B1B2 = 01,
G.Fast mid power)(1) and output power measured at input of transformer (1:1) with no assumed transformer insertion losses
(unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
40
40
80
80
50
50
40
40
TYP
75
MAX
UNIT
LEVEL(2)
Drive mode 1 (0Z), sourcing,
output offset < 20-mV deviation
A
Drive mode 1 (0Z), sinking,
output offset < 20-mV deviation
70
A
A
A
A
A
A
A
Drive mode 6 (10), sourcing,
output offset < 20-mV deviation
160
160
95
Drive mode 6 (10), sinking,
output offset < 20-mV deviation
Linear output current
mA
High power termination mode (00), sourcing,
output offset <20-mV deviation
High power termination mode (00), sinking,
output offset <20-mV deviation
90
Low power termination mode (Z0), sourcing,
output offset <20-mV deviation
77
Low power termination mode (Z0), sinking,
output offset <20-mV deviation
74
COMMON MODE
Input CM bias voltage
Output CM bias voltage
5.9
5.9
6
6
6.1
6.1
V
V
A
A
POWER SUPPLY
Maximum supply voltage
range
All modes
f = dc
12.6
V
A
A
Power-supply rejection
ratio
PSRR
61
dB
Drive mode 1 (0Z, ADSL2+)
13
15.9
20.1
18.9
24.3
A
A
Drive mode 2 (Z1, VDSL low power)
16.7
Drive mode 3 (11, G.Fast low power and
VDSL mid power)
22.5
27.2
33.1
A
Drive mode 4 (1Z, VDSL high power)
Drive mode 5 (01, G.Fast mid power)
Drive mode 6 (10, G.Fast high power)
High power line termination mode (00)
Low power line termination mode (Z0)
Power-down mode
24
32.1
36.7
13.6
8.3
29.8
38.9
45.3
16
36.5
47.8
56
A
A
A
A
A
A
IQ
Quiescent current
mA
18.9
11.6
2.4
10.2
1.9
Copyright © 2018, Texas Instruments Incorporated
7
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ = 100 pF, drive mode 5 (B1B2 = 01,
G.Fast mid power)(1) and output power measured at input of transformer (1:1) with no assumed transformer insertion losses
(unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
220
280
310
340
480
590
220
MAX
UNIT
LEVEL(2)
Drive mode 1 (0Z, ADSL2+),
line power = 8 dBm
D
Drive mode 2 (Z1, VDSL low power),
line power = 8 dBm
D
D
D
D
D
D
Drive mode 3 (11, G.Fast low power and
VDSL mid power), line power = 8 dBm
Drive mode 4 (1Z, VDSL high power),
line power = 8 dBm
Dynamic power
consumption
Drive mode 5 (01, G.Fast mid power),
line power = 4 dBm
mW
Drive mode 6 (10, G.Fast high power),
line power = 8 dBm
High power line termination mode (00),
line power = 4 dBm
Low power line termination mode (Z0),
line power = 4 dBm
120
23
D
D
Power-down mode
8
Copyright © 2018, Texas Instruments Incorporated
THS6301
www.ti.com.cn
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
Minimum logic high level
Maximum logic low level
Logic mid range
All digital pins, high
2.3
All digital pins, low
0.6
1.6
V
VMID
VFloat
IIH
All digital pins, driven externally
All digital pins, floating
1.2
1.3
V
Logic self-bias voltage
1.4
110
–75
1.5
V
Logic high-level leakage current
Logic low-level leakage current
All digital pins, logic level = 3.6 V
All digital pins, logic level = ground
135
µA
µA
IIL
–85
High power line termination mode (00) to
drive mode 6 (10, G.Fast high power)
64
50
Low power line termination mode (Z0) to
drive mode 6 (10, G.Fast high power)
Turn-on switching time
Turn-off switching time
ns
ns
Power down mode (ZZ) to Drive mode 6
(10, G.Fast high power)
60
Drive mode 6 (10, G.Fast high power) to
high power line termination mode (00)
76
Drive mode 6 (10, G.Fast high power) to
low power line termination mode (Z0)
400
380
Drive mode 6 (10, G.Fast high power) to
power-down mode (ZZ)
版权 © 2018, Texas Instruments Incorporated
9
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
6.7 Typical Characteristics
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
21
18
15
12
9
3
2
1
0
-1
-2
-3
-4
-5
-6
6
Drive Mode 6 (10)
Drive Mode 5 (01)
Drive Mode 4 (1Z)
Drive Mode 3 (11)
Drive Mode 2 (Z1)
Drive Mode 1 (0Z)
Drive Mode 6 (10)
Drive Mode 5 (01)
Drive Mode 4 (1Z)
Drive Mode 3 (11)
Drive Mode 2 (Z1)
Drive Mode 1 (0Z)
3
0
-3
10
100
1k
100
1k
Frequency (MHz)
Frequency (MHz)
D001
D002
VOUT = 1 VPP
VOUT = 1 VPP
图 1. Small-Signal Bandwidth
图 2. 3-dB Normalized Gain Small-Signal Bandwidth
21
18
15
12
9
110
100
90
80
70
60
50
40
30
20
10
0
HD2
HD3
Drive Mode 6 (10)
Drive Mode 5 (01)
Drive Mode 4 (1Z)
Drive Mode 3 (11)
Drive Mode 2 (Z1)
Drive Mode 1 (0Z)
6
3
100
1k
0 Z
Z 1
1 1
1 Z
0 1
1 0
Frequency (MHz)
Bias Mode
D003
D004
VOUT = 15 VPP
Frequency = 50 MHz, VOUT = 1 VPP
图 3. Large-Signal Bandwidth
图 4. Bias Modes vs Distortion
-55
-60
4
3.5
3
3.42
3.42
3.29
3.16
-65
2.9
2.9
-70
-75
2.5
2
-80
-85
1.5
1
-90
-95
-100
-105
-110
0.5
0
HD2
HD3
10
100
(0Z)
(Z1)
(11)
(1Z)
(01)
(10)
Frequency (MHz)
Drive Bias Modes
D005
D006
VOUT = 1 VPP
图 5. Distortion vs Frequency Drive Mode 6 (Bias 10)
图 6. Input Voltage Noise
10
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THS6301
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ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
Typical Characteristics (接下页)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
120
110
100
90
80
70
60
50
40
30
20
10
0
7
6
5
4
3
2
1
0
Bias 00
Bias Z0
6.04
5.6
1.57
(ZZ)
(00)
(Z0)
0.01
0.1
1
10
100
Termination Bias Modes
Frequency (MHz)
D007
D008
Simulation data
图 7. Termination Mode Noise Floor
图 8. Termination Mode Differential Output Impedance
10
7.5
5
120
90
10
7.5
5
120
VOUT = 15 VPP
VOUT = 8 VPP
VOUT = 15 VPP
VOUT = 8 VPP
VOCM (15 VPP)
90
VOCM (15 VPP
)
VOCM (8 VPP
)
VOCM (8 VPP)
60
60
2.5
0
30
2.5
0
30
0
0
-2.5
-5
-30
-60
-90
-120
-2.5
-5
-30
-60
-90
-120
-7.5
-10
-7.5
-10
Time (2.5 nsec/div)
Time (2.5 nsec/div)
D009
D010
SR down = 3200 V/µs, SR up = 2500 V/µs
SR down = 4000 V/µs, SR up = 3200 V/µs
图 9. Pulse Response Drive Mode 1 (Bias 0Z)
图 10. Pulse Response Drive Mode 2 (Bias Z1)
10
7.5
5
120
90
10
7.5
5
120
VOUT = 15 VPP
VOUT = 8 VPP
VOUT = 15 VPP
VOUT = 8 VPP
90
VOCM (15 VPP
)
VOCM (15 VPP
)
VOCM (8 VPP
)
VOCM (8 VPP
)
60
60
2.5
0
30
2.5
0
30
0
0
-2.5
-5
-30
-60
-90
-120
-2.5
-5
-30
-60
-90
-120
-7.5
-10
-7.5
-10
Time (2.5 nsec/div)
Time (2.5 nsec/div)
D011
D012
SR down = 6400 V/µs, SR up = 4400 V/µs
SR down = 7100 V/µs, SR up = 5400 V/µs
图 11. Pulse Response Drive Mode 3 (Bias 11)
图 12. Pulse Response Drive Mode 4 (Bias 1Z)
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THS6301
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Typical Characteristics (接下页)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
10
7.5
5
160
120
80
10
7.5
5
160
120
80
VOUT = 15 VPP
VOUT = 8 VPP
VOUT = 15 VPP
VOUT = 8 VPP
VOCM (15 VPP
)
VOCM (15 VPP
)
VOCM (8 VPP
)
VOCM (8 VPP
)
2.5
0
40
2.5
0
40
0
0
-2.5
-5
-40
-80
-120
-160
-2.5
-5
-40
-80
-120
-160
-7.5
-10
-7.5
-10
Time (2.5 nsec/div)
Time (2.5 nsec/div)
D013
D014
SR down = 8200 V/µs, SR up = 6500 V/µs
SR down = 10500 V/µs, SR up = 8000 V/µs
图 13. Pulse Response Drive Mode 5 (Bias 01)
图 14. Pulse Response Drive Mode 6 (Bias 10)
100
-40
VIN x 0.1
VOUT Bias 00
VOUT Bias Z0
VOUT Bias ZZ
Line Power = 4 dBm
Line Power = 8 dBm
-42.5
-45
75
50
-47.5
-50
25
-52.5
-55
0
-57.5
-60
-25
-50
-75
-100
-62.5
-65
-67.5
-70
-72.5
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
Time (5 nsec/div)
Frequency (Hz)
D015
D020
PAR = 15 dB, 1-in-64 missing tones
图 15. Pulse Response Termination and Power-Down Modes
图 16. MTPR G.Fast 212-MHz Profile (Bias 10)
-40
-35
-40
-45
-50
-55
-60
-65
-70
-75
TA = -40èC
TA = 0èC
TA = 25èC
TA = 50èC
TA = 85èC
Drive Mode 6 (10)
Drive Mode 5 (01)
Drive Mode 4 (1Z)
-45
-50
-55
-60
-65
-70
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
1M 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M110M
Frequency (Hz)
Frequency (Hz)
D021
D022
PAR = 15 dB, 1-in-64 missing tones, Line power = 8 dBm
PAR = 15 dB, 1-in-64 missing tones, line power = 8 dBm
图 17. MTPR Over Temperature G.Fast 212-MHz Profile (Bias
图 18. MTPR G.Fast 106-MHz Profile
10)
12
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THS6301
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Typical Characteristics (接下页)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
-45
-50
-55
-60
-65
-70
-75
-80
-40
-45
-50
-55
-60
-65
-70
-75
Drive Mode 6 (10)
Drive Mode 5 (01)
Drive Mode 4 (1Z)
TA = -40èC
TA = 0èC
TA = 25èC
TA = 50èC
TA = 85èC
1M 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M110M
1M 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M110M
Frequency (Hz)
Frequency (Hz)
D023
D024
PAR = 15 dB, 1-in-64 missing tones, line power = 4 dBm
Line power = 8 dBm, PAR = 15 dB, 1-in-64 missing tones
图 19. MTPR G.Fast 106-MHz Profile
图 20. MTPR Over Temperature G.Fast 106-MHz Profile (Bias
01)
-50
-50
Drive Mode 4 (1Z)
Drive Mode 3 (11)
Drive Mode 2 (Z1)
Drive Mode 4 (1Z)
Drive Mode 3 (11)
Drive Mode 2 (Z1)
-55
-60
-65
-70
-75
-80
-55
-60
-65
-70
-75
-80
1M
5M
10M
15M
20M
25M
30M
35M
1M
5M
10M
15M
20M
25M
30M
Frequency (Hz)
Frequency (Hz)
D025
D026
PAR = 15 dB, 1-in-64 missing tones, line power = 8 dBm
PAR = 15 dB, 1-in-4 missing tones, line power = 8 dBm
图 21. MTPR VDSL2-35b Profile
图 22. MTPR VDSL2-30a Profile
-50
-55
Drive Mode 4 (1Z)
Drive Mode 3 (11)
-55
-60
-65
-70
-75
-80
-85
Drive Mode 2 (Z1)
-60
-65
-70
-75
-80
-85
Drive Mode 1 (0Z)
-90
200k 2.5M
5M
7.5M
10M 12.5M 15M 17.5M
0
250k 500k 750k 1M 1.25M 1.5M 1.75M 2M 2.25M 2.5M
Frequency (Hz)
Frequency (Hz)
D027
D028
PAR = 15 dB, 1-in-4 missing tones, line power = 8 dBm
PAR = 15 dB, 1-in-4 missing tones, line power = 8 dBm
图 23. MTPR VDSL2-17a Profile
图 24. MTPR ADSL2+ Profile
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Typical Characteristics (接下页)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
625
600
575
550
525
500
475
450
425
400
375
350
425
400
375
350
325
300
275
250
225
200
175
Bias 10
Bias 01
Bias 1Z
Bias 1Z
Bias 11
Bias Z1
Bias 0Z
-10
-8
-6
-4
-2
0
2
4
6
8
-10
-8
-6
-4
-2
0
2
4
6
8
Tx Power (dBm)
Tx Power (dBm)
D029
D030
G.Fast 106-MHz profile used
VDSL2-30a profile used
图 25. G.Fast Modes Power Consumption
图 26. xDSL Modes Power Consumption
4
3
4
3
VOUT
B1 bias
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
VOUT
B1 bias
Time (50 nsec/div)
Time (50 nsec/div)
D033
D034
Bias mode 00 to 10 and 10 to 00
Bias mode ZZ to 0Z and 0Z to ZZ
图 27. Mode Switch Time 00 to 10
图 28. Mode Switch Time ZZ to 0Z
4
3
4
3
VOUT
B1 bias
VOUT
B2 bias
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
Time (50 nsec/div)
Time (50 nsec/div)
D031
D032
Bias mode ZZ to 1Z and 1Z to ZZ
Bias mode Z0 to Z1and Z1 to Z0
图 29. Mode Switch Time ZZ to 1Z
图 30. Mode Switch Time Z0 to Z1
14
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THS6301
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Typical Characteristics (接下页)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
56
54
52
50
48
46
44
42
40
38
48
46.5
45
43.5
42
40.5
39
37.5
36
34.5
33
-50
-30
-10
10
30
50
70
90
110
-50
-30
-10
10
30
50
70
90
110
Temperature TA (èC)
Temperature TA (èC)
D035
D036
图 31. IQ vs Temperature Drive Mode 6 (Bias 10)
图 32. IQ vs Temperature Drive Mode 5 (Bias 01)
33
32
31
30
29
28
27
26
25
24
23
36.5
35.5
34.5
33.5
32.5
31.5
30.5
29.5
28.5
27.5
26.5
25.5
24.5
-50
-30
-10
10
30
50
70
90
110
-50
-30
-10
10
30
50
70
90
110
Temperature TA (èC)
Temperature TA (èC)
D037
D038
图 33. IQ vs Temperature Drive Mode 4 (Bias 1Z)
图 34. IQ vs Temperature Drive Mode 3 (Bias 11)
24
23.5
23
18.8
18.3
17.8
17.3
16.8
16.3
15.8
15.3
14.8
14.3
13.8
13.3
22.5
22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
-50
-30
-10
10
30
50
70
90
110
-50
-30
-10
10
30
50
70
90
110
Temperature TA (èC)
Temperature TA (èC)
D039
D040
图 35. IQ vs Temperature Drive Mode 2 (Bias Z1)
图 36. IQ vs Temperature Drive Mode 1 (Bias 0Z)
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Typical Characteristics (接下页)
at TA ≈ 25°C, VS+ = 12 V, VS– = 0 V, voltage gain (AV) = 8.5 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIADJ = 75 kΩ, CIADJ
=
100 pF, and drive mode 5 (B1B2 = 01, G.Fast mid power mode) and output power measured at input of transformer (1:1) with
no assumed transformer insertion losses (unless otherwise noted)
18.5
11.6
11.3
11
18
17.5
17
10.7
10.4
10.1
9.8
16.5
16
15.5
15
9.5
9.2
14.5
14
8.9
8.6
13.5
8.3
-50
-30
-10
10
30
50
70
90
110
-50
-30
-10
10
30
50
70
90
110
Temperature TA (èC)
Temperature TA (èC)
D041
D042
图 37. IQ vs Temperature High-Power Termination Mode
图 38. IQ vs Temperature Low-Power Termination Mode
(Bias 00)
(Bias Z0)
2200
2.4
2000
1800
1600
1400
1200
1000
800
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
600
400
200
0
-50
-30
-10
10
30
50
70
90
110
-100 -80 -60 -40 -20
0
20 40 60 80 100
Temperature TA (èC)
Output Offset Voltage (mV)
D043
D044
Approximately 2100 units
图 39. IQ vs Temperature Power-Down Mode (Bias ZZ)
图 40. Output Offset Voltage Histogram
16
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THS6301
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ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
7 Detailed Description
7.1 Overview
The THS6301 is a current-feedback architecture, differential line driver designed for G.Fast and xDSL systems.
The device is targeted for use in G.Fast digital subscriber line (DSL) systems that enable native discrete
multitone modulation (DMT) signals and supports an 8-dBm line power up to 212 MHz with good linearity.
The device consists of a unique architecture consisting of an amplifier in a noninverting configuration with an
internally-fixed gain of 8.5 V/V. The THS6301 is designed to drive the high-performance G.Fast 212-MHz DSL
profile, but is also backwards-compatible to drive lower frequency profiles. The device features selectable bias
modes for the G.Fast 106-MHz profile, VDSL profiles, and ADSL profiles. These modes reduce the quiescent
current of the device based on the frequency requirements of the various DSL profiles to maximize power
efficiency. Along with adjustable bias modes, the device features two line-termination modes that maintain an
output impedance match with low power consumption. The line-termination modes allow for the device to be in a
low-power state without causing distortion on a shared signal line.
For further flexibility, the THS6301 features an IADJ pin that is used to further adjust the quiescent current of the
device. A resistor connected to this pin can be changed to increase or decrease the device current to meet
performance requirements and uses the lowest amount of power possible.
7.2 Functional Block Diagram
B1
B2
VS+
Digital Block
IN+
+
OUT+
VS+
œ
5kꢀ
5kꢀ
œ
VSœ
OUT-
+
IN-
IADJ
Bias Adjust
VSœ
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7.3 Feature Description
The THS6301 is a line driver that has a high current drive and a differential input and output. 图 41 shows an
example circuit of the THS6301 configured to drive the G.Fast 212-MHz DSL profile. The bias control pins B1
and B2 are set to 3.3 V and ground, respectively, to put the device in the G.Fast 212-MHz bias mode. This bias
mode optimizes the internal power consumption of the device to meet performance specifications of the G.Fast
212-MHz profile and can be changed to meet several different DSL profiles and other modes listed in 表 1. The
IADJ pin is biased with a 75-kΩ (RIADJ) resistor that adjusts the device quiescent current to a nominal state. RIADJ
can be increased to lower the quiescent current or decreased to raise the quiescent current of the device for fine-
tuning. CIADJ provides decoupling for the IADJ pin and is typically 100 pF.
The THS6301 has a 10-kΩ, internally-set differential input impedance and low output impedance. In 图 41 the
input impedance is matched to 100 Ω by using a 100-Ω resistor connected differentially across the inputs. This
value can easily be changed by using a different resistor to create the desired impedance at the input.
Remember that the impedance in the device is actually the parallel combination of 10 kΩ and the external input
resistor. For low impedances, this effect is minimal, but must be considered if the matched input impedance is
increased. The output impedance of the THS6301 in 图 41 is set by the two RSERIES resistors to match 100 Ω.
The internal output resistance is very low (< 2 Ω per output), so the output impedance is primarily set by the
RSERIES resistors. These resistors can be adjusted to match various output impedance values.
Digital Interface
12 V
B1
B2
VS+
RSERIES
+
IN+
1:n
OUT+
OUT-
œ
Differential
to Line
Differential
Input
RL
RSERIES
œ
IN-
+
VSœ
Bias Adjust
IADJ
图 41. G.Fast, 212-MHz Driving Mode Example Circuit
18
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THS6301
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ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
7.4 Device Functional Modes
The THS6301 features nine different device operational modes, as listed in 表 1, to accommodate the G.Fast,
xDSL, line termination, and power-down scenarios. The device is controlled by a 2-pin parallel interface that uses
three-level logic to control the device state. The G.Fast and xDSL modes change the quiescent current of the
device to meet signal performance requirements and maintain the lowest power possible, which allows for legacy
DSL compatibility with maximum power efficiency. The two line-termination modes maintain a low impedance at
the output and place the device in a low-power state. The line-termination modes allow for the muxing of multiple
devices to one output line by putting the non-driving devices in a state that does not add distortion to the line. A
power-down mode is also included to digitally shut down the device for the highest level of power savings. 表 1
lists the device power modes and the typical quiescent currents for each mode.
表 1. Bias Modes Truth Table
BIAS CONTROL PINS
TYPICAL QUIESCENT
CURRENT (RIADJ = 75
KΩ
MODE
DESCRIPTION
SSBW (VOUT = 1.7
VPP
RECOMMENDED DSL PROFILE
)
B1
B2
Power down
Z
Z
Power down
1.9 mA
N/A
N/A
Low-power
termination
Z
0
0
0
Line termination (low power)
10.2 mA
High-power
termination
Line termination (high power)
16 mA
N/A
Drive mode 1
Drive mode 2
0
Z
Z
1
ADSL2+
15.9 mA
20.1 mA
564 MHz
659 MHz
VDSL (low power)
G.Fast (low power) and VDSL (mid
power)
Drive mode 3
1
1
27.2 mA
755 MHz
Drive mode 4
Drive mode 5
Drive mode 6
1
0
1
Z
1
0
VDSL (high power)
G.Fast (mid power)
G.Fast (high power)
29.8 mA
38.9 mA
45.3 mA
605 MHz
864 MHz
814 MHz
7.5 Programming
The THS6301 programming is controlled by two parallel pins, B1 and B2. These pins use three-level logic to
create nine different combinations for each pair of pins. The pins have a high state (1) when the pin voltage is
greater than 2.3 V, a low state (0) when the pin voltage is less than 0.6 V, and an open state (Z) where the pin
floats at approximately 1.4 V or can be driven between 1.2 V and 1.6 V. 表 1 lists the logic combinations for the
two pins and the corresponding power modes.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a single-port, very-high-bit-rate linear xDSL, G.Fast differential line driver where the device drives a
twisted pair cable. The signal is generated by a high-speed, digital-to-analog converter (DAC) at low signal
swings that is amplified by the G.Fast line driver.
The G.Fast system is ac-coupled when transmitting information above the audio band. On the input of the line
driver, this ac-coupling translates into the series capacitors to isolate the dc voltage coming from the DAC output
common-mode voltage. On the output, a transformer is used to help isolate the 48 V present between the tip and
ring of the telephone line.
The transformer can be set to any useful ratio. In practice, the transformer-turn ratio is set between 1:1 and 1:1.4
for the device. The output transformer usually has the active impedance synthesis factor set to 5. This synthesis
factor means that the termination resistor (RT) is 1/5th of the load impedance reflected to the transformer
secondary. Thus, the correct termination can be selected based on the transformer-turn ratio.
Note that the resulting load detected by the amplifier may affect the amplifier linearity or output voltage swing
capabilities.
8.2 Typical Application
图 42 shows a typical application circuit for this device.
Digital
Interface
12 V
VS+
B1 B2
THS6301
0.1 µF
+
IN+
12 V
RSERIES
1:n
100 Ω
100 Ω
OUT+
L1
L2
100 Ω
œ
Twisted
Pair Cable
RT
2200 pF
Differential
Input
Secondary
Protection
RL
C1
C2
½ DAC3482
6 V
œ
100 Ω
OUT-
IN-
3rd-Order, Low-Pass
Filter
+
RSERIES
0.1 µF
Bias Adjust
100 pF
IADJ
VSœ
75 kΩ
图 42. Typical G.FAST Line Driver Configuration
20
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Typical Application (接下页)
8.2.1 Design Requirements
表 2 provides the design requirements for a G.Fast line driver, which is met by the THS6301 device.
表 2. Design Requirements
DESIGN REQUIREMENT
G.Fast, 106-MHz, 212-MHz transmit profile
Legacy DSL profile support
Supply voltage
CONDITION
Yes, using the bias control pins for line power = 8 dBm and PAR = 15 dBm
Yes
12 V
Output current drive
±80 mA, each output
High isolation from input to output
AC coupled
Power-down functionality
Input interface
Output transformer ratio
Surge protection
1:1.5
External needed
8.2.2 Detailed Design Procedure
The G.Fast signal input to the THS6301 comes from a high-speed DAC whose interleaving spurs are filtered out
using either a 3rd- or 5th-order filter. Digital pre-emphasis can be employed in the DAC output such that the
differential line driver compensates for the transmission line cable losses at long distance and high frequency.
The THS6301 is operated on a 12-V single supply. Resulting from the single-supply operation, the device input is
AC-coupled using a capacitor that blocks any DC current flowing out of the inputs to the adjacent circuitry. The
AC-coupling capacitor forms a high-pass filter with the device input impedance. This pole must be set at a
frequency low enough to not interfere with the desired xDSL or G.Fast signal.
The THS6301 differential outputs usually drive a 1:n output transformer with a transformer turns ratio that can be
changed depending upon the application. The output transformer selected must have low insertion loss in the
desired frequency band in order to maintain good multi-tone power rejection (MTPR) for a given line power. The
load is expected to be a transmission line with 100-Ω characteristic impedance on the primary side of the
transformer. Referred to the transformer secondary, the load detected by the amplifier is 1 / n2 with 1:n being the
transformer turn ratio. Practical limitations force the transformer-turn ratio to be between 1:1 and 1:1.6. At the
lighter load detected by the amplifier (1:1), the voltage swing is limited by the class AB output stage and the
maximum achievable swing of the amplifier. At the heaviest load (1:1.6), the voltage swing is limited by the
current drive capability of the amplifier. To satisfy the synthesis impedance factor and the loading, the termination
resistance (RT) can be set to RT = RL / 5 = 100 Ω / (5 × n2).
For surge protection, consider adding a gas discharge tube (GDT) on the primary side of the output transformer.
The gas discharge tube is required to shunt the large current that could flow through the cables during lightning
surge, and protect the device outputs. The secondary protection is also normally added after the series
resistance on the secondary transformer side. The secondary protection could be in the form of back to back
switching diodes, which also help limit the residual surge current flowing into the device outputs.
For the power-supply bypass, consider using X7R or X5R because of the better stability of these materials over
temperature.
版权 © 2018, Texas Instruments Incorporated
21
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
8.2.3 Application Curves
图 43 and 图 44 show the MTPR results for 212-MHz and 160-MHz G.Fast profiles, respectively.
-35
-40
-45
-50
-55
-60
-65
-70
-75
-40
-42.5
-45
Drive Mode 6 (10)
Drive Mode 5 (01)
Drive Mode 4 (1Z)
Line Power = 4 dBm
Line Power = 8 dBm
-47.5
-50
-52.5
-55
-57.5
-60
-62.5
-65
-67.5
-70
-72.5
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
1M 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M110M
Frequency (Hz)
Frequency (Hz)
D020
D022
PAR = 15 dB, 1-in-64 missing tones
PAR = 15 dB, 1-in-64 missing tones, line power = 8 dBm
图 43. MTPR G.Fast 212-MHz Profile
图 44. MTPR G.Fast 106-MHz Profile
22
版权 © 2018, Texas Instruments Incorporated
THS6301
www.ti.com.cn
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
9 Power Supply Recommendations
The THS6301 is recommended to operate using a total supply voltage of 12 V. If a lower or higher supply
voltage is required, select one that is between 11.4 V and 12.6 V for optimal performance. Use supply-
decoupling capacitors on the power-supply pins to minimize distortion caused by parasitic signals on the power
supply. This usage is especially important in applications where many devices share a single power-supply bus.
The device can be operated on split supplies (such as ±6 V). However, the bias adjust resistor must be tied to
the negative supply for proper device operation. When operating the device on split supply, pins 4 and 10 act as
the negative supply voltage pin. The thermal pad must be tied to either GND or the negative supply voltage in
split-supply operation. The device bias mode pins are now referenced to the negative supply voltage for the
different logic levels.
As with all high-speed amplifiers, supply bypass capacitors are required for operation of the THS6301. Multiple
capacitors are required to cover the entire frequency range of the device. For low frequency bypassing use a 10
µF or larger tantalum capacitor (see the description of C1 in the THS6301EVM User's Guide). Place this
capacitor within two or three centimeters of the amplifier. Use 0.1-µF and 1-nF high-frequency bypass capacitors
(these capacitors are labeled C2 and C3 on the EVM). Place these capacitors within two to three millimeters of
the amplifier and must be directly connected to the power-supply planes with low-impedance vias. Texas
Instruments recommends using the capacitors shown in the bill of materials (BOM) that accompanies the
THS6301EVM User's Guide. The capacitor part numbers are listed in the THS6301EVM user's guide.
10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the THS6301 requires careful attention
to board layout parasitics and external component types. Recommendations that optimize performance include:
a. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Excessive parasitic capacitance on
the input pin can cause instability. In the line driver application, the parasitic capacitance forms a pole with
the load detected by the amplifier and can reduce the effective bandwidth of the application circuit, thus
leading to degraded performance. To reduce unwanted capacitance, open a window around the signal I/O
pins in all ground and power planes around those pins. Otherwise, make sure that ground and power planes
are unbroken elsewhere on the board.
b. Minimize the distance (< 0.25") from the power-supply pins to high-frequency, 0.1-µF decoupling capacitors.
At the device pins, make sure that the ground and power-plane layout are not in close proximity to the signal
I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and decoupling
capacitors. Always decouple the power-supply connections with these capacitors.
c. Make sure the bias adjust resistor connected to the IADJ pin is not routed close to the device inputs in-order
to avoid any high-frequency noise coupling into the IADJ pin and result in unexpected device behavior.
d. Careful selection and placement of external components preserves the high-frequency performance of the
device. Use very-low reactance-type resistors. Surface-mount resistors function best and allow a tighter
overall layout. Metal-film or carbon composition, axially-leaded resistors also provide good high-frequency
performance. Again, keep the leads and printed circuit board (PCB) traces as short as possible. Never use
wire-wound type resistors in a high-frequency application.
e. Connections to other wideband devices on the board can be made with short, direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Use relatively wide traces (50 mils to 100 mils), preferably with ground and power
planes opened up around them.
f. Do not socket a high-speed part such as the THS6301. The additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely troublesome parasitic network that makes achieving a
smooth, stable frequency response almost impossible. Best results are obtained by soldering the device onto
the board.
g. TI recommends soldering the thermal pad to the PCB in order to conduct heat out of the device package.
Vias underneath the part help regulate the flow of free air and also help conduct heat out of the package.
版权 © 2018, Texas Instruments Incorporated
23
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
Layout Guidelines (接下页)
10.1.1 Power Dissipation and Thermal Considerations
For maximum performance and reliability, the designer must ensure that the design does not exceed a junction
temperature of 125°C. Between 125°C and 150°C, damage does not occur, but the performance of the amplifier
begins to degrade and long-term reliability suffers. The thermal characteristics of the device are dictated by the
package and the PCB. 公式 1 calculates maximum power dissipation for a given package:
PD(MAX) = (TJ(MAX) – TA) / RθJA
where
•
•
•
•
•
•
PD(MAX) is the maximum power dissipation in the amplifier (W)
TJ(MAX) is the absolute maximum junction temperature (°C)
TA is the ambient temperature (°C)
R
R
R
θJA = RθJC + RθCA
θJC is the thermal coefficient from silicon transistors to the case (°C/W)
θCA is the thermal coefficient from case to ambient temperature (°C/W)
(1)
For systems where heat dissipation is more critical, the THS6301 is offered in an 16-pin VQFN package with
thermal pad. Because of the thermal pad, the thermal coefficient for the VQFN package is substantially improved
over the traditional SOIC. The data for the VQFN packages with thermal pad assume a board layout that follows
the thermal pad layout guidelines referenced in this section and detailed in the Quad Flatpack No-Lead Logic
Packages application note. If the thermal pad is not soldered to the PCB, the thermal impedance increases
substantially, which may cause serious heat and performance issues. Be sure to always solder the thermal pad
to the PCB for optimum performance.
When determining whether or not the device satisfies the maximum power dissipation requirement, consider not
only quiescent power dissipation, but also dynamic power dissipation. Often times, this dissipation is difficult to
quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide
visibility into a possible problem.
24
版权 © 2018, Texas Instruments Incorporated
THS6301
www.ti.com.cn
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
10.2 Layout Example
Ground and power
plane exist on inner
layers
Ground and power plane
removed from inner layers
Remove GND and
Power plane under pins
2, 3, 6, and 15 to
minimize stray PCB
capacitance
GND
13
15
14
16
B1
Place 0.1-µF decoupling
OUT+
NC
NC
capacitors close (< 0.25") to
IADJ
NC 12
1
power-supply pin
+
IN+
2
œ
11
10
9
VS
œ
IN-
GND
3
4
Avoid narrow power and
ground traces to minimize
inductance between the pins
and decoupling capacitors
+
GND
GND
NC
NC
OUT-
6
NC
B2
7
GND
Place output resistors
on pins 6 and 15 as
close as possible to
minimize parasitic
capacitance and
5
8
prevent oscillation
图 45. Example Layout
版权 © 2018, Texas Instruments Incorporated
25
THS6301
ZHCSI36A –APRIL 2018–REVISED SEPTEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
《四方扁平封装无引线逻辑封装》应用手册
《ADSL 线路驱动器的有源输出阻抗》应用手册
THS6301EVM 用户指南
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS6301IRSAR
THS6301IRSAT
ACTIVE
QFN
QFN
RSA
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
THS
6301
ACTIVE
RSA
NIPDAU
THS
6301
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS6301IRSAR
THS6301IRSAT
QFN
QFN
RSA
RSA
16
16
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS6301IRSAR
THS6301IRSAT
QFN
QFN
RSA
RSA
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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