THS7347IPHPG4 [TI]
3-Channel RGBHV Video Buffer with I2C Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes;
| 型号： | THS7347IPHPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-Channel RGBHV Video Buffer with I2C Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes |
| 文件： | 总28页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS7347
www.ti.com
SLOS531–MAY 2007
3-Channel RGBHV Video Buffer with I2C™ Control, 2:1 Input Mux,
Monitor Pass-Through, and Selectable Input Bias Modes
FEATURES
APPLICATIONS
•
•
•
Projectors
Professional Video Systems
LCD/DLP®/LOCS Input Buffering
•
3-Video Amplifiers for CVBS, S-Video, EDTV,
HDTV Y'P'BP'R, G'B'R', and R'G'B' Video
•
H/V Sync Paths with Adjustable Schmitt
Trigger
DESCRIPTION
•
•
•
2:1 Input Mux
I2C Control of All Functions on Each Channel
Fabricated using the revolutionary complementary
silicon-germanium (SiGe) BiCom3 process, the
THS7347 is a low-power, single-supply 2.7-V to 5-V
3-channel integrated video buffer with horizontal (H)
and vertical (V) sync signal paths. It incorporates a
500-MHz bandwidth, 1200-V/µs unity-gain buffer
ideal for driving analog-to-digital converters (ADCs)
and video decoders. In parallel with the unity-gain
Unity-Gain Buffer Path for ADC Buffering:
–
500-MHz Bandwidth, 1200-V/µs Slew Rate
•
Monitor Pass-Through Function:
–
–
–
500-MHz Bandwidth, 1300-V/µs Slew Rate
6-dB Gain with SAG Correction Capable
High Output Impedance in Disable State
buffer,
a monitor pass-through path allows for
passing the input signal on to other systems. This
path has a 6-dB gain, 500-MHz bandwidth, 1300V/µs
slew rate, SAG correction capability, and high output
impedance while disabled.
•
Selectable Input Bias Modes:
–
–
–
–
AC-Coupled with Sync-Tip Clamp
AC-Coupled with Bias
DC-Coupled with Offset Shift
DC-Coupled
Each channel of the THS7347 is individually
I2C-configurable for all functions, including controlling
the 2:1 input mux. Its rail-to-rail output stage allows
for both ac- and dc-coupling applications.
•
+2.7-V to +5-V Single-Supply Operation
Total Power Consumption: 265 mW at 3.3 V
Disable Function Reduces Current to 0.1 µA
Rail-to-Rail Output:
•
•
•
–
Output Swings Within 0.1 V of the Rails,
Allowing AC- or DC-Output Coupling
•
Lead-free, RoHS TQFP Package
3.3 V
Input 1
0.1 mF
In A
0.1 mF
2:1
+
In B
X1
ADC
75 W
-
AC
Sync
TIP
DC
+Offset
Input 2
0.1 mF
75 W
DC
AC-
47 mF
+
Out
Clamp
Disable
= OPEN
BIAS
75 W
-
675 W
33 mF
SAG
Monitor
Output
75 W
1 kW
878 W
150 W
SCL
SDA
3.3 V
3.3 V Single-Supply Projector Input System with Monitor Pass-Through
(1 of 3 R'G'B' Channels Shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
THS7347
www.ti.com
SLOS531–MAY 2007
DESCRIPTION, CONTINUED
As part of the THS7347 flexibility, the device input can be selected for ac- or dc-coupled inputs. The ac-coupled
modes include a sync-tip clamp option for CVBS/Y'/G'B'R' with sync or a fixed bias for the C'/P'B/P'R/R'G'B'
channels without sync. The dc input options include a dc input or a dc+Offset shift to allow for a full sync
dynamic range at the output with 0 V input.
The THS7347 is available in a lead-free, RoHS-compliant TQFP package.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION(1)
PACKAGED DEVICES
THS7347IPHP
PACKAGE TYPE
TRANSPORT MEDIA, QUANTITY
Tray, 250
HTQFP-48 PowerPAD™
THS7347IPHPR
Tape and reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
THS7347
UNIT
V
VSS
VI
Supply voltage, GND to VA or GND to VDD
Input voltage
5.5
–0.4 to VA or VDD
±80
V
IO
Continuous output current
mA
Continuous power dissipation
See Dissipation Rating Table
TJ
Maximum junction temperature, any condition(2)
Maximum junction temperature, continuous operation, long term reliability(3)
Storage temperature range
+150
+125
°C
°C
°C
°C
V
TJ
Tstg
–65 to +150
300
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
1500
ESD ratings
CDM
MM
1500
V
100
V
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
(2) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
(3) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS
POWER RATING(1)(2)
(TJ = +125°C)
θJC
θJA
PACKAGE
(°C/W)
(°C/W)
TA = +25°C
TA = +85°C
HTQFP-48 with PowerPAD (PHP)
1.2
35
2.85 W
1.14 W
(1) This data was taken with a PowerPAD standard 3-inch by 3-inch, 4-layer printed circuit board (PCB) with internal ground plane
connections to the PowerPAD.
(2) Power rating is determined with a junction temperature of +125°C. This temperature is the point where distortion starts to substantially
increase and long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction
temperature at or below +125°C for best performance and reliability.
2
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SLOS531–MAY 2007
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
NOM
MAX UNIT
VDD
VA
Digital supply voltage
5
5
V
V
Analog supply voltage. Must be equal to or greater than VDD
Ambient temperature
VDD
–40
TA
+85
°C
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V
RL = 150 Ω 5 pF to GND for Monitor Output, 19 kΩ || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor
Output Pin, unless otherwise noted.
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/MAX/
TYP
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
+25°C
+25°C
UNIT
Small-signal
bandwidth
(–3 dB)
Buffer output
500
450
MHz
MHz
Typ
Typ
VO = 0.2 VPP
Monitor output
Buffer output
Monitor output
Buffer output
425
375
475
MHz
MHz
MHz
Typ
Typ
Typ
–1 dB Flatness
VO = 0.2 VPP
Large-signal
bandwidth
(–3 dB)
VO = 1 VPP
VO = 2 VPP
Monitor output
240
MHz
Typ
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
VO = 1 VPP
VO = 2 VPP
1050
1050
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Slew rate
1.2
Group delay at
100 kHz
1.2
ns
0.05/0.05
0.1/0.1
0.1/0.15
0.15/0.2
–58
%
Differential gain
NTSC/PAL
NTSC/PAL
%
degrees
degrees
dB
Differential phase
Total harmonic
distortion
f = 1 MHz
VO = 1 VPP
VO = 2 VPP
Monitor output
–57
dB
Typ
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
63
65
–40
–36
64
66
0
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
Ω
Typ
Typ
Signal-to-noise ratio
No weighting, up to 100 MHz
f = 100 MHz
Typ
Channel-to-channel
crosstalk
Typ
Typ
MUX Isolation
Gain
f = 100 MHz
Typ
f = 100 kHz; VO = 1 VPP
f = 100 kHz; VO = 2 VPP
Typ
6
5.8/6.25 5.75/6.3
5.75/6.35
Min/Max
Typ
6
Settling time
VIN = 1 VPP; 0.5% Settling
f = 10 MHz
6
Typ
0.3
0.4
Typ
Output impedance
Ω
Typ
DC PERFORMANCE
Output offset voltage
Buffer output
Monitor output
Buffer output
Monitor output
15
20
±80
±85
±85
±125
mV
mV
µV/°C
µV/°C
mV
V
Max
Max
Bias = dc
Bias = dc
±120
±125
20
Typ
Average offset
voltage drift
20
Typ
Bias = dc + shift, VIN = 0 V
Bias = ac
255
1.0
175/335 165/345
0.85/1.15 0.8/1.2
145/325 135/335
1.55/1.85 1.5/1.9
200/380 195/385
200/400 195/405
160/350
0.8/1.2
130/340
1.5/1.9
190/390
190/410
Min/Max
Min/Max
Min/Max
Min/Max
Min/Max
Min/Max
Buffer output
Bias output voltage
Bias = dc + shift, VIN = 0 V
Bias = ac
235
1.7
mV
V
Monitor output
Buffer output
290
300
mV
mV
Sync tip clamp
voltage
Bias = ac STC, clamp voltage
Monitor output
3
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SLOS531–MAY 2007
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V (continued)
RL = 150 Ω 5 pF to GND for Monitor Output, 19 kΩ || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor
Output Pin, unless otherwise noted.
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/MAX/
TYP
PARAMETER
DC PERFORMANCE, continued
Input bias current
TEST CONDITIONS
+25°C
+25°C
UNIT
Bias = dc; (–) implies IB out of the pin
Bias = dc
–1.3
–3.0
–3.5
–3.5
10
µA
nA/°C
µA
Max
Average bias current drift
Typ
Bias = ac STC, low bias
Bias = ac STC, mid bias
Bias = ac STC, high bias
2.3
5.8
8.1
0.9/3.6
3.8/8.0
0.8/3.8
3.7/8.2
0.7/3.9
3.6/8.3
5.5/11.1
Min/Max
Min/Max
Min/Max
Sync tip clamp bias current
µA
5.7/10.8 5.6/11.0
µA
INPUT CHARACTERISTICS
Input voltage range
Bias = dc
0 to 2
25
V
Typ
Typ
Typ
Typ
Bias = ac bias mode
Bias = dc, dc + shift, ac STC
kΩ
MΩ
pF
Input resistance
3
Input capacitance
1.5
OUTPUT CHARACTERISTICS: MONITOR OUTPUT
RL = 150 Ω to 1.65 V
3.15
3.05
3.05
2.9
2.9
2.8
2.8
V
V
Min
Min
Typ
Typ
Max
Max
Typ
Typ
Min
Min
RL = 150 Ω to GND
RL = 75 Ω to 1.65 V
RL = 75 Ω to GND
RL = 150 Ω to 1.65 V
RL = 150 Ω to GND
RL = 75 Ω to 1.65 V
RL = 75 Ω to GND
2.85
2.75
2.75
High output voltage swing
Low output voltage swing
V
V
0.15
0.1
0.25
0.18
0.28
0.21
0.29
0.22
V
V
0.25
0.08
80
V
V
Sourcing
Sinking
50
50
47
47
45
45
mA
mA
Output current
RL = 10 Ω to 1.65 V
75
OUTPUT CHARACTERISTICS: BUFFER OUTPUT
High output voltage swing
(Limited by input range and G = 0 dB)
2
1.8
1.75
0.13
1.75
0.14
V
V
Min
Load = 19 kΩ 8 pF to 1.65 V
Low Output voltage swing
(Limited by input range and G = 0 dB)
0.05
0.12
Max
Sourcing
Output Current
RL = 10 Ω to GND
RL = 10 Ω to 1.65 V
80
75
50
50
47
47
45
45
mA
mA
Min
Min
Sinking
POWER SUPPLY: ANALOG
Maximum operating voltage
Minimum operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
POWER SUPPLY: DIGITAL
Maximum operating voltage
Minimum operating voltage
Maximum quiescent current
Minimum quiescent current
VA
3.3
3.3
80
80
50
5.5
2.7
100
60
5.5
2.7
103
57
5.5
2.7
105
55
V
Max
Min
Max
Min
Typ
VA
V
VA, dc + shift mode, VIN = 100 mV
VA, dc + shift mode, VIN = 100 mV
Buffer output
mA
mA
dB
VDD
3.3
3.3
5.5
2.7
5.5
2.7
1.3
0.3
5.5
2.7
V
V
Max
Min
Max
Min
VDD
VDD, VIN = 0 V
VDD, VIN = 0 V
0.65
0.65
1.2
1.4
mA
mA
0.35
0.25
DISABLE CHARACTERISTICS: ALL CHANNELS DISABLED
Quiescent current
All channels disabled
0.1
5
µA
µs
µs
Typ
Typ
Typ
Turn-on time delay (tON
)
Time for lS to reach 50% of final value
after I2C control is initiated
Turn-on time delay (tOFF
)
2
4
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SLOS531–MAY 2007
ELECTRICAL CHARACTERISTICS, VA = VDD = 3.3 V (continued)
RL = 150 Ω 5 pF to GND for Monitor Output, 19 kΩ || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor
Output Pin, unless otherwise noted.
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/MAX/
TYP
PARAMETER
TEST CONDITIONS
+25°C
+25°C
UNIT
H/V SYNC CHARACTERISTICS: RLoad = 1 kΩ To GND(1)
Schmitt trigger adjust pin voltage
Schmitt trigger threshold range
Reference for Schmitt trigger
1.47
1.35/1.6 1.3/1.65
1.27/1.68
V
V
Min/Max
Typ
Allowable range for Schmitt trigger adjust
0.9 to 2
Positive-going input voltage threshold
relative to Schmitt trigger threshold
Schmitt trigger VT+
Schmitt trigger VT–
0.25
–0.3
10
V
V
Typ
Typ
Typ
Negative-going input voltage threshold
relative to Schmitt trigger threshold
Schmitt trigger threshold pin input
resistance
Input resistance into Control pin
kΩ
H/V Sync input impedance
H/V Sync high output voltage
H/V Sync low output voltage
H/V Sync source current
H/V Sync sink current
H/V Delay
10
3.15
0.01
50
MΩ
V
Typ
Min
Max
Min
Min
Typ
Typ
1 kΩ to GND
3.05
0.05
35
3.0
0.1
30
3.0
0.1
30
1 kΩ to GND
V
10 Ω to GND
mA
mA
ns
ns
10 Ω to 3.3 V
35
25
23
21
Delay from Input to output
6.5
5
H/V to buffer output skew
(1) Schmitt trigger threshold is defined by (VT+ – VT–)/2.
5
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ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V
RL = 150Ω || 5pF to GND for Monitor Output, 19kΩ || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output
Pin, unless otherwise noted.
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/MAX/
TYP
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
+25°C
+25°C
UNIT
Small-signal
bandwidth
(–3 dB)
Buffer output
550
500
MHz
MHz
Typ
Typ
VO = 0.2 VPP
Monitor output
Buffer output
Monitor output
Buffer output
450
400
525
MHz
MHz
MHz
Typ
Typ
Typ
–1 dB Flatness
VO = 0.2 VPP
Large-signal
bandwidth
(–3 dB)
VO = 1 VPP
VO = 2 VPP
Monitor output
325
MHz
Typ
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
VO = 1 VPP
VO = 2 VPP
1200
1350
V/µs
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Slew rate
1.15
Group delay at
100 kHz
1.15
ns
0.05/0.05
0.1/0.1
0.05/0.05
0.05/0.05
–71
%
Differential gain
NTSC/PAL
NTSC/PAL
%
degrees
degrees
dB
Differential phase
Total harmonic
distortion
f = 1 MHz
VO = 1 VPP
VO = 2 VPP
Monitor output
–67
dB
Typ
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
Buffer output
Monitor output
63
65
–40
–36
64
66
0
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
Ω
Typ
Typ
Signal-to-noise ratio
No weighting, up to 100 MHz
f = 100 MHz
Typ
Channel-to-channel
crosstalk
Typ
Typ
MUX Isolation
Gain
f = 100 MHz
Typ
f = 100 kHz; VO = 1 VPP
f = 100 kHz; VO = 2 VPP
Typ
6
5.8/6.25 5.75/6.3
5.75/6.35
Min/Max
Typ
6
Settling time
VIN = 1 VPP; 0.5% Settling
f = 10 MHz
6
Typ
0.3
0.4
Typ
Output impedance
Ω
Typ
DC PERFORMANCE
Output offset voltage
Buffer output
Monitor output
Buffer output
Monitor output
15
20
±80
±85
±85
±125
mV
mV
µV/°C
µV/°C
mV
V
Max
Max
Bias = dc
Bias = dc
±120
±125
20
Typ
Average offset
voltage drift
20
Typ
Bias = dc + shift, VIN = 0 V
Bias = ac
265
1.5
185/345 175/355
1.3/1.65 1.25/1.7
145/325 135/335
2.5/2.8 2.45/2.85
205/385 200/390
200/400 195/405
170/360
1.25/1.7
130/340
2.45/2.85
195/395
190/410
–3.5
Min/Max
Min/Max
Min/Max
Min/Max
Min/Max
Min/Max
Max
Buffer output
Bias output voltage
Bias = dc + shift, VIN = 0 V
Bias = ac
235
2.65
295
300
–1.4
mV
V
Monitor output
Buffer output
mV
mV
µA
Sync tip clamp
voltage
Bias = ac STC, clamp voltage
Monitor output
Input bias current
Bias = dc; (–) implies IB out of the pin
Bias = dc
–3.0
–3.5
Average bias current drift
10
nA/°C
µA
Typ
Bias = ac STC, low bias
Bias = ac STC, mid bias
Bias = ac STC, high bias
2.4
6.2
8.6
0.9/3.9
3.9/8.4
6/11.2
0.8/4.0
3.8/8.6
5.8/11.4
0.7/4.1
3.7/8.7
5.7/11.5
Min/Max
Min/Max
Min/Max
Sync tip clamp bias current
µA
µA
6
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ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V (continued)
RL = 150Ω || 5pF to GND for Monitor Output, 19kΩ || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output
Pin, unless otherwise noted.
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/MAX/
TYP
PARAMETER
INPUT CHARACTERISTICS
Input voltage range
TEST CONDITIONS
+25°C
+25°C
UNIT
Bias = dc
0 to 3.4
V
Typ
Typ
Typ
Typ
Bias = ac bias mode
25
3
kΩ
MΩ
pF
Input resistance
Bias = dc, dc + shift, ac STC
Input capacitance
1.5
OUTPUT CHARACTERISTICS: MONITOR OUTPUT
RL = 150 Ω to 2.5 V
4.8
4.7
4.65
4.55
4.6
4.5
4.6
4.5
V
V
Min
Min
Typ
Typ
Max
Max
Typ
Typ
Min
Min
RL = 150 Ω to GND
RL = 75 Ω to 2.5 V
RL = 75 Ω to GND
RL = 150 Ω to 2.5 V
RL = 150 Ω to GND
RL = 75 Ω to 2.5 V
RL = 75 Ω to GND
High output voltage swing
Low output voltage swing
4.7
V
4.6
V
0.2
0.25
0.19
0.28
0.23
0.30
0.24
V
0.1
V
0.24
0.085
110
110
V
V
Sourcing
Sinking
85
85
80
80
75
75
mA
mA
Output current
RL = 10 Ω to 2.5 V
OUTPUT CHARACTERISTICS: BUFFER OUTPUT
High output voltage swing
(Limited by input range and G = 0 dB)
3.4
3.1
3.0
3.0
V
V
Min
Load = 19 kΩ 8 pF to 2.5 V
Low output voltage swing
(Limited by input range and G = 0 dB)
0.05
0.12
0.13
0.14
Max
Sourcing
Output current
RL = 10 Ω to GND
RL = 10 Ω to 2.5 V
110
110
85
85
80
80
75
75
mA
mA
Min
Min
Sinking
POWER SUPPLY: ANALOG
Maximum operating voltage
Minimum operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
POWER SUPPLY: DIGITAL
Maximum operating voltage
Minimum operating voltage
Maximum quiescent current
Minimum quiescent current
VA
5.0
5.0
90
90
46
5.5
2.7
112
68
5.5
2.7
115
65
5.5
2.7
117
63
V
Max
Min
Max
Min
Typ
VA
V
VA, dc + shift mode, VIN = 100 mV
VA, dc + shift mode, VIN = 100 mV
Buffer Output
mA
mA
dB
VDD
5.0
5.0
1
5.5
2.7
2
5.5
2.7
3
5.5
2.7
3
V
V
Max
Min
Max
Min
VDD
VDD, VIN = 0 V
VDD, VIN = 0 V
mA
mA
1
0.5
0.4
0.4
DISABLE CHARACTERISTICS: ALL CHANNELS DISABLED
Quiescent current
All channels disabled
1
5
2
µA
µs
µs
Typ
Typ
Typ
Turn-on time delay (tON
)
Time for lS to reach 50% of final value
after I2C control is initiated
Turn-on time delay (tOFF
)
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ELECTRICAL CHARACTERISTICS, VA = VDD = 5 V (continued)
RL = 150Ω || 5pF to GND for Monitor Output, 19kΩ || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output
Pin, unless otherwise noted.
TYP
OVER TEMPERATURE
0°C to
+70°C
–40°C to
+85°C
MIN/MAX/
TYP
PARAMETER
TEST CONDITIONS
+25°C
+25°C
UNIT
H/V SYNC CHARACTERISTICS: RLoad = 1 kΩ To GND(1)
Schmitt trigger adjust pin voltage
Schmitt trigger threshold range
Reference for Schmitt trigger
1.54
1.43/1.65 1.38/1.7
1.35/1.73
V
V
Min/Max
Typ
Allowable range for Schmitt trigger adjust
0.9 to 2
Positive-going input voltage threshold
relative to Schmitt trigger threshold
Schmitt trigger VT+
Schmitt trigger VT–
0.25
–0.3
10
V
V
Typ
Typ
Typ
Negative-going input voltage threshold
relative to Schmitt trigger threshold
Schmitt trigger threshold pin input
resistance
Input resistance into Control pin
kΩ
H/V Sync input impedance
H/V Sync high output voltage
H/V Sync low output voltage
H/V Sync source current
H/V Sync sink current
H/V Delay
10
4.8
0.01
90
MΩ
V
Typ
Min
Max
Min
Min
Typ
Typ
1 kΩ to GND
4.7
0.05
60
4.6
0.1
55
4.6
0.1
55
1 kΩ to GND
V
10 Ω to GND
mA
mA
ns
ns
10 Ω to 5 V
50
30
27
25
Delay from input to output
6.5
5
H/V to buffer output skew
(1) Schmitt trigger threshold is defined by (VT+ – VT–)/2.
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TIMING REQUIREMENTS FOR I2C INTERFACE(1)(2)
At VDD = 2.7 V to 5 V.
STANDARD MODE
FAST MODE
PARAMETER
MIN
0
MAX
MIN
0
MAX
UNIT
kHz
µs
fSCL
tw(H)
tw(L)
tr
Clock frequency, SCL
100
400
Pulse duration, SCL high
4
0.6
1.3
Pulse duration, SCL low
4.7
µs
Rise time, SCL and SDA
1000
300
300
300
ns
tf
Fall time, SCL and SDA
ns
tsu(1)
th(1)
t(buf)
tsu(2)
th(2)
tsu(3)
Cb
Setup time, SDA to SCL
250
0
100
0
ns
Hold time, SCL to SDA
ns
Bus free time between stop and start conditions
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Capacitive load for each bus line
4.7
4.7
4
1.3
0.6
0.6
0.6
µs
µs
µs
4
µs
400
400
pF
(1) The THS7347 I2C address = 01011(A1)(A0)(R/W). See the Applications Information section for more information.
(2) The THS7347 was designed to comply with version 2.1 of the I2C specification.
t
t
t
t
f
w(H)
w(L)
r
SCL
SDA
t
t
h(1)
su(1)
Figure 1. SCL and SDA Timing
SCL
t
t
t
t
(buf)
su(2)
h(2)
su(3)
SDA
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions
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FUNCTIONAL BLOCK DIAGRAM
Channel 1
Input A
2:1
2:1
2:1
+
-
X1
Channel 2
Input A
Channel 1 Buffer
Output (To ADC)
AC
DC
+Offset
Sync
TIP
Clamp
Channel 3
Input A
DC
AC-
BIAS
+
-
Channel 1 Monitor
Output
H-Sync
Input A
Disable
= OPEN
675 W
V-Sync
Input A
Channel 1 SAG
150 W
1 kW
878 W
X1
+
-
Channel 2 Buffer
Output (To ADC)
AC
Sync
TIP
DC
+Offset
DC
+
-
Clamp
AC-
BIAS
Channel 2 Monitor
Output
Disable
= OPEN
675 W
150 W
Channel 2 SAG
1 kW
878 W
X1
+
-
Channel 3 Buffer
Output (To ADC)
AC
Sync
TIP
DC
+Offset
DC
Clamp
+
-
AC-
BIAS
Channel 3 Monitor
Output
Disable
= OPEN
675 W
150 W
Channel 3 SAG
1 kW
878 W
Channel 1
Input B
2:1
+
-
Horizontal Sync
Buffer OUTPUT
Channel 2
Input B
Channel 3
Input B
Horizontal Sync
Monitor OUTPUT
H-Sync
Input B
2:1
+
-
V-Sync
Input B
Vertical Sync
Buffer OUTPUT
10 kW
Vertical Sync
Monitor OUTPUT
+1.4 V
MUX
MODE
MUX
SELECT
SCHMITT
TRIGGER
ADJUST
I2C, I2C, PUC
A1 A0
SDA SCL
+VDD
+VA AGND
DGND
NOTE: The I2C address of the THS7347 is 01011(A1)(A0)(R/W).
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PIN CONFIGURATION
THS7347IPHP
HTQFP-48 (PHP)
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
CH. 1, BUFFER OUTPUT
1
CH. 1, INPUT A
2
CH. 1, BUFFER OUTPUT
AGND
CH. 2, INPUT A
CH. 3, INPUT A
H-SYNC, INPUT A
V-SYNC, INPUT A
AGND
3
4
+VA
5
CH. 2, BUFFER OUTPUT
CH. 2, BUFFER OUTPUT
AGND
6
THS7347
7
CH. 1, INPUT B
CH. 2, INPUT B
CH. 3, INPUT B
H-SYNC, INPUT B
V-SYNC, INPUT B
AGND
8
+VA
9
CH. 3, BUFFER OUTPUT
CH. 3, BUFFER OUTPUT
AGND
10
11
12
H-SYNC BUFFER OUTPUT
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PIN CONFIGURATION (continued)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
CH. 1, INPUT A
CH. 2, INPUT A
CH. 3, INPUT A
H-SYNC, INPUT A
V-SYNC, INPUT A
CH. 1, INPUT B
CH. 2, INPUT B
CH. 3, INPUT B
H-SYNC, INPUT B
V-SYNC, INPUT B
NO.
1
I
I
I
I
I
I
I
I
I
I
Video Input Channel 1, Input A
Video Input Channel 2, Input A
Video Input Channel 3, Input A
Horizontal Sync, Input A
2
3
4
5
Vertical Sync, Input A
7
Video Input Channel 1, Input B
Video Input Channel 2, Input B
Video Input Channel 3, Input B
Horizontal Sync, Input B
8
9
10
11
Vertical Sync, Input B
I2C Slave Address Control Bit A1. Connect to VDD for a logic 1 preset value or GND for a logic 0 preset
value.
I2C, A1
I2C, A0
SDA
17
18
19
20
I
I
I2C Slave Address Control Bit A0. Connect to VDD for a logic 1 preset value or GND for a logic 0 preset
value.
Serial data line of the I2C bus. Pull-up resistor should have a minimum value = 2 kΩ and a maximum
I/O
I
value = 19 kΩ. Pull up to VDD
.
I2C bus clock line. Pull-up resistor should have a minimum value = 2 kΩ and a maximum value = 19 -kΩ.
SCL
Pull up to VDD
.
Power-Up Condition. Connect to GND for all channels disabled upon power-up. Connect to VDD (logic
high) to set buffer outputs to OFF and monitor outputs ON with ac-bias configuration on Channels 1 to 3
and both H-Sync/V-Sync enabled.
PUC
21
I
Sets the MUX configuration control. Connect to logic low for MUX Select (pin 16) control of the MUX.
Connect to logic high for I2C control of the MUX.
MUX MODE
15
16
I
Controls the MUX selection when MUX MODE (pin 15) is set to logic low. Connect to logic low for MUX
selector set to Input A. Connect to logic high for MUX selector set to Input B.
MUX Select
I
Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B. Connect to ADC/Scalar/Decoder. Both
pins should be connected together on the PCB.
CH. 1, BUFFER OUTPUT
CH. 2, BUFFER OUTPUT
CH. 3, BUFFER OUTPUT
35, 36
31, 32
27, 28
25
O
O
O
O
O
Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B. Connect to ADC/Scalar/Decoder. Both
pins should be connected together on the PCB.
Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B. Connect to ADC/Scalar/Decoder. Both
pins should be connected together on the PCB.
H-SYNC BUFFER
OUTPUT
Horizontal Sync Buffer Output. Connect to ADC/Scalar H-sync input.
Vertical Sync Buffer Output. Connect to ADC/Scalar V-sync input.
V-SYNC BUFFER
OUTPUT
24
Video Monitor Pass-Through Output Channel 1 SAG Correction pin. If SAG is not used, connect Directly
to CH. 1, OUTPUT pin 46.
CH. 1, SAG
45
46
43
44
41
42
40
O
O
O
O
O
O
O
CH. 1, OUTPUT
CH. 2, SAG
Video Monitor Pass-Through Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B.
Video Monitor Pass-Through Output Channel 2 SAG Correction pin. If SAG is not used, connect Directly
to CH. 2, OUTPUT pin 44.
CH. 2, OUTPUT
CH. 3, SAG
Video Monitor Pass-Through Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B.
Video Monitor Pass-Through Output Channel 3 SAG Correction pin. If SAG is not used, connect Directly
to CH. 3, OUTPUT pin 42.
CH. 3, OUTPUT
Video Monitor Pass-Through Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B.
Horizontal Sync Monitor Pass-Through Output.
H-SYNC MONITOR
OUTPUT
V-SYNC MONITOR
OUTPUT
39
O
I
Vertical Sync Monitor Pass-Through Output.
6, 12, 13, 26,
30, 34, 37, 47
Ground Reference pin for analog signals. Internally, these pins connect to DGND, although it is
recommended to have the AGND and DGND connected to the proper signals for best results.
AGND
+VA
29, 33, 38, 48
I
I
I
Analog Positive Power Supply Input pins. Connect to 2.7 V to 5 V. Must be equal to or greater than VDD.
Digital Positive Supply pin for I2C circuitry and H-Sync/V-Sync outputs. Connect to 2.7 V to 5 V.
Digital GND pin for HV circuitry and I2C circuitry.
VDD
22
23
DGND
Defaults to 1.45 V (TTL compatible). Connect to external voltage reference to adjust H-Sync/V-Sync input
thresholds from 0.9 V to 2 V range.
Schmitt Trigger Adjust
14
I
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APPLICATIONS INFORMATION
The THS7347 is targeted for RGB+HV video buffer applications. Although it can be used for numerous other
applications, the needs and requirements of the video signal were the most important design parameters of the
THS7347. Built on the revolutionary complementary silicon-germanium (SiGe) BiCom3 process, the THS7347
incorporates many features not typically found in integrated video parts while consuming very low power. Each
channel configuration is completely independent of the other channels. This architecture allows for any
configuration for each channel to be dictated by the end user, rather than the part dictating what the
configuration must be—resulting in a highly flexible system.
The THS7347 has the following features:
•
•
•
•
•
•
I2C interface for easy interfacing to the system.
Single-supply 2.7-V to 5-V operation with low quiescent current of 80 mA at 3.3 V.
2:1 input mux.
Input configuration accepts dc, dc + shift, ac bias, or ac sync-tip clamp selection.
500-MHz unity-gain buffer amplifier to drive ADC/Scalar/Decoder.
Monitor Pass-Through path has an internal fixed gain of 2 V/V (+6 dB) amplifier that can drive two video lines
per channel with dc coupling, traditional ac coupling, or SAG-corrected ac coupling.
•
•
While disabled, the Monitor Pass-Through path has a very high output impedance (> 500 kΩ || 8 pF)
Power-Up Control (PUC) allows the THS7347 to be fully disabled or have the Monitor Pass-Through function
(with ac-bias mode on all channels) enabled upon initial device power-up.
Mux is controlled by either I2C or a general-purpose input/output (GPIO) pin, based on the MUX Mode pin
logic.
•
•
•
H-Sync and V-Sync paths have an externally-adjustable Schmitt trigger threshold
Disable mode reduces quiescent current to as low as 0.1-µA.
OPERATING VOLTAGE
The THS7347 is designed to operate from 2.7 V to 5 V over a -40°C to +85°C temperature range. The impact on
performance over the entire temperature range is negligible because of the implementation of thin film resistors
and high-quality, low temperature coefficient capacitors.
A 0.1-µF to 0.01-µF capacitor should be placed as close as possible to the power-supply pins. Failure to do so
may result in the THS7347 outputs ringing or oscillating. Additionally, a large capacitor, such as 100 µF, should
be placed on the power-supply line to minimize issues with 50-Hz/60-Hz line frequencies.
INPUT VOLTAGE
The THS7347 input range allows for an input signal range from ground to approximately (VS+ – 1.6 V). However,
because of the internal fixed gain of 2 V/V (+6 dB), the output is generally the limiting factor for the allowable
linear input range. For example, with a 5-V supply, the linear input range is from GND to 3.4 V. As a result of the
gain, the linear output range limits the allowable linear input range from GND to 2.5 V at most.
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APPLICATIONS INFORMATION (continued)
INPUT OVERVOLTAGE PROTECTION
The THS7347 is built using a very high-speed complementary bipolar and CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 3.
VS+
External
Internal
Circuitry
Input/
Output
Pin
Figure 3. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies. The
protection diodes can typically support 30 mA of continuous current when overdriven.
TYPICAL CONFIGURATION
A typical application circuit usng the THS7347 as an ac-coupled input video buffer is shown in Figure 4. It shows
the THS7347 driving a video ADC (such as the TVP7000) with 0-dB gain and also driving an output line with
6-dB gain. The Horizontal and Vertical Sync signals are also driven to the ADC and the Monitor Output
separately. Although the computer resolution R’G’B’HV signals are shown, these channels can easily be the
high-definition video (HD), enhanced-definition (ED), or standard-definition (SD) Y’P’BP’R (sometimes labeled
Y’U’V’ or incorrectly labeled Y’C’BC’R) channels. These channels could also be S-Video Y’/C’ channels and the
composite video baseband signal (CVBS). Note that the R’G’B’ channels could be professional/broadcast G’B’R’
signals or other R’G’B’ variations based on the placement of the sync signals that are commonly called R’G’sB’
(sync on Green) or R’sG’sB’s (sync on all signals).
The second set of inputs (B-Channels) shown are connected to another set of inputs. Again, these inputs can be
either HD, ED, SD, or R'G'B'/G'B'R' video signals. The THS7347 flexibility allows for virtually any input signal to
be driven into the THS7347 regardless of the other set of inputs. Simple control of the I2C configures the
THS7347 for any conceivable combination. For example, the THS7347 can be configured to have Channel 1
Input connected to input A while Channel 2 and Channel 3 are connected to input B. See the multiple application
notes sections explaining the I2C interface later in this document for details on configuring these options.
Note that the Y' term is used for the luma channels throughout this document, rather than the more common
luminance (Y) term. The reason for this usage is to account for the true definition of luminance as stipulated by
the CIE (International Commission on Illumination). Video departs from true luminance because a nonlinear
term, gamma, is added to the true RGB signals to form R'G'B' signals. These R'G'B' signals are then utilized to
mathematically create luma (Y'). Therefore, true luminance (Y) is not maintained, and thus the difference in
terminology arises.
This rationale is also utilized for the chroma (C') term. Chroma is derived from the nonlinear R'G'B' terms and
therefore it is also nonlinear. True chominance (C) is derived from linear RGB, and thus the difference between
chroma (C') and chrominance (C) exists. The color difference signals (P'B/ P'R/U'/V') are also referenced this way
to denote the nonlinear (gamma-corrected) signals.
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APPLICATIONS INFORMATION (continued)
R'G'B' (commonly labeled RGB) is also called G'B'R' (again commonly labeled as GBR) in professional video
systems. The SMPTE component standard stipulates that the luma information is placed on the first channel, the
blue color difference is placed on the second channel, and the red color difference signal is placed on the third
channel. This approach is consistent with the Y'P'BP'R nomenclature. Because the luma channel (Y') carries the
sync information and the green channel (G') also carries the sync information, it makes logical sense that G' be
placed first in the system. Since the blue color difference channel (P'B) is next and the red color difference
channel (P'R) is last, then it also makes logical sense to place the B' signal on the second channel and the R'
signal on the third channel, respectively. Thus, hardware compatibility is better achieved when using G'B'R'
rather than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels; this
configuration may not always be the case for all systems.
Monitor Output
2.2 mF
Red
75 W
75 W
Y’
2.2 mF
Green
75 W
75 W
75 W
P’B
P’R
2.2 mF
Blue
75 W
VA
VA
H-Sync 806 W
1.4 kW
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
V-Sync
806 W
+3.3 V +1.8 V
2
3
0.1 mF
VA
1.4 kW
4
ADC
Scalar/
Decoder
0.1 mF
VA
5
0.1 mF
6
Y’
THS7347
Component
7
30
29
28
27
26
25
8
480i
576i
75 W
2.2 mF
0.1 mF
9
10
11
12
480p
576p
720p
1080i
1080p
G’B’R’
P’B
P’R
75 W
2.2 mF
13 14 15 16 17 18 19 20 21 22 23 24
3.3 V
3.3 V
22 pF
75 W
H-Sync and
V-Sync
Not Used
0.1 mF
22 pF
100
100
VA = 3.3 V to 5 V
I2C
(1) Inputs and/or outputs can be ac- or dc-coupled if desired.
(2) H-Sync and V-Sync input resistance as shown above = 2.2kΩ, but may be changed to any desired resistance.
(3) If the Monitor or Buffer PCB trace is >25 mm, it is recommended to place at least a 10-Ω resistor in series with each
signal to reduce PCB parasitic issues
Figure 4. Typical R'G'B'HV and Y'P'BP'R AC-Coupled Inputs and DC-Coupled Output Configuration
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APPLICATIONS INFORMATION (continued)
I2C INTERFACE NOTES
The I2C interface is used to access the internal registers of the THS7347. I2C is a two-wire serial interface
developed by Philips Semiconductor (see the I2C Bus Specification, Version 2.1, January 2000). The THS7347
was designed in compliance with version 2.1 specifications. The bus consists of a data line (SDA) and a clock
line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the
I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device,
usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating
the SCL signal and device addresses. The master also generates specific conditions that indicate the START
and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master
device. The THS7347 works as a slave and supports the standard mode transfer (100 kbps) and fast mode
transfer (400 kbps) as defined in the I2C Bus Specification. The THS7347 has been tested to be fully functional
with the high-speed mode (3.4 Mbps) but it is not specified at this time.
Figure 5 shows the basic I2C start and stop access cycles.
The basic access cycle consists of the following:
•
•
•
•
A start condition
A slave address cycle
Any number of data cycles
A stop condition
SDA
SCL
S
P
Start
Condition
Stop
Condition
Figure 5. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
The master initiates data transfer by generating a start condition. The start condition exists when a
high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 5. All I2C-compatible
devices should recognize a start condition.
•
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 6). All devices
recognize the address sent by the master and compare it to the respective internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 7) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
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APPLICATIONS INFORMATION (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 6. I2C Bit Transfer
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 7. I2C Acknowledge
•
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 8).
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Stop
Acknowledge
MSB
Acknowledge
Slave Address
Data
Figure 8. I2C Address and Data Cycles
•
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 5). This transaction releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition.
Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start
condition followed by a matching address.
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APPLICATIONS INFORMATION (continued)
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. Figure 9 and Figure 10 show an example of a write cycle. Note that the
THS7347 does not allow multiple write transfers to occur. See the example, Writing to the THS7347, in
Section 12 for more information.
From Receiver
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
S
Slave Address
W
A
DATA
A
DATA
P
A
R = Read
From Transmitter
Figure 9. I2C Write Cycle
Acknowledge
(From Receiver)
Acknowledge
(Receiver)
Acknowledge
(Transmitter)
Start
Condition
A6
A5
A1 A0 R/W ACK D7
D6
D1 D0 ACK
D7
D6
D1 D0
ACK
SDA
I2C Device Address and
Read/Write Bit
Stop
Condition
First Data
Byte
Other
Data Bytes
Last Data Byte
Figure 10. Multiple Byte Write Transfer
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just
before it asserts the stop (P) condition. This sequence terminates a read cycle, as shown in Figure 11 and
Figure 12. Note that the THS7347 does not allow multiple read transfers to occur. See the example, Reading
from the THS7347, in Section 12 for more information.
A = No Acknowledge (SDA High)
S
Slave Address
R
A
DATA
A
DATA
P
A
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
Transmitter
Receiver
Figure 11. I2C Read Cycle
Start
Condition
Acknowledge
(From
Receiver)
Acknowledge
(From
Transmitter)
Not
Acknowledge
(Transmitter)
A6
A0 R/W ACK D7
D0
ACK
D7
D6
D1
D0 ACK
SDA
Stop
Condition
I2C Device Address and
Read/Write Bit
First Data
Byte
Other
Data Bytes
Last Data Byte
Figure 12. Multiple Byte Read Transfer
18
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APPLICATIONS INFORMATION (continued)
Slave Address
Both the SDA and the SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors
should range from 2 kΩ to 19 kΩ in order to comply with the I2C specification. When the bus is free, both lines
are high. The address byte is the first byte received following the START condition from the master device. The
first five bits (MSBs) of the address are factory-preset to 01011. The next two bits of the THS7347 address are
controlled by the logic levels appearing on the I2C, A1 and I2C, A0 pins. The I2C, A1 and I2C, A0 address inputs
can be connected to VDD for logic 1, GND for logic 0, or actively driven by TTL/CMOS logic levels. The device
address is set by the state of these pins and is not latched. Thus, a dynamic address control system could be
used to incorporate several devices on the same system. Up to four THS7347 devices can be connected to the
same I2C bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7347.
Table 1. THS7347 Slave Addresses
SELECTABLE WITH
ADDRESS PINS
READ/WRITE
BIT
FIXED ADDRESS
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 (A1)
Bit 1 (A0)
Bit 0 (R/W)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin
The THS7347 operates using only a single-byte transfer protocol similar to that illustrated in Figure 9 and
Figure 11. The internal subaddress registers and the functionality of each are given in Table 2. When writing to
the device, it is required to send one byte of data to the corresponding internal subaddress. If control of all three
channels is desired, then the master must cycle through all the subaddresses (channels) one at a time; see the
example, Writing to the THS7347 (in Section 12) for the proper procedure of writing to the THS7347.
During a read cycle, the THS7347 sends the data in its selected subaddress (or channel) in a single transfer to
the master device requesting the information. See the Reading from the THS7347 example (in Section 12) for
the proper procedure on reading from the THS7347.
On power-up, the THS7347 registers are dictated by the Power-Up Control (PUC) pin. If the PUC pin is tied to
GND, the THS7347 powers up in a fully disabled state. If the PUC pin is tied to VDD, upon power-up the
THS7347 is configured in the following state: ADC buffers disabled, monitor pass-through enabled, and ac-bias
on, for all three input channels. It remains in the state dictated by the PUC unti a valid write sequence is
completed.
Table 2. THS7347 Channel Selection Register Bit Assignments
BIT ADDRESS
REGISTER NAME
Channel 1
(b7b6b5....b0)
0000 0001
0000 0010
0000 0011
Channel 2
Channel 3
Channel H Sync, Channel V Sync, and
Disable Controls
0000 0100
19
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Channel Register Bit Descriptions
Each bit of the subaddress (channel selection) control register as described in the previous section allows the
user to individually control the THS7347 functionality. This process allows the user to control the functionality of
each channel independently with regard to the other channels. The bit description for Channel 1 through
Channel 3 is shown in Table 3, while the H/V sync channels and the analog channel states are described in
Table 4.
Table 3. THS7347 Channel Register (Channel 1 through Channel 3) Bit Decoder Table.
Use with Register Bit Codes (0000 0001), (0000 0010), and (0000 0011)
BIT
FUNCTION
BIT VALUE(S)
0
RESULT
500-kHz filter on the STC circuit
(MSB)
7
Sync-Tip Clamp Filter
1
5-MHz filter on the STC circuit
MUX Input A
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0
MUX Input A
MUX Input A
MUX Input A
MUX Input A
MUX Input B
MUX Input B
MUX Input B
6, 5, 4, 3
MUX Selection
MUX Input B
MUX Input B
Reserved; do not care
Reserved; do not care
Reserved; do not care
Reserved; do not care
Reserved; do not care
Reserved; do not care
Disables both monitor and buffer paths of the respective
channel/register
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Channel Mute
Input Mode = dc
Input Mode
+
Operation
2, 1, 0
(LSB)
Input Mode = dc + Shift
Input Mode = ac-bias
Input Mode = ac-STC with low bias
Input Mode = ac-STC with mid bias
Input Mode = ac-STC with high bias
Bit 7 (MSB): Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected.
Bits 6, 5, 4, 3: Selects the Input MUX channel.
Bits 2, 1, and 0 (LSB): Configures the channel mode and operation. See Table 4, Bits 6 and 5, for more
information with respect to the enable/disable state.
20
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Table 4. THS7347 Channel Register (H/V Sync Channel + Analog Channels State) Bit Decoder Table.
Use in Conjunction With Register Bit Code (0000 0100)
BIT
BIT
FUNCTION
VALUE(S)
RESULT
(MSB)
7
Reserved; Do not care
X
0
Reserved; do not care
Disables all monitor channels regardless of bits 2:0 of Register 1
through Register 3
Monitor Pass-Through Path Disable
Mode
(Use in Conjunction with Table 3)
6
5
1
0
1
Enables monitor channels functions dictated by each programmed
register code
Disables all buffer channels regardless of bits 2:0 of Register 1
through Register 3
Buffer Path Disable Mode
(Use in Conjunction with Table 3)
Enables buffer channel functions dictated by each programmed
register code
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0
MUX Input A
MUX Input B
4, 3
2, 1
Vertical Sync Channel MUX Selection
Reserved; do not care
Reserved; do not care
MUX Input A
MUX Input B
Horizontal Sync Channel MUX Selection
H/V Sync Paths Disable Mode
Reserved; do not care
Reserved; do not care
Disable H-Sync and V-Sync Channels
Enable H-Sync and V-Sync Channels
0
(LSB)
1
Bit (MSB) 7: Reserved; do not care.
Bit 6: Master Monitor Path Disable. Disables all monitor channels regardless of what is programmed into
each register channel (1 to 3).
Bit 5: Master Buffer Path Disable. Disables all buffer channels regardless of what is programmed into each
register channel (1 to 3).
Bits 4, 3: Selects the Input MUX channel for the Vertical Sync.
Bits 2, 1: Selects the Input MUX channel for the Horizontal Sync.
Bit 0 (LSB): Enables or disables the H-Sync and V-Sync Channels.
21
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WRITE AND READ EXAMPLES
These examples illustrate the proper way to write to and read from the THS7347.
WRITING TO THE THS7347
An I2C master initiates a write operation to the THS7347 by generating a start condition (S) followed by the
THS7347 I2C address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an
acknowledge from the THS7347, the master presents the subaddress (channel) it wants to write, consisting of
one byte of data, MSB first. The THS7347 acknowledges the byte after completion of the transfer. Finally, the
master presents the data it wants to write to the register (channel) and the THS7347 acknowledges the byte.
The I2C master then terminates the write operation by generating a stop condition (P). Note that the THS7347
does not support multi-byte transfers. To write to all three channels (or registers), this procedure must be
repeated for each register, one series at a time (that is, repeat steps 1 through 8 for each channel).
Step 1
0
I2C Start (Master)
S
Step 2
7
0
6
1
5
0
4
1
3
1
2
1
0
0
I2C General Address (Master)
X
X
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
7
0
6
0
5
0
4
0
3
0
2
1
0
I2C Write Channel Address (Master)
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
7
6
5
4
3
2
1
0
I2C Write Data (Master)
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the values shown in Table 3.
Step 7
9
I2C Acknowledge (Slave)
A
Step 8
0
I2C Stop (Master)
P
22
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READING FROM THE THS7347
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the THS7347 by generating a start condition (S) followed by the THS7347 I2C
address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an acknowledge from the
THS7347, the master presents the subaddress (channel) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7347 by
generating a start condition followed by the THS7347 I2C address, in MSB-first order, followed by a '1' to
indicate a read cycle. After an acknowledge from the THS7347, the I2C master receives one byte of data from
the THS7347. After the data byte has been transferred from the THS7347 to the master, the master generates a
not-acknowledge (A) followed by a stop. As with the Write function, to read all channels, steps 1 through 11
must be repeated for each channel desired.
THS7347 Read Phase 1:
Step 1
0
I2C Start (Master)
S
Step 2
7
0
6
1
5
0
4
1
3
1
2
1
0
0
I2C General Address (Master)
X
X
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
7
0
6
0
5
0
4
0
3
0
2
1
0
I2C Read Channel Address (Master)
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
0
I2C Start (Master)
P
THS7347 Read Phase 2:
Step 7
0
I2C Start (Master)
S
Step 8
7
0
6
1
5
0
4
1
3
1
2
1
0
1
I2C General Address (Master)
X
X
Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.
Step 9
9
I2C Acknowledge (Slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read Data (Slave)
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the logic values contained in the Channel Register.
Step 11
9
I2C Not-Acknowledge (Master)
A
Step 12
0
I2C Stop (Master)
P
23
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PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2007
PACKAGING INFORMATION
Orderable Device
THS7347IPHP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PHP
48
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
THS7347IPHPR
HTQFP
PHP
48
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
THS7347IPHPR
PHP
48
TAI
330
16
9.6
9.6
1.5
12
16
Q2
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
TAI
Length (mm) Width (mm) Height (mm)
THS7347IPHPR
PHP
48
346.0
346.0
33.0
Pack Materials-Page 2
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