THS770012IRGER [TI]
Broadband, Fully-Differential, 14-/16-Bit ADC Driver Amplifier; 宽带全差动， 14位/ 16位ADC驱动器放大器
| 型号： | THS770012IRGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Broadband, Fully-Differential, 14-/16-Bit ADC Driver Amplifier |
| 文件： | 总35页 (文件大小：1245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS770012
www.ti.com
SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
Broadband, Fully-Differential, 14-/16-Bit ADC Driver Amplifier
Check for Samples: THS770012
1
FEATURES
DESCRIPTION
The THS770012 is a wideband, fully-differential
amplifier, with adjustable gain range from +10dB to
+13.7dB (with external components). It is designed
and optimized specifically for driving 16-bit
analog-to-digital converters (ADCs) at input
frequencies up to 130MHz, and 14-bit ADCs at input
frequencies up to 200MHz. This device provides high
bandwidth, high-voltage output with low distortion and
low noise, critical in high-speed data acquisition
systems that require very high dynamic range, such
as wireless base stations and test and measurement
applications. This device also makes an excellent
differential amplifier for general-purpose, high-speed
differential signal chain and short line driver
applications.
23
•
900MHz Bandwidth at Gain of +10dB
3300V/µs Slew Rate, VOUT = 2V step
Adjustable Gain: +10dB to +13.7dB
•
•
•
IMD3: –100dBc, VOUT = 2VPP, RL = 400Ω,
f = 100MHz
•
•
OIP3: 47dBm, f = 100MHz
Noise Figure: 10.7 dB, f = 100MHz
APPLICATIONS
•
•
14-/16-Bit ADC Driver
ADC Driver for Wireless Base Station Signal
Chains: GSM, WCDMA, MC-GSM, LTE
•
ADC Driver for High Dynamic Range Test and
Measurement Equipment
The THS770012 operates on a nominal +5V single
supply, offers very fast, 7.5ns maximum recovery
time from overdrive conditions, and has
power-down mode for power saving. The THS770012
is offered in a Pb-free (RoHS compliant) and green,
a
Figure 1. THS770012 Driving 16-Bit ADC
200W
QFN-24
thermally-enhanced
package.
It
is
characterized for operation over the industrial
temperature range of –40°C to +85°C.
RO
50W
50W
AIN+
VIN-
30MHz
Bandpass
Filter
VOCM
16-Bit ADC
AIN-
VIN+
RELATED DEVICES
RO
200W
VOCM
DEVICE
DESCRIPTION
THS770012
(G=12dB)
Fixed Gain of +6dB, wideband, low-noise,
low-distortion, fully-differential amplifier
THS770006
Wideband, low-noise, low-distortion,
fully-differential amplifier
THS4509
PGA870
Figure 2. FFT Plot with Two-Tone Input at 96MHz
and 100MHz (see Application Information section)
Wideband, low-noise, low-distortion,
fully-differential, digitally-programmable
gain amplifier
0
-10
-20
ADS5481 to
ADS5485
16-bit, 80MSPS to 200MSPS ADCs
-30
-40
ADS6145
ADS6149
14-bit, 125MSPS ADC
14-bit, 250MSPS ADC
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Frequency - MHz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
THS770012
SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
TYPE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
THS770012IRGE THS770012IRGET
Tape and reel, 250
THS770012
VQFN-24
RGE
–40°C to +85°C
THS770012IRGE THS770012IRGER Tape and reel, 3000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Figure 3. DEVICE MARKING INFORMATION
= Pin 1 designator
THS7700
THS7700012IRGE = device name
12IRGE
TI = TI LETTERS
YM = YEAR MONTH DATE CODE
TI YMS
S = ASSEMBLY SITE CODE
LLLL = ASSY LOT CODE
LLLL
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
THS770012
UNIT
V
Power supply (VS+ to GND)
5.5
Ground to VS+
Ground to VS+
10
Input voltage range
V
Differential input voltage, VID
V
Continuous input current, II
mA
mA
°C
°C
°C
V
Continuous output current, IO
100
Storage temperature range, Tstg
Maximum junction temperature, TJ
Maximum junction temperature, continuous operation, long term reliability
Human body model (HBM)
–65°C to +150°C
+150
+125
2500
ESD ratings
Charged device model (CDM)
Machine model (MM)
1000
V
100
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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Product Folder Link(s): THS770012
THS770012
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SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
THERMAL INFORMATION
THS770012
UNITS
THERMAL METRIC(1)
RGE (24) PINS
θJA
Junction-to-ambient thermal resistance
44.1
35
θJC(top)
θJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
19
°C/W
0.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
18.8
8.9
θJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input
and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as
discussed in Test Circuits section.
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
AC PERFORMANCE
Gain = +10dB, VOUT = 200mVPP
900
810
680
540
845
790
680
548
130
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Gain = +11dB, VOUT = 200mVPP
Gain = +12dB, VOUT = 200mVPP
Gain = +13.7dB, VOUT = 200mVPP
Gain = +10dB, VOUT = 2VPP
Gain = +11dB, VOUT = 2VPP
Gain = +12dB, VOUT = 2VPP
Gain = +13.7dB, VOUT = 2VPP
Gain = +12dB, VOUT = 2VPP
VOUT = 2V step
Small-signal bandwidth
Large-signal bandwidth
Bandwidth for 0.1dB flatness
Slew rate
3300
3400
0.6
VOUT = 4V step
Rise time
VOUT = 2V step
Fall time
VOUT = 2V step
0.6
ns
Settling time to 0.1%
Input return loss, s11
Output return loss, s22
Reverse isolation, s12
VOUT = 2V step
2.2
ns
See s-Parameters section, f < 200MHz
See s-Parameterssection, f < 200MHz
See s-Parameters section, f < 200MHz
f = 10MHz
–18
–16
–60
–90
–70
–73
–74
–100
–85
–84
–73
–62
–76
–78
–78
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Second-order harmonic
distortion, Gain = +12dB, RL
400Ω, VOUT = 2VPP
f = 50MHz
=
f = 100MHz
f = 200MHz
f = 10MHz
Third-order harmonic distortion,
Gain = +12dB, RL = 400Ω, VOUT
= 2VPP
f = 50MHz
f = 100MHz
f = 200MHz
f = 50MHz, 10MHz spacing
f = 100MHz, 10MHz spacing
f = 150MHz, 10MHz spacing
f = 200MHz, 10MHz spacing
Second-order intermodulation
distortion, Gain = +12dB, RL
=
400Ω, VOUT = 2VPP
(1) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Copyright © 2010–2012, Texas Instruments Incorporated
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SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
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ELECTRICAL CHARACTERISTICS (continued)
Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input
and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as
discussed in Test Circuits section.
TEST
PARAMETER
TEST CONDITIONS
f = 50MHz, 10MHz spacing
MIN
TYP
MAX
UNIT
LEVEL(1)
–97
dBc
dBc
dBc
dBc
dBm
dBm
C
C
C
C
C
C
Third-order intermodulation
distortion, Gain = +12dB, RL
400Ω, VOUT = 2VPP
f = 100MHz, 10MHz spacing
f = 150MHz, 10MHz spacing
f = 200MHz, 10MHz spacing
–100
–92
–81
19.6
8.7
=
RL = 20Ω
RL = 400Ω
1dB compression point
f = 100MHz
Output third-order intercept
point
At device outputs, RL = 400Ω, f = 100MHz
47
dBm
C
Input-referred voltage noise
Ouput-referred voltage noise
f = 1MHz
f = 1MHz
f = 50 MHz
100Ω differential
f = 100 MHz
source
f = 200 MHz
Overdrive = ±0.5V
f = 200MHz
1.5
6
nV/√Hz
nV/√Hz
dB
C
C
C
C
C
B
C
C
9.5
10.7
12.3
5
Noise figure
dB
dB
Overdrive recovery
Output balance error
Output impedance
DC PERFORMANCE
7.5
ns
-60
4
dB
f = 100MHz
Ω
TA = +25°C, RL = 400Ω
TA = +25°C, RL = 100Ω
TA = –40°C to +85°C, RL = 400Ω
TA = –40°C to +85°C, RL = 100Ω
TA = +25°C
11.65
11.9
11.6
12.15
11.85
12.2
12.2
20
dB
dB
dB
dB
mV
mV
dB
dB
A
B
B
B
A
B
A
B
11.4
11.6
11.6
–20
Gain (+12dB gain setting)
Output offset
±2
TA = –40°C to +85°C
TA = +25°C
–22.5
36
22.5
60
Common-mode rejection ratio
TA = –40°C to +85°C
35
INPUT
Differential input resistance
Input common-mode range
OUTPUT
85
100
115
Ω
A
A
Inputs shorted together, VOCM = 2.5V
2.25
2.75
V
TA = +25°C
3.64
3.59
3.7
1.3
3.6
1.3
4.8
V
V
A
B
A
B
A
B
A
B
B
B
B
B
Each output with
200Ω to midsupply
Most positive output voltage
Least positive output voltage
Most positive output voltage
Least positive output voltage
Differential output voltage
TA = –40°C to +85°C
TA = +25°C
1.4
V
Each output with
200Ω to midsupply
TA = –40°C to +85°C
1.45
V
TA = +25°C
3.59
3.54
V
Each output with
50Ω to midsupply
TA = –40°C to +85°C
V
TA = +25°C
1.5
V
Each output with
50Ω to midsupply
TA = –40°C to +85°C
1.55
V
TA = +25°C, RL = 400Ω
4.4
4.2
VPP
VPP
mA
mA
TA = –40°C to +85°C, RL = 400Ω
TA = +25°C, RL = 10Ω
80
80
Differential output current drive
TA = –40°C to +85°C, RL =10Ω
4
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Product Folder Link(s): THS770012
THS770012
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SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS (continued)
Test conditions are at TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input
and output, and input and output referenced to midsupply, unless otherwise noted. Measured using evaluation module as
discussed in Test Circuits section.
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
OUTPUT COMMON-MODE VOLTAGE CONTROL
VOCM small-signal bandwidth
VOCM slew rate
VOUT_CM = 200mVPP
300
150
2.5
1
MHz
V/µs
V
C
C
C
A
VOUT_CM = 500mV step
Supplied by external source(2)
VOCM = 2.5V
VOCM voltage range
VOCM gain
2.25
2.75
0.98
–30
1.02
30
V/V
Output common-mode offset
from VOCM input
VOCM = 2.5V
±12
±30
mV
A
A
VOCM input bias current
POWER SUPPLY
2.25V ≤ VOCM ≤ 2.75V
–400
400
µA
Specified operating voltage
4.75
85
5
5.25
115
125
V
C
A
B
A
B
TA = +25°C
100
mA
mA
dB
dB
Quiescent current
TA = –40°C to +85°C
80
TA = +25°C, VS+ = 5V ±0.25V
TA = –40°C to +85°C, VS+ = 5V ±0.5V
60
90
Power-supply rejection ratio
59
POWER-DOWN
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
Device powers on below 0.5V
0.5
V
V
A
A
A
A
C
C
Device powers down above 2.0V
2
0.8
80
3
mA
µA
µs
µs
100
Turn-on time delay
Time to VOUT = 90% of final value
Time to VOUT = 10% of original value
10
Turn-off time delay
0.15
THERMAL CHARACTERISTICS
Specified operating range
–40
+85
°C
C
C
C
(3)
Thermal resistance, θJC
Junction to case (bottom)
Junction to ambient
8.9
°C/W
°C/W
(3)
Thermal resistance, θJA
44.1
(2) Limits set by best harmonic distortion with VOUT = 3VPP. VOCM voltage range can be extended if lower output swing is used or distortion
degradation is allowed, and increased bias current into pin is acceptable. For more information, see Figure 18 and Figure 34.
(3) Tested using JEDEC High-K test PCB. Thermal management of the final printed circuit board (PCB) should keep the junction
temperature below +125°C for long term reliability.
Copyright © 2010–2012, Texas Instruments Incorporated
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PIN CONFIGURATION
RGE PACKAGE
VQFN-24
(TOP VIEW)
24
23
22
21
20
19
200Ω
1
2
3
4
5
6
18
17
16
15
14
13
NC
PD
GS+
60Ω
140Ω
Unused
50Ω
2Ω
2Ω
V
V
-
+
OUT+
IN-
VOCM
V
-
+
V
IN+
OUT-
50Ω
60Ω
140Ω
V
Unused
GS-
OCM
200Ω
NC
7
8
9
10
11
12
PIN DESCRIPTIONS
PIN
DESCRIPTION
NO.
1
NAME
NC
No internal connection
2
PD
Power down. High = low power (sleep) mode. Low = active.
Inverting input pin
3
VIN–
VIN+
4
Non-inverting input pin
5
VOCM Output common-mode voltage control input pin
NC No internal connection
GND Ground. Must be connected to thermal pad.
6, 7
8, 9, 10, 11
12
13
14
15
16
17
18
19
NC
No internal connection
GS-
Gain-setting connection for inverting output
Unused Bonded to die, but not used. Tie to GND.
VOUT– Inverting output pin
VOUT+ Non-inverting output pin
Unused Bonded to die, but not used. Tie to GND.
GS+
NC
Gain-setting connection for non-inverting output
No internal connection
20, 21, 22,
23
VS+
NC
Power supply pins, +5V nominal
No internal connection
24
Thermal pad
Thermal pad on bottom of device is used for heat dissipation and must be tied to GND
6
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SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
TITLE
FIGURE
Figure 4
200mVPP Frequency Response Magnitude
200mVPP Frequency Response Phase
2VPP Frequency Response Magnitude
2VPP Frequency Response Phase
3VPP Frequency Response Magnitude
3VPP Frequency Response Phase
Small- and Large-Signal Pulse Response
Slew Rate vs Output Voltage Step
Overdrive Recovery
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Single-Ended Input Harmonic Distortion vs Frequency
Harmonic Distortion vs Frequency
Harmonic Distortion vs Output Voltage
Harmonic Distortion vs Load
Harmonic Distortion vs Gain
Harmonic Distortion vs Output Common-Mode Voltage
Intermodulation Distortion vs Frequency
Output Intercept Point vs Frequency
Maximum Differential Output Voltage Swing Peak-to-Peak vs Differential Load Resistance
Maximum/Minimum Single-Ended Output Voltage vs Differential Load Resistance
Differential Output Impedance vs Frequency
Frequency Response vs Capacitive Load
Recommended Output Resistance vs Capacitive Load
Common-Mode Rejection Ratio vs Frequency
Power-Supply Rejection Ratio vs Frequency
Turn-On Time
Turn-Off Time
Input and Output Voltage Noise vs Frequency
Output Balance Error vs Frequency
VOCM Small-Signal Frequency Response
Output Common-Mode Pulse Response
VOCM Input Bias Current vs VOCM Input Voltage
s-Parameters (Magnitude)
Noise Figure vs Frequency
Copyright © 2010–2012, Texas Instruments Incorporated
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SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
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TYPICAL CHARACTERISTICS
At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input and output, input
and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section.
200mVPP FREQUENCY RESPONSE MAGNITUDE
200mVPP FREQUENCY RESPONSE PHASE
45
3
0
V
= 200 mV
OUT
PP
V
= 200 mV
PP
OUT
0
G = 11 dB
G = 10 dB
-3
-6
-9
G = 11 dB
-45
-90
G = 13.7 dB
G = 12 dB
G = 13.7 dB
G = 12 dB
G = 10 dB
-135
-180
-12
-15
10M
100M
1G
1G
1G
1G
10M
100M
10G
Frequency - Hz
Frequency - Hz
Figure 4.
Figure 5.
2VPP FREQUENCY RESPONSE MAGNITUDE
2VPP FREQUENCY RESPONSE PHASE
45
3
0
V
= 2 V
V
= 2 V
OUT
PP
OUT
PP
0
G = 11 dB
G = 11 dB
-3
-6
-9
-45
-90
G = 10 dB
G = 13.7 dB
G = 12 dB
G = 10 dB
G = 13.7 dB
G = 12 dB
-135
-180
-12
-15
10M
100M
10M
100M
1G
10G
Frequency - Hz
Frequency - Hz
Figure 6.
Figure 7.
3VPP FREQUENCY RESPONSE MAGNITUDE
3VPP FREQUENCY RESPONSE PHASE
45
0
3
0
V
= 3 V
OUT
PP
V
= 3 V
PP
OUT
G = 11 dB
-3
-6
-9
G = 10 dB
G = 11 dB
-45
-90
-135
-180
G = 13.7 dB
G = 12 dB
G = 10 dB
G = 13.7 dB
G = 12 dB
-12
-15
10M
100M
10M
100M
1G
10G
Frequency - Hz
Frequency - Hz
Figure 8.
Figure 9.
8
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SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input and output, input
and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section.
SLEW RATE
SMALL- AND LARGE-SIGNAL PULSE RESPONSE
vs OUTPUT VOLTAGE STEP
3
2
4000
3000
2000
1000
0
1
0
-1
-2
-3
0
20
40
60
80
100
120
0
1
2
3
4
5
1G
5
Time - ns
Output Voltage - V
PP
Figure 10.
Figure 11.
SINGLE-ENDED INPUT
OVERDRIVE RECOVERY
HARMONIC DISTORTION vs FREQUENCY
2
1
0
-60
-65
8
HD
V
2
V
= 3 V
PP
IN
OUT
OUT
OUT
6
V
V
= 2 V
PP
-70
= 1 V
PP
4
-75
-80
2
V
OUT
-85
0
-90
-2
-4
-95
HD
3
V
V
V
= 3 V
= 2 V
= 1 V
-100
-105
OUT
OUT
OUT
PP
PP
PP
-1
-2
-6
-8
-110
-115
0
50
100
150
200
10M
100M
Times - ns
Frequency - Hz
Figure 12.
Figure 13.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
-60
-65
-65
-70
-75
-80
-85
-90
HD
V
f = 100 MHz,
= 400 W
2
R
= 3 V
L
HD
2
OUT
OUT
OUT
PP
-70
V
V
= 2 V
= 1 V
PP
PP
-75
-80
-85
HD
3
-90
-95
HD
3
-100
-105
V
V
V
= 3 V
= 2 V
= 1 V
OUT
OUT
OUT
PP
PP
PP
-95
-110
-115
-100
10M
100M
1G
0
1
2
3
4
Frequency - Hz
V
- Output Voltage - V
OUT
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input and output, input
and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section.
HARMONIC DISTORTION
vs LOAD
HARMONIC DISTORTION
vs GAIN
-50
-60
-70
-80
-65
-70
-75
-80
-85
-90
V
= 2 V
,
PP
OUT
f = 100 MHz,
= 2 V
R
L
= 400 W
V
OUT
PP
HD
2
HD
2
HD
3
HD
3
-90
-100
9
10
11
12
13
14
0
200
400
600
- Load - W
800
1K
Gain - dB
R
L
Figure 16.
Figure 17.
HARMONIC DISTORTION
vs OUTPUT COMMON-MODE VOLTAGE
INTERMODULATION DISTORTION
vs FREQUENCY
-20
-30
-40
-50
-60
-70
-80
-90
-60
-65
-70
-75
-80
-85
-90
IMD2
f = 100 MHz
V
V
V
= 3 V Envelope,
PP
OUT
OUT
OUT
= 2 V Envelope,
PP
V
= 3 V
HD2
OUT
PP
= 1 V Envelope
PP
= 3 V
PP
V
OUT
HD3
IMD3
V
= 3 V Envelope,
PP
OUT
V
= 2 V Envelope,
PP
OUT
V
= 1 V Envelope
PP
OUT
-95
V
= 2 V
HD2
OUT
PP
-100
V
= 2 V
PP
HD3
OUT
-100
-110
-105
-110
50
70
90
110
130
150
170
190
1.75
2
2.25
2.5
2.75
3
3.25
Frequency - MHz
V
- Output Common-Mode Voltage - V
OCM
Figure 18.
Figure 19.
OUTPUT INTERCEPT POINT
vs FREQUENCY
MAXIMUM DIFFERENTIAL OUTPUT VOLTAGE SWING
PEAK-TO-PEAK vs DIFFERENTIAL LOAD RESISTANCE
5.5
90
80
70
OIP
2
5.0
Maximum
4.5
Differential
4.0
V
60
50
OUT_PP
3.5
3.0
2.5
2.0
1.5
1.0
40
30
OIP
3
20
10
0
R
V
= 400 W,
L
= 3 V Envelope
PP
OUT
10
100
1k
50
70
90
110 130
Frequency - MHz
170
190
150
Load Resistance - W
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input and output, input
and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section.
MAXIMUM/MINIMUM SINGLE-ENDED OUTPUT VOLTAGE
vs DIFFERENTIAL LOAD RESISTANCE
DIFFERENTIAL OUTPUT IMPEDANCE
vs FREQUENCY
1000
4.0
3.5
Maximum Single-Ended V
OUT
3.0
2.5
2.0
100
10
Minimum Single-Ended V
OUT
1.5
1.0
10
1
1M
100
Load Resistance - W
1k
10M
100M
Frequency - Hz
1G
10G
Figure 22.
Figure 23.
FREQUENCY RESPONSE
vs CAPACITIVE LOAD
RECOMMENDED OUTPUT RESISTANCE
vs CAPACITIVE LOAD
9
6
3
0
1000
100
10
C
= 10 pF, R = 53.6W
O
L
C
= 20 pF, R = 53.6W
O
L
C
C
= 44 pF, R = 16W
L
O
= 94 pF, R = 8.5W
L
O
-3
-6
C
= 440 pF, R = 2.4W
L
O
1
100M
10M
1G
10G
1
10
100
Capacitive Load - pF
1000
Frequency - Hz
Figure 24.
Figure 25.
COMMON-MODE REJECTION RATIO
vs FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
30
20
10
10
0
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
Frequency - Hz
Frequency - Hz
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input and output, input
and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section.
TURN-ON TIME
TURN-OFF TIME
4
3
4
3
Power-Down
V
OUT
2
2
1
1
0
0
V
Power-Down
OUT
-1
-1
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
16
20
24
28
32
36
40
Time - ms
Time - ms
Figure 28.
Figure 29.
INPUT AND OUTPUT VOLTAGE NOISE
vs FREQUENCY
OUTPUT BALANCE ERROR
vs FREQUENCY
10
9
0
-10
-20
-30
-40
-50
-60
-70
-80
V
= 500mV
PP
8
OUT
Output Voltage Noise
7
6
5
4
3
2
1
0
Input Voltage Noise
1M
10M
100M
1G
10G
10K
100M
1M
Frequency - Hz
10M
100K
Frequency - Hz
Figure 30.
Figure 31.
VOCM SMALL-SIGNAL FREQUENCY RESPONSE
OUTPUT COMMON-MODE PULSE RESPONSE
3
0
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
-3
-6
-9
-12
-15
-18
0
50
100
150
200
250
300
350
400
1M
10M
100M
1G
Time - ns
Frequency - Hz
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS+ = +5V, VOCM = +2.5V, VOUT = 2VPP, RL = 400Ω differential, G = +12dB, differential input and output, input
and output pins referenced to midsupply, unless otherwise noted. Measured using EVM as discussed in Test Circuits section.
VOCM INPUT BIAS CURRENT
vs VOCM INPUT VOLTAGE
s-PARAMETERS
(MAGNITUDE)
50
0
20
0
Gain = 10 dB to 13.7 dB
s22
-50
-20
-40
s11
-100
-150
-200
-250
s12
-60
-80
-300
-350
-100
1M
10M
100M
1G
10G
1.5
2
2.5
3
3.5
Frequency - Hz
V
Voltage - V
OCM
Figure 34.
Figure 35.
NOISE FIGURE
vs FREQUENCY
20
18
16
14
12
10
8
100 W Differential Source
6
4
2
0
10M
100M
1G
Frequency - Hz
Figure 36.
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TEST CIRCUITS
OVERVIEW
The standard THS770012 evaluation module (EVM) is used for testing the typical performance shown in the
Typical Characteristics, with changes as noted below. The EVM schematic is shown in Figure 37. The signal
generators and analyzers used for most tests have single-ended 50Ω input and output impedance. The
THS770012 EVM is configured to convert to and from a single-ended 50Ω impedance by using RF transformers
or baluns 1:1 (CX2156NL from Pulse, supplied as a standard configuration of the EVM) to allow easy connection
to standard lab equipment. For line input termination, two 49.9Ω resistors (R5 and R6) are placed to ground on
the input transformer output pins (terminals 1 and 3). In combination with the 100Ω input impedance of the
device, the total impedance seen by the line is 50Ω.
Gain is set by placing external components R11, R12, R13, and R14 as described below in Setting the Gain
section.
A resistor network is used on the amplifier output to present various loads (RL) and maintain line output
termination to 50Ω. Depending on the test conditions, component values are changed as shown in Table 1, or as
otherwise noted. As a result of the voltage divider on the output formed by the load component values, the
amplifier output is attenuated. The Loss column in Table 1 shows the attenuation expected from the resistor
divider. The output transformer causes slightly more loss, so these numbers are approximate.
Table 1. Load Component Values(1)
LOAD RL
100Ω
R15 AND R17
25Ω
R16
LOSS
6dB
Open
69.8Ω
57.6Ω
52.3Ω
200Ω
86.6Ω
16.8dB
25.5dB
31.8dB
400Ω
187Ω
1kΩ
487Ω
(1) The total load includes 50Ω termination by the test equipment. Components are chosen to achieve load and 50Ω line termination
through a 1:1 transformer.
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+
+
+ +
+
THS770012
-
Figure 37. THS770012IRGE EVM Schematic
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TEST DESCRIPTIONS
The following sections describe how the tests were performed, as well as the EVM circuit modifications that were
made (if any). Modifications made for test purposes include changing capacitors to resistors, resistors to
capacitors, the shorting/opening of components, etc., as noted. Unless otherwise noted, C1, C2, C9, and C13
are all changed to 0.1µF to give basically flat frequency response from below 1MHz to the bandwidth of the
amplifier, and gain is set to nominal +12dB.
Frequency Response: 200mVPP, 2VPP, 3Vpp
The test is run on the standard EVM using the transformers in the signal path.
A network analyzer is connected to the input and output of the EVM with 50Ω coaxial cables and set to measure
the forward transfer function (s21). The input signal frequency is swept with signal level set for desired output
amplitude.
The test ran for gains of +10dB, +11dB, +12dB and +13.7dB with component values changed per Table 2 in
Setting the Gain section.
s-Parameters: s11, s22, and s12
The standard EVM is used with both R15 and R17 = 24.9Ω, and R16 = open, to test the input return loss, output
return loss, and reverse isolation. A network analyzer is connected to the input and output of the EVM with 50Ω
coaxial cables and set to measure the appropriate transfer function: s11, s22, or s12. Note the transformers are
included in the signal chain in order to retrieve proper measurements with single-ended test equipment. The
impact is minimal from 10MHz to 200MHz, but further analysis is required to fully de-embed the respective
effects.
Frequency Response with Capacitive Load
The standard EVM is used with R15 and R17 = RO, R16 = CLOAD, C9 and C13 = 953Ω, R21 = open, T2
removed, and jumpers placed across terminals 3 to 4 and 1 to 6. A network analyzer is connected to the input
and output of the EVM with 50Ω coaxial cables and set to measure the forward transfer function (s21). Different
values of load capacitance are placed on the output (at R16) and the output resistor values (R15 and R17)
changed until an optimally flat frequency response is achieved with maximum bandwidth.
Distortion
The standard EVM is used for measurement of single-tone harmonic distortion and two-tone intermodulation
distortion. For differential distortion measurements, the standard EVM is used with no modification. For
single-ended input distortion measurements, the standard EVM is used with with T1 removed and jumpers
placed across terminals 3 to 4 and 1 to 6, and R5 and R6 = 100Ω. A signal generator is connected to the J1
input of the EVM with 50Ω coaxial cables, with filters inserted inline to reduce distortion from the generator. The
J3 output of the EVM is connected with 50Ω coaxial cables to a spectrum analyzer to measure the
fundamental(s) and distortion products.
Noise Figure
The standard EVM is used with T1 changed to a 1:2 impedance ratio transformer (Mini-Circuits ADT2), R15 and
R17 = 24.9Ω, and R5, R6, and R16 = open. A noise figure analyzer is connected to the input and output of the
EVM with 50Ω coaxial cables. The noise figure analyzer provides a 50Ω (noise) source so that the data are
adjusted to refer to a 100Ω source.
Transient Response, Slew Rate, Overdrive Recovery
The standard EVM is used with T1 and T2 removed and jumpers placed across terminals 3 to 4 and 1 to 6; R15,
R17, and R25 = 49.9Ω; C1, C2, C9, and C13 = 0Ω; and R5, R6, R16, and R21 = open. A differential waveform
generator is connected to the input of the EVM with 50Ω coaxial cables at J1 and J2. The differential output at J3
and J4 is connected with 50Ω coaxial cables to an oscilloscope to measure the outputs. Waveform math in the
oscilloscope is used to combine the differential output of the device.
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Power-Down
The standard EVM is used with T1 and T2 removed, jumpers placed across terminals 3 to 4 and 1 to 6, R15 and
R17 = 49.9Ω, C9 and C13 = 0Ω, and R5, R6, R16, and R21 = open. A waveform generator is connected to the
power-down input of the EVM with a 50Ω coaxial cable at J8. The differential output at J3 and J4 is connected
with 50Ω coaxial cables to an oscilloscope to measure the outputs. J1 is left disconnected so that the output is
driven to the VOCM voltage when the device is active, and discharged through the resistive load on the output
when disabled. Both outputs are the same and only one is shown.
Differential Z-out
The standard EVM is used with R15 and R17 = 24.9Ω, and R16 = open. A network analyzer is connected to the
output of the EVM at J3 with 50Ω coaxial cable, both inputs are terminated with a 50Ω load, and a
high-impedance differential probe is used for the measurement. The analyzer is set to measure the forward
transfer function (s21). The analyzer with probe input is calibrated across the open resistor pads of R16 and the
signal is measured at the output pins of the device. The output impedance is calculated using the known resistor
values and the attenuation caused by R15 and R17.
Output Balance Error
The standard EVM is used with R15 and R17 = 100Ω, and R16 = 0Ω. A network analyzer is connected to the
input of the EVM with 50Ω coaxial cable, the output is left open, and a high-impedance differential probe is used
for the measurement. The analyzer is set to measure the forward transfer function (s21). The analyzer with probe
input is calibrated at the input pins of the device and the signal is measured from the shorted pads of R16 to
ground.
Common-Mode Rejection
The standard EVM is used with T1 removed and jumpers place across terminals 3 to 4, 1 to 6, and 1 to 3. A
network analyzer is connected to the input and output of the EVM with 50Ω coaxial cable and set to measure the
forward transfer function (s21).
VOCM Frequency Response
The standard EVM is used with T2 removed and jumpers across terminals 3 to 4 and 1 to 6; R10, R15, and
R17 = 49.9Ω; C3 and C4 = 0Ω; and R9, R16, and R21 = open. A network analyzer is connected to the VOCM
input of the EVM at J7 and output of the EVM with 50Ω coaxial cable, and set to measure the forward transfer
function (s21). The input signal frequency is swept with the signal level set for 200mV. Each output at J3 and J4
is measured as single-ended, and because both are the same, only one output is shown.
VOCM Slew Rate and Pulse Response
The standard EVM is used with T2 removed and jumpers across terminals 3 to 4 and 1 to 6; R10, R15, and
R17 = 49.9Ω; C9 and C13 = 0Ω; and C3, C4, R9, R16, and R21 = open. A waveform generator is connected to
the VOCM input of the EVM at J7 with 50Ω coaxial cable. The differential output at J3 and J4 is connected with
50Ω coaxial cable to an oscilloscope to measure the outputs. J1 is left disconnected so that the output is driven
to the VOCM voltage. Both outputs are the same, so only one is shown.
Input/Output Voltage Noise, Settling Time, and Power-Supply Rejection
These parameters are taken from simulation.
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THEORY OF OPERATION
GENERAL DESCRIPTION
The THS770012 is a wideband, fully differential amplifier designed and optimized specifically for driving 14-bit
and 16-bit ADCs at input frequencies up to 200MHz. This device provides high bandwidth, low distortion, and low
noise, which are critical parameters in high-speed data acquisition systems that require very high dynamic range,
such as wireless base stations and test and measurement applications. It also makes an excellent differential
amplifier for general-purpose, high-speed differential signal chain and short line-driver applications. The device
has an operating power-supply range of 4.75V to 5.5V. The THS770012 has proprietary circuitry to provide very
fast recovery from overdrive conditions and has a power-down mode for power saving. The THS770012 is
offered in a Pb-free (RoHS compliant) and green, QFN-24 thermally-enhanced package. It is characterized for
operation over the industrial temperature range of –40°C to +85°C.
The amplifier uses two negative-feedback loops. One is for the primary differential amplifier and the other
controls the common-mode operation.
Primary Differential Amplifier
The primary amplifier of the THS770012 is a fully-differential op amp with on-chip gain setting resistors. The gain
of the device can be changed by using external components as described in Setting the Gain section below. The
nominal gain with no external connections is set to +12dB with RF = 200Ω and RG = 50Ω.
VOCM Control Loop
The output common-mode voltage is controlled through a second negative-feedback loop. The output
common-mode voltage is internally sensed and compared to the VOCM pin. The loop then works to drive the
difference, or error voltage, to zero in order to maintain the output common-mode voltage = VOCM (within the loop
gain and bandwidth of the loop). For more details on fully-differential amplifier theory and use, see application
report SLOA054, Fully-Differential Amplifiers, available for download from www.ti.com.
OPERATION
Differential to Differential
The THS770012 is a fully-differential amplifier that can be used to amplify differential input signals to differential
output signals. A basic block diagram of the circuit with nominal gain of +12dB is shown in Figure 38. The
differential input to differential output configuration gives the best performance; the signal source and load should
be balanced.
200W
Differential
Input
Differential
Output
50W
VIN-
VOUT+
VOUT-
VIN+
50W
200W
THS770012
Figure 38. Differential Input to Differential Output Amplifier
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Single-Ended to Differential
The THS770012 can be used to amplify and convert single-ended input signals to differential output signals. A
basic block diagram of the circuit with nominal gain of +12dB is shown in Figure 39. In order to maintain proper
balance in the amplifier and avoid offsets at the output, the alternate input must be biased and the impedance
matched to the signal input. For example, if a 50Ω source biased to 2.5V provides the input, the alternate input
should be tied to 2.5V through 50Ω. If a 50Ω source is ac-coupled to the input, the alternate input should be
ac-coupled to ground through 50Ω. Note that the ac coupling should provide a similar frequency response to
balance the gain over frequency.
VREF
200W
Differential
Output
Bias and
Impedance
Match
50W
VOUT+
Single-Ended
VOUT-
Input
50W
200W
THS770012
Figure 39. Single-Ended Input to Differential Output Amplifier
Setting the Gain
Gain is adjustable by placing external components in positions R11, R12, R13, and R14 on the EVM. Table 2
below shows the component values for setting gain from +10dB to +13.7dB. The different configurations and
values change the effective value of the internal feedback, where the gain is determined by the resultant effective
RF/RG, where RG = 50Ω
Table 2. Gain Settings
GAIN
+10dB
+11dB
+12dB
R11, R12
Open
R13, R14
140 Ω
EFFECTIVE RF
140 || 340 + 60 = 159 Ω
140 || 723 + 60 = 177 Ω
Open
523 Ω
Open
Open
140 + 60 = 200 Ω
(140 || 200 + 60)´(140 + 200)
200
+13.7dB (AC gain), +12dB
(DC gain)(1)
= 242 W
0.1 µF capacitors
Open
(1) Using 0.1 µF capacitors for R11 and R12 limits the low frequency response to the default value of +12dB at frequency below about
10kHz. For +13.7dB gain at DC, connect pins 13 and 18 of the device to a low impedance voltage source equal to VOCM (+2.5V
nominal).
Setting the Output Common-Mode Voltage
The VOCM input controls the output common-mode voltage. VOCM has no internal biasing network and must be
driven by an external source or resistor divider network to the positive power supply. In ac-coupled applications,
the VOCM input impedance and bias current are not critical, but in dc-coupled applications where more accuracy
is desired, the input bias current of the pin should be considered. For best harmonic distortion with VOUT = 3VPP
,
the VOCM input should be maintained within the operating range of 2.25V to 2.75V. The VOCM input voltage can
be operated outside this range if lower output swing is used or distortion degradation is allowed, and increased
bias current into the pin is acceptable. For more information, see Figure 18 and Figure 34. It is recommended to
use a 0.1µF decoupling capacitor from the VOCM pin to ground to prevent noise and other spurious signals from
coupling into the common-mode loop of the amplifier.
Input Common-Mode Voltage Range
The THS770012 is designed primarily for ac-coupled operation. With input dc blocking, the input common-mode
voltage of the device is driven to the same voltage as VOCM by the outputs. Therefore, as long as the VOCM input
is maintained within the operating range of 2.25V to 2.75V, the input common-mode of the main amplifier is also
maintained within its linear operating range of 2.25V to 2.75V. If the device is used with dc coupled input, the
driving source needs to bias the input to its linear operating range of 2.25V to 2.75V for proper operation.
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Operation with Split Supply ±2.5V
The THS770012 can be operated using a split ±2.5V supply. In this case, VS+ is connected to +2.5V, and GND
(and any other pin noted to be connected to GND) is connected to -2.5V. As with any device, the THS770012 is
impervious to what the user decides to name the levels in the system. In essence, it is simply a level shift of the
power pins by –2.5V. If everything else is level-shifted by the same amount, the device sees no difference. With
a ±2.5V power supply, the VOCM range is 0V ±0.25V; therefore, power-down levels are –2.5V = on and +2.5V =
off, and input and output voltage ranges are symmetrical about 0V. This design has certain advantages in
systems where signals are referenced to ground, and as noted in the following section, for driving ADCs with low
input common-mode voltage requirements in dc-coupled applications.
Driving Capcitive Loads
The THS770012 is tested as described previously, with the data shown in the typical graphs. Due to the internal
gain resistor architecture used on the device, the only practical means to avoid stability problems such as
overshoot/ringing, gain peaking, and oscillation when driving capacitive loads is to place small resistors in series
with the outputs (RO) to isolate the phase shift caused by the capacitive load from the feedback loop of the
amplifier. Note there are 2Ω internal resistors in series with each output to help maintain stability. The Typical
Characteristics graphs show recommended values for an optimally flat frequency response with maximum
bandwidth. Smaller values of RO can be used if more peaking is allowed, and larger values can be used to -
reduce the bandwidth.
Driving ADCs
The THS770012 is designed and optimized for the highest performance to drive differential input ADCs.
Figure 40 shows a generic block diagram of the THS770012 driving an ADC. The primary interface circuit
between the amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means
to bias the signal to the input common-mode voltage required by the ADC. Filters range from single-order real
RC poles to higher-order LC filters, depending on the requirements of the application. Output resistors (RO) are
shown on the amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
200W
RO
50W
VOUT+
AIN+
VIN-
Filter
and
VOCM
ADC
CM
Bias
VIN+
AIN-
VOUT-
RO
50W
200W
VOCM
THS770012
Figure 40. Generic ADC Driver Block Diagram
The key points to consider for implementation are described in the following three subsections.
SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier + filter + ADC adds in RMS fashion. Noise from the amplifier is
bandwidth-limited by the filter. Depending on the amplitude of the signal and the bandwidth of the filter, the SNR
of the amplifier + filter can be calculated. To get the combined SNR, this value is then squared, added to the
square of the ADC SNR, and the square-root is taken. If the SNR of the amplifier + filter equals the SNR of the
ADC, the combined SNR is 3dB higher and for minimal inpact on the ADC's SNR the SNR of the amplifier + filter
should be 10dB or more lower. The combined SNR calculated in this manner is usually accurate to within ±1dB
of actual implementation.
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SFDR Considerations
Theoretically, the spurious-free dynamic range (SFDR) of the amplifier + filter + ADC adds linearly on a
spur-by-spur basis. The amplifier output spurs are linearly related solely to the input signal and the SFDR is
usually set by second-order or third-order harmonic distortion for single-tone inputs, and by second-order or
third-order intermodulation distortion for two-tone inputs. Harmonic and second-order intermodulation distortion
can be filtered to some degree by the antialias filter, but not third-order intermodulation distortion. Generally, the
ADC also has the same distortion products, but as a result of the sampling nature and potential for clock
feedthrough, there may be spurs not linearly related solely to the input signal. When the spurs from the amplifier
+ filter are known, each can be directly added to the same spur from the ADC. This is a worst-case analysis
based on the assumption the spurs sources are in phase. If the spur of the amplifier + filter equals the spur of the
ADC, the combined spur is 6dB higher. The combined spur calculated in this manner is usually accurate to within
±6dB of actual implementation, but higher variations have been observed especially in second-order
performance as a result of phase shift in the filter.
Common-mode phase shift introduced by the filter nullifies the basic assumption that the spur sources are in
phase. This phase shift can lead to better performance than predicted as the spurs become phase shifted, and
there is the potential for cancellation as the phase shift reaches 180°.
Differential phase and magnitude imbalance in the filter as a result of mismatched components caused by
nominal tolerance can severely degrade the second-order distortion of the ADC. Single-order RC filters cause
very little differential phase shift with nominal tolerances of 5% or less, but higher-order LC filters are very
sensitive to component mismatch. For instance, a third-order Butterworth bandpass filter with 100MHz center
frequency and 20MHz bandwidth shows up to 20° differential phase imbalance in a Spice Monte Carlo analysis
with 2% component tolerances. Therefore, while a prototype may work, production variance is unacceptable. Low
tolerance 1% components and low order filter is recommended for best performance. Otherwise a transformer or
balun is recommended at the ADC input to restore the phase balance in the input signal to the ADC.
ADC Input Common-Mode Voltage Considerations
The input common-mode voltage range of the ADC must be observed for proper operation. In an ac-coupled
application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is
accomplished in different ways depending on the ADC. Some use internal bias networks and others use external
components, such as resistors, from each input to the CM output of the ADC. When ac coupling, the output
common-mode voltage of the amplifier is a don’t care for the ADC, and VOCM should be set for optimum
performance of the amplifier.
DC-coupled applications vary in complexity and requirements, depending on the ADC. Devices such as the
ADS5424 require a nominal 2.4V input common-mode, while others such as the ADS5485 require a nominal
3.1V input common-mode, and still others like the ADS6149 require 1.5V and the ADS4149 require 0.95V. Given
the THS770012 output common-mode range, ADCs with input common-mode closer to 2.5V are easier to
dc-couple to, and require little or no level shifting. For applications that require a different common-mode voltage
between the amplifier and the ADC, a resistor network can be used, as shown in Figure 41. With ADCs that have
internal resistors (RINT) that bias the ADC input to VCM, the bias resistors do not affect the desired value of RP,
but do cause more attenuation of the differential input signal. Knowing the differential input resistance is required
and sometimes, that is all that is provided.
VREF
RP
RO
VAMP+
VADC+
ADC
CIN
Amp
RIN
VAMP-
VADC-
RO
RP
VREF
Figure 41. Resistor Network to DC Level Shift Common-Mode Voltage
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For common-mode analysis, assume that VAMP± = VOCM and VADC± = VADC (the specification for the ADC input
common-mode voltage). VREF is chosen to be a voltage within the system (such as the ADC or amplifier analog
supply) or ground, depending on whether the voltage must be pulled up or down, and RO is chosen to be a
reasonable value, such as 49.9Ω. With these known values, RP can be found by using Equation 1:
VADC - VREF
RP = RO
VAMP - VADC
(1)
The insertion of this resistor network also attenuates the amplifier output signal. The gain (or loss) can be
calculated by Equation 2:
2RP || ZIN
GAIN =
2RO + 2RP || ZIN
(2)
Using the gain and knowing the full-scale input of the ADC, VADC FS, the required amplitude to drive the ADC with
the network can be calculated using Equation 3:
VADC FS
VAMP PP
=
GAIN
(3)
Using the ADC examples given previously, Table 3 shows sample calculations of the value of RP and VAMP FS for
full-scale drive, and then for –1dB (often times, the ADC drive is backed off from full-scale in applications, so
lower amplitudes may be acceptable). All voltages are in volts, resistors in Ω (the nearest standard value should
be used), and gain as noted. Table 3 does not include the ADS5424 because no level shift is required with this
device.
Table 3. Example RP for Various ADCs
VOCM
VADC
VREF
RINT
(Ω)
RO
(Ω)
RP
(Ω)
GAIN
(V/V)
GAIN
(dB)
VADC FS VAMP PP
VAMP PP
–1dBFS (VPP)
ADC
(VDC
)
(VDC
)
(VDC
)
(VPP
)
FS (VPP
)
ADS5485
ADS6149
ADS4149
ADS4149
2.5
3.1
5
1k
50
50
50
50
158.3
75.0
30.6
81.6
0.73
0.60
0.38
0.62
–2.71
–4.44
–8.40
–4.15
2
2
2
2
4.10
3.65
2.97
4.69
2.88
2.5
1.5
0
NA
NA
NA
3.33
2.5
0(1)
0.95
0.95
0
5.26
2.5
3.23
(1) THS770012 with ±2.5V supply.
The calculated values for the ADS5485 give the lowest attenuation, and because of the high VFS, it requires
3.65VPP from the amplifier to drive to –1dBFS. Performance of the THS770012 is still very good up to 130MHz at
this level, but the designer may want to further back off from full-scale for best performance and consider trading
reduced SNR performance for better SFDR performance.
The values calculated for the ADS6149 show reasonable design targets and should work with good performance.
Note the ADS6149 does not have buffered inputs, and the inputs have equivalent resistive impedance that varies
with sampling frequency. In order to account for the increased loss, half of this resistance should be used for the
value of RINT in Equation 2.
The values calculated for the low input common-mode of the ADS4149 result in large attenuation of the amplifier
signal leading to 5.26VPP being required for full-scale ADC drive. This amplitude is greater than the maximum
capability of the device. With a single +5V supply, the THS770012 is not suitable to drive this ADC in dc-coupled
applications unless the ADC input is backed off towards –6dBFS. Another option is to operate the THS770012
with a split ±2.5V supply, and is shown in the last row of Table 3. For this situation, if the +2.5V is used as the
pull-up voltage, only 2.88VPP is required for the –1dBFS input to the ADS4149. See the Operation with Split
Supply ±2.5V section for more detail. Note that the ADS4149 does not have buffered inputs and the inputs have
equivalent resistive impedance that varies with sampling frequency. In order to account for the increased loss,
half of this resistance should be used for the value of RINT in Equation 2.
As with any design, testing is recommended to validate whether it meets the specific design goals.
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APPLICATION INFORMATION
THS770012 DRIVING 16-BIT ADC
To illustrate the performance of the THS770012 as an ADC driver, the device is tested with a 16-bit ADC.
For testing purposes, a 30MHz, second-order Butterworth bandpass filter with center frequency at 100MHz is
designed. The design target for the source impedance is 40Ω differential, and for load impedance is 400Ω
differential. Therefore, approximately 1dB insertion loss is expected in the pass-band, requiring the amplifier
output amplitude to be 2.5VPP to drive the ADC to –1dBFS.
The output noise voltage specification for the THS770012 is 6 nV/√Hz. With 2.5VPP amplifier output voltage
swing and 30MHz bandwidth, the expected SNR from the amplifier + antialias filter is 88.5dBc. When added in
combination with the 16-bit ADC, the expected total SNR is 75.2dBFS for the typical case.
Figure 42 shows the resulting FFT plot when driving the ADC to –1dBFS with a single-tone 95MHz sine wave,
and sampling at 130MSPS. Test results show 100dBc SFDR from the forth-order harmonic and 74.4 dBFS SNR;
analysis of the plot is shown in Table 4 versus typical ADC specifications. The test results from circuit board to
circuit board shows over 10dB of variation in the second order harmonic due to component tolerance. Using
lower 1% tolerance components or adding a balun between the filter and ADC inputs resulted in less variation
and the typical expected results should be better than 95dBc SFDR and 74dB SNR.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Frequency - MHz
Figure 42. FFT Plot of THS770012 + 30MHz BPF + 16-Bit ADC with 95MHz Single-Tone Input Sampling at
130MSPS
Table 4. Analysis of FFT for THS770012 + BPF + 16-Bit ADC at 95MHz vs Typical ADC Specifications
CONFIGURATION
THS770012 + BPF + 16Bit ADC
16-Bit ADC Only (typ)
ADC INPUT
–1dBFS
SNR
HD2
HD3
74.4dBFS
75.2dBFS
–101dBc
–100dBc
–101dBc
–100dBc
–1dBFS
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EVM AND LAYOUT RECOMMENDATIONS
Figure 37 is the THS770012RGE EVM schematic, and Figure 43 through Figure 46 show the layout details of the
EVM PCB. Table 5 is the bill of materials for the EVM as supplied from TI. It is recommended to follow the layout
of the external components as close as possible to the amplifier, ground plane construction, and power routing.
General layout guidelines are:
1. Place a 2.2µF to 10µF capacitor on each supply pin within 2 inches from the device. It can be shared among
other op amps.
2. Place a 0.01µF to 0.1µF capacitor on each supply pin to ground as close as possible to the device.
Placement within 1mm of the device supply pins ensures best performance.
3. Keep output traces as short as possible to minimize parasitic capacitance and inductance. Doing so reduces
unwanted characteristics such as peaking in the frequency response, overshoot, and ringing in the pulse
response, and results in a more stable design.
4. To reduce parasitic capacitance, ground plane and power-supply planes should be removed from device
output pins.
5. The VOCM pin must be biased to a voltage between 2.25V to 2.75V for proper operation. Place a 0.1µF to
0.22µF capacitor to ground as close as possible to the device to prevent noise coupling into the
common-mode.
6. For best performance, drive circuits and loads should be balanced and biased to keep the input and output
common-mode voltage between 2.25V to 2.75V. AC-coupling is a simple way to achieve this performance.
7. The THS770012 is provided in a thermally enhanced PowerPAD™ package. The package is constructed
using a downset leadframe on which the die is mounted. This arrangement results in low thermal resistance
to the thermal pad on the underside of the package. Excellent thermal performance can be achieved by
following the guidelines in TI application reports SLMA002, PowerPAD™ Thermally-Enhanced Package and
SLMA004, PowerPAD™ Made Easy. For proper operation, the thermal pad on the bottom of the device must
be tied to the same voltage potential as the GND pin on the device.
Figure 44. EVM Layout: Bottom Layer
Figure 43. EVM Layout: Top Layer
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Figure 45. EVM Layout: Layer 2
Figure 46. EVM Layout: Layer 3
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Table 5. THS770012RGE EVM Bill of Materials
SMD
SIZE
REFERENCE
DESIGNATOR
MANUFACTURER
PART NUMBER
DISTRIBUTOR
PART NUMBER
ITEM
DESCRIPTION
QTY
1
2
3
4
CAP, 10.0uF, CERAMIC, X7R, 10V
CAP, 0.1uF, CERAMIC, X7R, 16V
CAP, 0.01uF, CERAMIC, X7R, 16V
CAP, 100pF, CERAMIC, NPO, 50V
1206
0603
0402
0402
C4, C5, C6
C7, C8
3
2
2
1
(TDK) C3216X7R1A106K
(AVX) 0603YC104KAT2A
(AVX) 0402YC103KAT2A
(AVX) 04025A101KAT2A
(DIGI-KEY) 445-4043-1-ND
(DIGI-KEY) 478-1239-1-ND
(DIGI-KEY) 478-1114-1-ND
(DIGI-KEY) 478-4979-1-ND
C10, C11
C12
C1, C2, C3, C9,
C13
5
6
CAP, 1000pF, CERAMIC, X7R, 50V
OPEN
0402
0402
5
4
(AVX) 04025C102KAT2A
(DIGI-KEY) 478-1101-1-ND
R11, R12, R13,
R14
7
RESISTOR, 0 OHM
0402
0402
0402
0402
0402
0603
R4, R21
R5, R6
R16
2
2
1
2
2
2
2
(PANASONIC) ERJ-2GE0R00X
(PANASONIC) ERJ-2RKF49R9X
(PANASONIC) ERJ-2RKF57R6X
(PANASONIC) ERJ-2RKF1870X
(DIGI-KEY) P0.0JCT-ND
(DIGI-KEY) P49.9LCT-ND
(DIGI-KEY) P57.6LCT-ND
(DIGI-KEY) P187LCT-ND
8
RESISTOR, 49.9 OHM, 1/10W, 1%
RESISTOR, 57.6 OHM, 1/10W, 1%
RESISTOR, 187 OHM, 1/10W, 1%
RESISTOR, 1K OHM, 1/10W, 1%
RESISTOR, 10K OHM, 1/10W, 1%
TRANSFORMER, BALUN
9
10
11
12
13
R15, R17
R9, R10
R25, R26
T1, T2
(PANASONIC) ERJ-2RKF1001X (DIGI-KEY) P1.00KLCT-ND
(PANASONIC) ERJ-3EKF1002V (DIGI-KEY) P10.0KHCT-ND
(PULSE) CX2156NL
(SPC) 15459
(DIGI-KEY) 553-1499-ND
(NEWARK) 79K5034
JACK, BANANA RECEPTANCE, 0.25"
DIA. HOLE
14
J5, J6
3
15
16
17
18
19
20
21
22
23
24
CONNECTOR, SMA PCB JACK
CONNECTOR, EDGE, SMA PCB JACK
HEADER, 0.1" CTRS, 0.025" SQ. PINS
SHUNTS
J7, J8
J1, J2, J3, J4
JP1, JP2
JP1, JP2
TP3
2
4
2
2
1
2
1
4
4
(AMPHENOL) 901-144-8RFX
(JOHNSON) 142-0701-801
(SULLINS) PBC36SAAN
(SULLINS) SSC02SYAN
(KEYSTONE) 5000
(NEWARK) 34C8151
(NEWARK) 90F2624
3 POS.
(DIGI-KEY) S1011E-36-ND
(DIGI-KEY) S9002-ND
(DIGI-KEY) 5000K-ND
(DIGI-KEY) 5001K-ND
TEST POINT, RED
TEST POINT, BLACK
TP1, TP2
U1
(KEYSTONE) 5001
IC, THS770012
(TI) THS770012RGE
STANDOFF, 4-40 HEX, 0.625" LENGTH
SCREW, PHILLIPS, 4-40, .250"
BOARD, PRINTED CIRCUIT
(KEYSTONE) 1808
(DIGI-KEY) 1808K-ND
(DIGI-KEY) H703-ND
PMSSS 440 0025 PH
(TI) EDGE# 6515711 REV.A
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 0V to +5.5V and the output voltage range of 0V to +5.5V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate
properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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REVISION HISTORY
Changes from Revision A (November 2010) to Revision B
Page
•
•
•
Changed to Revision B, May 2011 ....................................................................................................................................... 1
Deleted "using a......have changes" from THS770012 Driving ADS5493 section last part of the first sentence ............... 23
Deleted paragraphs, Figure 39 and section title under the first bulleted lists of THS770012 Driving ADS5493
section. Also deleted the next section title and "and bulit on the EVM" in the sentence under the title. ........................... 23
Changes from Revision B (May 2011) to Revision C
Page
•
Deleted all ADS5493 information .......................................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Nov-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
THS770012IRGER
THS770012IRGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS770012IRGER
THS770012IRGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS770012IRGER
THS770012IRGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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