THVD1439_V03 [TI]
THVD14x9x 3-V to 5.5-V RS-485 Transceivers With 4-kV Surge Protection and 1.8-V VIO Capability;
| 型号： | THVD1439_V03 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | THVD14x9x 3-V to 5.5-V RS-485 Transceivers With 4-kV Surge Protection and 1.8-V VIO Capability |
| 文件： | 总30页 (文件大小：1804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THVD1439, THVD1439V
THVD1449, THVD1449V
SLLSF79B – APRIL 2021 – REVISED SEPTEMBER 2021
THVD14x9x 3-V to 5.5-V RS-485 Transceivers With 4-kV Surge Protection and 1.8-V
VIO Capability
1 Features
2 Applications
•
Meets or exceeds the requirements of the TIA/
EIA-485A standard
3-V to 5.5-V Supply Voltage
VIO Support from 1.65-V to VCC supply level
(THVD1439V, THVD1449V)
Bus I/O protection
•
•
•
•
•
•
Wireless infrastructure
Factory automation
Motor drives
Building automation
HVAC
•
•
•
Grid infrastructure
– ± 4-kV IEC 61000-4-5 1.2/50-μs surge
– ± 15-kV IEC 61000-4-2 Contact discharge
– ± 15-kV IEC 61000-4-2 Air-gap discharge
– ± 4-kV IEC 61000-4-4 Electrical fast transient
– ± 15-kV HBM ESD
3 Description
THVD14x9(V) devices are half-duplex RS-485
transceivers with integrated surge protection. Surge
protection is achieved by integrating transient voltage
suppressor (TVS) diodes in the standard 8-pin SOIC
(D) package. This feature increases the reliability by
providing better immunity to noise transients coupled
to the data cable which eliminates the need for
external protection components.
– ± 15-V DC bus fault
Available in two speed grades
•
– THVD1439, THVD1439V: 250 kbps
– THVD1449, THVD1449V: 12 Mbps
Extended ambient
temperature range: -40°C to 125°C
Extended operational
common-mode range: ± 12 V
Large receiver hysteresis for noise rejection
Low Power Consumption
– Standby supply current: < 3 µA
– Current during operation: < 5 mA
Glitch-free power-up/down for hot plug-in capability
Open, short, and idle bus failsafe
1/8 Unit load (up to 256 bus nodes)
Industry standard 8-pin SOIC
•
•
THVD1439 and THVD1449 operate from a single
3.3-V or 5-V supply. The THVD1439V and
THVD1449V devices support an additional VIO supply
to operate the IOs from as low as 1.65 V supply level.
The devices in this family feature a wide common-
mode voltage range making them suitable for multi-
point applications over long cable runs.
•
•
•
•
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
THVD1439
THVD1439V
THVD1449
THVD1449V
for drop-in compatibility
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available devices, see the orderable addendum at the
end of the data sheet.
VIO
VCC
VCC
A
B
A
R
R
B
DE / RE
RE
DE
D
D
GND
GND
THVD14x9V Block Diagram
THVD14x9 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1439, THVD1439V
THVD1449, THVD1449V
SLLSF79B – APRIL 2021 – REVISED SEPTEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 ESD Ratings, IEC ...................................................... 5
6.4 Recommended Operating Conditions ........................6
6.5 Thermal Information ...................................................6
6.6 Power Dissipation ...................................................... 6
6.7 Electrical Characteristics ............................................7
6.8 Switching Characteristics (THVD1439,
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagrams....................................... 14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information .........................................19
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................22
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Receiving Notification of Documentation Updates..25
12.3 Support Resources................................................. 25
12.4 Trademarks.............................................................25
12.5 Electrostatic Discharge Caution..............................25
12.6 Glossary..................................................................25
THVD1439V) ................................................................9
6.9 Switching Characteristics (THVD1449,
THVD1449V) ................................................................9
6.10 Typical Characteristics............................................10
7 Parameter Measurement Information..........................12
4 Revision History
Changes from Revision A (June 2021) to Revision B (September 2021)
Page
•
Changed document status from Advanced Information to Production data ...................................................... 1
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Device Comparison Table
PART NUMBER
THVD1439
DUPLEX
ENABLES
VIO
No
SIGNALING RATE
NODES
Separate DE and RE
Combined DE / RE
Separate DE and RE
Combined DE / RE
up to 250 kbps
THVD1439V
THVD1449
Yes
No
Half
256
up to 12 Mbps
THVD1449V
Yes
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5 Pin Configuration and Functions
R
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VCC
B
V
R
V
B
A
IO
CC
RE
DE
DE/RE
D
A
D
GND
GND
Not to scale
Not to scale
Figure 5-1. THVD1439, THVD1449, 8-Pin (SOIC),
Top View
Figure 5-2. THVD1439V, THVD1449V, 8-Pin (SOIC),
Top View
PIN
THVD1439
I/O
DESCRIPTION
THVD1439,
THVD1449
NAME
V,
THVD1449V
VIO
R
-
1
2
-
P
O
I
1.8-V to 5-V supply for R, D, and RE/DE
Receiver data output
1
2
3
RE
DE
Receiver enable, active low (2 MΩ internal pull-up)
Driver enable, active high
-
I
Driver enable (Active high), Receiver enable (Active Low). (2 MΩ
internal pull-down)
DE/ RE
-
3
I
D
4
5
4
5
I
Driver data input
Device ground
GND
-
A
B
6
7
6
7
I/O
I/O
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
3.3-V to 5-V supply
for the device
VCC
8
8
P
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
-0.5
–15
MAX
7
UNIT
Supply voltage
Logic supply voltage
Bus voltage
VCC
V
V
V
VIO
VCC+0.2
15
Range at any bus pin (A or B)
Range at any logic pin (R, D, DE, or RE) THVD1439,
THVD1449
Input voltage
Input voltage
–0.3
–0.3
5.7
V
V
Range at any logic pin (R, D, DE, or RE)
THVD1439V, THVD1449V
VIO+0.2
Receiver output current
Storage temperature
IO
–24
–65
24
mA
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Bus terminals and GND
±15,000
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
All pins except bus terminals
and GND
V(ESD)
Electrostatic discharge
±4,000
±1,500
V
Charged-device model (CDM), per JEDEC specification JESD22-C102(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings, IEC
VALUE
UNIT
Contact Discharge, per IEC 61000-4-2
Air-Gap Discharge, per IEC 61000-4-2
Per IEC 61000-4-4
±15,000
±15,000
±4,000
±4,000
V(ESD)
Electrostatic discharge
Bus terminals
V
V(EFT)
Electrical fast transient
Surge
Bus terminals
Bus terminals
V
V
V(surge)
Per IEC 61000-4-5, 1.2/50 μs
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
5.5
UNIT
VCC
VIO
VI
Supply voltage
V
V
V
V
V
IO Supply Voltage (V Variant)
1.65
0
VCC
5.5
THVD1439, THVD1449
Input voltage on logic pins (R, D,
DE, or RE)
VI
THVD1439V, THVD1449V
0
VIO
12
VI
Input voltage at bus pins (A or B) (1)
-12
High-level input voltage (R, D, DE,
or RE)
VIH
VIL
VIH
VIL
0.67 * VIO
VIO
0.33 * VIO
5.5
V
V
V
V
THVD1439V, THVD1449V
THVD1439, THVD1449
Low-level input voltage (R, D, DE, or
RE)
0
2
0
High-level input voltage (R, D, DE,
or RE)
Low-level input voltage (R, D, DE, or
RE)
0.8
VID
IO
Differential input voltage
Output current, driver
-12
-60
-8
12
60
8
V
mA
mA
Ω
IOR
RL
Output current, receiver
Differential load resistance
54
THVD1439, THVD1439V
THVD1449, THVD14149V
250
12
kbps
Mbps
°C
1/tUI
TA
Signaling rate
Operating ambient temperature
-40
125
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.5 Thermal Information
THVD1439 THVD1439V
THVD1449 THVD1449V
THERMAL METRIC(1)
UNIT
D (SOIC)
8 PINS
120.7
50.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.5
ψJB
62.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Power Dissipation
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
160
UNIT
THVD1439
THVD1449
THVD1439
THVD1449
THVD1439
THVD1449
250 kbps
12 Mbps
250 kbps
12 Mbps
250 kbps
12 Mbps
Unterminated
mW
RL = 300 Ω, C L = 50 pF (driver)
290
Driver and receiver enabled,
VCC = 5.5 V, TA = 125 °C,
50% duty cycle square wave at signaling RL = 100 Ω, CL = 50 pF (driver)
190
RS-422 load
PD
mW
mW
290
rate
250
RS-485 load
RL = 54 Ω, CL = 50 pF (driver)
320
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V (See Figure 7-1 )
1.5
2.1
2
V
V
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, 4.5 V ≤ VCC ≤ 5.5 V (See Figure
7-1 )
Driver differential output
voltage magnitude
|VOD
|
RL = 100 Ω (See Figure 7-2 )
RL = 54 Ω (See Figure 7-2 )
2
2.5
2
V
V
1.5
Change in differential output
voltage
Δ|VOD
|
RL = 54 Ω (See Figure 7-2 )
–50
1
50
3
mV
V
VOC
Common-mode output voltage RL = 54 Ω (See Figure 7-2 )
VCC / 2
Change in steady-state
ΔVOC(SS)
RL = 54 Ω (See Figure 7-2 )
common-mode output voltage
–50
–250
50
mV
mA
IOS
Short-circuit output current
DE = VCC, -12 V ≤ VO ≤ 12 V
250
Receiver
VI = 12 V
DE = 0 V, VCC
VI = -7 V
75
–40
–75
135
II
Bus input current
–100
–135
μA
= 0 V or 5.5 V
VI = -12 V
Positive-going input threshold
voltage(1)
VTH+
VTH-
40
125
200
–40
mV
mV
Negative-going input threshold
voltage(1)
–200
–125
250
Over common-mode range of ±12 V
VHYS
Input hysteresis
mV
mV
VTH_FSH
Input fail-safe threshold
–40
40
IOH = -4 mA; VIO= 1.65 V - 3 V
THVD1439V,
THVD1449V
VIO – 0.4 VIO – 0.2
VCC – 0.4 VCC – 0.2
IOH = -8 mA; VIO= 3 V - 5.5 V
IOH = -8 mA
VOH
Output high voltage
Output low voltage
V
THVD1439,
THVD1449
IOL = 8 mA; VIO = 3 V - 5.5 V
IOL = 4 mA; VIO = 1.65 V - 3 V
THVD1439V,
THVD1449V
VOL
0.2
0.4
1
V
THVD1439,
THVD1449
IOL = 8 mA
IOZ
Output high-impedance current VO = 0 V or VCC, RE = VCC
–1
µA
Logic
THVD1439V,
THVD1449V
3 V ≤ VCC ≤ 5.5 V, 1.65 ≤ VIO ≤ VCC V, 0 V ≤ VIN ≤
VIO
–5
–5
5
5
µA
µA
IIN
Input current (D, DE, RE)
THVD1439,
THVD1449
3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC
Thermal Protection
TSHDN Thermal shutdown threshold
THYS Thermal shutdown hysteresis
Temperature rising
150
170
10
℃
℃
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply
Driver and receiver
enabled (THVD1439,
THVD1449)
RE = 0 V, DE = VCC, No
load
3
4
mA
Driver enabled, receiver RE = VCC, DE = VCC
disabled No load
,
2
3
mA
mA
Supply current (quiescent)
VCC=3.6 V
Driver disabled, receiver RE = 0 V, DE = 0 V, No
1.7
2.2
enabled
load
Driver and receiver
disabled (THVD1439,
THVD1449)
RE = VCC, DE = 0 V, D
= open, No load
0.1
3.5
1.5
5
µA
ICC
Driver and receiver
enabled (THVD1439,
THVD1449)
RE = 0 V, DE = VCC, No
load
mA
Driver enabled, receiver RE = VCC, DE = VCC
disabled No load
,
2.5
1.8
3.8
2.4
mA
mA
Supply current (quiescent)
VCC=5.5 V
Driver disabled, receiver RE = 0 V, DE = 0 V, No
enabled
load
Driver and receiver
disabled (THVD1439,
THVD1449)
RE = VCC, DE = 0 V, D
= open, No load
0.2
3
µA
DE/RE=VIO, D=open,
No load
Driver Enabled
5
5
µA
µA
THVD1439V,
THVD1449V
IIO
VIO supply current (quiescent)
DE/RE= 0 V, D=open,
No load
Receiver enabled
(1) Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–
.
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6.8 Switching Characteristics (THVD1439, THVD1439V)
250-kbps devices (THVD1439, 39V), over recommended operating conditions. All typical values are at 25 ℃.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Differential output rise/fall time
Propagation delay
300
570
450
1200
650
50
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See Figure 7-3
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
25
240
2
125
600
4
See Figure
7-4 and Figure 7-5
RE = 0 V
RE = VCC
tPZH, tPZL
Enable time
Pulse width (logic low) on DE pin
to initiate device shutdown
tSHDN
RE = VCC
300
ns
Receiver
tr, tf
Differential output rise/fall time
Propagation delay
9
25
110
7
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
CL = 15 pF
See Figure 7-6
70
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
22
60
tPZH(1)
,
DE = VCC
DE = 0 V
See Figure 7-7
See Figure 7-8
120
185
tPZL(1)
tPZH(2)
tPZL(2)
,
,
Enable time
4
10
μs
tD(OFS)
tD(FSO)
Delay to enter fail-safe operation
Delay to exit fail-safe operation
14
25
20
40
36
66
μs
ns
CL = 15 pF
DE = 0 V
See Figure 7-9
RE pulse width to initiate device
shutdown
tSHDN
300
ns
6.9 Switching Characteristics (THVD1449, THVD1449V)
12-Mbps devices (THVD1449, 49V), over recommended operating conditions. All typical values are at 25 ℃.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Differential output rise/fall time
Propagation delay
2
7
12
10
25
25
3.5
75
65
4
ns
ns
ns
ns
ns
μs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See Figure 7-3
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
25
18
2
See Figure 7-4 and
Figure 7-5
RE = 0 V
RE = VCC
tPZH, tPZL
Enable time
Pulse width (logic low) on DE pin
to initiate device shutdown
tSHDN
RE = VCC
300
ns
Receiver
tr, tf
Differential output rise/fall time
Propagation delay
3
10
110
4
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
CL = 15 pF
See Figure 7-6
30
60
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
10
90
30
tPZH(1)
,
DE = VCC
DE = 0 V
See Figure 7-7
See Figure 7-8
130
tPZL(1)
tPZH(2)
tPZL(2)
,
,
Enable time
4
10
μs
tD(OFS)
tD(FSO)
Delay to enter fail-safe operation
Delay to exit fail-safe operation
14
25
20
35
36
55
μs
ns
CL = 15 pF
DE = 0 V
See Figure 7-9
Pulse width (logic high) on RE pin
to initiate device shutdown
tSHDN
300
ns
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6.10 Typical Characteristics
6.5
4.8
4.2
3.6
3
VCC = 3.3 V
VCC = 5 V
VOH
(
VCC = 3.3 V)
6
5.5
5
VOL
VOH
VOL
(
VCC = 3.3 V)
(
VCC = 5 V)
(
VCC = 5 V)
4.5
4
3.5
3
2.4
1.8
1.2
0.6
0
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Driver Output Current (mA)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Driver Output Current (mA)
DE = VCC
D = 0 V
TA= 25 °C
DE = VCC
D = 0 V
TA= 25 °C
Figure 6-2. Driver Differential Output voltage vs
Driver Output Current
Figure 6-1. Driver Output Voltage vs Driver Output
Current
650
65
60
55
50
45
40
35
30
Rise time (VCC = 3.3 V)
625
600
575
550
525
500
475
450
425
Fall time (VCC = 3.3 V)
Rise time (VCC = 5 V)
Fall time (VCC = 5 V)
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100 120 140
VCC (V)
Temperature ( C)
TA= 25 °C
RL = 54 Ω
DE = D = VCC
spacer
Figure 6-3. Driver Output Current vs Supply
Voltage
Figure 6-4. THVD1439, THVD1439V Driver Rise or
Fall Time vs Temperature
500
80
tPHL (VCC = 3.3 V)
tPLH (VCC = 3.3 V)
tPHL (VCC = 5 V)
tPLH (VCC = 5 V)
VCC = 3.3 V
VCC = 5 V
75
70
65
60
55
50
45
40
35
490
480
470
460
450
440
430
0
25
50
75 100 125 150 175 200 225 250
Signaling Rate (kbps)
-40
-20
0
20
40
60
80
100 120 140
Temperature (C)
TA= 25 °C
RL = 54 Ω
spacer
Figure 6-6. THVD1439, THVD1439V Supply Current
vs Signal Rate
Figure 6-5. THVD1439, THVD1439V Driver
Propagation Delay vs Temperature
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22
21
20
19
18
17
16
15
14
13
12
11
18.5
17.5
16.5
15.5
14.5
13.5
12.5
Rise time (VCC = 3.3 V)
Fall time (VCC = 3.3 V)
Rise time (VCC = 5 V)
Fall time (VCC = 5 V)
tPHL (VCC = 3.3 V)
tPLH (VCC = 3.3 V)
tPHL (VCC = 5 V)
tPLH (VCC = 5 V)
10
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Temperature ( C)
Temperature (C)
Figure 6-8. THVD1449, THVD1449V Driver Rise or
Fall Time vs Temperature
Figure 6-7. THVD1449, THVD1449V Driver
Propagation Delay vs Temperature
90
85
80
75
70
65
60
55
50
45
40
35
VCC = 3 V
VCC = 5 V
0
2000
4000
6000
8000
10000
12000
Signaling Rate (kbps)
TA= 25 °C
RL = 54 Ω
Figure 6-9. THVD1449, THVD1449V Supply Current vs Signal Rate
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7 Parameter Measurement Information
Vcc
375 Ω
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
Figure 7-1. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
V
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
OC
Figure 7-2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
V
cc
0 V
Vcc
DE
50%
V
I
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
Input
50 Ω
V
50%
10%
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
Figure 7-3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
B
R
=
DE
50 Ω
L
t
PZH
=
C
L
50 pF
110 Ω
V
Input
Generator
OH
90%
V
I
50%
V
O
~
~ 0V
t
PHZ
Figure 7-4. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
50%
10%
VOL
VI
Generator
50 Ω
Figure 7-5. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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3 V
50%
V
I
A
B
0 V
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
VOH
Generator
I
90%
CL=15 pF
50%
RE
V
OD
10%
V
OL
tr
t
f
Figure 7-6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
Figure 7-7. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
Figure 7-8. Measurement of Receiver Enable Times With Driver Disabled
0 V
VA - VB
A
VA = 0 V or -750 mV
VB = 0 V or +750 mV
-1.5 V
R
VO
tD(FSO)
tD(OFS)
B
CL= 15 pF
RE
VCC
0 V
0 V
VO
VCC / 2
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Figure 7-9. Fail-Safe Delay Measurements
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8 Detailed Description
8.1 Overview
THVD14x9(V) devices are surge-protected, half duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 250 kbps and 12 Mbps respectively. Surge protection is achieved by
integrating transient voltage suppressor (TVS) diodes in the standard 8-pin SOIC (D) package.
THVD1439 and THVD1449 devices have active-high driver enables and active-low receiver enables. A standby
current of less than 1.5 µA (VCC = 3.6 V) can be achieved by disabling both driver and receiver. THVD1439V and
THVD1449V have a single enable/disable pin that either enables the driver or the receiver at a time.
8.2 Functional Block Diagrams
VCC
A
R
B
RE
DE
D
GND
Figure 8-1. THVD1439 and THVD1449 Block Diagram
VIO
VCC
A
B
R
DE / RE
D
GND
Figure 8-2. THVD1439V and THVD1449V Block Diagram
8.3 Feature Description
8.3.1 Electrostatic Discharge (ESD) Protection
The bus pins of the THVD14x9(V) transceiver family include on-chip ESD protection against ±15-kV HBM and
±15-kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far
more severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge
resistance, R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As
stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method.
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R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
Figure 8-3. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment.
Common discharge events occur because of human contact with connectors and cables.
8.3.2 Electrical Fast Transient (EFT) Protection
Inductive loads such as relays, switch contactors, or heavy-duty motors can create high-frequency bursts during
transition. The IEC 61000-4-4 test is intended to simulate the transients created by such switching of inductive
loads on AC power lines. Figure 8-4 shows the voltage waveforms in to 50-Ω termination as defined by the IEC
standard.
1
Time
15 ms at 5 kHz
0.75 ms at 100 kHz
300 ms
1
Time
200 µs at 5 kHz
10 µs at 100 kHz
1
0.5
Time
5 ns
50ns
Figure 8-4. EFT Voltage Waveforms
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Internal ESD protection circuits of the THVD14x9(V) protect the transceivers against ±4-kV EFT. With careful
system design, one could achieve EFT Criterion A (no data loss when transient noise is present).
8.3.3 Surge Protection
Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages
and currents), or the switching of power systems, including load changes and short circuit switching. These
transients are often encountered in industrial environments, such as factory automation and power-grid systems.
Figure 8-5 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The diagram on the left shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The diagram on the right shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
Figure 8-5. Power Comparison of ESD, EFT, and Surge Transients
Figure 8-6 shows the test setup used to validate THVD14x9 surge performance according to the IEC 61000-4-5
1.2/50-μs surge pulse.
80 O
A
Surge Generator
2 O Source Impedance
80 O
THVD14x9
GND
B
Coupling Network
Figure 8-6. THVD14x9(V) Surge Test Setup
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THVD14x9(V) product family is robust to ±4-kV surge transients without the need for any external components.
The transient current and voltage waveforms resulting from a +4-kV surge test as described in Figure 8-6 are
shown in Figure 8-7. The bus pin voltage is clamped by the integrated surge protection diodes such that the
internal circuitry is not damaged during the surge event. The clamping voltage at the bus pins for versus the total
current from the surge generator is shown in Figure 8-8.
120
Voltage (V)
Current (A)
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
0
20
40
60
80
100
120
Time (ns)
Figure 8-7. Transient current and voltage waveforms from +4-kV Surge Test. The current waveform is
the total current output from the generator and the voltage waveform is the voltage at A or B pin of the
transceiver.
100
90
80
70
60
50
40
30
20
10
0
15 20 25 30 35 40 45 50 55 60 65 70 75
VCLAMP at Bus Pins at Peak Current (V)
Figure 8-8. Clamping voltage at bus pins vs total surge current from the surge generator
8.3.4 Enhanced Receiver Noise Immunity
The differential receivers of THVD14x9(V) family feature fully symmetric thresholds to maintain duty cycle of
the signal even with small input amplitudes. In addition, 250 mV (typical) hysteresis guarantees excellent noise
immunity.
8.3.5 Failsafe Receiver
The differential receivers of the THVD14x9(V) family are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the receiver will output a fail-safe logic high state if the input amplitude stays for longer
than tD(OFS) at less than |VTH_FSH|.
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8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE
pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 8-1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between
VTH+ and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 8-2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
ENABLE
OUTPUT
FUNCTION
RE
R
VTH+ < VID
L
H
Receive valid bus high
Indeterminate bus state
VTH- < VID < VTH+
L
Indeterminate
VID < VTH-
X
L
L
Z
Z
H
H
H
Receive valid bus low
Receiver disabled
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
THVD14x9(V) are half-duplex RS-485 transceivers with integrated system-level surge protection. Standard
8-pin SOIC (D) package allows drop-in replacement into existing systems and eliminate system-level protection
components.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, with a value that matches the
characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Figure 9-1. Typical RS-485 Network With Half-Duplex Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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10000
1000
100
5%, 10%, and 20% Jitter
Conservative
Characteristics
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
Figure 9-2. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 12 Mbps for the THVD1449(V)) in cases where the interconnect is
short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
(1)
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD14x9(V) devices consist of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
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9.2.2 Detailed Design Procedure
RS-485 transceivers operate in noisy industrial environments typically require surge protection at the bus
pins. Figure 9-3 compares 4-kV surge protection implementation with a regular RS-485 transceiver (such as
THVD14x0) against with the THVD14x9(V). The internal TVS protection of the THVD14x9(V) achieves ±4-kV
IEC 61000-4-5 surge protection without any additional external components, reducing system level bill of
materials.
System level surge protection implementation
using a typical RS-485 transceiver
3.3V œ 5 V
100nF
VCC
10k 10k
MOV
TBU
R
RxD
/RE
TVS
A
DIR
MCU/
B
DE
UART
DIR
TBU
D
TxD
RS-485 transceiver
10k
MOV
GND
System level surge protection implementation
using THVD14x9 transceiver
3.3V œ 5 V
100nF
VCC
10k 10k
R
RxD
DIR
/RE
A
B
MCU/
UART
DE
D
DIR
TxD
THVD24x9
10k
GND
Figure 9-3. Implementation of System-Level Surge Protection Using THVD14x9(V)
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9.2.3 Application Curves
Ch 2: D Input, Ch4: VOD VCC = 5 V
Ch1: R Output
Data rate: 12 Mbps
Ch 2: D Input, Ch4: VAB VCC = 3.3 V
Ch1: R Output
Data rate: 12 Mbps
Figure 9-4. THVD1449 Waveforms with 54-Ω
Termination and VCC = 5 V
Figure 9-5. THVD1449 Waveforms with 54-Ω
Termination and VCC = 3.3 V
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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11 Layout
11.1 Layout Guidelines
Additional external protection components generally are not needed when using THVD14x9(V) transceivers.
1. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance. Apply 100-nF to 220-nF decoupling capacitors
as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board.
2. Use at least two vias for VCC and ground connections of decoupling capacitors to minimize effective via
inductance.
3. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in these lines during
transient events.
11.2 Layout Example
2
Via to GND
1
Via to VCC
C
R
VCC
B
R
3
R
RE
DE
R
MCU
A
3
R
GND
D
2
Figure 11-1. THVD1439, THVD1449 Layout Example
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2
1
Via to GND
Via to VCC
Via to VIO
2
1
C
C
VCC
B
VIO
3
R
R
R
MCU
DE / RE
A
3
R
GND
D
2
Figure 11-2. THVD1439V THVD1449V Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: THVD1439 THVD1439V THVD1449 THVD1449V
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTHVD1449VDR
THVD1439DR
THVD1439VDR
THVD1449DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
NIPDAUAG
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
T1439
1439V
T1449
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1439DR
THVD1439VDR
THVD1449DR
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
6.4
5.2
5.2
5.2
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD1439DR
THVD1439VDR
THVD1449DR
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
346.0
346.0
346.0
346.0
346.0
346.0
29.0
29.0
29.0
Pack Materials-Page 2
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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