THVD1510 [TI]
具有 ±18kV IEC ESD 保护功能的 5V RS-485 收发器;
| 型号： | THVD1510 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ±18kV IEC ESD 保护功能的 5V RS-485 收发器 |
| 文件： | 总42页 (文件大小：1221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
具有 ±18kV IEC ESD 保护功能的 THVD15xx 5V RS-485 收发器
1 特性
每个器件由 5V 单电源供电。该系列中的器件具有扩展
共模电压范围，因此这些器件适用于长电缆上的 多点
应用。
1
•
符合或超过 TIA/EIA-485A 标准要求
4.5V 至 5.5V 电源电压
•
•
集成总线 I/O 保护
THVD15xx 系列器件采用小型 VSSOP 封装，适用于
空间受限的 应用。这些器件在自然通风环境下的额定
温度范围为 –40°C 至 125°C。
–
–
–
–
±30kV HBM ESD
±18kV IEC 61000-4-2 ESD 接触放电
±25kV IEC 61000-4-2 ESD 空气间隙放电
±4kV IEC 61000-4-4 电气快速瞬变
器件信息(1)
器件型号
THVD1510
封装
VSSOP (8)
封装尺寸（标称值）
3.00mm × 3.00mm
4.90mm × 3.91mm
3.00mm × 3.00mm
3.00mm × 3.00mm
3.00mm × 3.00mm
8.65mm × 3.91mm
•
•
•
•
•
扩展级运行共模：± 15V
低 EMI 500kbps 和 50Mbps 数据速率
扩展温度范围：-40°C 至 125°C
用于噪声抑制的大接收器滞后
低功耗
THVD1550
SOIC (8)
THVD1551
THVD1512
VSSOP (8)
VSSOP (10)
VSSOP (10)
SOIC (14)
THVD1552
–
–
低待机电源电流：小于 1µA
运行期间的电流：< 1mA
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
•
•
适用于热插拔功能的无干扰加电/断电
开路、短路和空闲总线失效防护
THVD1510 和 THVD1550 简化原理图
1/8 单位负载选项（多达 256 个总线节点）
1
R
小尺寸 VSSOP 封装（可节省布板空间）或 SOIC
封装（可实现快插兼容性）
2
7
6
RE
B
A
3
4
DE
D
2 应用
•
•
•
•
•
•
•
•
电机驱动器
THVD1551 简化原理图
工厂自动化与控制
电网基础设施
楼宇自动化
HVAC 系统
视频监控
8
A
B
2
R
7
6
5
Z
Y
3
D
过程分析
THVD1512 和 THVD1552 简化原理图
电信基础设施
(9)12
A
B
2(1)
3(2)
R
(8)11
RE
3 说明
4(3)
5(4)
DE
D
(7)10
(6)9
Z
Y
THVD15xx 是一系列抗噪 RS-485/RS-422 收发器，专
用于在恶劣的工业环境中运行。这些器件的总线引脚可
耐受高级别的 IEC 电气快速瞬变 (EFT) 和 IEC 静电放
电 (ESD) 事件，从而无需使用其他系统级保护组件。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEV1
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
目录
9.2 Functional Block Diagrams ..................................... 14
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 15
10 Application and Implementation........................ 18
10.1 Application Information...................................... 18
10.2 Typical Application ............................................... 18
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 25
13 器件和文档支持 ..................................................... 26
13.1 器件支持................................................................ 26
13.2 第三方产品免责声明.............................................. 26
13.3 相关链接................................................................ 26
13.4 接收文档更新通知 ................................................. 26
13.5 社区资源................................................................ 26
13.6 商标....................................................................... 26
13.7 静电放电警告......................................................... 26
13.8 术语表 ................................................................... 26
14 机械、封装和可订购信息....................................... 27
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Power Dissipation ..................................................... 7
7.6 Electrical Characteristics........................................... 8
7.7 Switching Characteristics.......................................... 9
7.8 Switching Characteristics.......................................... 9
7.9 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
8
9
4 修订历史记录
Changes from Revision B (July 2018) to Revision C
Page
•
Changed the Description of pins 13 and 14 in the Pin Functions table for THVD1512, THVD1552 D package................... 5
Changes from Revision A (January 2018) to Revision B
Page
•
Added TSD to the Electrical Characteristics table ................................................................................................................... 8
Changes from Original (September 2017) to Revision A
Page
•
•
Changed the Machine model (MM) value From: ±400 To: ±200 in the ESD Ratings............................................................ 6
Changed the VOH MIN value From: 2.4 V To: 4 V in the Electrical Characteristics table ..................................................... 8
2
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
5 Device Comparison Table
PART NUMBER
THVD1512
THVD1510
THVD1552
THVD1551
THVD1550
DUPLEX
ENABLES
DE, RE
DE, RE
DE, RE
None
SIGNALING RATE
NODES
Full
Half
Full
Full
Half
up to 500 kbps
256
up to 50 Mbps
196
DE, RE
6 Pin Configuration and Functions
THVD1510, THVD1550 Devices
8-Pin D Package (SOIC)
Top View
THVD1510, THVD1550 Devices
8-Pin DGK Package (VSSOP)
Top View
R
/RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
R
/RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
A
GND
GND
Not to scale
Not to scale
Pin Functions
PIN
D
6
I/O
DESCRIPTION
NAME
A
DGK
6
7
4
3
5
1
8
2
Bus input/output
Bus input/output
Digital input
Digital input
Ground
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
Driver data input
B
7
D
4
DE
GND
R
3
Driver enable, active high (2 MΩ internal pull-down)
Device ground
5
1
Digital output
Power
Receive data output
VCC
RE
8
5-V supply
2
Digital input
Receiver enable, active low (2 MΩ internal pull-up)
Copyright © 2017–2018, Texas Instruments Incorporated
3
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
THVD1551 Device
8-Pin DGK Package (VSSOP)
Top View
VCC
R
1
2
3
4
8
7
6
5
A
B
Z
Y
D
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DGK
A
8
7
3
4
2
1
5
6
Bus input
Bus input
Digital input
Ground
Bus input, A (complementary to B)
Bus input, B (complementary to A)
Driver data input
B
D
GND
R
Device ground
Digital output
Power
Receive data output
VCC
Y
5-V supply
Bus output
Bus output
Bus output, Y (complementary to Z)
Bus output, Z (complementary to Y)
Z
4
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
THVD1552 Device
14-Pin D Package (SOIC)
Top View
THVD1512, THVD1552 Devices
10-Pin DGS Package (VSSOP)
Top View
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
VCC
A
R
/RE
DE
R
RE
1
2
3
4
5
10
9
VCC
A
B
DE
8
B
D
Z
D
7
Z
GND
GND
Y
GND
6
Y
8
NC
Not to scale
Not to scale
Pin Functions
PIN
D
I/O
DESCRIPTION
NAME
A
DGS
9
12
11
5
Bus input
Bus input
Bus input, A (complementary to B)
Bus input, B (complementary to A)
Driver data input
B
8
D
4
Digital input
Digital input
Ground
DE
GND
NC
R
4
3
Driver enable, active high (2 MΩ internal pull-down)
Device ground
6, 7(1)
1, 8
2
5
—
1
—
Internally not connected
Receive data output
Digital output
Power
—
10
5-V supply.
VCC
5-V supply. These pins are not connected together internally, so power must
be applied to both.
13, 14
—
Power
Y
9
10
3
6
7
2
Bus output
Bus output
Digital input
Bus output, Y (Complementary to Z)
Z
Bus output, Z (Complementary to Y)
RE
Receiver enable, active low (2 MΩ internal pull-up)
(1) These pins are internally connected
Copyright © 2017–2018, Texas Instruments Incorporated
5
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
Bus voltage
VCC
–0.5
7
V
Range at any bus pin (A, B, Y, or Z) as
differential or common-mode with respect to
GND
–18
18
V
Input voltage
Range at any logic pin (D, DE, or RE)
IO
–0.3
–24
–65
5.7
24
V
Receiver output current
Storage temperature, Tstg
mA
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±18,000
±25,000
±30,000
UNIT
Contact discharge, per IEC 61000-4-2
Air-gap discharge, per IEC 61000-4-2
Bus terminals and GND
Bus terminals and GND
Bus terminals and GND
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
All pins except Bus
terminals and GND
V(ESD)
Electrostatic discharge
Electrical fast transient
V
±8,000
±1,500
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
Machine model (MM), per JEDEC JESD22-A115-A
±200
V(EFT)
Per IEC 61000-4-4
Bus terminals
±4,000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
5.5
UNIT
V
VCC
VI
Supply voltage
Input voltage at any bus terminal(1)
-15
15
V
High-level input voltage (driver, driver enable, and receiver enable
inputs)
VIH
VIL
2
0
VCC
0.8
V
V
Low-level input voltage (driver, driver enable, and receiver enable
inputs)
VID
IO
Differential input voltage
Output current, driver
-15
-60
-8
15
60
8
V
mA
mA
Ω
IOR
RL
Output current, receiver
Differential load resistance
54
THVD1510, THVD1512
Signaling rate
500
50
kbps
Mbps
°C
1/tUI
THVD1550, THVD1551, THVD1552
TA
TJ
Operating ambient temperature
Junction temperature
-40
-40
125
150
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.4 Thermal Information
THVD1510
THVD1550
THVD1551
THVD1510
THVD1550
THVD1512
THVD1552
THVD1552
THERMAL METRIC(1)
UNIT
D (SOIC)
8 PINS
112.4
62.7
D (SOIC)
14 PINS
88.0
DGK (VSSOP)
8 PINS
151.7
62.8
DGS (VSSOP)
10 PINS
151.4
59.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
45.4
62.0
44.1
81.3
81.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
15.4
11.3
7.8
6.5
ψJB
61.3
43.7
79.8
79.9
RθJC(bot)
N/A
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Dissipation
PARAMETER
TEST CONDITIONS
VALUE
210
UNIT
THVD151x 500 kbps
THVD155x 50 Mbps
THVD151x 500 kbps
THVD155x 50 Mbps
THVD151x 500 kbps
THVD155x 50 Mbps
Unterminated
mW
RL = 300 Ω, CL = 50 pF (driver)
350
Driver and receiver enabled,
VCC = 5.5 V, TA = 125 °C,
50% duty cycle square wave at
signaling rate
220
RS-422 load
PD
mW
mW
RL = 100 Ω, CL = 50 pF (driver)
330
250
RS-485 load
RL = 54 Ω, CL = 50 pF (driver)
340
Copyright © 2017–2018, Texas Instruments Incorporated
7
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V, (See 图 11)
RL = 100 Ω (See 图 12)
1.5
2
2.7
3
V
V
V
Driver differential output
voltage magnitude
|VOD
|
RL = 54 Ω (See 图 12)
1.5
2.7
Change in differential output
voltage
Δ|VOD
|
–200
1
200
3
mV
V
Common-mode output
voltage
VOC
VCC/2
RL = 54 Ω (See 图 12)
Change in steady-state
ΔVOC(SS) common-mode output
–200
–250
200
250
mV
mA
voltage
IOS
Short-circuit output current
DE = VCC, -15 V ≤ VO ≤ 15V
Receiver
VI = 12 V
VI = 15 V
VI = -7 V
VI = -15 V
VI = 12 V
VI = 15 V
VI = -7 V
VI = -15 V
75
95
125
156
THVD151x
DE = 0 V, VCC = 0 V or 5.5 V
THVD155x
-100
-215
-40
-85
II
Bus input current
μA
115
150
-75
160
200
-130
-280
-180
Receiver
Positive-going input
threshold voltage
VTH+
See(1)
–200
–85
–20
mV
Negative-going input
threshold voltage
Over common-mode range of - 7 V to +12 V
Over common-mode range of ± 15 V
VTH-
VHYS
VTH+
–135
50
See(1)
mV
mV
mV
Input hysteresis
Positive-going input
threshold voltage
See(1)
–220
–85
–20
Negative-going input
threshold voltage
VTH-
–135
See(1)
mV
VHYS
VOH
VOL
Input hysteresis
50
VCC - 0.3
0.2
mV
V
Output high voltage
Output low voltage
IOH = -8 mA
IOL = 8 mA
4
-1
0.4
1
V
Output high-impedance
current
IOZ
VO = 0 V or VCC, RE = VCC
µA
Logic
IIN
Input current (D, DE, RE)
4.5 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC
–5
0
5
µA
Supply
RE = 0 V, DE = VCC
No load
,
Driver and receiver enabled
Driver enabled, receiver disabled
Driver disabled, receiver enabled
Driver and receiver disabled
700
400
400
1000
620
630
1
µA
µA
µA
RE = VCC, DE = VCC
No load
,
ICC
Supply current (quiescent)
RE = 0 V, DE = 0 V,
No load
RE = VCC, DE = 0 V,
D = open, No load
0.1
µA
°C
TSD
Thermal shutdown temperature
170
(1) Under any specific conditions, VTH+ is specified to be at least VHYS higher than VTH–
.
8
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
7.7 Switching Characteristics
500-kbps devices (THVD1510, THVD1512) over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Differential output rise/fall time
Propagation delay
300
400
350
600
500
15
ns
ns
ns
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See 图 13
Pulse skew, |tPHL – tPLH
|
Disable time (THVD1510,
THVD1512)
tPHZ, tPLZ
110
200
ns
See 图 14 and 图 15
RE = 0 V
RE = VCC
100
2
500
4
ns
µs
Enable time (THVD1510,
THVD1512)
tPZH, tPZL
Receiver
tr, tf
Differential output rise/fall time
Propagation delay
15
50
25
60
10
ns
ns
ns
tPHL, tPLH
tSK(P)
CL = 15 pF
See 图 16
Pulse skew, |tPHL – tPLH
|
Disable time (THVD1510,
THVD1512)
tPHZ, tPLZ
30
60
40
ns
ns
tPZH(1)
,
DE = VCC
DE = 0 V
See 图 17
See 图 18
100
tPZL(1)
tPZH(2)
tPZL(2)
,
,
Enable time (THVD1510,
THVD1512)
3
8
μs
7.8 Switching Characteristics
50-Mbps devices (THVD1550, THVD1551, THVD1552) over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Differential output rise/fall time
Propagation delay
1
5
2
6
16
ns
ns
ns
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See 图 13
10
Pulse skew, |tPHL – tPLH
|
3.5
Disable time (THVD1550,
THVD1552)
tPHZ, tPLZ
10
22
ns
See 图 14 and 图 15
RE = 0 V
RE = VCC
10
2
22
4
ns
Enable time (THVD1550,
THVD1552)
tPZH, tPZL
μs
Receiver
tr, tf
Differential output rise/fall time
Propagation delay
1
3
6
45
2
ns
ns
ns
tPHL, tPLH
tSK(P)
CL = 15 pF
See 图 16
30
Pulse skew, |tPHL – tPLH
|
Disable time (THVD1550,
THVD1552)
tPHZ, tPLZ
8
18
90
ns
ns
tPZH(1)
,
DE = VCC
DE = 0 V
See 图 17
See 图 18
55
tPZL(1)
tPZH(2)
tPZL(2)
,
,
Enable time (THVD1550,
THVD1552)
3
8
μs
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9
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
7.9 Typical Characteristics
5
4.5
4
4.5
4
VOL
VOH
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
10 20 30 40 50 60 70 80 90 100 110
0
10 20 30 40 50 60 70 80 90 100 110
IO - Driver Output Current (mA)
IO - Driver Output Current (mA)
D001
D002
VCC = 5 V
DE = VCC
D = 0 V
VCC = 5 V
DE = VCC
D = 0 V
图 1. Driver Output Voltage vs Driver Output Current
图 2. Driver Differential Output Voltage vs Driver Output
60
50
40
30
20
10
0
460
450
440
430
420
410
400
390
380
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-40
-20
0
20
40
60
80
100
120
VCC - Supply Voltage (V)
Temperature (èC)
D003
D004
TA = 25°C
DE = VCC
RL = 54 Ω
D = VCC
图 3. Driver Output Current vs Supply Voltage
图 4. THVD1510 Driver Rise or Fall Time vs Temperature
395
390
385
380
375
370
365
360
355
350
345
340
335
330
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D005
D006
图 5. THVD1510 Driver Propagation Delay vs Temperature
图 6. THVD1550 Driver Rise or Fall Time vs Temperature
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Typical Characteristics (接下页)
14
80
70
60
50
40
30
20
10
0
12
10
8
6
4
2
0
-40
-20
0
20
40
60
80
100
120
50
100 150 200 250 300 350 400 450 500
Temperature (èC)
Signaling Rate (Kbps)
D007
D008
RL = 54 Ω
图 7. THVD1550 Driver Propagation Delay vs Temperature
图 8. THVD1510 Supply Current vs Signal Rate
7
6
5
4
3
2
1
0
90
VIT- (-7 V) VIT+ (-7 V)
VIT- (0 V) VIT+ (0 V)
VIT- (12 V) VIT+ (12 V)
80
70
60
50
40
30
20
10
0
-170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50
0
5
10
15
20
25
30
35
40
45
50
Differential Input Voltage (mV)
D010
Signaling Rate (Mbps)
D009
RL = 54 Ω
图 10. Receiver Output vs Input
图 9. THVD1550 Supply Current vs Signal Rate
8 Parameter Measurement Information
375 Ω
Vcc
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
图 11. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
V
OC
图 12. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
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Parameter Measurement Information (接下页)
V
cc
Vcc
DE
50%
V
I
0 V
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
50%
10%
Input
50 Ω
V
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
图 13. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
V
B
R
110 Ω
=
DE
50 Ω
L
t
PZH
=
C
L
Input
OH
50 pF
90%
Generator
V
I
50%
V
O
~
~ 0V
t
PHZ
图 14. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
Generator
50%
10%
VOL
VI
50 Ω
图 15. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
3 V
50%
V
I
A
B
0 V
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
VOH
Generator
I
90%
50%
10%
CL=15 pF
RE
V
OD
V
tr
OL
t
f
图 16. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
图 17. Measurement of Receiver Enable/Disable Times With Driver Enabled
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Parameter Measurement Information (接下页)
Vcc
0V
Vcc
VI
50%
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
图 18. Measurement of Receiver Enable Times With Driver Disabled
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9 Detailed Description
9.1 Overview
THVD1510 and THVD1550 are low-power, half-duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 500 kbps and 50 Mbps respectively.
THVD1551 is fully enabled with no external enabling pins. THVD1512 and THVD1552 have active-high driver
enables and active-low receiver enables. A standby current of less than 1 µA can be achieved by disabling both
driver and receiver.
9.2 Functional Block Diagrams
VCC
R
RE
A
B
DE
D
GND
图 19. THVD1510 and THVD1550
VCC
A
R
D
R
B
VCC
Z
Y
D
GND
图 20. THVD1551
VCC
A
R
R
B
RE
DE
D
Z
Y
D
GND
图 21. THVD1512 and THVD1552
9.3 Feature Description
Internal ESD protection circuits of the THVD15xx protect the transceivers against electrostatic discharges (ESD)
according to IEC 61000-4-2 of up to ±18 kV and against electrical fast transients (EFT) according to IEC 61000-
4-4 of up to ±4 kV. With careful system design, one could achieve ±4 kV EFT Criterion A (no data loss when
transient noise is present).
14
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Feature Description (接下页)
The THVD15xx device family provides internal biasing of the receiver input thresholds in combination with large
input-threshold hysteresis. The receiver output remains logic high under a bus-idle or bus-short conditions
without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient
temperature range from –40°C to 125°C.
9.4 Device Functional Modes
9.4.1 Device Functional Modes for THVD1510 and THVD1550
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
表 1. Driver Function Table for THVD1510 and THVD1550
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 2. Receiver Function Table for THVD1510 and THVD1550
DIFFERENTIAL INPUT
VID = VA – VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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9.4.2 Device Functional Modes for THVD1551
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic
states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the
differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns
high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left
open while the driver is enabled, output Y turns high and Z turns low.
表 3. Driver Function Table for THVD1551
INPUT
OUTPUTS
FUNCTIONS
D
H
Y
H
L
Z
L
Actively drive bus high
Actively drive bus low
L
H
L
OPEN
H
Actively drive bus high by default
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the
receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R,
turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs
causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus
lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
表 4. Receiver Function Table for THVD1551
DIFFERENTIAL INPUT
VID = VA – VB
OUTPUT
FUNCTION
R
H
?
VTH+ < VID
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Fail-safe high output
Fail-safe high output
Fail-safe high output
VTH- < VID < VTH+
VID < VTH-
L
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
H
H
H
9.4.3 Device Functional Modes for THVD1512 and THVD1552
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
Y turns high and Z turns low.
表 5. Driver Function Table for THVD1512 and THVD1552
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
Y
H
L
Z
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 6. Receiver Function Table for THVD1512 and THVD1552
DIFFERENTIAL INPUT
VID = VA – VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The THVD15xx family consists of half-duplex and full-duplex RS-485 transceivers commonly used for
asynchronous data transmissions. For half-duplex devices, the driver and receiver enable pins allow for the
configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires), and
allows each node to transmit data on one pair while simultaneously receiving data on the other pair.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates
over longer cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
图 22. Typical RS-485 Network With Half-Duplex Transceivers
Y
Z
A
B
R
D
R
R
R
R
R
R
T
T
T
T
DE
RE
Master
R
Slave
D
RE
D
DE
D
B
A
Z
Y
A
B
Z
Y
R
Slave
D
R RE DE D
图 23. Typical RS-485 Network With Full-Duplex Transceivers
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Typical Application (接下页)
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图 24. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 50 Mbps for the THVD1550, THVD1551 and THVD1552) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections of varying phase as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in 公式 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12 kΩ. Because the THVD15xx family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
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Typical Application (接下页)
10.2.1.4 Receiver Failsafe
The differential receivers of the THVD15xx family are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VTH+, VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the Electrical Characteristics table,
differential signals more negative than –200 mV will always cause a low receiver output, and differential signals
more positive than 200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output will
be high. Only when the differential input is more than VHYS below VTH+ will the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, Vhys, as well as the value of VTH+
.
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Typical Application (接下页)
10.2.1.5 Transient Protection
The bus pins of the THVD15xx transceiver family include on-chip ESD protection against ±30-kV HBM and ±18-
kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图 25. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 26 compares the pulse power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left-hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right-hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图 26. Power Comparison of ESD, EFT, and Surge Transients
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Typical Application (接下页)
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
图 27 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图 27. Comparison of Transient Energies
10.2.2 Detailed Design Procedure
图 28 and 图 29 suggest a protection circuit against 1 kV surge (IEC 61000-4-5) transients. 表 7 shows the
associated bill of materials.
5V
100nF
100nF
10k
V
CC
R1
R
RxD
TVS
RE
DE
D
A
B
MCU/
UART
DIR
TxD
R2
10k
GND
图 28. Transient Protection Against Surge Transients for Half-Duplex Devices
22
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THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
Typical Application (接下页)
5V
100nF
R1
10k
V
CC
TVS
A
B
R
RxD
DIR
RE
R2
R1
MCU/
UART
DE
D
DIR
TxD
TVS
Z
Y
10k
GND
R2
图 29. Transient Protection Against Surge Transients for Full-Duplex Devices
表 7. Bill of Materials
DEVICE
XCVR
R1
FUNCTION
ORDER NUMBER
MANUFACTURER
5-V, RS-485 transceiver
THVD15xx
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
CDSOT23-SM712
Vishay
Bourns
R2
TVS
Bidirectional 400-W transient suppressor
版权 © 2017–2018, Texas Instruments Incorporated
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THVD1510, THVD1512
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
10.2.3 Application Curves
500 kbps
50 Mbps
图 31. THVD1550 Waveforms with 60-Ω Termination
图 30. THVD1510 Waveforms with 60-Ω Termination
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
24
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THVD1550, THVD1551, THVD1552
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
12 Layout
12.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
12.2 Layout Example
5
Via to ground
C
Via to VCC
4
R
6
6
R
R
1
R
MCU
5
TVS
THVD15x0
5
图 32. Half-Duplex Layout Example
版权 © 2017–2018, Texas Instruments Incorporated
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THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 8. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
THVD1510
THVD1512
THVD1550
THVD1551
THVD1552
13.4 接收文档更新通知
要接收文档更新通知，请转至 TI.com.cn 上您的器件的产品文件夹。请在右上角单击通知我 按钮进行注册，即可收
到产品信息更改每周摘要（如有）。有关更改的详细信息，请查看任意已修订文档的修订历史记录。
13.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.6 商标
E2E is a trademark of Texas Instruments.
13.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
26
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
版权 © 2017–2018, Texas Instruments Incorporated
31
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THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
32
版权 © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
www.ti.com.cn
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
版权 © 2017–2018, Texas Instruments Incorporated
33
THVD1510, THVD1512
THVD1550, THVD1551, THVD1552
ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
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PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
TYP
4.75
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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版权 © 2017–2018, Texas Instruments Incorporated
THVD1510, THVD1512
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
10
SYMM
6
5
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
版权 © 2017–2018, Texas Instruments Incorporated
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THVD1510, THVD1512
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ZHCSGQ1C –SEPTEMBER 2017–REVISED DECEMBER 2018
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
1
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
36
版权 © 2017–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1510D
THVD1510DGK
THVD1510DGKR
THVD1510DR
THVD1512DGS
THVD1512DGSR
THVD1550D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
75
80
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
VD1510
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
DGK
DGK
D
NIPDAUAG
NIPDAUAG | SN
NIPDAU
1510
8
2500 RoHS & Green
2500 RoHS & Green
1510
8
VD1510
1512
VSSOP
VSSOP
SOIC
DGS
DGS
D
10
10
8
80
RoHS & Green
NIPDAUAG
NIPDAUAG | SN
NIPDAU
2500 RoHS & Green
1512
75
80
RoHS & Green
RoHS & Green
VD1550
1550
THVD1550DGK
THVD1550DGKR
THVD1550DR
THVD1551DGK
THVD1551DGKR
THVD1552D
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG
NIPDAUAG | SN
NIPDAU
8
2500 RoHS & Green
2500 RoHS & Green
1550
8
VD1550
1551
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
80
RoHS & Green
NIPDAUAG
NIPDAUAG | SN
NIPDAU
8
2500 RoHS & Green
1551
14
10
10
14
50
80
RoHS & Green
RoHS & Green
1552
THVD1552DGS
THVD1552DGSR
THVD1552DR
VSSOP
VSSOP
SOIC
DGS
DGS
D
NIPDAUAG
NIPDAUAG | SN
NIPDAU
1552
2500 RoHS & Green
2500 RoHS & Green
1552
1552
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1510DGKR
THVD1510DGKR
THVD1510DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
5.3
5.3
6.4
5.3
5.3
6.4
5.3
5.3
5.3
6.5
3.4
3.4
5.2
3.4
3.4
5.2
3.4
3.4
3.4
9.0
1.4
1.4
2.1
1.4
1.4
2.1
1.4
1.4
1.4
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8
THVD1512DGSR
THVD1550DGKR
THVD1550DR
VSSOP
VSSOP
SOIC
DGS
DGK
D
10
8
8
THVD1551DGKR
THVD1552DGSR
THVD1552DGSR
THVD1552DR
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGS
DGS
D
8
10
10
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD1510DGKR
THVD1510DGKR
THVD1510DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
366.0
364.0
340.5
366.0
364.0
340.5
364.0
366.0
364.0
340.5
364.0
364.0
336.1
364.0
364.0
336.1
364.0
364.0
364.0
336.1
50.0
27.0
25.0
50.0
27.0
25.0
27.0
50.0
27.0
32.0
8
THVD1512DGSR
THVD1550DGKR
THVD1550DR
VSSOP
VSSOP
SOIC
DGS
DGK
D
10
8
8
THVD1551DGKR
THVD1552DGSR
THVD1552DGSR
THVD1552DR
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGS
DGS
D
8
10
10
14
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
THVD1510D
THVD1510DGK
THVD1512DGS
THVD1550D
D
SOIC
VSSOP
VSSOP
SOIC
8
8
75
80
80
75
80
80
50
80
507
330
330
507
330
274
507
330
8
3940
500
4.32
2.88
2.88
4.32
2.88
2.88
4.32
2.88
DGK
DGS
D
6.55
6.55
8
10
8
500
3940
500
THVD1550DGK
THVD1551DGK
THVD1552D
DGK
DGK
D
VSSOP
VSSOP
SOIC
8
6.55
6.55
8
8
500
14
10
3940
500
THVD1552DGS
DGS
VSSOP
6.55
Pack Materials-Page 3
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Copyright © 2023，德州仪器 (TI) 公司
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