TIBPAL16L8-15MWB [TI]
High-Performance Impact PAL Circuits 20-CFP -55 to 125;
| 型号： | TIBPAL16L8-15MWB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Performance Impact PAL Circuits 20-CFP -55 to 125 时钟 输入元件 可编程逻辑 |
| 文件： | 总18页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16L8’
J OR W PACKAGE
High-Performance Operation:
Propagation Delay . . . 15 ns Max
(TOP VIEW)
Power-Up Clear on Registered Devices (All
Register Outputs are Set High, but Voltage
Levels at the Output Pins Go Low)
I
I
I
I
I
I
I
I
I
V
1
2
3
4
5
6
7
8
9
10
20
19
18
CC
O
I/O
Package Options Include Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) 300-mil DIPs
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
Dependable Texas Instruments Quality and
Reliability
I
3-STATE
REGISTERED
Q OUTPUTS
I/O
PORTS
DEVICE
INPUTS O OUTPUTS
12
11
O
I
PAL16L8
PAL16R4
PAL16R6
PAL16R8
10
8
2
0
0
0
0
6
4
2
0
GND
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
8
TIBPAL16L8’
FK PACKAGE
8
(TOP VIEW)
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT-X circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
3
2 1 20 19
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
18
17
16
15
14
4
5
6
7
8
9 10 11 12 13
Pin assignments in operating mode
The TIBPAL16’ M series is characterized for
operation over the full military temperature range
of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R4’
J OR W PACKAGE
TIBPAL16R4’
FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
CC
I
I
I
I
I
I
I
I
I/O
I/O
Q
Q
Q
3
2
1
20 19
18
I/O
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
Q
Q
Q
Q
13 I/O
12 I/O
11 OE
9 10 11 12 13
GND
TIBPAL16R6’
J OR W PACKAGE
TIBPAL16R6’
FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
CC
I
I
I
I
I
I
I
I
I/O
Q
Q
Q
Q
Q
Q
3
2
1
20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
12 I/O
11 OE
GND
TIBPAL16R8’
J OR W PACKAGE
TIBPAL16R8’
FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
CC
I
I
I
I
I
I
I
I
Q
Q
Q
Q
Q
Q
Q
Q
3
2
1
20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
11 OE
Pin assignments in operating mode
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
functional block diagrams (positive logic)
TIBPAL16L8’
≥1
&
EN
O
7
32 X 64
O
7
7
7
7
7
7
7
16 x
I/O
I/O
I/O
I/O
I/O
I/O
10
16
16
I
6
6
TIBPAL16R4’
OE
CLK
EN 2
C1
I = 1
≥1
&
8
Q
Q
Q
Q
2
32 X 64
1D
8
8
8
16 x
8
16
16
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
7
7
7
4
4
denotes fused inputs
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
EN 2
C1
I = 1
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
32 X 64
1D
16 x
8
16
16
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL16R8’
OE
CLK
EN 2
C1
I = 1
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
32 X 64
1D
8
8
8
8
8
8
8
16 x
8
16
16
I
8
8
denotes fused inputs
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16L8-15M logic diagram (positive logic)
1
I
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I/O
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I
Fuse number = First fuse number + Increment
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R4-15M logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
I/O
Q
128
160
192
224
2
I
256
288
320
352
384
416
448
480
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 1
1D
C1
768
800
832
864
896
928
960
992
I = 1
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 1
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 1
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I/O
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R6-15M logic diagram (positive logic)
1
CLK
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I = 1
1D
Q
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 1
1D
Q
C1
768
800
832
864
896
928
960
992
I = 1
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 1
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 1
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 1
1D
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R8-15M logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
I = 1
1D
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
Q
C1
224
2
I
256
288
320
352
384
416
448
480
I = 1
1D
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 1
1D
C1
768
800
832
864
896
928
960
992
I = 1
1D
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 1
1D
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 1
1D
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 1
1D
C1
1792
1824
1856
1888
1920
1952
1984
2016
I = 1
1D
12
11
Q
C1
OE
Fuse number = First fuse number + Increment
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
IH
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
12
0
9
50
High
Low
t
w
Pulse duration, clock (see Note 2)
ns
10
15
0
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
ns
ns
°C
su
h
T
–55
25
125
A
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f
only for clock high or low, but not for both simultaneously.
. The minimum pulse durations specified are
clock
electrical characteristics over recommended operating free-air temperature range
TIBPAL16R4-15M
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
‡
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
3.3
OH
OL
OH
OL
I
0.35
0.5
20
Outputs
I/O ports
Outputs
I/O ports
Pin 1, 11
All others
Pin 1, 11
I/O ports
All others
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
V
= 2.7 V
= 0.4 V
µA
µA
OZH
OZL
I
O
100
–20
–250
0.2
O
V = 5.5 V
I
mA
0.1
50
I
IH
V
CC
= 5.5 V,
V = 2.7 V
I
100
25
µA
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 0.4 V
–0.25
–250
220
mA
mA
mA
IL
I
§
V
O
= 0.5 V
–30
OS
V = 0,
I
Outputs open
170
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid
test equipment degradation.
O
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
electrical characteristics over recommended operating free-air temperature range
TIBPAL16L8-15M
TIBPAL16R6-15M
TIBPAL16R8-15M
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
I = –18 mA
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
3.3
OH
OL
OH
OL
I
0.35
0.5
20
Outputs
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
= 2.7 V
= 0.4 V
µA
µA
OZH
OZL
I
O
O
I/O ports
Outputs
100
–20
–250
0.2
V
I/O ports
Pin 1, 11
All others
Pin 1, 11
I/O ports
All others
I/O ports
All others
V = 5.5 V
I
mA
0.1
50
I
V
= 5.5 V,
= 5.5 V,
V = 2.7 V
I
100
20
µA
IH
IL
CC
CC
–0.25
–0.2
–250
220
I
V
V = 0.4 V
I
mA
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.5 V
O
–30
mA
mA
OS
CC
V = 0,
I
Outputs open
170
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid
test equipment degradation.
O
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
§
f
t
50
MHz
ns
max
pd
I, I/O
CLK↑
OE↓
O, I/O
Q
8
7
8
7
8
8
15
12
12
12
15
15
t
t
t
t
t
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 1
ns
pd
en
dis
en
dis
Q
ns
OE↑
Q
ns
I, I/O
I, I/O
O, I/O
O, I/O
ns
ns
†
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be calculated
accordingly.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
The TIBPAL16R4-15M with date codes prior to 9616A must be programmed according to programming
algorithms/specificationscorrespondingtotheTIBPAL16R4-12C. TheTIBPAL16R4-15Mwithdatecode9616A
or newer must be programmed according to programming algorithms/specifications corresponding to the
TIBPAL16R4-10C.
Regardless of date code, the TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M must be
programmed according to programming algorithms/specifications corresponding to the TIBPAL16L8-12C,
TIBPAL16R6-12C, and TIBPAL16R8-12C, respectively. Failure to do so may damage the devices.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
Table 1. Programming Reference Table
(see Note 3)
DESC SMD
NUMBER
FAMILY/PINOUT
CODE
DEVICE
TIBPAL16L8-15MJB
TIBPAL16L8-15MFKB
TIBPAL16L8-15MWB
TIBPAL16R4-15MJB
TIBPAL16R4-15MFKB
TIBPAL16R4-15MWB
TIBPAL16R6-15MJB
TIBPAL16R6-15MFKB
TIBPAL16R6-15MWB
TIBPAL16R8-15MJB
TIBPAL16R8-15MFKB
TIBPAL16R8-15MWB
5962-8515509RA
5962-85155092A
5962-8515509SA
5962-8515512RA
5962-85155122A
5962-8515512SA
5962-8515511RA
5962-85155112A
5962-8515511SA
5962-8515510RA
5962-85155102A
5962-8515510SA
9A/17
9A/717
9A/17
A1/24
0A1/724
A1/24
9A/24
9A/724
9A/24
9A/24
9A/724
9A/24
NOTE 3: Programming information for TIBPAL16R4-15M with date codes
9616A or newer. Programming information for TIBPAL16L8-15M,
TIBPAL16R6-15M, and TIBPAL16R8-15M regardless of date code.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
3 V
0
Timing
Input
High-Level
1.5 V
1.5 V 1.5 V
Pulse
t
t
w
h
t
su
3 V
0
Data
Input
3 V
0
1.5 V
1.5 V
Low-Level
Pulse
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
3 V
0
Output
Control
(low-level
enabling)
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
0
pd
t
pd
pd
t
en
V
OH
t
dis
In-Phase
Output
1.5 V
1.5 V
1.5 V
≈ 3.3 V
OL
V
OL
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+ 0.5 V
t
pd
t
V
OL
V
OH
OL
t
Out-of-Phase
Output
(see Note D)
dis
1.5 V
t
en
V
V
V
≈ 0 V
OH
Waveform 2
S1 Open
(see Note B)
1.5 V
– 0.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
OH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t .
pd en dis
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, t and t ≤ 2 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-85155092A
5962-8515509RA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
5962-8515509SA
W
FK
J
Call TI
5962-85155102A
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
5962-8515510RA
A42
N / A for Pkg Type
N / A for Pkg Type
5962-8515510SA
W
FK
J
Call TI
5962-85155112A
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
5962-8515511RA
A42
N / A for Pkg Type
N / A for Pkg Type
5962-8515511SA
W
FK
J
Call TI
5962-85155122A
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
5962-8515512RA
A42
N / A for Pkg Type
N / A for Pkg Type
5962-8515512SA
W
FK
J
Call TI
TIBPAL16L8-15MFKB
TIBPAL16L8-15MJ
TIBPAL16L8-15MJB
TIBPAL16L8-15MWB
TIBPAL16R4-15MFKB
TIBPAL16R4-15MJB
TIBPAL16R4-15MWB
TIBPAL16R6-15MFKB
TIBPAL16R6-15MJ
TIBPAL16R6-15MJB
TIBPAL16R6-15MWB
TIBPAL16R8-15MFKB
TIBPAL16R8-15MJB
TIBPAL16R8-15MWB
LCCC
CDIP
CDIP
CFP
POST-PLATE N / A for Pkg Type
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
J
W
FK
J
Call TI
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
W
FK
J
Call TI
LCCC
CDIP
CDIP
CFP
POST-PLATE N / A for Pkg Type
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
J
W
FK
J
Call TI
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
W
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2009
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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