TIBPAL16R4-10MFKB [TI]
HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS; 高性能Impact -X é PAL电路
| 型号： | TIBPAL16R4-10MFKB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| 文件： | 总23页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
•
High-Performance Operation:
f
f
f
(no feedback)
TIBPAL16R’-7C Series . . . 100 MHz Min
TIBPAL16R’-10M Series . . . 62.5 MHz Min
(internal feedback)
TIBPAL16R’-7C Series . . . 100 MHz Min
TIBPAL16R’-10M Series . . . 62.5 MHz Min
max
(TOP VIEW)
max
I
I
I
I
I
I
I
I
I
V
1
2
3
4
5
6
7
8
9
10
20
19
18
CC
O
I/O
(external feedback)
max
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
TIBPAL16R’-7C Series . . . 74 MHz Min
TIBPAL16R’-10M Series . . . 52.5 MHz Min
Propagation Delay
TIBPAL16L’-7C Series . . . 7 ns Max
TIBPAL16L’-10M Series . . . 10 ns Max
12
11
O
I
•
•
•
Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
GND
Preload Capability on Output Registers
Simplifies Testing
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
(TOP VIEW)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
3
2
1
20 19
18
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
4
5
6
7
8
17
16
15
14
•
•
Security Fuse Prevents Duplication
Dependable Texas Instruments Quality and
Reliability
9 10 11 12 13
I/O
PORT
S
I
3-STATE
REGISTERED
Q OUTPUTS
DEVICE
INPUTS O OUTPUTS
PAL16L8
PAL16R4
PAL16R6
PAL16R8
10
8
2
0
0
0
0
6
4
2
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
Pin assignments in operating mode
8
8
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
Alloftheregisteroutputsaresettoalowlevelduringpower-up. Extracircuitryhasbeenprovidedtoallowloading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Copyright 1992, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
TIBPAL16R4’
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
CC
I
I
I
I
I
I
I
I
I/O
I/O
Q
Q
Q
3
2
1
20 19
18
I/O
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
Q
Q
Q
Q
9 10 11 12 13
13 I/O
12 I/O
11 OE
GND
TIBPAL16R6’
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
CC
I
I
I
I
I
I
I
I
19 I/O
3
2
1
20 19
18
18
17
16
15
14
13
12
11
Q
Q
Q
Q
Q
Q
I/O
OE
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
TIBPAL16R8’
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
CC
I
I
I
I
I
I
I
I
Q
Q
Q
Q
Q
Q
Q
Q
3
2
1
20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
11 OE
Pin assignments in operating mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL16L8-7C, TIBPAL16R4-7C
TIBPAL16L8-10M, TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
functional block diagrams (positive logic)
TIBPAL16L8’
≥1
&
EN
O
7
32 X 64
O
7
7
7
7
7
7
7
16 x
I/O
I/O
I/O
I/O
I/O
I/O
10
16
16
I
6
6
TIBPAL16R4’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
32 X 64
1D
8
8
8
16 x
8
16
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
16
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
32 X 64
1D
16 x
8
16
16
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL16R8’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
32 X 64
1D
8
8
8
8
8
8
8
16 x
8
16
16
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL16L8-7C
TIBPAL16L8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
logic diagram (positive logic)
1
I
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I/O
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL16R4-7C
TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
I/O
Q
128
160
192
224
2
I
256
288
320
352
384
416
448
480
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
C1
768
800
832
864
896
928
960
992
I = 0
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I/O
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL16R6-7C
TIBPAL16R6-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I = 0
1D
Q
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
Q
C1
768
800
832
864
896
928
960
992
I = 0
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 0
1D
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL16R8-7C
TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
I = 0
1D
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
Q
C1
224
2
I
256
288
320
352
384
416
448
480
I = 0
1D
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
C1
768
800
832
864
896
928
960
992
I = 0
1D
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 0
1D
C1
1792
1824
1856
1888
1920
1952
1984
2016
I = 0
1D
12
11
Q
C1
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
0
5
5
7
0
0
100
High
Low
ns
t
w
Pulse duration, clock (see Note 2)
t
su
t
h
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
ns
ns
°C
T
A
25
75
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
3.2
–1.5
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
V
OH
OL
OH
0.3
0.5
100
V
OL
‡
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
pF
pF
pF
OZH
O
‡
= 0.4 V
–100
100
OZL
O
V = 5.5 V
I
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–80
–70
160
5
–250
–130
180
IL
§
V
O
= 0.5 V
–30
OS
V = 0,
I
Outputs open
CC
C
C
C
f = 1 MHz,
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
i
V = 2 V
O
6
o
V = 2 V
CLK
6
clk
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I/O leakage is the worst case of I
and I or I
and I respectively.
OZH IH
OZL
IL
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
without feedback
100
100
74
with internal feedback
(counter configuration)
‡
f
MHz
max
with external feedback
1 or 2 outputs switching
3
3
2
5.5
6
7
7.5
6.5
3
t
O, I/O
ns
I, I/O
pd
8 outputs switching
R1 = 200 Ω,
R2 = 390 Ω,
See Figure 6
t
CLK↑
CLK↑
OE↓
Q
4
ns
ns
ns
ns
ns
ns
ns
pd
pd
en
§
t
Feedback input
t
t
t
t
t
Q
4
4
7.5
7.5
9
OE↑
Q
dis
en
dis
I, I/O
I, I/O
O, I/O
O, I/O
6
6
9
¶
Skew between registered outputs
= 5 V, T = 25°C.
0.5
sk(o)
†
‡
§
All typical values are at V
See section for f
CC
specifications.
A
max
ThisparameterappliestoTIBPAL16R4’andTIBPAL16R6’only(seeFigure4forillustration)andiscalculatedfromthemeasuredf
feedback in the counter configuration.
withinternal
max
¶
This parameter is the measurement of the difference between the fastest and slowest t (CLK-to-Q) observed when multiple registered outputs
are switching in the same direction.
pd
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
12
†
0
8
62.5
High
Low
ns
t
w
Pulse duration, clock (see Note 2)
8
†
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
10
0
ns
ns
°C
su
†
h
T
–55
25
125
A
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
–0.8
3.2
–1.5
IK
CC
CC
CC
CC
I
I
= –2 mA
= 12 mA
= 2.7 V
2.4
V
OH
OL
OH
OL
I
0.3
0.5
100
–0.1
–0.25
1
V
‡
I
V
µA
OZH
O
0, Q outputs
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V
O
= 0.4 V
mA
mA
OZL
CC
I/O ports
V = 5.5 V
I
I
CC
I/O ports
All others
100
25
V
CC
= 5.5 V,
I
IH
V = 2.7 V
I
µA
‡
I
V
V
V
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 0.4 V
–0.08 –0.25
–70 –130
mA
mA
mA
pF
IL
CC
CC
CC
I
§
I
I
V
O
= 0.5 V
–30
OS
CC
V = GND,
I
V = 2 V
I
Outputs open
140
5
200
C
C
C
f = 1 MHz,
f = 1 MHz,
f = 1 MHz,
i
V = 2 V
O
6
pF
o
V = 2 V
CLK/OE
6
pF
clk/oe
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I/O leakage is the worst case of I
and I or I
and I respectively.
OZH IH
OZL
IL
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006C – D3115, MAY 1988 – REVISED OCTOBER 1990
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
62.5
MAX
UNIT
without feedback
with internal feedback
(counter configuration)
‡
f
62.5
MHz
max
with external feedback
52.5
2
t
t
t
t
t
t
t
I, I/O
O, I/O
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 6
6
4
10
9
ns
ns
ns
ns
ns
ns
ns
pd
CLK↑
CLK↑
OE↓
Q
1
pd
§
Feedback input
5
pd
Q
1
1
2
1
4
4
6
6
10
10
12
10
en
dis
en
dis
OE↑
Q
I, I/O
I, I/O
O, I/O
O, I/O
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
specifications. f
See section for f
section.
with external feedback is not production tested but is calculated from the equation found in the f
max
max
max
§
ThisparameterappliestoTIBPAL16R4’andTIBPAL16R6’only(seeFigure4forillustration)andiscalculatedfromthemeasuredf
feedback in the counter configuration.
withinternal
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 volts and Pin 1 at V , raise Pin 11 to V
.
IHH
CC
IL
Apply either V or V to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
V
IHH
Pin 11
IL
t
t
d
su
t
t
w
d
V
V
V
V
IH
Pin 1
IL
V
V
IH
OH
OL
Registered I/O
Input
Output
IL
Figure 1. Preload Waveforms
NOTE 3: t = t = t = 100 ns to 1000 ns V
su
= 10.25 V to 10.75 v
d
h
IHH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
occur until all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not
CC
V
CC
5 V
4 V
†
t
pd
(600 ns TYP, 1000 ns MAX)
V
V
OH
Active Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
f
SPECIFICATIONS
max
f
without feedback, see Figure 3
max
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t + t ).
su
h
However, the minimum f
is determined by the minimum clock period (t high + t low).
max
w w
1
1
f
without feedback
Thus,
or
.
max
(t
t )
(t high
w
t low)
w
su
h
CLK
LOGIC
ARRAY
C1
1D
t
+ t
h
su
or
high + t low
t
w
w
Figure 3. f
Without Feedback
max
f
with internal feedback, see Figure 4
max
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
1
f
with internal feedback
Thus,
.
max
(t
t
CLK to FB)
su
pd
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
LOGIC
ARRAY
C1
1D
t
t
CLK-to-FB
pd
su
Figure 4. f
With Internal Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
f
SPECIFICATIONS
max
f
with external feedback, see Figure 5
max
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(t + t CLK-to-Q).
su
pd
1
f
with external feedback
Thus,
.
max
(t
t
CLK to Q)
su
pd
CLK
NEXT DEVICE
LOGIC
ARRAY
C1
1D
t
t
CLK-to-Q
t
su
su
pd
Figure 5. f
With External Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
High-Level
Pulse
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
Data
Input
Low-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
(3.5 V) [3 V]
(0.3 V) [0]
Output
Control
(low-level
enabling)
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
en
t
pd
t
t
t
dis
pd
V
OH
In-Phase
Output
≈ 3.3 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+0.5 V
OL
V
OL
V
OL
t
pd
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
–0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ), PRR ≤ 1 MHz,
t = t = 2 ns, duty cycle = 50%; For M suffix, use the voltage levels indicated in brackets [ ], PRR ≤ 10 MHz, t and t ≤ 2 ns, duty
r
f
r
f
cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
8
7
6
5
220
200
180
160
140
120
100
t
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
PLH
4
3
t
t
(CLK to Q)
(CLK to Q)
PHL
PLH
T
C
= 25 °C
= 50 pF
2
1
A
L
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
0
4.5
–75 –50 –25
0
25
50
75
100 125
4.75
5
5.25
5.5
T
A
– Free-Air Temperature – °C
V
CC
– Supply Voltage – V
Figure 7
Figure 8
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
8
7
6
5
16
14
12
10
V
= 5 V
= 25 °C
CC
T
A
R1 = 200 Ω
t
(I, I/O to O, I/O)
PHL
R2 = 390 Ω
1 Output Switching
t
(I, I/O to O, I/O)
PLH
4
3
8
6
t
(CLK to Q)
PHL
t
(CLK to Q)
PLH
(CLK to Q)
t
PHL
t
(CLK to Q)
PLH
t
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
PLH
V
C
= 5 V
= 50 pF
2
1
4
2
CC
L
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
0
0
–75 –50 –25
0
25
50
75 100 125
0
100
200
300
400
500
600
T
A
– Free-Air Temperature – °C
C
– Load Capacitance – pF
L
Figure 9
Figure 10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992
TYPICAL CHARACTERISTICS
POWER DISSIPATION
†
vs
PROPAGATION DELAY TIME
vs
FREQUENCY
8-BIT COUNTER MODE
NUMBER OF OUTPUTS SWITCHING
0.8
0.7
0.6
0.5
1000
900
800
700
600
V
= 5 V
= 25 °C
CC
V
CC
= 5 V
T
A
R1 = 200 Ω
R2 = 390 Ω
C
= 50 pF
L
8-Bit Counter
T
A
= 0 °C
T
= 25 °C
= 80 °C
A
0.4
0.3
T
A
0.2
0.1
0
1
4
10
40
100
2
3
4
5
6
7
8
Number of Outputs Switching
F – Frequency – MHz
Figure 11
Figure 12
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
8
7
6
t
(I, I/O to O, I/O)
PHL
t
(I, I/O to O, I/O)
PLH
5
t
(CLK to Q)
PHL
4
3
t
(CLK to Q)
PLH
2
1
V
= 5 V
= 25 °C
= 50 pF
CC
T
A
C
L
R1 = 200 Ω
R2 = 390 Ω
0
0
1
2
3
4
5
6
7
8
Number of Outputs Switching
Figure 13
†
Outputs switching in the same direction (t
t
/t
t
PLH compared to PLH PHL to PHL)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
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Arrow/Schweber (408) 441-9700, (510) 490-9477;
Hall-Mark (408) 432-4000; Marshall (408) 942-4600;
Wyle (408) 727-2500; Zeus (408) 629-4789.
COLORADO: Anthem (303) 790-4500; Arrow/Schweber
(303) 799-0258; Hall-Mark (303) 790-1662; Marshall (303)
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CONNECTICUT: Anthem (203) 575-1575; Arrow/Schweber
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Tampa: Hall-Mark (813) 541-7440; Marshall (813)
573-1399.
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(404) 623-4400; Marshall (404) 923-5750.
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(8:00 a.m. – 5:00 p.m. CST)
D0892
1992 Texas Instruments Incorporated
Printed in U.S.A.
SRPS006D
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
FK
J
5962-85155172A
5962-8515517RA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
LIFEBUY
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
LIFEBUY
LIFEBUY
OBSOLETE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
1
1
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-1-220-UNLIM
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
5962-8515517SA
W
FK
J
1
5962-85155182A
LCCC
CDIP
CFP
1
5962-8515518RA
1
5962-8515518SA
W
FK
J
1
5962-85155192A
LCCC
CDIP
CFP
1
5962-8515519RA
1
5962-8515519SA
W
FK
J
1
5962-85155202A
LCCC
CDIP
CFP
1
5962-8515520RA
1
5962-8515520SA
W
FK
J
1
TIBPAL16L8-10MFKB
TIBPAL16L8-10MJB
TIBPAL16L8-10MWB
TIBPAL16L8-7CFN
TIBPAL16L8-7CN
TIBPAL16R4-10MFKB
TIBPAL16R4-10MJB
TIBPAL16R4-10MWB
TIBPAL16R4-7CFN
TIBPAL16R4-7CN
TIBPAL16R6-10MFKB
TIBPAL16R6-10MJB
TIBPAL16R6-10MWB
TIBPAL16R6-7CFN
TIBPAL16R6-7CN
TIBPAL16R8-10MFKB
TIBPAL16R8-10MJB
TIBPAL16R8-10MWB
TIBPAL16R8-7CFN
TIBPAL16R8-7CN
LCCC
CDIP
CFP
1
1
W
FN
N
1
PLCC
PDIP
LCCC
CDIP
CFP
46
20
1
FK
J
1
W
FN
N
1
PLCC
PDIP
LCCC
CDIP
CFP
Call TI
FK
J
1
1
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-1-220-UNLIM
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
W
FN
N
1
PLCC
PDIP
LCCC
CDIP
CFP
46
20
1
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
OBSOLETE
FK
J
1
W
FN
N
1
PLCC
PDIP
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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