TIBPAL20R4-10CNT [TI]
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS; 高性能Impact -X PAL电路
| 型号： | TIBPAL20R4-10CNT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS |
| 文件： | 总24页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
TIBPAL20L8’
JT OR NT PACKAGE
•
High-Performance Operation:
f
f
f
(no feedback)
TIBPAL20R’ . . . 71.4 MHz
(internal feedback)
TIBPAL20R’ . . . 58.8 MHz
(external feedback)
TIBPAL20R’ . . . 55.5 MHz
max
(TOP VIEW)
max
I
I
I
I
I
I
I
I
V
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
1
24
23
22
21
20
19
18
17
16
15
14
13
CC
2
max
3
4
Propagation Delay
5
TIBPAL20’ . . . 10 ns Max
6
•
•
•
Functionally Equivalent, but Faster Than
Existing 24-Pin PLD Circuits
7
8
I
I
I
9
Preload Capability on Output Registers
Simplifies Testing
10
11
12
I
I
GND
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
TIBPAL20L8’
FN PACKAGE
•
Package Options Include Plastic Chip
Carriers in Addition to Plastic and Ceramic
DIPs
(TOP VIEW)
•
•
Security Fuse Prevents Duplication
4
5
3
2
1
28 27 26
25
Dependable Texas Instruments Quality and
Reliability
I
I
I
I/O
I/O
I/O
6
24
23
7
I/O
PORT
S
I
3-STATE
REGISTERED
Q OUTPUTS
DEVICE
8
NC
22 NC
21 I/O
20 I/O
19 I/O
INPUTS O OUTPUTS
9
I
I
I
PAL20L8
PAL20R4
PAL20R6
PAL20R8
14
12
12
12
2
0
0
0
0
6
4
2
0
10
11
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
12 13 14 15 16 17 18
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT-X circuits combine the latest Advanced
NC – No internal connection
Pin assignments in operating mode
Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance
substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions
and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction
in board space.
Alloftheregisteroutputsaresettoalowlevelduringpowerup. Extracircuitryhasbeenprovidedtoallowloading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Copyright 1992, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
TIBPAL20R4’
JT OR NT PACKAGE
TIBPAL20R4’
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
I/O
Q
Q
Q
Q
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25 I/O
I
5
6
7
8
9
I
24
23
Q
Q
I
NC
22 NC
I
I
I
21
20
Q
Q
9
I/O
I/O
I
10
11
10
11
12
I
I
19 I/O
12 13 14 15 16 17 18
GND
OE
TIBPAL20R6’
JT OR NT PACKAGE
TIBPAL20R6’
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
TIBPAL20R8’
JT OR NT PACKAGE
TIBPAL20R8’
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
Q
Q
Q
Q
Q
Q
Q
Q
I
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
NC – No internal connection
Pin assignments in operating mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL20L8-10C, TIBPAL20R4-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
functional block diagrams (positive logic)
TIBPAL20L8’
≥1
&
EN
O
7
40 X 64
O
7
7
7
7
7
7
7
20 x
I/O
I/O
I/O
I/O
I/O
I/O
14
20
20
I
6
6
TIBPAL20R4’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
40 X 64
1D
8
8
8
20 x
12
20
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
20
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
40 X 64
1D
20 x
12
20
20
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL20R8’
OE
EN 2
CLK
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
40 X 64
1D
8
8
8
8
8
8
8
20 x
12
20
20
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL20L8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
logic diagram (positive logic)
1
I
Increment
20
0
4
8
12
16
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
I/O
I/O
I/O
I/O
I/O
O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
10 2520
14
13
I
I
I
I
11
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL20R4-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I/O
I/O
2240
2280
2320
2360
2400
2440
2480
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL20R6-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
20
0
4
8
12
16
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
Q
C1
2240
2280
2320
2360
2400
2440
2480
I/O
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
I = 0
1D
120
160
200
240
Q
C1
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
Q
Q
Q
Q
Q
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
C1
2240
2280
2320
2360
2400
2440
2480
I = 0
1D
C1
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
†
0
7
71.4
High
Low
†
ns
t
w
Pulse duration, clock (see Note 2)
7
†
t
t
Setup time, input or feedback before clock↑
10
ns
su
†
Hold time, input or feedback after clock↑
0
0
ns
h
T
Operating free-air temperature
25
75
°C
A
†
f
, t , t , and t do not apply for TIBPAL20L8’.
clock w su
h
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
–0.8
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –3.2 mA
= 24 mA
2.4
OH
OL
OH
OL
I
0.3
0.5
20
O, Q outputs
‡
I
V
= 5.25 V,
= 5.25 V,
V
= 2.7 V
= 0.4 V
µA
µA
OZH
CC
CC
O
I/O ports
100
–20
–100
0.2
O, Q outputs
I/O ports
‡
I
V
V
O
OZL
I
I
I
I
V
CC
V
CC
V
CC
= 5.25 V,
= 5.25 V,
= 5.25 V,
V = 5.5 V
I
mA
µA
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–0.25
mA
mA
IL
§
V
V
= 5.25 V,
= 5.25 V,
V = 0.5 V
O
–30
–70 –130
210
OS
CC
V = 0,
CC
I
I
mA
CC
Outputs open,
f = 1 MHz,
f = 1 MHz,
f = 1 MHz,
OE = V
IH
C
C
C
V = 2 V
I
7
8
pF
pF
pF
i
V = 2 V
O
o
V = 2 V
CLK
12
clk
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
71.4
MAX
UNIT
without feedback
with internal feedback
(counter configuration)
¶
f
58.8
MHz
max
with external feedback
55.5
3
t
t
I, I/O
O, I/O
R1 = 200 Ω,
R2 = 390 Ω,
8
5
10
8
pd
pd
#
CLK↑
Q
2
ns
ns
t
pd
CLK↑
Feedback input
See Figure 6
7
t
t
t
t
OE↓
OE↑
I, I/O
I, I/O
Q
2
2
3
2
6
6
8
8
10
10
10
10
ns
ns
ns
ns
en
dis
en
dis
Q
O, I/O
O, I/O
||
t
Skew between registered outputs
0.5
ns
sk(o)
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
CC
I/O leakage is the worst case of I
A
and I or I
and I respectively.
OZH IH
OZL
IL
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
¶
#
See section for f
specifications. f
does not apply for TIBPAL20L8’.
max
max
ThisparameterappliestoTIBPAL20R4’andTIBPAL20R6’only(seeFigure4forillustration)andiscalculatedfromthemeasuredf
feedback in the counter configuration.
This parameter is the measurement of the difference between the fastest and slowest t (CLK-to-Q) observed when multiple registered outputs
withinternal
max
||
pd
are switching in the same direction.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 volts and Pin 1 at V , raise Pin 13 to V
.
CC
IL
IHH
Apply either V or V to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 13 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
V
IHH
Pin 13
IL
t
t
d
su
t
t
w
d
V
V
V
V
IH
Pin 1
IL
V
V
IH
OH
OL
Registered I/O
Input
Output
IL
Figure 1. Preload Waveforms
NOTE 3: t = t = t = 100 ns to 1000 ns V
su
= 10.25 V to 10.75 v
d
h
IHH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
occur until all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not
CC
V
CC
5 V
4 V
†
t
pd
(600 ns TYP, 1000 ns MAX)
V
V
OH
Active Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
f
SPECIFICATIONS
max
f
without feedback, see Figure 3
max
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t + t ).
su
h
However, the minimum f
is determined by the minimum clock period (t high + t low).
max
w w
1
1
f
without feedback
Thus,
or
.
max
(t
t )
(t high
w
t low)
w
su
h
CLK
LOGIC
ARRAY
C1
1D
t
+ t
h
su
or
high + t low
t
w
w
Figure 3. f
Without Feedback
max
f
with internal feedback, see Figure 4
max
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
1
f
with internal feedback
Thus,
.
max
(t
t
CLK to FB)
su
pd
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
LOGIC
ARRAY
C1
1D
t
t
CLK-to-FB
pd
su
Figure 4. f
With Internal Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
f
SPECIFICATIONS
max
f
with external feedback, see Figure 5
max
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(t + t CLK-to-Q).
su
pd
1
f
with external feedback
Thus,
.
max
(t
t
CLK to Q)
su
pd
CLK
NEXT DEVICE
LOGIC
ARRAY
C1
1D
t
t
CLK-to-Q
t
su
su
pd
Figure 5. f
With External Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
0.3 V
High-Level
Pulse
3.5 V
0.3 V
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Low-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
3.5 V
0.3 V
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
en
t
pd
t
t
t
dis
pd
V
OH
In-Phase
Output
≈ 3.3 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+0.5 V
OL
V
OL
V
OL
t
pd
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
–0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t ≤ 2 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
8
7
6
5
220
200
180
160
140
120
100
t
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
PLH
V
= 5.25 V
CC
V
CC
= 5 V
4
3
t
t
(CLK to Q)
(CLK to Q)
PHL
PLH
V
CC
= 4.75 V
T
C
= 25 °C
= 50 pF
2
1
A
L
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
0
4.75
0
25
50
75
5
5.25
T
A
– Free-Air Temperature – °C
V
CC
– Supply Voltage – V
Figure 7
Figure 8
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
8
7
6
5
16
V
= 5 V
= 25 °C
CC
T
A
14
12
10
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
t
PLH
4
3
8
6
t
(CLK to Q)
PHL
t
(CLK to Q)
PLH
(CLK to Q)
t
PHL
t
(CLK to Q)
PLH
t
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
PLH
V
C
= 5 V
= 50 pF
2
1
4
2
CC
L
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
0
0
0
25
50
75
0
100
200
300
400
500
600
T
A
– Free-Air Temperature – °C
C
– Load Capacitance – pF
L
Figure 9
Figure 10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
TYPICAL CHARACTERISTICS
POWER DISSIPATION
†
vs
PROPAGATION DELAY TIME
vs
FREQUENCY
8-BIT COUNTER MODE
NUMBER OF OUTPUTS SWITCHING
0.8
0.7
0.6
0.5
1000
900
800
700
600
V
= 5 V
= 25 °C
CC
V
CC
= 5 V
T
A
R1 = 200 Ω
R2 = 390 Ω
C
= 50 pF
L
8-Bit Counter
T
A
= 0 °C
T
= 25 °C
= 80 °C
A
0.4
0.3
T
A
0.2
0.1
0
1
4
10
40
100
2
3
4
5
6
7
8
Number of Outputs Switching
F – Frequency – MHz
Figure 11
Figure 12
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
8
7
6
t
(I, I/O to O, I/O)
PHL
t
(I, I/O to O, I/O)
PLH
5
t
(CLK to Q)
PHL
4
3
t
(CLK to Q)
PLH
2
1
V
= 5 V
= 25 °C
= 50 pF
CC
T
A
C
L
R1 = 200 Ω
R2 = 390 Ω
0
0
1
2
3
4
5
6
7
8
Number of Outputs Switching
Figure 13
†
Outputs switching in the same direction (t
t
/t
t
PLH compared to PLH PHL to PHL)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
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B0892
1992 Texas Instruments Incorporated
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TI North
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Offices
Distributors
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D0892
1992 Texas Instruments Incorporated
SRPS008A
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PDIP
PLCC
PDIP
PLCC
PDIP
PLCC
PDIP
Drawing
TIBPAL20L8-10CFN
TIBPAL20L8-10CNT
TIBPAL20R4-10CFN
TIBPAL20R4-10CNT
TIBPAL20R6-10CFN
TIBPAL20R6-10CNT
TIBPAL20R8-10CFN
TIBPAL20R8-10CNT
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
FN
28
24
28
24
28
24
28
24
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
NT
Call TI
FN
Call TI
NT
Call TI
FN
37
15
37
15
Level-1-220-UNLIM
Level-NC-NC-NC
Level-1-220-UNLIM
Level-NC-NC-NC
ACTIVE
NT
ACTIVE
FN
ACTIVE
NT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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