TIBPAL20R4-5C [TI]
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS; 高性能Impact -X PAL电路型号: | TIBPAL20R4-5C |
厂家: | TEXAS INSTRUMENTS |
描述: | HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS |
文件: | 总35页 (文件大小:433K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
•
High-Performance Operation:
f
f
f
(no feedback)
max
TIBPAL20R’ -5C Series . . . 125 MHz Min
TIBPAL20R’ -7M Series . . . 100 MHz Min
(internal feedback)
TIBPAL20R’ -5C Series . . . 125 MHz Min
TIBPAL20R’ -7M Series . . . 100 MHz Min
(TOP VIEW)
I
I
I
I
I
I
I
I
V
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
max
1
24
23
22
21
20
19
18
17
16
15
14
13
CC
2
3
(external feedback)
max
4
TIBPAL20R’ -5C Series . . . 117 MHz Min
TIBPAL20R’ -7M Series . . . 74 MHz Min
Propagation Delay
5
6
7
TIBPAL20L8-5C Series . . . 5 ns Max
TIBPAL20L8-7M Series . . . 7 ns Max
TIBPAL20R’ -5C Series
(CLK-to-Q) . . . 4 ns Max
TIBPAL20R’ -7M Series
8
I
I
I
9
10
11
12
I
I
GND
(CLK-to-Q) . . . 6.5 ns Max
•
•
•
Functionally Equivalent, but Faster Than,
Existing 24-Pin PLDs
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
Preload Capability on Output Registers
Simplifies Testing
(TOP VIEW)
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
4
3
2
1
28 27 26
25
5
I
I
I
I/O
I/O
I/O
6
24
23
7
Security Fuse Prevents Duplication
8
NC
22 NC
21 I/O
20 I/O
19 I/O
9
I
I
I
I/O
PORT
S
I
3-STATE
REGISTERED
Q OUTPUTS
10
11
DEVICE
INPUTS O OUTPUTS
PAL20L8
PAL20R4
PAL20R6
PAL20R8
14
12
12
12
2
0
0
0
0
6
4
2
0
12 13 14 15 16 17 18
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
NC – No internal connection
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
This document contains information on products in more than one
phase of development. The status of each device is indicated on the
page(s) specifying its electrical characteristics.
Copyright 1992, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL20R4’
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
I/O
Q
Q
Q
Q
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25 I/O
I
5
6
7
8
9
I
24
23
Q
Q
I
NC
22 NC
I
I
I
21
20
Q
Q
9
I/O
I/O
I
10
11
10
11
12
I
I
19 I/O
12 13 14 15 16 17 18
GND
OE
TIBPAL20R6’
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
TIBPAL20R8’
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
Q
Q
Q
Q
Q
Q
Q
Q
I
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
NC – No internal connection
Pin assignments in operating mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL20L8-5C, TIBPAL20R4-5C
TIBPAL20L8-7M, TIBPAL20R4-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
functional block diagrams (positive logic)
TIBPAL20L8’
≥1
&
EN
O
7
40 X 64
O
7
7
7
7
7
7
7
20 x
I/O
I/O
I/O
I/O
I/O
I/O
14
20
20
I
6
6
TIBPAL20R4’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
40 X 64
1D
8
8
8
20 x
12
20
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
20
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
40 X 64
1D
20 x
12
20
20
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL20R8’
OE
EN 2
CLK
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
40 X 64
1D
8
8
8
8
8
8
8
20 x
12
20
20
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL20L8-5C
TIBPAL20L8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
I
Increment
20
0
4
8
12
16
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
I/O
I/O
I/O
I/O
I/O
O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
10 2520
14
13
I
I
I
I
11
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL20R4-5C
TIBPAL20R4-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I/O
I/O
2240
2280
2320
2360
2400
2440
2480
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL20R6-5C
TIBPAL20R6-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
CLK
Increment
20
0
4
8
12
16
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
Q
C1
2240
2280
2320
2360
2400
2440
2480
I/O
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL20R8-5C
TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
I = 0
1D
120
160
200
240
Q
C1
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
Q
Q
Q
Q
Q
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
C1
2240
2280
2320
2360
2400
2440
2480
I = 0
1D
C1
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL20L8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
V
0.8
V
IL
I
I
–3.2
24
mA
mA
°C
OH
OL
Low-level output current
T
A
Operating free-air temperature
0
25
75
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
2.7
–1.5
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
V
OH
OL
OH
I
0.3
0.5
100
V
OL
‡
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
pF
pF
OZH
O
‡
= 0.4 V
–100
100
OZL
O
V = 5.5 V
I
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–250
–130
210
IL
§
V
O
= 0.5 V
–30
–70
OS
V = 0,
I
Outputs open
CC
C
C
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
8.5
10
i
V
O
= 2 V
o
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I/O leakage is the worst case of I
and I or I
and I , respectively.
OZH IH
OZL
IL
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL20L8-5CJT
TIBPAL20L8-5CFN
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
TIBPAL20L8-5CNT
PARAMETER
UNIT
MIN
MAX
MIN
MAX
with up to 4 outputs
switching
I, I/O
I, I/O
O, I/O
O, I/O
1.5
5
1.5
5
t
ns
pd
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
with more than 4
outputs switching
1.5
5
1.5
5.5
t
t
I, I/O
I, I/O
O, I/O
O, I/O
2
2
7
7
2
2
7
7
ns
ns
en
dis
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL20R4-5C, TIBPAL20R6-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
0
4
125
High
Low
ns
t
w
Pulse duration, clock
4
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
4.5
0
ns
ns
°C
su
h
T
0
25
75
A
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL20R4-5C, TIBPAL20R6-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
2.7
–1.5
IK
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
V
OH
OL
OH
I
0.3
0.5
100
V
OL
‡
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
OZH
O
‡
= 0.4 V
–100
100
OZL
O
V = 5.5 V
I
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–250
–130
210
IL
§
V
O
= 0.5 V
–30
–70
OS
V = 0,
I
Outputs open
CC
I
8.5
7.5
10
7
pF
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
C
C
i
CLK/OE
I/O
V
O
= 2 V
pF
o
Q
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL20R4-5CJT
TIBPAL20R4-5CNT
TIBPAL20R6-5CJT
TIBPAL20R6-5CNT
TIBPAL20R4-5CFN
TIBPAL20R6-5CFN
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
without feedback
125
125
¶
f
with internal feedback (counter configuration)
with external feedback
125
125
MHz
max
117
111
t
t
t
t
t
t
t
t
t
t
CLK↑
CLK↑
I, I/O
OE↓
Q
1.5
4
3.5
5
1.5
4.5
3.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pd
pd
pd
en
dis
en
dis
r
Internal feedback
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
I/O
Q
1.5
1.5
1
1.5
1.5
1
6
6
OE↑
Q
6.5
7
7
I, I/O
I, I/O
I/O
I/O
2
2
7
2
7
2
7
1.5
1.5
0.5
1.5
1.5
0.5
f
#
Skew between registered outputs
= 5 V, T = 25°C.
sk(o)
†
‡
§
All typical values are at V
CC
I/O leakage is the worst case of I
A
OZL
and I or I
and I , respectively.
IL
OZH IH
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
¶
#
See ’f
Specification’ near the end of this data sheet.
max
is the skew time between registered outputs.
t
sk(o)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
0
4
125
High
Low
ns
t
w
Pulse duration, clock
4
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
4.5
0
ns
ns
°C
su
h
T
0
25
75
A
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
TIBPAL20R8-5CJT
TIBPAL20R8-5CNT
TIBPAL20R8-5CFN
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
2.7
–1.5
–0.8
2.7
–1.5
V
V
IK
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
2.4
OH
OL
OZH
OZL
I
OH
I
0.3
0.5
100
0.3
0.5
100
V
OL
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
O
= 0.4 V
–100
100
–100
100
O
V = 5.5 V
I
V = 2.7 V
I
25
25
IH
V = 0.4 V
I
–250
–130
210
–250
–130
210
IL
‡
V
O
= 0.5 V
–30
–70
–30
–70
OS
V = 0, Outputs open
I
CC
I
8.5
7.5
10
6.5
5.5
8
pF
pF
C
C
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
i
CLK/OE
V
O
= 2 V
o
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL20R8-5CJT
TIBPAL20R8-5CFN
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
TIBPAL20R8-5CNT
PARAMETER
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
without feedback
125
125
§
f
with internal feedback (counter configuration)
with external feedback
125
125
MHz
max
117
111
with up to 4 outputs
switching
CLK↑
CLK↑
Q
Q
1.5
1.5
4
4
1.5
1.5
4
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
t
pd
ns
with more than 4
outputs switching
4.5
¶
t
t
t
CLK↑
OE↓
OE↑
Internal feedback
3.5
6
3.5
6
ns
ns
ns
pd
en
dis
Q
Q
1.5
1
1.5
1
6.5
7
t
t
t
1.5
1.5
0.5
1.5
1.5
0.5
ns
ns
ns
r
f
#
Skew between outputs
= 5 V, T = 25°C.
sk(o)
†
‡
All typical values are at V
CC
A
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
§
¶
#
See ’f
Specification’ near the end of this data sheet.
max
This parameter is calculated from the measured f
with internal feedback in a counter configuration (see Figure 4 for illustration).
max
is the skew time between registered outputs.
t
sk(o)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
V
V
IL
I
I
mA
mA
OH
OL
Low-level output current
12
†
f
Clock frequency
0
5
5
100
MHz
ns
clock
High
Low
†
t
w
Pulse duration, clock
†
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
7
0
ns
ns
°C
su
†
h
T
–55
25
125
A
†
f
, t , t , and t do not apply to TIBPAL16L8’
clock w su
h
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
–0.8
2.7
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
OH
OL
OH
OL
I
0.25
0.5
20
0, Q outputs
I
V
CC
V
CC
= 5.5 V,
= 5.5 V,
V
= 2.7 V
= 0.4 V
µA
OZH
O
O
I/O ports
100
–20
–250
1
0, Q outputs
I/O ports
I
V
µA
mA
µA
OZL
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 5.5 V
I
I
CC
I/O ports
All others
100
25
V = 2.7 V
I
CC
IH
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 0.4 V
–250
µA
mA
mA
IL
I
‡
I
V
O
= 0.5 V
–30
–70 –130
OS
CC
I
V = GND, OE = V
I
,
IH
Outputs open
220
I
8.5
7.5
10
pF
pF
C
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
i
CLK/OE
C
V
O
= 2 V
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITION
MIN
100
100
MAX
UNIT
without feedback
with internal feedback
(counter configuration)
§
f
MHz
max
with external feedback
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 8
74
1
t
t
t
t
t
t
I, I/O
O, I/O
Q
7
7
ns
ns
ns
ns
ns
ns
pd
pd
en
dis
en
dis
CLK
OE↓
OE↑
I, I/O
I, I/O
1
Q
1
8
Q
1
10
9
O, I/O
O, I/O
1
1
10
§
See’f
Specification’neartheendofthisdatasheet.f
max
doesnotapplyforTIBPAL20L8′. f
specifications section.
withexternalfeedbackisnotproductiontested
max
max
and is calculated from the equation found in the f
max
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
asynchronous preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 volts and Pin 1 at V , raise Pin 13 to V
.
CC
IL
IHH
Apply either V or V to the output corresponding to the register to be preloaded.
Lower Pin 13 to 5 V.
Remove output voltage, then lower Pin 13 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
IHH
Pin 13
5 V
V
IL
t
t
+ t
t
d
d
su
h
V
V
V
OH
IH
Registered Output
Input
Output
V
OL
IL
Figure 1. Asynchronous Preload Waveforms
NOTE 3: t = t = t = 100 ns to 1000 ns, V
su IHH
= 10.25 V to 10.75 V
d
h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
power-up reset, see Figure 2
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
occur until all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not
CC
V
CC
5 V
4 V
†
t
pd
(600 ns typ, 1000 ns MAX)
V
V
OH
Active Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
Clock
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
f
SPECIFICATIONS
max
f
without feedback, see Figure 3
max
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t + t ).
su
h
However, the minimum fmax is determined by the minimum clock period (t high + t low).
w
w
1
1
f
without feedback
Thus,
or
.
max
(t
t )
(t high
w
t low)
w
su
h
CLK
Logic
Array
C1
1D
t
+ t
h
su
or
high + t low
t
w
w
Figure 3. f
Without Feedback
max
f
with internal feedback, see Figure 4
max
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
1
f
with internal feedback
Thus,
.
max
(t
t
CLK to FB)
su
pd
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
C1
1D
t
t
CLK-to-FB
pd
su
Figure 4. f
With Internal Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
f
SPECIFICATIONS
max
f
with external feedback, see Figure 5
max
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(t + t CLK-to-Q).
su
pd
1
f
with external feedback
Thus,
.
max
(t
t
CLK to Q)
su
pd
CLK
Next Device
Logic
Array
C1
1D
t
t
CLK-to-Q
t
su
su
pd
Figure 5. f
With External Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
THERMAL INFORMATION
thermal management of the TIBPAL20R8-5C
Thermal management of the TIBPAL20R8-5CNT and TIBPAL20R8-5CFN is necessary when operating at
certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system
application will determine the appropriate level of management.
Determining the level of thermal management is based on factors such as power dissipation (P ), ambient
D
temperature (T ), and transverse airflow (FPM). Figures 6 (a) and 6 (b) show the relationship between ambient
A
temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be
determined at a particular ambient temperature and device power dissipation level in order to ensure the device
specifications.
Figure 7 illustrates how power dissipation varies as a function of frequency and the number of outputs switching
simultaneously. It should be noted that all outputs are fully loaded (C = 50 pF). Since the condition of eight fully
L
loaded outputs represents the worst-case condition, each application must be evaluated accordingly.
MINIMUM TRANSVERSE AIR FLOW
MINIMUM TRANSVERSE AIR FLOW
vs
vs
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE
1000
800
1000
800
P
P
P
= 1.6 W
= 1.4 W
= 1.2 W
D
D
P
= 1.6 W
= 1.4 W
= 1.2 W
600
600
D
D
P
P
D
D
P
= 1 W
= 0.8 W
D
P
= 1 W
= 0.8 W
D
P
D
P
D
P
D
P
D
400
200
0
400
200
0
= 0.6 W
= 0.6 W
0
0
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
T
A
– Ambient Temperature – °C
T – Ambient Temperature – °C
A
(a) TIBPAL20-5CNT
(b) TIBPAL20R8-5CFN
Figure 6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
20
TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
THERMAL INFORMATION
POWER DISSIPATION
vs
FREQUENCY
1800
1600
1400
1200
1000
800
V
= 5 V
= 25 °C
= 50 pF
CC
T
A
C
L
8 Outputs Switching
7 Outputs Switching
6 Outputs Switching
5 Outputs Switching
4 Outputs Switching
3 Outputs Switching
2 Outputs Switching
1 Output Switching
600
1
2
4
10
20
40
100 200
f – Frequency – MHz
Figure 7
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21
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
3 V
0
1.5 V
1.5 V 1.5 V
High-Level
Timing
Input
Pulse
t
t
w
h
t
su
3 V
0
Low-Level
Pulse
3 V
1.5 V
1.5 V
Data
Input
1.5 V 1.5 V
0
(see Note B)
(see Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
3 V
0
Output
Control
(low-level
enabling)
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
0
pd
t
pd
(see Note B)
t
en
V
OH
t
80 %
20 %
dis
1.5 V
1.5 V
In-Phase
Output
≈ 2.7 V
OL
V
OL
t
t
f
r
Waveform 1
S1 Closed
(see Note C)
1.5 V
V
+ 0.5 V
t
t
pd
pd
V
OL
V
OH
20 %
80 %
t
Out-of-Phase
Output
(see Note D)
dis
1.5 V
1.5 V
t
en
V
OL
V
V
≈ 0 V
OH
t
f
t
r
Waveform 2
S1 Open
(see Note C)
1.5 V
– 0.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
OH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. All input pulses have the following characteristics: For C suffix, PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%; For M suffix,
r
f
PRR ≤ 10 MHz, t = t ≤ 2 ns, duty cycle = 50%
r
f
C. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 8. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
22
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
metastable characteristics of TIBPAL20R4-5C, TIBPAL20R6-5C, and TIBPAL20R8-5C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between V and V . This metastable condition
IL
IH
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and ∆t for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (∆t) after SCLK. The exclusive OR gate detects
the occurrence of a failure and increments the failure counter.
DUT
Noise
Generator
V
IH
Comparator
MTBF
Counter
Data in
1D
1D
C1
1D
C1
+
V
IL
Comparator
SCLK
C1
1D
C1
SCLK + ∆t
Figure 9. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
Data
SCLK
SCLK + ∆t
∆t
∆t
Time (sec)
# Failures
MTBF
t
= ∆t – CLK to Q (max)
rec
Figure 10. Timing Diagram
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
By using the described test circuit, MTBF can be determined for several different values of ∆t (see Figure 9).
Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop.
Figure 11 shows the results for the TIBPAL20’-5C operating at 1 MHz.
9
8
7
6
5
4
3
2
1
10
10
10
10
10
10
10
10
10
10 yr
1 yr
1 mo
1 wk
1 day
1 hr
1 min
10 s
f
f
= 1 MHz
clk
= 500 kHz
data
0
10
20
30
40
50
60
70
∆t (ns)
Figure 11. Metastable Characteristics
From the data taken in the above experiment, an equation can be derived for the metastable characteristics at
other clock frequencies.
1
(
C2 x t)
The metastable equation:
f
x f
x C1 e
SCLK
data
MTBF
The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,
–3
these constants can be solved for: C1 = 4.37 X 10 and C2 = 2.01
Therefore
1
3
( 2.01 x t)
f
x f
x 4.37 x 10
e
SCLK
data
MTBF
definition of variables
DUT (Device Under Test): The DUT is a 5-ns registered PLD programmed with the equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a
violation of the device specifications.
f
f
(system clock frequency): Actual clock frequency for the DUT.
SCLK
(data frequency): Actual data frequency for a specified input to the DUT.
data
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
t
(metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given
rec
MTBF failure rate. t
= ∆t – t (CLK to Q, max)
rec
pd
∆t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAL20R4/R6/R8-5C series. For
additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI
Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS
Circuits.’’
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
24
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
20
15
10
5
0
–10
–20
–30
V
T
A
= 5 V
= 25 °C
V
T
A
= 5 V
= 25 °C
CC
CC
–40
–50
0
–60
–70
–80
–90
–5
–10
–15
–100
–20
–0.8 –0.6 –0.4 –0.2
0
0.2
0.4 0.6
0.8
0
0.5
1
1.5
2
2.5
3
V
OL
– Low-Level Output Voltage – V
V
OH
– High-Level Output Voltage – V
Figure 12
Figure 13
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
220
200
180
160
140
120
V
V
= 5.5 V
= 5.25 V
CC
CC
V
V
V
= 4.5 V
= 4.75 V
= 5 V
CC
CC
CC
100
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
Figure 14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
PROPAGATION DELAY TIME
FREQUENCY
vs
8-BIT COUNTER MODE
SUPPLY VOLTAGE
6
5
1100
1000
900
T
C
= 25 °C
= 50 pF
A
L
V
= 5 V
CC
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
T
A
= 80 °C
4
3
t
(I, I/O to O, I/O)
PHL
T
A
= 25 °C
t
(I, I/O to O, I/O)
PLH
T
= 0 °C
A
t
(CLK to Q)
2
1
PLH
T
A
= 0 °C
T
A
= 80 °C
t
(CLK to Q)
PHL
800
700
0
1
2
4
10
20
40
100 200
4.5
4.75
V
5
5.25
5.5
– Supply Voltage – V
f – Frequency – MHz
CC
Figure 15
Figure 16
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
16
14
12
10
6
5
V
C
= 5 V
= 50 pF
V
T
= 5 V
= 25 °C
CC
L
CC
A
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
t
(I, I/O to O, I/O)
4
3
PHL
t
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
PLH
8
6
t
(CLK to Q)
PHL
2
1
t
(CLK to Q)
PLH
t
(CLK to Q)
PHL
50
4
2
t
(I, I/O to O, I/O)
PLH
t
(CLK to Q)
PLH
0
0
–75 –50 –25
0
25
75 100 125
0
100
200
300
400
500
600
T
A
– Free-Air Temperature – °C
C
– Load Capacitance – pF
L
Figure 17
Figure 18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
26
TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
SKEW BETWEEN OUTPUTS
PROPAGATION DELAY TIME
vs
vs
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
0.8
0.7
0.6
0.5
6
5
V
T
= 5 V
= 25 °C
V
T
C
= 5 V
= 25 °C
= 50 pF
CC
A
CC
A
L
R1 = 200 Ω
R2 = 200 Ω
C
R1 = 200 Ω
R2 = 200 Ω
= 50 pF
L
8-Bit Counter
4
3
2
0.4
0.3
Outputs Switching in the Opposite Direction
= t
= t
= t
= t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
(CLK to Q)
PHL
PLH
PHL
PLH
0.2
0.1
1
0
Outputs Switching in the Same Direction
(CLK to Q)
0
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching
Number of Outputs Switching
Figure 19
Figure 20
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D0892
1992 Texas Instruments Incorporated
SRPS010F
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-87671193A
5962-8767119KA
ACTIVE
ACTIVE
FK
28
24
24
28
24
28
24
28
24
28
24
28
24
24
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-1-220-UNLIM
Level-NC-NC-NC
Call TI
W
5962-8767119LA
ACTIVE
CDIP
PLCC
PDIP
PLCC
PDIP
PLCC
PDIP
PLCC
PDIP
LCCC
CDIP
CFP
JT
1
TIBPAL20L8-5CFN
TIBPAL20L8-5CNT
TIBPAL20R4-5CFN
TIBPAL20R4-5CNT
TIBPAL20R6-5CFN
TIBPAL20R6-5CNT
TIBPAL20R8-5CFN
TIBPAL20R8-5CNT
TIBPAL20R8-7MFKB
TIBPAL20R8-7MJTB
TIBPAL20R8-7MWB
ACTIVE
FN
NT
FN
NT
FN
NT
FN
NT
FK
37
15
ACTIVE
OBSOLETE
OBSOLETE
ACTIVE
Call TI
37
15
Level-1-220-UNLIM
Level-NC-NC-NC
Call TI
ACTIVE
OBSOLETE
OBSOLETE
ACTIVE
Call TI
1
1
1
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
JT
ACTIVE
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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