TIC12400QDCPRQ1_技术文档

TIC12400-Q1

ZHCSGP5C –AUGUST 2017 –REVISED FEBRUARY 2022

适用于汽车系统，具有集成式ADC 和可调湿性电流的

TIC12400-Q1 24 路输入多开关检测接口(MSDI)

1 特性

3 说明

• 符合汽车应用要求

• 具有符合AEC-Q100 标准的下列特性：

TIC12400-Q1 是一款先进的多开关检测接口 (MSDI)，

用于检测 12V 汽车系统中的外部开关状态。

TIC12400-Q1 配有集成的 10 位 ADC，用于对多位模

拟开关进行监控，并采用比较器以独立于 MCU 的方式

对数字开关进行监控。可为 ADC 和比较器设定检测阈

值，从而支持各种开关拓扑和系统非理想特性。该器件

监控多达 24 路直接开关输入，并可配置其中 10 路输

入以监控接地或连接到电池的开关。可为每路输入设定

6 种独特的湿性电流设置，从而支持不同的应用场景。

该器件支持所有开关输入的唤醒操作，因此无需持续使

MCU 保持活动状态，进而可降低系统功耗。

TIC12400-Q1 还提供集成故障检测、ESD 保护和诊断

功能，从而提高系统稳健性。TIC12400-Q1 支持 2 种

工作模式：连续模式和轮询模式。连续模式下将连续提

供湿性电流。轮询模式下将根据可编程计时器来定期接

通湿性电流以对输入状态进行采样，从而显著降低系统

功耗。

– 器件温度等级1：–40°C 至125°C 的工作环境

温度范围

– 器件HBM ESD 分类等级H2

– 器件CDM ESD 分类等级C4B

• 提供功能安全

– 有助于进行功能安全系统设计的文档

• 旨在支持12V 汽车系统，并提供过压和欠压警告

• 监控多达24 路直接开关输入，并可配置其中10 路

输入以监控接地或连接到电池的开关

• 开关输入可承受高达40V 的电压（负载突降条件）

和低至−24V 的电压（反极性条件）

• 6 种可配置的湿性电流设置：

（0mA、1mA、2mA、5mA、10mA 和15mA）

• 适用于多位模拟开关监控的10 位集成ADC

• 适用于数字开关监控并具有4 个可编程阈值的集成

比较器

器件信息

封装⁽¹⁾

• 轮询模式下的超低工作电流：

封装尺寸（标称值）

器件型号

68μA 典型值（t_POLL= 64ms，t_{POLL_ACT}

128μs，

=

TIC12400-Q1

TSSOP (38)

9.70mm × 4.40mm

全部24 路输入均有效，比较器模式，所有开关均

打开）

• 使用3.3V/5V 串行外设接口(SPI) 协议直接与MCU

对接

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

VBAT

Voltage

Regulator

GND

37

38

• 可产生中断来支持所有输入的唤醒操作

• 集成电池和温度传感

VS

VDD 19

VDD

/INT

IN0

IN1

IN2

13

14

25

/INT

/CS

24

15

/CS

• 采用适当的外部组件根据ISO-10605 在输入引脚上

实现±8kV 接触放电ESD 保护

• 38 引脚TSSOP 封装

IN9

33

MCU

SCLK 16

SCLK

MOSI

MISO

GPIO

SI

17

SO 18

IN10

IN11

IN12

34

35

36

TIC12400-Q1

RESET 21

20

CAP_A

CAP_D 23

2 应用

IN23

12

22

9

CAP_PRE

• 车身控制模块和网关

• 汽车照明

AGND

EP

DGND 28

Copyright

©

2016, Texas Instruments Incorporated

• 制热和制冷

• 电动座椅

• 后视镜

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCPS260

TIC12400-Q1

ZHCSGP5C –AUGUST 2017 –REVISED FEBRUARY 2022

www.ti.com.cn

Table of Contents

8.6 Register Maps...........................................................48

8.7 Programming Guidelines.........................................115

9 Application Information Disclaimer........................... 119

9.1 Application Information............................................119

9.2 Using TIC12400-Q1 in a 12 V Automotive System.119

9.3 Resistor-coded Switches Detection in

Automotive Body Control Module..............................121

10 Power Supply Recommendations............................125

11 Layout.........................................................................126

11.1 Layout Guidelines................................................. 126

11.2 Layout Example.................................................... 127

12 Device and Documentation Support........................128

12.1 接收文档更新通知................................................. 128

12.2 支持资源................................................................128

12.3 Trademarks...........................................................128

12.4 Electrostatic Discharge Caution............................128

12.5 术语表................................................................... 128

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Timing Requirements................................................10

6.7 Typical Characteristics.............................................. 11

7 Parameter Measurement Information..........................13

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................16

8.4 Device Functional Modes..........................................29

8.5 Programming............................................................ 45

Information.................................................................. 128

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (February 2020) to Revision C (February 2022)

Page

• 添加了特性“提供功能安全”.............................................................................................................................1

• 将提到的旧术语实例全部更改为控制器和响应器................................................................................................ 1

Changes from Revision A (September 2017) to Revision B (February 2020)

Page

• Added ADC error for 0 mA current setting in 节6.5 table...................................................................................6

• Added RIN_SC spec for V_Sabove 7 V in 节6.5 table........................................................................................6

• Added RIN_COMP spec for V_Sabove 7 V in 节6.5 table..................................................................................6

• Changed WC_CFG0 for CSO and CSI in matrix mode in 表8-59 .................................................................115

Changes from Revision * (August 2017) to Revision A (September 2017)

Page

• Changed the I_WETTvalue in the Electrical Characteristics table.........................................................................6

• Changed From: 4.5 V ≤V_S≤5 V To: 4.5 V ≤V_S< 5.5 V in 图6-6 ..............................................................11

• Changed From: 4.5 V ≤V_S≤35 V To: 5.5 V ≤V_S≤35 V in 图6-7 ........................................................... 11

• Changed the Microcontroller Wake-Up section, and 图8-9 .............................................................................24

• Changed 表9-5 ............................................................................................................................................. 123

• Changed text in list item 2 From: current ranging between 4.3 mA and 5.6 mA. To: current ranging between

4.5 mA and 5.5 mA (for V_S–IN_X≥3 V condition). .....................................................................................123

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5 Pin Configuration and Functions

IN13

1

2

3

38

VS

37

36

IN14

IN15

VS

IN12

35

34

IN16

IN17

4

5

IN11

IN10

6

7

33

32

IN18

IN19

IN9

IN8

IN20

AGND

IN21

8

9

31

30

IN7

IN6

IN5

Exposed

Pad

10

11

29

28

IN22

IN23

DGND

IN4

12

13

27

26

IN0

IN1

IN3

IN2

14

15

25

24

/CS

/INT

16

17

18

19

23

22

21

20

SCLK

CAP_D

SI

CAP_PRE

RESET

SO

VDD

CAP_A

Not to Scale

图5-1. DCP (TSSOP) Package, 38-Pin, Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

1

NAME

IN13

IN14

IN15

IN16

IN17

IN18

IN19

IN20

AGND

IN21

IN22

IN23

IN0

I/O

P

Ground switch monitoring input with current source.

Ground for analog circuitry.

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

I/O

I

Ground switch monitoring input with current source.

Ground/V_BATswitch monitoring input with configurable current sink or source.

Active-low input. Chip select from the controller for the SPI Interface.

Serial clock output from the controller for the SPI Interface.

Serial data input for the SPI Interface.

IN1

CS

SCLK

SI

I

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Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

18

SO

O

P

Serial data output for the SPI Interface.

3.3 V to 5.0 V logic supply for the SPI communication. The SPI I/Os are not fail-safe

protected: VDD needs to be present during any SPI traffic to avoid excessive leakage

currents and corrupted SPI I/O logic levels.

19

20

V_DD

CAP_A

I/O

External capacitor connection for the analog LDO. Use capacitance value of 100 nF.

Keep RESET low for normal operation and drive RESET high and release it to perform a

hardware reset of the device. The RESET pin is connected to ground via a 1MΩ pull-down

resistor. If not used, the RESET pin shall be grounded to avoid any accidental device reset

due to coupled noise onto this pin.

21

RESET

I

22

23

CAP_Pre

CAP_D

I/O

External capacitor connection for the pre-regulator. Use capacitance value of 1 μF.

External capacitor connection for the digital LDO. Use capacitance value of 100 nF.

Open drain output. Pulled low (internally) upon change of state on the input or occurrence of

a special event.

24

INT

O

25

26

27

28

29

30

31

32

33

34

35

36

37

38

IN2

IN3

I/O

P

Ground/V_BATswitch monitoring input with configurable current sink or source.

Ground for digital circuitry.

IN4

DGND

IN5

I/O

P

Ground/V_BATswitch monitoring input with configurable current sink or source.

Ground switch monitoring input with current source.

IN6

IN7

IN8

IN9

IN10

IN11

IN12

V_S

Ground switch monitoring input with current source.

Power supply input pin.

V_S

P

Power supply input pin.

Exposed Pad. The exposed pad is not electrically connected to AGND or DGND. Connect

EP to the board ground to achieve rated thermal and ESD performance.

---

EP

P

(1) I = input, O = output, I/O = input and output, P = power.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).⁽¹⁾

MIN

-0.3

-24

MAX

40⁽²⁾

6

UNIT

V

V_S, INT

V_DD, SCLK, SI, SO, CS, RESET

V

IN0- IN23

Input voltage

40⁽²⁾

5.5

2

V

CAP_Pre

-0.3

-40

V

CAP_A

CAP_D

V

Operating junction temperature, T_J

Storage temperature, T_stg

150

155

°C

-55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Tested for load dump and jump start conditions with nominal operating voltage no greater than 16 V for the life of a 12-V automotive

system. Refer to 节9.2 for more details.

6.2 ESD Ratings

VALUE

±2000

±4000

±500

UNIT

All pins

Pins IN0-IN23⁽²⁾

Human-body model (HBM), per AEC Q100-002⁽¹⁾

All pins

Charged-device model (CDM), per AEC Q100-011

Contact discharge, un-powered, per ISO- 10605:

Corner pins (pin 1, 19, 20 and 38)

±750

•

External components: capacitor = 15 nF; resistor = 10 Ω

Pins IN0-IN23

±8000

•

ESD generator parameters: storage capacitance = 150 pF; discharge

V_(ESD)

Electrostatic discharge

V

resistance = 330 Ωor 2000 Ω

Contact discharge, powered-up, per ISO- 10605:

•

External components: capacitor = 15 nF; resistor = 33 Ω

Pins IN0-IN23

±8000

•

ESD generator parameters: storage capacitance = 150 pF or 330pF;

discharge resistance = 330 Ωor 2000 Ω

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) ±4-kV rating on pins IN0-IN23 are stressed with respect to GND (with AGND, DGND, and EP tied together).

6.3 Recommended Operating Conditions

Over operating free-air temperature range and V_S= 12 V (unless otherwise noted).

MIN

4.5

3.0

0

NOM

MAX

35 ⁽²⁾

5.5

UNIT

V

V_S

Power supply voltage

Logic supply voltage

V_DD

V

V_/INT

V_INX

V_RESET

V_{SPI_IO}

f_SPI

INT pin voltage

35⁽²⁾

5.5

V

IN0 to IN23 input voltage

RESET pin voltage

0

V

0

V

SPI input/output logic level

SPI communication frequency

Operating free-air temperature

0

V_DD

4M

V

20⁽¹⁾

-40

Hz

°C

T_A

125

(1) Lowest frequency characterized.

(2) Tested for load dump and jump start conditions with nominal operating voltage no greater than 16-V for the life of a 12-V automotive

system. Refer to 节9.2 for more details.

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6.4 Thermal Information

TIC12400-Q1

DCP (TSSOP)

38 PINS

33.6

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18.4

15.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JT

15.0

ψ_JB

R_θJC(bot)

1.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Over operating free-air temperature range, V_S= 4.5 V to 35 V, and V_DD= 3 V to 5.5 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

Continuous mode V_SContinuous mode, I_WETT= 10 mA, all switches open, no active ADC

power supply current conversion or comparator comparison, no unserviced interrupt

I_{S_CONT}

5.6

7

mA

I_{S_POLL_COMP_25}

I_{S_POLL_COMP_85}

I_{S_POLL_COMP}

I_{S_POLL_ADC_25}

I_{S_POLL_ADC_85}

I_{S_POLL_ADC}

T_A= 25°

68

75

100

110

170

105

120

180

µA

Polling mode V_S

power supply average

current in comparator

mode

Polling mode, t_POLL= 64 ms, t_POLL_ACT= 128

µs, all 24 channels active and configured to

T_A= -40° to 85°C

T_A= -40° to 125°C

T_A= 25°

comparator mode, all switches open, I_WETT

10 mA, no unserviced interrupt

=

Polling mode, t_POLL= 64 ms, t_{POLL_ACT}= 128

µs, all 24 channels active and configured to

ADC mode, all switches open, I_WETT= 10 mA,

no unserviced interrupt

Polling mode V_S

power supply average T_A= -40° to 85°C

current in ADC mode

T_A= -40° to 125°C

Reset mode V_Spower

supply current

I_{S_RESET}

I_{S_IDLE_25}

I_{S_IDLE_85}

I_{S_IDLE}

Reset mode, V_RESET= V_DD. V_S= 12 V, all switches open, T_A=25°C

12

50

1.5

17

75

µA

V

TRIGGER bit in CONFIG register = logic 0, T_A= 25°C, no

unserviced interrupt

V_Spower supply

average current in

idle state

TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 85°C, no

unserviced interrupt

95

TRIGGER bit in CONFIG register = logic 0, T_A= -40°C to 125°C, no

unserviced interrupt

145

10

Logic supply current

from V_DD

I_DD

SCLK = SI = 0 V, CS = INT = V_DD, no SPI communication

Threshold for rising V_Sfrom device OFF condition resulting in INT

pin assertion and a flagged POR bit in the INT_STAT register

V_{POR_R}

V_{POR_F}

V_{OV_R}

3.85

1.95

35

4.5

2.8

40

Power on reset (POR)

voltage for V_S

Threshold for falling V_Sfrom device normal operation to reset mode

and loss of SPI communication

V

Over-voltage (OV)

condition for V_S

Threshold for rising V_Sfrom device normal operation resulting in

INT pin assertion and a flagged OV bit in the INT_STAT register

V

Over-voltage (OV)

condition hysteresis

for V_S

V_{OV_HYST}

1

3.5

V

Threshold for rising V_Sfrom under-voltage condition resulting in INT

pin assertion and a flagged UV bit in the INT_STAT register

V_{UV_R}

V_{UV_F}

3.85

3.7

4.5

4.4

V

Under-voltage (UV)

condition for V_S

Threshold for falling V_Sfrom under-voltage condition resulting in

INT pin assertion and a flagged UV bit in the INT_STAT register

Under-voltage (UV)

condition hysteresis

for V_S

V_{UV_HYST}

75

275

mV

(1)

V_{DD_F}

Threshold for falling V_DDresulting in loss of SPI communication

2.5

50

2.9

V

Valid V_DDvoltage

hysteresis

V_{DD_HYST}

150

mV

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6.5 Electrical Characteristics (continued)

Over operating free-air temperature range, V_S= 4.5 V to 35 V, and V_DD= 3 V to 5.5 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤100Ω , MINIMUM RESISTANCE

VALUE WITH SWITCH OPEN ≥5000 Ω)

1 mA setting

2 mA setting

0.84

1.71

2.39

4.3

1

2

1.14

2.32

5.5

4.5 V ≤V_S≤35 V

4.5 V ≤V_S< 5 V

5 V ≤V_S≤35 V

4.5 V ≤V_S< 6 V

6 V ≤V_S≤35 V

4.5 V ≤V_S< 6.5 V

6.5 V ≤V_S≤35 V

5 mA setting

10 mA setting

15 mA setting

Wetting current

accuracy for CSO

(switch closed)

5

5.6

I_WETT(CSO)

mA

2.4

11

8.4

10

11.4

16.5

17

2.4

12.5

0.75

1.6

15

1.1

1 mA setting

2 mA setting

5 mA setting

10 mA setting

2.05

3.3

2.2

4.5 V ≤V_S≤35 V

Wetting current

accuracy for CSI

(switch closed)

4.3

5.6

7.1

I_WETT(CSI)

mA

9.2

11.5

16.5

13.4

19.2

11

4.5 V ≤V_S< 6 V

6 V ≤V_S≤35 V

15 mA setting

10 mA setting,

13.7

1.7

Voltage drop from IN_x

pin to AGND across

CSI (switch open)

R

_SW= 5 kΩ

15 mA setting,

_SW= 5 kΩ

V_{CSI_DROP_OPEN}

V

4.5 V ≤V_S≤35 V

R

2 mA setting, I_IN= 1

mA (4.5V ≤VS ≤

35V)

1.2

1.3

1.5

V

5 mA setting, I_IN

=

1mA or 2 mA

Voltage drop from INx

pin to ground across

CSI (switch closed)

V_{CSI_DROP_CLOSED}

4.5 V ≤V_S≤35 V

10 mA setting, I_IN

1 mA, 2 mA, or 5

mA

=

15 mA setting, I_IN

=

1 mA, 2 mA, 5 mA,

or 10 mA

2.1

V

WETTING CURRENT ACCURACY (ANALOG SWITCHES)

1 mA setting

2 mA setting

0.88

1.8

4.3

4.5

9

1

2

1.13

2.25

5.5

4.5 V ≤V_S≤35 V, V_S–V_INX≥2.5 V

5

5.5 V ≤V_S≤35 V, V_S–V_INX≥2.5 V

5.5 V ≤V_S≤35 V, V_S–V_INX≥3 V

6 V ≤V_S≤35 V, V_S–V_INX≥4 V

6.5 V ≤V_S≤35 V, V_S–V_INX≥5 V

Wetting current

accuracy

5 mA setting

I_WETT

mA

5

5.5

10 mA setting

15 mA setting

10

15

11

12.5

16.5

LEAKAGE CURRENTS

I_{IN_LEAK_OFF}

-4

5.3

0.5

0 V ≤V_INx≤V_S, channel disabled (EN_INx register bit= logic 0)

Leakage current at

input INx when

channel is disabled

µA

0 V ≤V_INx≤V_S, channel disabled (EN_INx register bit= logic 0),

T_A= 25°C

I_{IN_LEAK_OFF_25}

-0.5

Leakage current at

input INx when

wetting current setting

is 0mA

µA

I_{IN_LEAK_0mA}

-110

-5

110

0 V ≤V_INx≤6 V, 6 V ≤V_S≤35 V , I_WETTsetting = 0 mA

Leakage current at

input INx under loss

of GND condition

V_S= 24 V, 0 V ≤V_INx≤24 V, all grounds (AGND, DGND, and EP)

I_{IN_LEAK_LOSS_OF_GND}

µA

= 24 V, V_DDshorted to the grounds⁽¹⁾

Leakage current at

input INx under loss

of V_Scondition

I_{IN_LEAK_LOSS_OF_VS}

5

0 V ≤V_INx≤24 V, V_Sshorted to the grounds = 0 V, V_DD= 0 V

LOGIC LEVELS

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6.5 Electrical Characteristics (continued)

Over operating free-air temperature range, V_S= 4.5 V to 35 V, and V_DD= 3 V to 5.5 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.35

UNIT

I_/INT= 2 mA

I_/INT= 4 mA

INT output low

voltage

V_{/INT_L}

V

0.6

V_{SO_L}

V_{SO_H}

SO output low voltage I_SO= 2 mA

0.2V_DD

V

SO output high

I_SO= -2 mA

voltage

0.8V_DD

0.7V_DD

1.6

SI, SCLK, and CS

input low voltage

V_{IN_L}

0.3V_DD

V

SI, SCLK, and CS

input high voltage

V_{IN_H}

RESET input low

voltage

V_{RESET_L}

V_{RESET_H}

0.8

RESET input high

voltage

R_{RESET_25}

R_RESET

V_RESET= 0 to 5.5 V, T_A=25°C

0.85

0.2

1.25

1.7

2.1

RESET pin internal

pull-down resistor

MΩ

V_RESET= 0 to 5.5 V, T_A= –40° to 125°C

SWITCH INPUT AND V_SMEASUREMENT CONVERSION PARAMETERS

RES

Resolution

10

–1

Bits

LSB

V_OFFSET

V_FSE

ADC Offset error

0 mA setting

0

1

ADC Full-scale error 0 mA setting

10

–10

4.5 V ≤V_S≤35 V, 100 Ω resistance to

12

42

17

51

26

64

ground at INx

4.5 V ≤V_S≤35 V, 300 Ω resistance to

ground at INx

1 mA setting

LSB

4.5 V ≤V_S≤35 V, 600 Ω resistance to

87

102

34

122

45

ground at INx

4.5 V ≤V_S≤35 V, 100 Ω resistance to

ground at INx

28

4.5 V ≤V_S≤35 V, 300 Ω resistance to

ground at INx

2 mA setting

89

102

205

85

122

236

105

296

620

202

486

823

301

582

879

4.5 V ≤V_S≤35 V, 600 Ω resistance to

ground at INx

181

72

5 V ≤V_S≤35 V, 100 Ω resistance to ground

at INx

Switch input

conversion output

5 V ≤V_S≤35 V, 300 Ω resistance to ground

at INx

OUT_SW

5 mA setting

223

393

142

333

430

166

325

450

256

512

171

427

683

256

512

768

5 V ≤V_S≤35 V, 600 Ω resistance to ground

at INx

6 V ≤V_S≤35 V, 100 Ω resistance to ground

at INx

6 V ≤V_S≤35 V, 250 Ω resistance to ground

at INx

10 mA setting

6 V ≤V_S≤35 V, 400 Ω resistance to ground

at INx

6.5 V ≤V_S≤35 V, 100 Ω resistance to

ground at INx

6.5 V ≤V_S≤35 V, 200 Ω resistance to

ground at INx

15 mA setting

6.5 V ≤V_S≤35 V, 300 Ω resistance to

ground at INx

V_Smeasurement

output tolerance to

full-scale range

±2%

V_Smeasurements (V_S≥4.5 V), VS_RATIO= 0 in register CONFIG

V_Smeasurements (V_S≥4.5 V), VS_RATIO= 1 in register CONFIG

INx measurements

OUT_VS

6

9

V_FSR

Input full-scale range V_Smeasurements (V_S≥4.5 V), VS_RATIO= 0 in register CONFIG

V_Smeasurements (V_S≥4.5 V), VS_RATIO= 1 in register CONFIG

V

30

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6.5 Electrical Characteristics (continued)

Over operating free-air temperature range, V_S= 4.5 V to 35 V, and V_DD= 3 V to 5.5 V (unless otherwise noted).

PARAMETER

Input resistance

ADC Equivalent input

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INx measurements

240

kΩ

R_{IN, SC}

resistance, V_Sabove Input switch measurement, I_LOAD= 30 µA

7 V

135

234

356

kΩ

THRES_COMP Setting = 2 V

88

85

73

68

130

126

105

95

172

170

137

124

ADC Equivalent input

resistance, V_Sabove

THRES_COMP Setting = 3 V

7 V

THRES_COMP Setting = 2.7 V

R_{IN, COMP}

THRES_COMP Setting = 4 V

INx measurements

2

-

V_Smeasurements (V_S≥4.5 V), VS_RATIO = 0 in register

3

Input voltage divider

factor⁽¹⁾

R_RATIO

CONFIG

V_Smeasurements (V_S≥4.5 V), VS_RATIO = 1 in register

CONFIG

10

-

COMPARATOR PARAMETERS

Comparator threshold

for 2 V

V_{TH_ COMP_2V}

V_{TH_ COMP_2p7V}

V_{TH_ COMP_3V}

V_{TH_ COMP_4V}

THRES_COMP = 2 V

THRES_COMP = 2.7 V

THRES_COMP = 3 V

THRES_COMP = 4 V

1.85

2.4

2.25

2.9

V

Comparator threshold

for 2.7 V

Comparator threshold

for 3 V

2.85

3.7

3.3

Comparator threshold

for 4 V

4.35

THRES_COMP = 2 V

THRES_COMP = 2.7 V

THRES_COMP = 3 V

THRES_COMP = 4 V

THRES_COMP = 2 V

THRES_COMP = 2.7 V

THRES_COMP = 3 V

THRES_COMP = 4 V

4.5

5

Minimum V_S

requirement for

proper detection

V_{S_COMP}

V

5.5

6.5

30

35

43

130

105

95

Comparator

equivalent input

resistance

R_{IN, COMP}

kΩ

(1) Verified by design.

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6.6 Timing Requirements

V_S= 4.5 V to 35 V, V_DD= 3 V to 5.5 V, and 10 pF capacitive load on SO unless otherwise noted; verified by design and

characterization.

PARAMETER

TEST CONDITION

MIN

NOM

MAX UNIT

SWITCH MONITORING, INTERRUPT, STARTUP AND RESET

t_{POLL_ACT}Polling active time accuracy

Polling mode

-12%

12%

t_{POLL_ACT}

Polling mode with matrix

enabled

Polling active time accuracy for matrix inputs

_M

t_POLL

Polling time accuracy

Polling mode

12%

µs

t_COMP

Comparator detection time

18

24

Sample and hold time

included

t_ADC

ADC Conversion time

µs

t_{CCP_TRA}Transition time between last input sampling and start of

20

µs

clean current

N

t_{CCP_ACT}Clean current active time

t_STARTUPPolling startup time

-12%

200

12%

300

2

400

2.5

µs

t_{INT_ACTIV}

Active INT assertion duration

1.5

ms

E

t_{INT_INACT}

INT de-assertion duration during a pending interrupt

3

80

2

4

5

ms

µs

IVE

t_{INT_IDLE}Interrupt idle time

100

120

Time required to keep the RESET pin high to successfully

t_RESET

reset the device (no pending interrupt)⁽¹⁾

Delay between a fault event (OV, UV, TW, or TSD) to a

high to low transition on the INT pin

t_REACT

20

µs

See 图7-2 for OV example.

SPI INTERFACE

t_LEAD

t_LAG

Falling edge of CS to rising edge of SCLK setup time

Falling edge of SCLK to rising edge of CS setup time

SI to SCLK falling edge setup time

100

30

ns

t_SU

t_HOLD

t_VALID

t_SO(EN)

SI hold time after falling edge of SCLK

20

Time from rising edge of SCLK to valid SO data

Time from falling edge of CS to SO low-impedance

70

60

Loading of 1 kΩ to GND.

See 图7-3.

t_SO(DIS)

Time from rising edge of CS to SO high-impedance

60

ns

t_R

t_F

SI, CS, and SCLK signals rise time

SI, CS, and SCLK signals fall time

5

30

ns

t_{INTER_FR}Delay between two SPI communication ( CS low)

1.5

µs

sequences

AME

t_CKH

t_CKL

SCLK High time

SCLK Low time

120

ns

Delay between valid V_DDvoltage and initial SPI

communication

t_INITIATION

45

µs

(1) If there is a pending interrupt (/INT pin asserted low), it can take up to 1ms for the device to complete the reset.

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6.7 Typical Characteristics

18

16

14

12

10

8

16

14

12

10

8

I_WETT=1mA

I_WETT=2mA

I_WETT=5mA

I_WETT=10mA

I_WETT=15mA

I_WETT=1mA

I_WETT=2mA

I_WETT=5mA

I_WETT=10mA

I_WETT=15mA

6

4

2

0

5

10

15

20

V_Svoltage (V)

25

30

35

40

-40 -20

0

20

40

60

Temperature (C)

80 100 120 140 160

D001

T_A= 25°C

V_S= 12 V

图6-1. Wetting Current Output - CSO vs. V_SVoltage

图6-2. Wetting Current Output - CSO vs. Temperature

4

1000

ADC Code Min

ADC Code Max

3.75

3.5

3.25

3

THRES_COMP=2V

THRES_COMP=2.7V

THRES_COMP=3V

THRES_COMP=4V

800

600

400

200

0

2.75

2.5

2.25

2

1.75

5

505 1005 1505 2005 2505 3005 3505 4005 4505 5000

Equivalent Input Resistance (W)

0

5

10

15

20

V_Svoltage (V)

25

30

35

40

ADDP0C0lo1_t

D001

I_(WETT)= 1 mA

图6-4. ADC Code vs. Equivalent Input Resistance

T_A= 25°C

4.5 V ≤V_S≤35 V

图6-3. Comparator Threshold vs. V_SVoltage

1200

1000

800

600

400

200

0

700

ADC Code Min

ADC Code Max

600

500

400

300

200

100

0

ADC Code Min

ADC Code Max

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

ADD0C01_

I_(WETT)= 2 mA

4.5 V ≤V_S≤35 V

I_(WETT)= 5 mA

4.5 V ≤V_S< 5.5 V

图6-5. ADC Code vs. Equivalent Input Resistance

图6-6. ADC Code vs. Equivalent Input Resistance

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6.7 Typical Characteristics (continued)

1100

1000

900

800

700

600

500

400

300

200

900

800

700

600

500

400

300

200

100

0

ADC Code Min

ADC Code Max

ADC Code Min

ADC Code Max

100

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

ADD0C01_

I_(WETT)= 5 mA

图6-7. ADC Code vs. Equivalent Input Resistance

5.5 V ≤V_S≤35 V

I_(WETT)= 10 mA

4.5 V ≤V_S< 6 V

图6-8. ADC Code vs. Equivalent Input Resistance

1100

900

1000

900

800

700

600

500

400

300

200

100

0

800

700

600

500

400

300

200

100

0

ADC Code Min

ADC Code Max

ADC Code Min

ADC Code Max

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

ADD0C01_

I_(WETT)= 10 mA

6 V ≤V_S≤35 V

I_(WETT)= 15 mA

4.5 V ≤V_S< 6.5 V

图6-9. ADC Code vs. Equivalent Input Resistance

图6-10. ADC Code vs. Equivalent Input Resistance

1100

1000

900

800

700

600

500

400

300

200

100

0

ADC Code Min

ADC Code Max

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Equivalent Input Resistance (W)

ADD0C01_

I_(WETT)= 15 mA

图6-11. ADC Code vs. Equivalent Input Resistance

6.5 V ≤V_S≤35 V

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7 Parameter Measurement Information

V_DD

t_INITIATION

t_INTERFRAME

/CS

tt_LAG

t

tt_CKH

t

tt_CKLt

tt_LEAD

t

SCLK

t_HOLD

tt_SU

t

SI

t_SO(EN)

t_VALID

t_SO(DIS)

SO

图7-1. SPI Timing Parameters

V_{OV_R}

V_S

t_REACT

/INT

V_{/INT_L}

图7-2. t_REACTTiming Parameters

V_{IN_H}

/CS

SO

t_SO(DIS)

SO

V_{SO_H}

GND

图7-3. t_SO(DIS)Timing Parameters

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8 Detailed Description

8.1 Overview

The TIC12400-Q1 is an advanced 24-input Multiple Switch Detection Interface (MSDI) device designed to detect

external mechanical switch status in a 12 V automotive system by acting as an interface between the switches

and the low-voltage microcontroller. The TIC12400-Q1 is an integrated solution that replaces many discrete

components and provides integrated protection, input serialization, and system wake-up capability.

The device monitors 14 switches to GND and 10 additional switches that can be programmed to be connected to

either GND or V_BAT. It features SPI interface to report individual switch status and provides programmability to

control the device operation. The TIC12400-Q1 features a 10-bit ADC which is useful to monitor analog inputs

such as resistor coded switches that have multiple switching positions. To monitor only digital switches, an

integrated comparator can be used instead to monitor the input status. The device has 2 modes of operation:

continuous mode and polling mode. The polling mode is a low-power mode that can be activated to reduce

current drawn in the system by only turning on the wetting current for a small duty cycle to detect switch status

changes. An interrupt is generated upon detection of switch status change and it can be used to wake up the

microcontroller to bring the entire system back to operation.

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8.2 Functional Block Diagram

V_S

37

V_S

38

V_S

Over-voltage

protection

1mA to 15mA

or

Over-temperature

protection

OFF

SW

Under-voltage

protection

IN0

IN1

IN2

IN3

13

14

AGND

ESD

Protection

1mA to 15mA

22

Pre-regulator

CAP_PRE

or

OFF

25

26

SW

AGND

20

23

Analog LDO

Digital LDO

CAP_A

CAP_D

V_test

+

V_S

œ

AGND

Power management

AGND

1mA to 15mA

V_S

or

OFF

IN9

33

SW

ESD

Protection

1mA to 15mA

V_DIG

or

OFF

Oscillator

24

/INT

AGND

R1

SW

ADC

State

machine

AGND

19

15

16

17

18

21

V_DD

/CS

V_S

Control

logic

SCLK

SI

AGND

MUX

Input/

output

buffer

1mA to 15mA

or

OFF

SO

Registers

SW

RESET

IN10 34

R5

SW

+

ESD

Protection

Digital Block

35

œ

IN11

1MΩ

+

V_S

DGND

œ

AGND

IN12 36

AGND

1

IN13

1mA to 15mA

or

OFF

SW

IN23 12

ESD

Protection

AGND

DGND

9

28

DGND

AGND

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8.3 Feature Description

8.3.1 V_SPin

The V_Ssupply provides power to the entire chip and it is designed to be connected directly to a 12 V automotive

battery via a reverse-polarity blocking diode.

8.3.2 V_DDPin

The V_DDsupply is used to determine the logic level on the SPI communication interface, source the current for

the SO driver, and sets the pull-up voltage for the CS pin. It can also be used as a possible external pull-up

supply for the INT pin in addition to the V_Sand it shall be connected to a 3 V to 5.5 V logic supply. Removing

V_DDfrom the device disables SPI communications but does not reset the register configurations.

8.3.3 Device Initialization

When the device is powered up for the first time, the condition is called Power-On Reset (POR), which sets the

registers to their default values and initializes the device state machine. The internal POR controller holds the

device in a reset condition until V_Shas reached V_{POR_R}, at which the reset condition is released with the device

registers and state machine initialized to their default values. After the initialization process is completed, the INT

pin is asserted low to notify the microcontroller, and the register bit POR in the INT_STAT register is asserted to

logic 1. The SPI flag bit POR is also asserted at the SPI output (SO).

During device initialization, factory settings are programmed into the device to allow accurate device operation.

The device performs a self-check after the device is programmed to ensure correct settings are loaded. If the

self-check returns an error, the CHK_FAIL bit in the INT_STAT register will be flagged to logic 1 along with the

POR bit. If this event occurs the microcontroller is recommended to initiate software reset (see section Software

Reset) to re-initialize the device to allow the correct settings to be re-programmed.

8.3.4 Device Trigger

After device initialization, the TIC12400-Q1 is ready to be configured. The microcontroller can use SPI

commands to program desired settings to the configuration registers. Once the device configuration is

completed, the microcontroller is required to set the bit TRIGGER in the CONFIG register to logic 1 in order to

activate wetting current and start external switch monitoring.

After switch monitoring initiates, the configuration registers turn into read-only registers (with the exception of the

TRIGGER, CRC_T, and RESET bits in the CONFIG register and all bits in the CCP_CFG1 register). If at any

time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER in

the CONFIG register to logic 0 to stop wetting current and switch monitoring. The microcontroller can then

program configuration registers to the desired settings. Once the re-configuration is completed the

microcontroller can set the TRIGGER bit back to logic 1 to re-start switch monitoring.

Note the cyclic redundancy check (CRC) feature stays accessible when TRIGGER bit is in logic 1, allowing the

microcontroller to verify device settings at all time. Refer to section Cyclic Redundancy Check (CRC) for more

details of the CRC feature.

8.3.5 Device Reset

There are 3 ways to reset the TIC12400-Q1 and re-initialize all registers to their default values:

8.3.5.1 V_SSupply POR

The device is turned off and all register contents are lost if the V_Svoltage drops below V_{POR_F}. To turn the device

back on, the V_Svoltage must be raised back above V_{POR_R}, as illustrated in 图 8-1. The device then starts the

initialization process as described in section Device Initialization.

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V_S

Device

OFF

Normal

Operation

Device

OFF

Normal

Operation

V_{POR_R}

V_{POR_F}

Time

图8-1. V_Sis Lowered Below the POR Threshold, Then Ramped Back Up to Complete a POR Cycle

8.3.5.2 Hardware Reset

Microcontroller can toggle the RESET pin to perform a hardware reset to the device. The RESET pin is internally

pulled-down via a resistor (1.25 MΩ typical) and must be kept low for normal operation. When the RESET pin is

toggled high, the device enters the reset state with most of the internal blocks turned off and consumes very little

current of I_{S_RESET}. Switch monitoring and SPI communications are stopped in the reset state, and all register

contents are cleared. When RESET pin is toggled back low, all the registers are set to their default values and

the device state machine is re-initialized, similar to a POR event. When the re-initialization process is completed

the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to

notify the microcontroller that the device has completed the reset process.

Note in order to successfully reset the device, the RESET pin needs to be kept high for a minimum duration of

t_RESET. The pin is required to be driven with a stable input (below V_{RESET_L}for logic low or above V_{RESET_H}for

logic H) to prevent the device from accidental reset.

8.3.5.3 Software Reset

In addition to hardware reset the microcontroller can also issue a SPI command to initiate software reset.

Software reset is triggered by setting the RESET bit in the register CONFIG to logic 1, which re-initializes the

device with all registers set to their default values. Once the re-initialization process is completed, the INT pin is

asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the

microcontroller that the device has completed the reset process.

8.3.6 V_SUnder-Voltage (UV) Condition

During normal operation of a typical 12 V automotive system, the V_Svoltage is usually quite stable and stays

well above 11 V. However, the V_Svoltage may drop temporarily during certain vehicle operations, such as cold

cranking. If the V_Svoltage drops below V_{UV_F}, the TIC12400-Q1 enters the under-voltage (UV) condition since

there is not enough voltage headroom for the device to accurately generate wetting currents. The following

describes the behavior of the TIC12400-Q1 under UV condition:

1. All current sources and sinks de-activate and switch monitoring stops.

2. Interrupt is generated by asserting the INT pin low and the bit UV in the interrupt register (INT_STAT) is

flagged to logic 1. The bit UV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is

asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is

cleared on the rising edge of CS provided that the interrupt register has been read during the SPI

transaction.

3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status,

if needed, can be retrieved without interruption.

4. The device continues to monitor the V_Svoltage, and the UV condition sustains if the V_Svoltage continues to

stay below V_{UV_R}. No further interrupt is generated once cleared.

Note: the device resets as described in section VS Supply POR if the V_Svoltage drops below V_{POR_F}

.

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When the V_Svoltage rises above V_{UV_R}, the INT pin is asserted low to notify the microcontroller that the UV

condition no longer exists. The UV bit in the register INT_STAT is flagged to logic 1 and the bit UV_STAT bit is

de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the UV condition. The device

resumes operation using current register settings (regardless of the INT pin and SPI communication status) with

polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the

end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent

polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT

pin is released afterwards.

The following diagram describes the TIC12400-Q1 operation at various different V_Svoltages. If the V_Svoltage

stays above V_{UV_F}(Case 1), the device stays in normal operation. If the V_Svoltage drops below V_{UV_F}but stays

above V_{POR_F}(Case 2), the device enters the UV condition. If V_Svoltage drops below V_{POR_F}(Case 3), the

device resets and all register settings are cleared. The microcontroller is then required to re-program all the

configuration registers in order to resume normal operation after the V_Svoltage recovers.

V_S

tCrankingt

Device

OFF

V_{POR_R}

Case 1

V_{UV_F}

Case 2

V_{POR_F}

Case 3

Time

图8-2. TIC12400-Q1 Operation at Various V_SVoltage Levels

8.3.7 V_SOver-Voltage (OV) Condition

If V_Svoltage rises above V_{OV_R}, the TIC12400-Q1 enters the over-voltage (OV) condition to prevent damage to

internal structures of the device on the V_Sand INx (for battery-connected switches) pins. The following describes

the behavior of the TIC12400-Q1 under OV condition:

1. All current sources and sinks de-activate and switch monitoring stops.

2. Interrupt is generated by asserting the INT pin low and the bit OV in the interrupt register (INT_STAT) is

flagged to logic 1. The bit OV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is

asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is

cleared on the rising edge of CS provided that the interrupt register has been read during the SPI

transaction.

3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status,

if needed, can be retrieved without any interruption.

4. The device continues to monitor the V_Svoltage, and the OV condition sustains if the V_Svoltage continues to

stay above V_{OV_R}- V_{OV_HYST}. No further interrupt is generated once cleared.

When the V_Svoltage drops below V_{OV_R}- V_{OV_HYST}, the INT pin is asserted low to notify the microcontroller that

the over-voltage condition no longer exists. The OV bit in the register INT_STAT is flagged to logic 1 and the bit

OV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the OV condition.

The device resumes operation using current register settings (regardless of the INT pin and SPI communication

status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is

generated at the end of the first polling cycle and the detected switch status becomes the baseline status for

subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared

and the INT pin is released afterwards.

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8.3.8 Switch Inputs Settings

IN0 to IN23 are inputs connected to external mechanical switches. The switch status of each input, whether

open or closed, is indicated by the status registers. 表 8-1 below describes various settings that can be

configured for each input. Note: some settings are shared between multiple inputs. It is required to first stop

device operation by setting the TRIGGER bit low in the register CONFIG before making any configuration

changes, as described in Device Trigger.

表8-1. TIC12400-Q1 Wetting Current and Threshold Setting Details

Threshold

Current Source (CSO) /

Current Sink (CSI)

Supported Switch

Type

Input

Wetting Current

Comparator Input

Mode

ADC Input Mode

THRES0 to

CSO

CSI

Switch to GND

Switch to VBAT

IN0

IN1

THRES7

WC_IN0_IN1

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

THRES_COMP_IN

0_IN3

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN2

WC_IN2_IN3

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN3

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN4

WC_IN4

WC_IN5

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN5

THRES_COMP_IN

4_IN7

THRES_COM

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN6

WC_IN6_IN7

WC_IN8_IN9

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN7

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN8

THRES0 to

THRES7

CSO

CSI

Switch to GND

Switch to VBAT

IN9

THRES_COMP_IN

8_IN11

THRES0 to

THRES7

IN10

IN11

IN12

IN13

IN14

IN15

IN16

IN17

WC_IN10

WC_IN11

CSO

Switch to GND

THRES0 to

THRES7

THRES2A

THRES2B

WC_IN12_13

WC_IN14_15

WC_IN16_17

THRES2A

THRES2B

THRES_COMP_IN

12_IN15

THRES2A

THRES2B

THRES2A

THRES2B

THRES2A

THRES2B

THRES2A

THRES2B

THRES_COMP_IN

16_IN19

THRES3A

THRES3B

THRES3C

IN18

IN19

CSO

Switch to GND

WC_IN18_19

THRES3A

THRES3B

THRES3C

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表8-1. TIC12400-Q1 Wetting Current and Threshold Setting Details (continued)

Threshold

Current Source (CSO) /

Current Sink (CSI)

Supported Switch

Type

Input

Wetting Current

Comparator Input

Mode

ADC Input Mode

THRES3A

THRES3B

THRES3C

IN20

IN21

IN22

CSO

Switch to GND

WC_IN20_21

THRES3A

THRES3B

THRES3C

THRES_COMP_IN

20_IN23

THRES3A

THRES3B

THRES3C

WC_IN22

WC_IN23

THRES3A

THRES3B

THRES3C

THRES8

IN23

CSO

Switch to GND

THRES9

8.3.8.1 Input Current Source and Sink Selection

Among the 24 inputs, IN10 to IN23 are intended for monitoring only ground-connected switches and are

connected to current sources. IN0 to IN9 can be programmed to monitor either ground-connected switches or

battery-connected switches by configuring the CS_SELECT register. The default configuration of the IN0-IN9

inputs after POR is to monitor ground-connected switches (current sources are selected). To set an input to

monitor battery-connected switches, set the corresponding bit to logic 1.

8.3.8.2 Input Mode Selection

The TIC12400-Q1 has a built-in ADC and a comparator that can be used to monitor resistor coded switches or

digital switches. Digital switch inputs have only two states, either open or closed, and can be adequately

detected by a comparator. Resistor coded switches may have multiple positions that need to be detected and an

ADC is appropriate to monitor the different states. Each input of the TIC12400-Q1 can be individually

programmed to use either a comparator or an ADC by configuring the appropriate bits in the MODE register

depending on the knowledge of the external switch connections. The benefit of using a comparator instead of an

ADC to monitor digital switches is its reduced polling time which translates to overall power saving when the

device operates in the low-power polling mode.

Comparator input mode is selected by default for all enabled inputs upon device reset.

8.3.8.3 Input Enable Selection

The TIC12400-Q1 provides switch status monitoring for up to 24 inputs, but there might be circumstances in

which not all inputs need to be constantly monitored. The microcontroller may choose to enable or disable

monitoring of certain inputs by configuring the IN_EN register. Setting the corresponding bit to logic 0 de-

activates the wetting current source and sink, and stops switch status monitoring for the input. Disabling

monitoring of unused inputs reduces overall power consumption of the device.

All inputs are disabled by default upon device reset.

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8.3.8.4 Thresholds Adjustment

When an input is configured as comparator input mode, the threshold level for interrupt generation can be

programmed by setting the THRES_COMP register. The threshold level settings can be set for each individual

input groups and each group consists of 4 inputs. Four threshold levels are available: 2 V, 2.7 V, 3 V, and 4 V.

When an input is configured as ADC input mode the threshold level for interrupt generation can be configured

from 0 to 1023 different levels by setting the THRES_CFG1 to THRES_CFG2 registers. One threshold level can

be programmed individually for each of the inputs from IN0 to IN11. Additionally, one common threshold, shared

between inputs IN0 to IN11, can be programmed by configuring the THRES_COM bits in register MATRIX. The

common threshold acts independently from the threshold THRES0 to THRES7. Inputs IN12 to IN17 use 2 preset

threshold levels (THRES2A and THRES2B). Inputs 18 to 22 use 3 preset threshold levels (THRES3A,

THRES3B, and THRES3C). Input 23 uses 5 preset threshold levels (THRES3A, THRES3B, THRES3C,

THRES8, and THRES9).

When multiple threshold settings are used for ADC inputs, the thresholds levels need to be configured properly.

Use the rules below (see 表8-2) when setting up the threshold levels:

表8-2. Proper Threshold Configuration for ADC Inputs

INPUT

IN12 to IN17

IN18 to IN22

IN23

PROPER THRESHOLD CONFIGURATION

THRES2B ≥THRES2A

THRES3C ≥THRES3B ≥THRES3A

THRES9 ≥THRES8 ≥THRES3C ≥THRES3B ≥THRES3A

Remember to use caution when setting up the threshold for switches that are connected externally to the battery

as there is a finite voltage drop (as high as V_{CSI_DROP_OPEN}for 10 mA and 15 mA settings) across the current

sinks. Therefore, even for an open switch, the voltage on the INx pin can be as high as V_{CSI_DROP_OPEN}and the

detection threshold shall be configured above it. It shall also be noted that a lower wetting current sink setting

may not be strong enough to pull the INx pin close to ground in the presence of a leaky open external switch, as

illustrated in the diagram below (see 图8-3). In this example, the external switch, although in the open state, has

large leakage current and can be modelled as an equivalent resistor (R_DIRT) of 5 kΩ. The 2 mA current sink is

only able to pull the INx pin voltage down to 4 V, even if the switch is in the open state.

Battery- connected switch

+

14V

R_DIRT

R_SW

œ

V_BAT

5kΩ

GND

Open

TIC12400-Q1

INx

2mA

GND

图8-3. Example Showing the Calculation of the INx Pin Voltage for A Leaky Battery-Connected Switch

It is possible to configure an input to ADC input mode, instead of comparator input mode, to monitor single-

threshold digital switches. The following programming procedure is recommended under such configuration:

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表8-3. Recommended Threshold Configuration When Using an ADC Input to Monitor Digital Switches

INPUT

RECOMMENDED THRESHOLD CONFIGURATION

IN0 to IN11

Configure the desired threshold to one of the settings from THRES0 to THRES7 and map it accordingly

•

Configure the desired threshold to THRES2B

Set THRES2A to the same code as THRES2B

Disable interrupt generation for THRES2A by configuring the INT_EN_CFG1 or INT_EN_CFG2

register.

IN12 to IN17

IN18 to IN22

IN23

•

Configure the desired threshold to THRES3C

Set THRES3A and THRES3B to the same code as THRES3C.

Disable interrupt generation for THRES3A and THRES3B by configuring the INT_EN_CFG3 or

INT_EN_CFG4 register.

•

Configure the desired threshold to THRES9

Set THRES3A, THRES3B, THRES3C, and THRES8 to the same code as THRES9.

Disable interrupt generation for THRES3A, THRES3B, THRES3C, and THRES8 by configuring the

INT_EN_CFG4 register.

8.3.8.5 Wetting Current Configuration

There are 6 different wetting current settings (0 mA, 1 mA, 2 mA, 5 mA, 10 mA, and 15 mA) that can be

programmed by configuring the WC_CFG0 and WC_CFG1 registers. 0 mA is selected by default upon device

reset.

To monitor resistor coded switches, a lower wetting current setting (1 mA, 2 mA, or 5 mA) is generally desirable

to get the resolution needed to resolve different input voltages while keeping them within the ADC full-scale

range (0 V to 6 V). Higher wetting current settings (10 mA and 15 mA) are useful to clean switch contact

oxidation that may form on the surface of an open switch contact. If switch contact cleaning is required for

resistor coded switches, the clean current polling (CCP) feature (Refer to 节 8.4.3.1) can be activated to

generate short cleaning pulses periodically using higher wetting current settings at the end of every polling cycle.

The accuracy of the wetting current has stronger dependency on the V_Svoltage when V_Svoltage is low. The

lower the V_Svoltage falls, the more deviation on the wetting currents from their nominal values. Refer to

I_{WETT (CSO)}and I_{WETT (CSI)}specifications for more details.

8.3.9 Interrupt Generation and INT Assertion

The INT pin is an active-low, open-drain output that asserts low when an event such as switch input state

change, temperature warning, over-voltage shutdown, and so fourth, is detected by the TIC12400-Q1. An

external pull-up resistor to V_DDis needed on the INT pin (see 图8-4). The INT pin can also be connected directly

to a 12 V automotive battery to support the microcontroller wake-up feature, as describe in 节8.3.9.3.

TIC12400-Q1

Microcontroller

V_DD

/INT

GPI

AGND

GND

AGND

GND

图8-4. INT Connection Example #1

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8.3.9.1 INT Pin Assertion Scheme

TIC12400-Q1 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be

adjusted by configuring the INT_CONFIG bit in the CONFIG register.

If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low

upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has

been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The

content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every

SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as

illustrated in 图8-5.

ñ INT_STAT register

content cleared

Event occurance

ñ /INT pin released

/INT

/CS

Register READ

(non- INT_STAT register)

Register READ

(INT_STAT register)

图8-5. Static INT Assertion Scheme

In some system implementations an edge-triggered based microcontroller might potentially miss the INT

assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking

up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC12400-Q1

provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used

(INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of t_{INT_ACTIVE}and is de-

asserted back to high if the INT_STAT register has not been read after t_{INT_ACTIVE}has elapsed. The INT is kept

high for a duration of t_{INT_INACTIVE}, and is re-asserted low after t_{INT_INACTIVE}has elapsed. The INT pin continues

to toggle until the INT_STAT register is read.

If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s

CS rising edge and the content of the INT_STAT register is also cleared, as shown in 图 8-6. If the INT_STAT

register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ

command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in 图8-7.

ñ INT_STAT register

content cleared

Event

ñ /INT pin released

occurance

tt_{INT_INACTIVE}

t

/INT

/CS

t_{INT_ACTIVE}

Register READ

(INT_STAT register)

图8-6. Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_ACTIVE}

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ñ INT_STAT register

content cleared

ñ /INT pin will not be re-

asserted t_{INT_INACTIVE}

after /INT returns high

Event

occurance

tt_{INT_INACTIVE}

t

/INT

/CS

t_{INT_ACTIVE}

Register READ

(INT_STAT register)

图8-7. Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_INACTIVE}

The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can

only be changed when bit TRIGGER is logic 0 in the CONFIG register.

8.3.9.2 Interrupt Idle Time (t_{INT_IDLE}) Time

Interrupt idle time (t_{INT_IDLE}) is implemented in TIC12400-Q1 to:

• Allow the INT pin enough time to be pulled back high by the external pull-up resistor and allow the next

assertion to be detectable by an edge-triggered microcontroller.

• Minimize the chance of glitching on the INT pin if back-to-back events occur.

When there is a pending interrupt event and the interrupt event is not masked, t_{INT_IDLE}is applied after the

READ command is issued to the INT_STAT register. If another event occurs during the interrupt idle time the

INT_STAT register content is updated instantly but the INT pin is not asserted low until t_{INT_IDLE}has elapsed. If

another READ command is issued to the INT_STAT register during t_{INT_IDLE}, the INT_STAT register content is

cleared immediately, but the INT pin is not re-asserted back low after t_{INT_IDLE}has elapsed. An example of the

interrupt idle time is given below to illustrate the INT pin behavior under the static INT assertion schemes:

/INT pin is not

asserted until

t_{INT_IDLE}has expired

1^stEvent

occurance

2^ndEvent

occurance

/INT

/CS

tt_{INT_IDLE}

Register READ

(INT_STAT register)

Register READ

(INT_STAT register)

图8-8. INT Assertion Scheme With t_{INT_IDLE}

8.3.9.3 Microcontroller Wake-Up

Using a few external components, the INT pin can be used for wake-up purpose to activate a voltage regulator

via its inhibit inputs. An implementation example is shown in 图 8-9. This implementation is especially useful for

waking up a microcontroller in sleep mode to allow significant system-level power savings.

Before the wake-up event, the INT pin is in high impedance state on the TIC12400-Q1. The microcontroller can

be kept in sleep state with all its GPIOs in logic low. Hence, Q2 remains off with its based in logic low state and

the base of Q1 is weakly pulled-high to the V_Slevel. This causes Q1 to remain off, and the LDO_EN signal is

pulled-down to logic low to disable the regulator's output. V_DDis therefore unavailable to both the TIC12400-Q1

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device and the microcontroller and SPI communication is not supported. Switch status monitoring, however, is

still active in the TIC12400-Q1.

When an event such as switch status change, temperature warning, O V and so fourth occurs, the INT pin is

asserted low by TIC12400-Q1, causing Q1 to turn on to activate the voltage regulator. The microcontroller is

then reactivated, and the communication between the microcontroller and the TIC12400-Q1 is reestablished.

The microcontroller can then access stored event information using SPI communication. Note: since the INT pin

is de-asserted after the INT_STAT register is read, the microcontroller is required to keep the regulator on by

driving the μC_LDO_EN signal high. This allows V_DDto stay high to provide power to the microcontroller and

support SPI communications.

The wake-up implementation is applicable only when the device is configured to use the static INT assertion

scheme.

Regulator

V_IN

+

V_BAT

10kΩ

œ

V_OUT

Q1

GND

Microcontroller

LDO_EN

10kΩ

TIC12400-Q1

10kΩ

GND

V3p3

V_DD

10kΩ

/INT

ꢀC_INT

GPIO 1

GPIO 2

Q2

ꢀC_LDO_EN

AGND

GND

10kΩ

GND

图8-9. INT Connection to Support Microcontroller Wake-Up

8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions

Each switch input can be programmed to enable or disable interrupt generation upon status change by

configuring registers INT_EN_COMP1 to INT_EN_COMP2 (for comparator inputs) and INT_EN_CFG1 to

INT_EN_CFG4 (for ADC inputs). Interrupt generation condition can be adjusted for THRES_COM (for IN0-IN11)

by adjusting the IN_COM_EN bit in the MATRIX register.

The abovementioned registers can also be used to control interrupt generation condition based on the following

settings:

1. Rising edge: an interrupt is generated if the current input measurement is above the corresponding

threshold and the previous measurement was below.

2. Falling edge: an interrupt is generated if the current input measurement is below the corresponding

threshold and the previous measurement was above.

3. Both edges: changes of the input voltage in either direction results in an interrupt generation.

Note interrupt generation from switch status change is disabled for all inputs by default upon device reset.

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8.3.9.5 Detection Filter

When monitoring the switch input status, a detection filter can be configured by setting the DET_FILTER bits in

the CONFIG register to generate Switch Status Change (SSC) interrupt only if the same input status (w.r.t the

threshold) is sampled consecutively. This detection filter can be useful to debounce inputs during a switch toggle

event. Four different filtering schemes are available:

1. Generate an SSC interrupt, if the voltage level at an input crossed its threshold.

2. Generate an SSC interrupt, if the voltage level at an input crossed its threshold and the status is stable (w.r.t.

the threshold) for at least 2 consecutive polling cycles.

3. Generate an SSC interrupt, if the voltage level at an input crossed its threshold and the status is stable (w.r.t.

the threshold) for at least 3 consecutive polling cycles.

4. Generate an SSC interrupt, if the voltage level at an input crossed its threshold and the status is stable (w.r.t.

the threshold) for at least 4 consecutive polling cycles.

The default value of switch status is stored internally after the 1st detection cycle, even if detection filter (by

configure the DET_FILTER in the CONFIG register) is used. An example is illustrated below with the assumption

that DET_FILTER in register CONFIG is set to 11 (SSC interrupt is generated if the input crosses the threshold

and the status is stable w.r.t. the threshold for at least 4 consecutive detection cycles). Assume switch status

change is detected in the 3rd detection cycle and stays the same for the next 3 cycles.

DETECTION CYCLE

1

2

3

4

5

6

•

Default Switch status stored

INT asserted

•

INT asserted

SSC flagged

Switch status change

detected

Event

—

SSC flagged

The detection filter applies to all enabled inputs regardless of their input modes (ADC or comparator) selection.

The detection filter counter is reset to 0 when the TRIGGER bit in the CONFIG register is de-asserted to logic 0.

Upon device reset, the default setting for the detection filter is set to generating an SSC interrupt at every

threshold crossing.

Note: the detection filter does not apply to the common threshold THRES_COM.

8.3.10 Temperature Monitor

When multiple switch inputs are closed and high wetting current setting is enabled, considerable power can be

dissipated by the device and raise the device temperature. TIC12400-Q1 has integrated temperature monitoring

and protection circuitry to put the device in low power mode to prevent damage due to overheating. Two types of

temperature protection mechanisms are integrated in the device: Temperature Warning (TW) and Temperature

Shutdown (TSD). The triggering temperatures and hysteresis are specified in 表8-4 below:

表8-4. Temperature Monitoring Characteristics of TIC12400-Q1

PARAMETER

MIN

130

150

TYP

140

160

15

MAX

155

UNIT

°C

Temperature warning trigger temperature (T_TW

)

Temperature shutdown trigger temperature (T_TSD

)

175

°C

Temperature hysteresis (T_HYS) for T_TWand T_TSD

°C

8.3.10.1 Temperature Warning (TW)

When the device temperature goes above the temperature warning trigger temperature (T_TW), the TIC12400-Q1

performs the following operations:

1. Generate an interrupt by asserting the INT pin low and flag the TW bit in INT_STAT register to logic 1. The

TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.

2. The TW_STAT bit of the IN_STAT_MISC register is flagged to logic 1.

3. If the TW_CUR_DIS_CSO or TW_CUR_DIS_CSO bit in CONFIG register is set to logic 0 (default), the

wetting current is adjusted down to 2 mA for 10 mA or 15 mA settings. The wetting current stays at its pre-

configured value if 0 mA, 1 mA, 2 mA, or 5 mA setting is used.

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4. Maintain the low wetting current as long as the device junction temperature stays above T_TW- T_HYS

.

The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the

INT_STAT register has been read during CS low. The TIC12400-Q1 continues to monitor the temperature, but

does not issue further interrupts if the temperature continues to stay above T_TW- T_HYS. The status bit TW_STAT

in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature warning condition exists.

If desired, the reduction of wetting current down to 2 mA setting (from 10 mA or 15 mA) can be disabled by

setting the TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1. The interrupt is still

generated ( INT asserted low and INT_STAT interrupt register is updated) when the temperature warning event

occurs but the wetting current is not reduced. This setting applies to both the polling and continuous mode

operation. Note: if the feature is enabled, switch detection result might be impacted upon T_TWevent if the wetting

current is reduced to 2 mA from 10 mA or 15 mA.

When the temperature drops below T_TW- T_HYS, the INT pin is asserted low (if released previously) to notify the

microcontroller that the temperature warning condition no longer exists. The TW bit of the interrupt register

INT_STAT is flagged logic 1. The TW_STAT bit in the IN_STAT_MISC register is de-asserted back to logic 0. The

device resumes operation using the current programmed settings (regardless of the INT and CS status).

8.3.10.2 Temperature Shutdown (TSD)

After the device enters TW condition, if the junction temperature continues to rise and goes above the

temperature shutdown threshold (T_TSD), the TIC12400-Q1 enters the Temperature Shutdown (TSD) condition

and performs the following operations:

1. Opens all the switches connected to the current sources and sinks to prevent any further heating due to

excessive current flow.

2. Generate an interrupt by asserting the INT pin (if not already asserted) low and flag the TSD bit in the

INT_STAT register to logic 1. The TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.

3. The TSD_STAT bit of the IN_STAT_MISC register is flagged to logic 1. The TW_STAT bit also stays at logic

1.

4. SPI communication stays on and all register settings stay intact without resetting. Previous switch status, if

needed, can be retrieved without any interruption.

5. Maintain the setting as long as the junction temperature stays above T_TSD- T_HYS

.

The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the

INT_STAT register has been read during CS low. The TIC12400-Q1 continues to monitor the temperature, but

does not issue further interrupts if the temperature continues to stay above T_TSD- T_HYS. The status bit

TSD_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature shutdown

condition exists.

When the temperature drops below T_TSD- T_HYS, the INT pin is asserted low (if released previously) to notify the

microcontroller that the temperature shutdown condition no longer exists. The TSD bit of the interrupt register

INT_STAT is flagged logic 1. In the IN_STAT_MISC register, the TSD_STAT bit is de-asserted back to logic 0,

while the TW_STAT bit stays at logic 1. The device resumes operation using the wetting current setting

described in section Temperature Warning if the temperature stays above T_TW- T_HYS. Note: the polling restarts

from the first enabled channel and the SSC interrupt is generated at the end of the first polling cycle. The

detected switch status from the first polling cycle becomes the default switch status for subsequent polling.

8.3.11 Parity Check and Parity Generation

The TIC12400-Q1 uses parity bit check to ensure error-free data transmission from and to the SPI controller.

The device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data

on SO (including the parity bit) is an odd number (that is Bit0 ⊕Bit1 ⊕–⊕Bit30 ⊕Bit31⊕Parity = 1).

The device also uses odd parity check after receiving data on SI from the SPI controller. If the total number of

ones in the received data (including the parity bit) is an even number the received data is discarded. The INT will

be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1 to notify the host

that transmission error occurred. The PRTY_FAIL flag is also asserted during SPI communications.

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8.3.12 Cyclic Redundancy Check (CRC)

The TIC12400-Q1 includes a CRC module to support redundancy checks on the configuration registers to

ensure the integrity of data. The CRC calculation is based on the ITU-T X.25 implementation, and the CRC

polynomial (0x1021) used is popularly known as CRC-CCITT-16 since it was initially proposed by the ITU-T

(formerly CCITT) committee. The CRC calculation rule is defined in 表8-5:

表8-5. CRC Calculation Rule

CRC RULE

CRC result width

Polynomial

VALUE

16 bits

x¹⁶+ x¹²+ x⁵+1 (1021h)

Initial (seed) value

Input data reflected

Result data reflected

XOR value

FFFFh

No

0000h

The CRC calculation is done on all the configuration registers starting from register CONFIG and ending at

register MODE. The device substitutes a zero for each reserved configuration register bit during the CRC

calculation. The CRC calculation can be triggered by asserting the CRC_T bit in the CONFIG register. Once

completed, the CRC_CALC interrupt bit in the INT_STAT register is asserted and an interrupt is issued. The 16-

bit CRC calculation result is stored in the register CRC. This interrupt can be disabled by de-asserting the

CRC_CALC_EN bit in the INT_EN_CFG0 register. It is important to avoid writing data to the configuration

registers when the device is undergoing CRC calculations to prevent false calculation results.

图 8-10 shows the block diagram of the CRC module. The module consists of 16 shift-registers and 3 exclusive-

OR gates. The registers start with 1111-1111-1111-1111 (or FFFFh) and the module performs an XOR function

and shifts its content until the last bit of the register string is used. The final register’s content after the last data

bit is the calculated CRC value of the data set and the content is stored in the CRC register.

Note the CRC_T bit self-clears after the CRC calculation is completed. Logic 1 is used for CRC_T bit during

CRC calculation.

X15 X14 X13 X12

X11 X10

X9

X8

X7

X6

X5

X4

X3

X2

X1

X0

+

XOR

Data

MSB

LSB

图8-10. CCITT-16 CRC Module Block Diagram

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8.4 Device Functional Modes

The TIC12400-Q1 has 2 modes of operation: continuous mode and polling mode. The following sections

describe the two operation modes in details as well as some of the advanced features that could be activated

during normal operations.

8.4.1 Continuous Mode

In continuous mode, wetting current is continuously applied to each enabled input channel, and the status of

each channel is sampled sequentially (starting from the IN0 to IN23). The TIC12400-Q1 monitors enabled inputs

and issues an interrupt (if enabled) if a switch status change event is detected. The wetting current setting for

each input can be individually adjusted by configuring the WC_CFG0 and WC_CFG1 to the 0 mA, 1 mA, 2 mA, 5

mA, 10 mA, or 15 mA setting. Each input is monitored by either a comparator or an ADC depending on the

setting of the input mode in the register MODE.

图 8-11 below illustrates an example of the timing diagram of the detection sequence in continuous mode. After

the TRIGGER bit in register CONFIG is set to logic 1, it takes t_STARTUPto activate the wetting current for all

enabled inputs. The wetting currents stay on continuously, while each input is routed to the ADC and comparator

for sampling in a sequential fashion. After conversion and comparison is done for an input, the switch status

(below or above detection threshold) is stored in registers (IN_STAT_COMP for comparator inputs and

IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) to be used as the default state for subsequent detection

cycles. The digital values (if the input is configured as ADC input mode) are stored in the registers ANA_STAT0

to ANA_STAT11. After the end of the first polling cycle, the INT pin is asserted low to notify the microcontroller

that the default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC

are also asserted to logic 1. The polling cycle time (t_POLL) determines how frequently each input is sampled and

can be configured in the register CONFIG.

Input sampling restarts

from first enabled input

after t_{POLL_TIME}

Wetting

current

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

t

tt_STARTUP

t

IN0

IN1

IN3

tt_ADCor t_COMP

t

tt_ADCor t_COMP

t

IN23

/INT

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

Time

图8-11. An Example of the Detection Sequence in Continuous Mode

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The INT_STAT register is cleared and INT pin de-asserted if a SPI READ command is issued to the register.

Note: the interrupt is always generated after the 1st detection cycle (after the TRIGGER bit in register CONFIG is

set to logic 1). In subsequent detection cycles, the interrupt is generated only if switch status change is detected.

No wetting currents are applied to 0 mA- configured inputs, although some biasing current (as specified by

I_{IN_LEAK_0mA}) may still flow in and out of the input. Threshold crossing monitoring is still performed for the input

using one or more of the defined thresholds. The 0 mA setting is useful for the integrated ADC or comparator to

measure applied voltage on a specific input without being affected by the device wetting current.

8.4.2 Polling Mode

The polling mode can be activated to reduce current drawn in ignition-off condition to conserve battery charge.

Unlike the continuous mode, the current sources and sinks do not stay on continuously in the polling mode.

Instead, they are turned on or off sequentially from IN0 to IN23 and cycled through each individual input channel.

The microcontroller can be put to sleep to reduce overall system power. If a switch status change (SSC) is

detected by the TIC12400-Q1, the INT pin (if enabled for the input channel) is asserted low (and the SSC bit in

INT_STAT register and the SPI status flag SSC are also asserted to logic 1). The INT pin assertion can be used

to wake up the system regulator which, in turn, wakes up the microcontroller as described in section

Microcontroller Wake-Up. The microcontroller can then use SPI communication to read the switch status

information.

The polling is activated when the TRIGGER bit in the CONFIG register is set to logic 1. There are 2 different

polling schemes that can be configured in TIC12400-Q1: standard polling and matrix polling.

8.4.2.1 Standard Polling

In standard polling mode, wetting current is applied to each input for a pre-programmed polling active time

between 64 μs and 2048 μs, set by the POLL_ACT_TIME bits in the CONFIG register. At the end of the

wetting current application, the input voltage is sampled by the comparator (if input is configured as comparator

input mode) or the ADC (if input is configured as ADC input mode). Each input is cycled through in sequential

order from IN0 to IN23. Sampling is repeated at a frequency from 2 ms to 4096 ms, set by the POLL_TIME bits

in the CONFIG register. Wetting currents are applied to closed switches only during the polling active time;

hence, the overall system current consumption can be greatly reduced.

Similar to continuous mode, after the first polling cycle, the switch status of each input (below or above detection

threshold) is stored in registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1

for ADC inputs) to be used as the default state for subsequent polling cycles. The digital values (if the input is

configured as ADC input mode) are stored in the registers ANA_STAT0 to ANA_STAT11. The INT pin is asserted

low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in INT_STAT

register and the SPI status flag SSC are also asserted to logic 1. The INT_STAT register is cleared and INT pin

de-asserted if a SPI READ command is issued to the register. Note the interrupt is always generated after the

1st polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent polling cycles the

interrupt is generated only if switch status change is detected.

An example of the timing diagram of the polling mode operation is shown in 图8-12.

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Wetting current is

activated for

t_{POLL_ACT_TIME}

Wetting

current

Input sampling restarts

from first enabled input

after t_{POLL_TIME}

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_ACT_TIME}t

tt_{POLL_TIME}

t

tt_STARTUP

t

tt_{POLL_ACT_TIME}t

tt_STARTUP

t

IN0

IN1

IN3

tt_ADCor t_COMP

t

tt_ADCor t_COMP

t

IN23

/INT

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

tt_ADCor t_COMP

t

Time

图8-12. An Example of the Polling Sequence in Standard Polling Mode

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If the switch position changes between two active polling times, no interrupt will be generated and the status

registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) will

not reflect such a change. An example is shown in 图8-13.

Wetting

current

Switch

state

Ignored

Initial switch

switch state

state change

change

/INT

/INT asserted

due to initial

state change

/CS

Time

图8-13. Example for Ignored Switch Position Change Between 2 Wetting Current Cycles

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8.4.2.2 Matrix polling

TIC12400-Q1

V_S

1mA to 15mA

or

OFF

IN10

34

ESD

Protection

IN11

35

IN12

36

V_S

IN13

1

IN14

2

1mA to 15mA

or

OFF

IN15

3

6 x 6 matrix

ESD

Protection

5 x 5 matrix

4 x 4 matrix

SW

IN4

27

ESD

SW

1mA to 15mA

Protection

or

OFF

IN5

29

AGND

SW

IN6

30

SW

IN7

31

SW

IN8

32

SW

IN9

33

ESD

1mA to 15mA

Protection

or

OFF

AGND

图8-14. TIC12400-Q1 Matrix Configuration

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From IN4 to IN15 a special input switch matrix (see 图 8-14) can be configured and monitored in addition to the

standard switches to GND and V_BAT. This feature could be useful to monitor a special switch input configuration

called Matrix Inputs as required by some specific OEMs.

Three different matrix configurations are possible, and are defined by MATRIX bits in the MATRIX register. If the

MATRIX bits are set to ‘00’ all inputs are treated as standard inputs with identical polling active time

according to the POLL_ACT_TIME bits in the CONFIG register. Any settings other than ‘00’ for MATRIX bits

causes the polling active time for the matrix inputs to be configured according to POLL_ACT_TIME_M bits in the

MATRIX register. Inputs that are not part of the matrix configuration will be configured using the

POLL_ACT_TIME bits in the CONFIG register. t_{POLL_ACT_TIME_M}should be configured properly to allow sufficient

time for the current source and sink to charge or discharge the capacitors (if any) connected to the switch inputs.

表8-6. TIC12400-Q1 Matrix Configuration Settings

4 x 4 MATRIX

5 x 5 MATRIX

6 x 6 MATRIX

Input

Current Source Or Polling Active Time

Current Source Or

Polling Active Time

Setting

Current Source Or

Polling Active Time

Setting

Sink

CSI

Setting

Sink

CSI

Sink

CSI

IN4

IN5

IN6

IN7

POLL_ACT_TIME_

M

POLL_ACT_TIME_M

POLL_ACT_TIME

Configurable to

CSO or CSI

IN8

IN9

CSI

POLL_ACT_TIME

Configurable to

CSO or CSI

Configurable to CSO

or CSI

POLL_ACT_TIME_M

IN10

IN11

IN12

IN13

IN14

IN15

CSO

POLL_ACT_TIME_

M

POLL_ACT_TIME_M

POLL_ACT_TIME

The TIC12400-Q1 implements a different polling scheme when matrix input is configured. After the polling

sequence is started (by setting TRIGGER bit in CONFIG register to logic 1), the polling takes place within the

matrix input group first before the rest of the standard inputs are polled. After the matrix inputs are polled, the

switch status of each input combination (below or above detection threshold) is stored internally in registers

IN_STAT_MATRIX0 and IN_STAT_MATRIX1, and it is used as the default state for subsequent matrix polling

cycles. The standard inputs follow the same polling behavior as described in section Standard Polling. After the

polling cycle is completed on matrix and standard inputs, the INT pin is asserted low to notify the microcontroller

that the default switch status is ready to be read. The SSC bit in the INT_STAT register and the SPI status flag

SSC are also asserted to logic 1.

The INT_STAT register is cleared and INT pin de-asserted if a SPI READ command is issued to the register.

Note: the interrupt is always generated after the 1st complete polling cycle (after the TRIGGER bit in register

CONFIG is set to logic 1). In subsequent polling cycles, the interrupt is generated only if switch status change is

detected.

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Note the following programming requirement when using the matrix polling:

• It is critical to program the CSO/CSI configuration for each matrix input appropriately according to 表8-6 to

avoid incorrect switch status detection.

• It is mandatory to set higher wetting current for the sinks (IN4-IN9) than the sources (IN10-IN15). The actual

current flowing through the external switches will be the lesser of the two settings. If the same setting is used

for both the sink and the source, the detected result might be incorrect. Because of this, the 15 mA setting

shall not be used for the current sources and the 1 mA setting shall not be used for the current sinks.

Depending on the type of matrix switches, the TIC12400-Q1 might require some specific wetting current

settings to be able to distinguish between switch open or closed states.

• If TW_CUR_DIS_CSO or TW_CUR_DIS_CSI is set to logic 0 in the CONFIG register, wetting current is

reduced to 2 mA for 10 mA and 15 mA settings upon TW event. Since it’s mandatory to have higher wetting

current for the sinks (IN4-IN9) than the sources (IN10-IN15) during matrix polling, 表8-7 below summarizes

the only possible settings if TW event is expected:

表8-7. Possible Wetting Current Settings for the Matrix Polling Mode if TW_CUR_DIS=0 and TW Event is

Expected

CSO (IN10-IN15)

1 mA

CSI (IN4-IN9)

2 mA, 5 mA, 10 mA, and 15 mA

5 mA

RESULTING WETTING CURRENT

1 mA

2 mA

If higher wetting current is needed and TW event might be expected, the TW wetting current reduction feature

needs to be disabled by setting TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1.

• Only comparator input mode is supported for the matrix polling. Do not program the matrix inputs into ADC

input mode. The comparison takes place on the source side (IN10-IN15) since the sink side is pulled to

ground. Interrupt generation condition can be set by configuring the INT_EN_COMP1 and INT_EN_COMP2

registers for inputs IN10 to IN15.

Some programmability is removed when matrix polling mode is used, as listed below:

• To keep the polling scheme simple, the ability to disable inputs is removed for the matrix inputs. Only 3

configurations (4×4, 5×5, and 6×6) can be used for the matrix polling. Standard inputs outside the matrix

input group can still be disabled, if desired.

• Detection filter (by configuring the DET_FILTER in the CONFIG register) does not apply to the matrix inputs,

but still applies to the standard inputs outside the matrix input group.

• When matrix polling is selected, continuous mode is not available to the standard inputs outside the matrix

input group.

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图8-15 illustrates an example of the polling sequence for the 6×6 matrix input configuration:

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

t

Wetting

current

t_{POLL_ACT_TIME_M}

t_STARTUP

IN10

IN11

IN12

IN13

IN14

IN15

IN4 to IN5 to IN6 to IN7 to IN8 to IN9 to

GND

IN0

IN1

tt_{POLL_ACT_TIME}

t

tt_ADCor t_COMP

t

IN2

IN3

IN16

IN17

IN23

/INT

/CS

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

Read on INT_STAT register

release the /INT pin

Time

图8-15. Polling Scheme for 6×6 Matrix Inputs

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图 8-16 illustrates an example of the polling sequence for the 5×5 matrix input configuration. Note: the input IN9

and IN15 are included in the standard polling sequence.

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

t

Wetting

current

t_{POLL_ACT_TIME_M}

t_STARTUP

IN10

IN11

IN12

IN13

IN14

IN0

IN4 to IN5 to IN6 to IN7 to IN8 to

GND GND GND GND GND

tt_{POLL_ACT_TIME}

t

IN1

tt_ADCor t_COMP

t

IN2

IN3

IN9

IN15

IN23

/INT

/CS

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

Read on INT_STAT register

release the /INT pin

Time

图8-16. Polling Scheme for 5×5 Matrix Inputs

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图 8-17 illustrates an example of the polling sequence for the 4×4 matrix input configuration. Note: inputs IN8,

IN9, IN14, and IN15 are included in the standard polling sequence.

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

t

Wetting

current

t_{POLL_ACT_TIME_M}

t_STARTUP

IN10

IN11

IN12

IN13

IN4 to IN5 to IN6 to IN7 to

GND GND GND GND

IN0

IN1

IN2

IN3

IN8

IN9

IN14

tt_{POLL_ACT_TIME}

t

tt_ADCor t_COMP

t

IN23

/INT

/CS

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

Read on INT_STAT register

release the /INT pin

Time

图8-17. Polling Scheme for 4×4 Matrix Inputs

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8.4.3 Additional Features

There are additional features that can be enabled during continuous and polling mode to increase robustness of

device operation or provide more system information. These features are described in detail in the following

sections.

8.4.3.1 Clean Current Polling (CCP)

To detect resistor coded switches or reduce overall power consumption of the chip, a lower wetting current

setting is recommended. However, certain system design requires 10 mA or higher cleaning current to clear

oxide build-up on the mechanical switch contact surface when the current is applied to closed switches. A

special type of polling, called the Clean Current Polling (CCP), can be used for this application.

If CCP is enabled each polling cycle consists of two wetting current activation steps. The first step uses the

wetting current setting configured in the WC_CFG0 and WC_CFG1 registers as in the continuous mode or

polling mode. The second step (cleaning cycle) is activated simultaneously for all CCP enabled inputs at a time

t_{CCP_TRAN}after the normal polling step of the last enabled input. Interrupt generation and INT pin assertion is not

impacted by the clean current pulses.

The wetting current and its active time for the cleaning cycle can be configured in the CCP_CFG0 register. The

cleaning cycle can be disabled, if desired, for each individual input by programming the CCP_CFG1 register.

CCP is available for both continuous mode and polling mode. To use the CCP feature, at least one input

(standard or matrix) or the 节8.4.3.3 has to be enabled.

Note: that although CCP can be enabled in Matrix polling mode, it is not an effective way to clean the matrix

switch contact, since the current supplied from the TIC12400-Q1 is divided and distributed across multiple matrix

channels.

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图8-18 illustrates the operation of the CCP when the device is configured to the standard polling mode.

Wetting

current

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

t

t_STARTUP

IN0

t_STARTUP

IN1

IN2

tt_ADCor t_COMP

t

tt_{CCP_TIME}

t

IN22

IN23

tt_{CCP_TRAN}

t

/INT

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

/CS

Read on INT_STAT register

release the /INT pin

Time

图8-18. Standard Polling With CCP Enabled

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图8-19 illustrates the operation of the CCP when the device is configured to the continuous mode:

Wetting

current

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

t

t_STARTUP

IN0

t_STARTUP

IN1

IN2

tt_ADCor t_COMP

t

tt_{CCP_TIME}

t

IN22

IN23

/INT

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

/CS

Read on INT_STAT register

release the /INT pin

Time

图8-19. Continue Mode With CCP Enabled

8.4.3.2 Wetting Current Auto-Scaling

The 10 mA and 15 mA wetting current settings are useful to clean oxide build-up on the mechanical switch

contact surface when the switch changes state from open to close. After the switch is closed, it is undesirable to

keep the wetting current level at high level if only digital switches are monitored since it results in high current

consumption and could potentially heat up the device quickly if multiple inputs are monitored. The wetting current

auto-scaling feature helps mitigate this issue.

When enabled (AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit = logic 0 in the WC_CFG1 register),

wetting current is reduced to 2 mA from 10 mA or 15 mA setting after switch closure is detected. The threshold

used to determine a switch closure is the threshold configured in the THRES_COMP register for inputs

configured as comparator input mode. For inputs configured as ADC input mode, the threshold used to

determine a switch closure depends on the input number, as described in 表8-8 below.

表8-8. Threshold Used to Determine a Switch Closure for Wetting Current Auto-scaling for ADC Inputs

INPUT

IN0-IN11

IN12 to IN17

IN18 to IN22

IN23

THRESHOLD USED TO DETERMINE A SWITCH CLOSURE

Mapped threshold from THRES0 to THRES7

THRES2B

THRES3C

THRES9

The current reduction takes place N cycles after switch closure is detected on an input, where N depends on the

setting of the DET_FILTER bits in the CONFIG register:

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• DET_FILTER= 00: wetting current is reduced immediately in the next detection cycle after a closed switch is

detected.

• DET_FILTER= 01: wetting current is reduced when a closed switch is detected and the switch status is stable

for at least 2 consecutive detection cycles.

• DET_FILTER= 10: wetting current is reduced when a closed switch is detected and the switch status is stable

for at least 3 consecutive detection cycles.

• DET_FILTER= 11: wetting current is reduced when a closed switch is detected and the switch status is stable

for at least 4 consecutive detection cycles.

The wetting current is adjusted back to the original setting of 10 mA or 15 mA at a time of N cycles after an open

switch is detected, where N again depends on the DET_FILTER bit setting in the CONFIG register. 图 8-20

depicts the behavior of the wetting current auto-scaling feature.

Switch open

Switch closed

Auto-scaling

disabled

15mA

0mA

Auto-scaling

enabled

2mA

图8-20. Wetting Current Auto-scaling Behavior

The wetting current auto-scaling only applies to 10 mA and 15 mA settings and is only available in continuous

mode. If AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit is set to logic 1 in the WC_CFG1 registers,

the wetting current stays at its original setting when a closed switch is detected. Power dissipation needs to be

closely monitored when wetting current auto-scaling is disabled for multiple inputs as the device could heat up

quickly when high wetting current settings are used. If the auto-scaling feature is disabled in continuous mode,

the total power dissipation can be approximated using 方程式1.

P

=V_Sì

(

I_{S _CONT}+ I_{WETT (TOTAL)}

)

TOTAL

(1)

where I_{WETT (TOTAL)}is the sum of all wetting currents from all input channels. Increase in device junction

temperature can be calculated based on P × R_θJA. The junction temperature must be below T_TSDfor proper

device operation. An interrupt will be issued when the junction temperature exceeds T_TWor T_TSD. For detailed

description of the temperature monitoring, please refer to sections Temperature Warning (TW) and Temperature

Shutdown (TSD).

8.4.3.3 V_SMeasurement

When the TIC12400-Q1 is used to monitor resistor-coded switches, the V_Ssupply voltage level becomes critical.

If V_Sis not sufficiently high, the device might not have enough headroom to produce accurate wetting currents.

This could impact the accuracy of the switch status monitoring. It is imperative for the microcontroller to have

knowledge of the V_Svoltage on a constant basis in such a case.

Measurement of V_Svoltage is a feature in TIC12400-Q1 that can be enabled by setting the VS_MEAS_EN bit in

register CONFIG to logic 1. If enabled, at the end of every detection and polling cycle, the voltage on the V_Spin

is sampled and converted by the ADC to a digital value. The conversion takes one extra t_ADC, and the converted

value is recorded in the ANA_STAT12 register.

The V_Smeasurement supports two different V_Svoltage ranges that can be configured by the VS_RATIO bit in

the CONFIG register. By default (VS_RATIO= logic 0), the supported V_Svoltage range is from 4.5 V to 9 V, and

V_Svoltage in excess of 9 V results in a saturated ADC raw code of 1023. This setting provides better

measurement resolution at lower V_Svoltages. When VS_RATIO bit is set to logic 1, the supported V_Svoltage

range is widened to 4.5 V to 30 V, and V_Svoltage in excess of 30 V results in a saturated ADC raw code of

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1023. This setting allows wider measurement range but more coarse measurement resolution. It is important to

adjust the detection thresholds accordingly depending on the V_Svoltage range configured.

Four different measurement thresholds can be programmed by the TIC12400-Q1: VS0_THRES2A/B and

VS1_THRES2A/B. The value of these thresholds can be programmed by configuring registers THRES_CFG0 to

THRES_CFG3 and the mapping can be programmed by configuring registers THRESMAP_VS0_THRES2A/B

and THRESMAP_VS1_THRES2A/B bits in the register THRESMAP_CFG2. When setting the thresholds follow

the rules in 表8-9 below.

表8-9. Proper Threshold Configuration for V_SMeasurements

V_STHRESHOLD

PROPER THRESHOLD CONFIGURATION

VS0_THRES2B ≥VS0_THRES2A

VS1_THRES2B ≥VS1_THRES2A

VS0

VS1

After the V_Smeasurement is enabled for the first time, the V_Smeasurement interrupt is always generated ( INT

pin is asserted low, and the VS0 or VS1 bit in the INT_STAT register is flagged to logic 1) at the end of the first

polling cycle to notify the microcontroller the initial V_Smeasurement result is ready to be retrieved. The

VS0_STAT and VS1_STAT bits from register IN_STAT_MISC indicate the status of the V_Svoltage with respect to

the thresholds, and the ANA_STAT12 register stores the converted digital value of the V_Svoltage. The SPI

status flag VS_TH is also asserted to logic 1 during SPI communications. Note the status detected in the first

polling cycle becomes the baseline value of comparison for subsequent V_Smeasurements and the interrupt will

be generated only if threshold crossing is detected.

Similar to regular inputs, the interrupt generation conditions can be programmed by setting the VS_TH0_EN and

VS_TH1_EN bits in the INT_EN_CFG4 register to the following settings:

1. Rising edge: an interrupt is generated if the current V_Smeasurement is above the corresponding threshold

and the previous measurement was below.

2. Falling edge: an interrupt is generated if the current V_Smeasurement is below the corresponding threshold

and the previous measurement was above.

3. Both edges: changes of the V_Smeasurement status in either direction results in an interrupt generation.

Interrupt generation can also be disabled by setting VS_TH0_EN or VS_TH1_EN to logic 0 in register

INT_EN_CFG4. Once disabled, V_Svoltage crossing does not flag the VS0 or VS1 bit in INT_STAT register and

does not assert INT pin low. To only mask the INT pin from assertion (while keeping INT_STAT register

updated), configure the VS1_EN and VS0_EN bits in register INT_EN_CFG0 to logic 0.

Note the V_Smeasurement is only intended to be used as part of switch detection sequence to determine the

validity of the switch detection states that are reported by the TIC12400-Q1. It is not intended to be used for

standalone supply monitoring, such as monitoring cranking voltages, due to the potentially delayed response

being part of the polling sequence. The V_Smeasurement result is accurate for V_Sabove 4.5 V.

By default, the V_Svoltage measurement is disabled upon device reset.

8.4.3.4 Wetting Current Diagnostic

When the TIC12400-Q1 is used to monitor safety-critical switches, it may be valuable for the microcontroller to

have knowledge of the operating status of the wetting current sources and sinks. This can be achieved by

activating the wetting current diagnostic feature provided for inputs IN0 to IN3. IN0 and IN1 can be diagnosed for

defective wetting current sources, while IN2 and IN3 can be diagnosed for defective current sinks.

The wetting current diagnostic feature can be activated by setting the WET_D_INx_EN bits in the CONFIG

register to 1 for the desired inputs, where x can be 0, 1, 2, or 3. If activated, the TIC12400-Q1 checks the status

of the wetting current sources and sinks for the configured input periodically as part of the polling sequence. If

the wetting current is determined to be flawed, the TIC12400-Q1 pulls the INT pin low to notify the host and flag

the WET_DIAG bit in the INT_STAT register to logic 1. The OI bit in the SPI flag is also asserted during SPI

transactions. The microcontroller can then read bits IN0_D to IN3_D in register IN_STAT_MISC to learn more

information on which wetting current source/sink is defective.

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The wetting current diagnostic is not performed for inputs that are disabled (IN_EN_x bit = 0 in the IN_EN

register) from polling, even if the feature is activated for those inputs. Also, it is critical to configure the current

source/sink appropriately (CSO for IN0 and IN1, and CSI for IN2 and IN3) and program the input to ADC input

mode before activating the wetting current diagnostic feature to prevent false interrupts from being generated.

The wetting current diagnostic feature can be performed regardless of the states of external switches, and it is

available in both continuous mode and polling mode.

图 8-21 shows an example of the feature carried out in a typical polling sequence. In this example, it can be

observed that the wetting current is activated for duration of t_{POLL_ACT}+ t_ADCfor each input diagnosed (IN0 or

IN2). Normal polling sequence resumes with IN4 and the wetting current is activated for t_{POLL_ACT}for the rest of

the inputs. The diagnostic is not executed on inputs IN1 and IN3 in this example since they are disabled.

Wetting current is activated for

Input sampling restarts

t_{POLL_ACT_TIME}+ t_ADC(or t_COMP) for

channels with WCD enabled

Wetting

current

from first enabled input

after t_{POLL_TIME}

TRIGGER bit set

to logic 1 in

CONFIG register

tt_{POLL_TIME}

tt_ADCor t_COMP

t

tt_STARTUP

t

tt_{POLL_ACT_TIME}

t

tt_STARTUP

t

IN0

IN2

IN4

tt_ADCor t_COMP

t

tt_ADCor t_COMP

t

IN23

/INT

ñ Default input status is stored

ñ /INT pin is asserted after the

1^stdetection cycle

tt_ADCor t_COMP

t

Time

图8-21. An Example of the Polling Sequence in Standard Polling Mode With Wetting Current Diagnostic

Enabled

8.4.3.5 ADC Self-Diagnostic

In addition to the wetting current diagnostic, another feature– the ADC self-diagnostic, can be enabled to

monitor the integrity of the internal ADC.

The ADC self-diagnostic feature is activated by setting the ADC_DIAG_T bit in the CONFIG register to logic 1.

Once enabled, the TIC12400-Q1 periodically sends a test voltage to the ADC. The conversion result is stored in

the ADC_SELF_ANA bits in the register ANA_STAT12 and is compared with a pre-defined code to determine

whether the conversion is performed properly. If an error is detected, the TIC12400-Q1 pulls the INT pin low to

notify the host and flag the ADC_DIAG bit in the INT_STAT to logic 1. The bit ADC_D in register IN_STAT_MISC

is updated with the result from the self-diagnostic. The ADC self-diagnostic feature is available in both

continuous mode and polling mode.

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8.5 Programming

The SPI interface communication consists of the 4 pins: CS, SCLK, SI, and SO. The interface can work with

SCLK frequency up to 4 MHz.

8.5.1 SPI Communication Interface Buses

8.5.1.1 Chip Select ( CS)

The system microcontroller selects the TIC12400-Q1 to receive communication using the CS pin. With the CS

pin in a logic LOW state, command words may be sent to the TIC12400-Q1 through the serial input (SI) pin, and

the device information can be retrieved by the microcontroller via the serial output (SO) pin. The falling edge of

the CS enables the SO output and latches the content of the interrupt register INT_STAT. The microcontroller

may issue a READ command to retrieve information stored in the registers. Rising edge on the CS pin initiates

the following operations:

1. Disable the output driver and makes SO high-impedance.

2. INT pin is reset to logic HIGH if a READ command to the INT_STAT register was issued during CS = LOW.

To avoid corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur

only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure no incomplete SPI words are

sent to the device. The CS pin should be externally pulled up to VDD by a 10 kΩresistor.

8.5.1.2 System Clock (SCLK)

The system clock (SCLK) input is used to clock the internal shift register of the TIC12400-Q1. The SI data is

latched into the input shift register on the falling edge of the SCLK signal. The SO pin shifts the device stored

information out on the rising edge of SCLK. The SO data is available for the microcontroller to read on the falling

edge of SCLK.

False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be

in a logic LOW state whenever CS makes any transition. Therefore, it is recommended that the SCLK pin gets

pulled to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS

is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin remains as a high

impedance output. Refer to 图8-22 and 图8-23 for examples of typical SPI read and write sequence.

8.5.1.3 Slave In (SI)

The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling

edge of the SCLK. To program a complete word, 32 bits of information must be entered into the device. The SPI

logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been

clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit of the

INT_STAT register is asserted to logic 1 and the INT pin will be asserted low. The data received is considered

invalid. Note the SPI_FAIL bit is not flagged if SCLK is not present.

8.5.1.4 Slave Out (SO)

The SO pin is the output from the internal shift register. The SO pin remains high-impedance until the CS pin

transitions to a logic LOW state. The negative transition of CS enables the SO output driver and drives the SO

output to the HIGH state (by default). The first positive transition of SCLK makes the status data bit 31 available

on the SO pin. Each successive positive clock makes the next status data bit available for the microcontroller to

read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in, first-out scheme, with both

input and output words transferring the most significant bit (MSB) first.

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8.5.2 SPI Sequence

图8-22 and 图8-23 depict the SPI communication sequence during read and write operations for the TIC12400-

Q1.

Bit 31

(MSB)

Bit 0

(LSB)

...

Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22

Bit 1

Read/

Write

SI

Register address

Data in

PAR

0

Bit 31

(MSB)

Bit 0

(LSB)

...

Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22

Bit 1

SO

Status flag

Data out

PAR

SPI_ PRTY_

POR

SSC VS_TH TEMP

OI

FAIL

图8-22. TIC12400-Q1 Read SPI Sequence

Bit 31

(MSB)

Bit 0

(LSB)

...

Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22

Bit 1

Read/

Write

SI

Register address

Data in

PAR

1

Bit 31

(MSB)

Bit 0

(LSB)

Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22

Bit 1

SO

Status flag

Previous content of the

register addressed

PAR

SPI_ PRTY_

FAIL FAIL

POR

SSC VS_TH TEMP

OI

图8-23. TIC12400-Q1 Write SPI Sequence

8.5.2.1 Read Operation

The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of

the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent a valid

command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication

errors.

On the SO bus, the status flags will be outputted from the TIC12400-Q1, followed by the data content in the

register that was requested. The LSB is the parity bit used to detect communication errors.

Note there are several test mode registers used in the TIC12400-Q1 in addition to the normal functional

registers, and a READ command to these test registers returns the register content. If a READ command is

issued to an invalid register address, the TIC12400-Q1 returns all 0s.

8.5.2.2 Write Operation

The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of the

register to be accessed follows next on the SI bus. Note: the register needs to be a writable configuration

register, or otherwise the command will be ignored. The content from bit 24 to bit 1 represents the data to be

written to the register. The LSB (bit 0) is the parity bit used to detect communication errors.

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On the SO bus, the status flags will be output from the TIC12400-Q1, followed by the previous data content of

the written register. The previous content of the register is latched after the full register address is decoded in the

SI command (after bit 25 is transmitted). The new data will replace the previous data content at the end of the

SPI transaction if the SI write is a valid command (valid register address and no SPI/parity error). If the write

command is invalid, the new data will be ignored and the register content will remain unchanged. The LSB is the

parity bit used to detect communication errors.

Note: there are several test mode registers used in the TIC12400-Q1 in addition to the normal functional

registers. A WRITE command to these test registers has no effect on the register content, even though the

register content is returned on the SO output. If a WRITE command is issued to an invalid register address, the

SO output returns all 0s.

8.5.2.3 Status Flag

The status flags are output from SO during every READ or WRITE SPI transaction to indicate system conditions.

These bits do not belong to an actual register, but their content is mirrored from the interrupt register INT_STAT.

A READ command executed on the INT_STAT would clear both the bits inside the register and the status flag.

The following table describes the information that can be obtained from each SPI status flag:

表8-10. TIC12400-Q1 SPI Status Flag Description

SYMBOL

NAME

DESCRIPTION

This flag mirrors the POR bit in the interrupt register INT_STAT, and it indicates, if set to 1, that a reset event has

occurred. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. Refer to 节

8.3.5 for more details.

POR

Power-on Reset

This flag mirrors the SPI_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI

responder in (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into

the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly

32 bits have been clocked in. In case the word length exceeds or does not meet the required size, the SPI_FAIL

bit, which mirrors its value to this SPI_FAIL status flag, of the interrupt register INT_STAT will be set to 1 and the

INT pin will be asserted low. The data received will be considered invalid. Once the INT_STAT register is read, its

content will be cleared on the rising edge of CS. The SPI_FAIL status flag, which mirrors the SPI_FAIL bit in the

INT_STAT register, will also be de-asserted. Note the SPI_FAIL bit is not flagged if SCLK is not present.

SPI_FAIL

SPI Error

This flag mirrors the PRTY_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI

responder in (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the

received data (including the parity bit) is an even number, the received data is discarded. The INT will be

asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1, and the

PRTY_FAIL status flag, which mirrors the PRTY_FAIL bit in the INT_STAT register, is also set to 1. Once the

INT_STAT register is read, its content will be cleared on the rising edge of CS. The PRTY_FAIL status flag, which

mirrors the PRTY_FAIL bit in the INT_STAT register, will also be de-asserted.

PRTY_FAIL

Parity Fail

This flag mirrors the SSC bit in the interrupt register INT_STAT and it indicates, if set to 1, that one or more switch

inputs crossed a threshold. To determine the origin of the state change, the microcontroller can read the content

of registers IN_STAT_COMP (if input is set to comparator input mode), IN_STAT_ADC0 to IN_STAT_ADC1 (if

input is set to ADC input mode), or IN_STAT_MATRIX0 to IN_STAT_MATRIX1 (if input is set to matrix input).

Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge of CS. The SSC

status flag, which mirrors the SSC bit in the INT_STAT register, will also be de-asserted.

SSC

VS_TH

TEMP

Switch State Change

This flag is set to 1 if either VS0 or VS1 bit in the interrupt register INT_STAT is flagged to 1. It indicates the V_S

voltage crosses one or more thresholds defined by VS0_THRES2A, VS0_THRES2B, VS1_THRES2A, or

V_SThreshold Crossing VS1_THRES2B. To determine the origin of the threshold crossing, the microcontroller can read register bits

VS0_STAT and VS1_STAT in the register IN_STAT_MISC. Once the interrupt register (INT_STAT) is read, its

content will be cleared on the rising edge of CS, and the VS_TH status flag will also be de-asserted.

This flag is set to 1 if either Temperature Warning (TW) or Temperature Shutdown (TSD) bit in the interrupt

register INT_STAT is flagged to 1. It indicates a TW event or a TSD event has occurred. It is also flagged to 1 if a

TW event or a TSD event is cleared. The interrupt register INT_STAT should be read to determine which event

Temperature Event

occurred. The SPI controller can also read the IN_STAT_MISC register to get information on the temperature

status of the device. Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge

of CS, and the TEMP status flag will also be de-asserted.

Other interrupt include interrupts such as OV, UV, CRC_CALC. WET_DIAG, ADC_DIAG and CHK_FAIL. This

flag will be asserted 1 when any of the above mentioned bits is flagged in the interrupt register INT_STAT. The

interrupt register INT_STAT should be read to determine which one or more events occurred. The SPI controller

can also read the IN_STAT_MISC register to get information on the latest status of the device. Once the

OI

Other Interrupt

INT_STAT register is read, its content will be cleared on the rising edge of CS, and the OI status flag will also be

de-asserted.

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8.6 Register Maps

表 8-11 lists the memory-mapped registers for the TIC12400-Q1. All register offset addresses not listed in 表

8-11 should be considered as reserved locations and the register contents should not be modified.

表8-11. TIC12400-Q1 Registers

OFFSET

1h

TYPE

R

RESET

20h

ACRONYM

REGISTER NAME

SECTION

Go

DEVICE_ID

INT_STAT

Device ID Register

2h

RC

R

1h

Interrupt Status Register

CRC Result Register

Go

3h

FFFFh CRC

Go

4h

R

0h

IN_STAT_MISC

IN_STAT_COMP

Miscellaneous Status Register

Comparator Status Register

Go

5h

R

Go

6h-7h

8h-9h

R

IN_STAT_ADC0, IN_STAT_ADC1 ADC Status Register

Go

R

IN_STAT_MATRIX0,

IN_STAT_MATRIX1

Matrix Status Register

Go

Ah-16h

17h-19h

1Ah

R

0h

ANA_STAT0- ANA_STAT12

RESERVED

ADC Raw Code Register

Go

RESERVED

—

0h

—

R/W

CONFIG

Device Global Configuration Register

Input Enable Register

Go

1Bh

IN_EN

1Ch

CS_SELECT

Current Source/Sink Selection Register

Wetting Current Configuration Register

Clean Current Polling Register

Comparator Threshold Control Register

1Dh-1Eh

1Fh-20h

21h

WC_CFG0, WC_CFG1

CCP_CFG0, CCP_CFG1

THRES_COMP

22h-23h

INT_EN_COMP1,

INT_EN_COMP2

Comparator Input Interrupt Generation Control

Register

24h

R/W

0h

INT_EN_CFG0

Global Interrupt Generation Control Register

Go

25h-28h

INT_EN_CFG1- INT_EN_CFG4

ADC Input Interrupt Generation Control

Register

29h-2Dh

2Eh- 30h

R/W

0h

THRES_CFG0- THRES_CFG4

ADC Threshold Control Register

ADC Threshold Mapping Register

Go

THRESMAP_CFG0-

THRESMAP_CFG2

31h

32h

R/W

0h

Matrix

Mode

Matrix Setting Register

Mode Setting Register

Go

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8.6.1 DEVICE_ID Register (Offset = 1h) [Reset = 20h]

DEVICE_ID is shown in 图8-24 and described in 表8-12.

Return to Summary Table.

This register represents the device ID of the TIC12400-Q1.

图8-24. DEVICE_ID Register

23

22

10

21

9

20

8

19

18

RESERVED

R-0h

17

16

15

3

14

2

13

1

12

0

11

7

6

5

4

RESERV

ED

MAJOR

MINOR

R-0h

R-2h

LEGEND: R = Read only

表8-12. DEVICE_ID Register Field Descriptions

Bit

Field

Type

Reset

Description

23-11

RESERVED

R

0h

RESERVED

10-4

MAJOR

R

2h

These 7 bits represents major revision ID. For TIC12400-Q1 the

major revision ID is 2h.

3-0

MINOR

R

0h

These 4 bits represents minor revision ID. For TIC12400-Q1 the

minor revision ID is 0h

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8.6.2 INT_STAT Register (Offset = 2h) [reset = 1h]

INT_STAT is shown in 图8-25 and described in 表8-13.

Return to Summary Table.

This register records the information of the event as it occurs in the device. A READ command executed on this

register clears its content and resets the register to its default value. The INT pin is released at the rising edge of

the CS pin from the READ command.

图8-25. INT_STAT Register

23

22

21

20

19

18

17

16

RESERVED

R-0h

15

14

13

12

11

10

9

8

RESERVED

R-0h

CHK_FAIL

RC-0h

ADC_DIAG

RC-0h

WET_DIAG

RC-0h

VS1

VS0

CRC_CALC

RC-0h

7

6

5

4

3

2

1

0

UV

OV

TW

TSD

SSC

RC-0h

PRTY_FAIL

RC-0h

SPI_FAIL

RC-0h

POR

RC-1h

RC-0h

LEGEND: R = Read only; RC = Read to clear

表8-13. INT_STAT Register Field Descriptions

Bit

Field

Type

Reset

Description

23-14

RESERVED

R

0h

RESERVED

13

CHK_FAIL

RC

0h

0h = Default factory setting is successfully loaded upon device

initialization or the event status got cleared after a READ command

was executed on the INT_STAT register.

1h = An error is detected when loading factory settings into the

device upon device initialization.

During device initialization, factory settings are programmed into the

device to allow proper device operation. The device performs a self-

check after the device is programmed to diagnose whether correct

settings are loaded. If the self-check returns an error, the CHK_FAIL

bit is flagged to logic 1 along with the POR bit. The host controller is

then recommended to initiate a software reset (see section Software

Reset) to re-initialize the device and allow correct settings to be re-

programmed.

12

ADC_DIAG

RC

0h

0h = No ADC self-diagnostic error is detected or the event status got

cleared after a READ command was executed on the INT_STAT

register.

1h = ADC self-diagnostic error is detected.

The ADC Self-Diagnostic feature (see section ADC Self-Diagnostic)

can be activated to monitor the integrity of the internal ADC. The

ADC_DIAG bit is flagged to logic 1 if an ADC error is diagnosed.

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表8-13. INT_STAT Register Field Descriptions (continued)

Bit

Field

WET_DIAG

Type

Reset

Description

11

RC

0h

0h = No wetting current error is detected, or the event status got

cleared after a READ command was executed on the INT_STAT

register.

1h = Wetting current error is detected.

The Wetting Current Diagnostic feature (see section Wetting Current

Diagnostic) can be activated to monitor the integrity of the internal

current sources or sinks. The WET_DIAG bit is flagged to logic 1 if a

wetting current error is diagnosed.

10

VS1

RC

0h

0h = No V_Svoltage state change occurred with respect to

VS1_THRES2A or VS1_THRES2B or the status got cleared after a

READ command was executed on the INT_STAT register.

1h = V_Svoltage state change occurred with respect to

VS1_THRES2A or VS1_THRES2B.

The VS1 interrupt bit indicates whether V_Svoltage state change

occurred with respect to thresholds VS1_THRES2A and

VS1_THRES2B if the V_SMeasurement feature (see section VS

Measurement) is activated.

9

VS0

RC

0h

0h = No V_Svoltage state change occurred with respect to

VS0_THRES2A or VS0_THRES2B or the status got cleared after a

READ command was executed on the INT_STAT register.

1h = V_Svoltage state change occurred with respect to

VS0_THRES2A or VS0_THRES2B.

The VS0 interrupt bit indicates whether V_Svoltage state change

occurred with respect to thresholds VS0_THRES2A and

VS0_THRES2B if the V_SMeasurement feature (see section VS

Measurement) is activated.

8

7

6

CRC_CALC

RC

0h

0h = CRC calculation is running, not started, or was acknowledged

after a READ command was executed on the INT_STAT register.

1h = CRC calculation is finished.

CRC calculation (see section Cyclic Redundancy Check (CRC)) can

be triggered to make sure correct register values are programmed

into the device. Once the calculation is completed, the CRC_CALC

bit is flagged to logic 1 to indicate completion of the calculation, and

the result can then be accessed from the CRC (offset = 3h) register.

UV

0h = No under-voltage condition occurred or cleared on the V_Spin,

or the event status got cleared after a READ command was

executed on the INT_STAT register.

1h = Under-voltage condition occurred or cleared on the V_Spin.

When the UV bit is flagged to logic 1, it indicates the Under-Voltage

(UV) event has occurred. The bit is also flagged to logic 1 when the

event clears. For more details about the UV operation, please refer

to section VS under-voltage (UV) condition.

OV

0h = No over-voltage condition occurred or cleared on the V_Spin, or

the event status got cleared after a READ command was executed

on the INT_STAT register.

1h = Over-voltage condition occurred or cleared on the V_Spin.

When the OV bit is flagged to logic 1, it indicates the Over-Voltage

(OV) event has occurred. The bit is also flagged to logic 1 when the

event clears. For more details about the OV operation, please refer

to section VS over-voltage (OV) condition.

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表8-13. INT_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

TW

RC

0h

0h = No temperature warning event occurred or the event status got

cleared after a READ command was executed on the INT_STAT

register.

1h = Temperature warning event occurred or cleared.

When the TW bit is flagged to logic 1, it indicates the temperature

warning event has occurred. The bit is also flagged to logic 1 when

the event clears. For more details about the temperature warning

operation, please refer to section Temperature Warning (TW)

4

TSD

RC

0h

0h = No temperature Shutdown event occurred or the event status

got cleared after a READ command was executed on the INT_STAT

register.

1h = Temperature Shutdown event occurred or cleared.

When the TSD bit is flagged to logic 1, it indicates the temperature

shutdown event has occurred. The bit is also flagged to logic 1 when

the event clears. For more details about the temperature shutdown

operation, please refer to section Temperature shutdown (TSD)

3

SSC

RC

0h

0h = No switch state change occurred or the status got cleared after

a READ command was executed on the INT_STAT register.

1h = Switch state change occurred.

The Switch State Change (SSC) bit indicates whether input threshold

crossing has occurred from switch inputs IN0 to IN23. This bit is also

flagged to logic 1 after the first polling cycle is completed after device

polling is triggered.

2

PRTY_FAIL

RC

0h

0h = No parity error occurred in the last received SI stream or the

error status got cleared after a READ command was executed on the

INT_STAT register.

1h = Parity error occurred.

When the PRTY_FAIL bit is flagged to logic 1, it indicates the last

SPI responder in (SI) transaction has a parity error. The device uses

odd parity. If the total number of ones in the received data (including

the parity bit) is an even number, the received data is discarded. The

value of this register bit is mirrored to the PRTY_FLAG SPI status

flag.

1

SPI_FAIL

RC

0h

0h = 32 clock pulse during a CS = low sequence was detected or the

error status got cleared after a READ command was executed on the

INT_STAT register.

1h = SPI error occurred

When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI

responder in (SI) transaction is invalid. To program a complete word,

32 bits of information must be entered into the device. The SPI logic

counts the number of bits clocked into the IC and enables data

latching only if exactly 32 bits have been clocked in. In case the word

length exceeds or does not meet the required length, the SPI_FAIL

bit is flagged to logic 1, and the data received is considered invalid.

The value of this register bit is mirrored to the SPI_FLAG SPI status

flag. Note the SPI_FAIL bit is not flagged if SCLK is not present.

52

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表8-13. INT_STAT Register Field Descriptions (continued)

Bit

Field

POR

Type

Reset

Description

0

RC

1h

0h = no Power-On-Reset (POR) event occurred or the status got

cleared after a READ command was executed on the INT_STAT

register.

1h = Power-On-Reset (POR) event occurred.

The Power-On-Reset (POR) interrupt bit indicates whether a reset

event has occurred. A reset event sets the registers to their default

values and re-initializes the device state machine. This bit is

asserted after a successful power-on-reset, hardware reset, or

software reset. The value of this register bit is mirrored to the POR

SPI status flag.

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8.6.3 CRC Register (Offset = 3h) [Reset = FFFFh]

CRC is shown in 图8-26 and described in 表8-14.

Return to Summary Table.

This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its

own calculated value to ensure correct register settings are programmed to the device.

图8-26. CRC Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

CRC

R-FFFFh

LEGEND: R = Read only

表8-14. CRC Register Field Descriptions

Bit

Field

Type

Reset

Description

23-16

RESERVED

R

0h

Reserved

15-0

CRC

R

FFFFh

CRC-16-CCITT calculation result: Bit1: LSB of CRC Bit16: MSB or

CRC

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8.6.4 IN_STAT_MISC Register (Offset = 4h) [Reset = 0h]

IN_STAT_MISC is shown in 图8-27 and described in 表8-15.

Return to Summary Table.

This register indicates current device status unrelated to switch input monitoring.

图8-27. IN_STAT_MISC Register

23

15

7

22

21

13

5

20

19

18

17

16

RESERVED

R-0h

14

12

11

10

9

8

RESERVED

R-0h

ADC_D

R-0h

IN3_D

R-0h

IN2_D

R-0h

IN1_D

R-0h

IN0_D

R-0h

6

4

3

2

1

0

VS1_STAT

VS0_STAT

R-0h

UV_STAT

R-0h

OV_STAT

R-0h

TW_STAT

R-0h

TSD_STAT

R-0h

表8-15. IN_STAT_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

23-13

12

RESERVED

R

0h

Reserved

ADC_D

R

0h

0h = No error is identified from ADC self-diagnostic.

1h = An error is identified from ADC self-diagnostic.

11

10

9

IN3_D

0h = Current sink on IN3 is operational.

1h = Current sink on IN3 is abnormal.

IN2_D

0h = Current sink on IN2 is operational.

1h = Current sink on IN2 is abnormal.

IN1_D

0h = Current source on IN1 is operational.

1h = Current source on IN1 is abnormal.

8

IN0_D

0h = Current source on IN0 is operational.

1h = Current source on IN0 is abnormal.

7-6

VS1_STAT

0h = V_Svoltage is below threshold VS1_THRES2A.

1h = V_Svoltage is below threshold VS1_THRES2B and equal to or

above threshold VS1_THRES2A.

2h = V_Svoltage is equal to or above threshold VS1_THRES2B.

3h = N/A.

5-4

VS0_STAT

R

0h

0h = V_Svoltage is below threshold VS0_THRES2A.

1h = V_Svoltage is below threshold VS0_THRES2B and equal to or

above threshold VS0_THRES2A.

2h = V_Svoltage is equal to or above threshold VS0_THRES2B.

3h = N/A

3

2

1

UV_STAT

OV_STAT

TW_STAT

R

0h

0h = V_Svoltage is above the under-voltage condition threshold.

1h = V_Svoltage is below the under-voltage condition threshold.

0h = V_Svoltage is below the over-voltage condition threshold.

1h = V_Svoltage is above the over-voltage condition threshold.

0h = Device junction temperature is below the temperature warning

threshold T_TW

1h = Device junction temperature is above the temperature warning

threshold T_TW

.

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表8-15. IN_STAT_MISC Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0h = Device junction temperature is below the temperature shutdown

threshold T_TSD

1h = Device junction temperature is above the temperature shutdown

threshold T_TSD

0

TSD_STAT

R

0h

.

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8.6.5 IN_STAT_COMP Register (Offset = 5h) [Reset = 0h]

IN_STAT_COMP is shown in 图8-28 and described in 表8-16.

Return to Summary Table.

This register indicates whether an input is below or above the comparator threshold when it is configured as

comparator input mode.

图8-28. IN_STAT_COMP Register

23

22

21

20

19

18

17

16

INC_23

R-0h

INC_22

R-0h

INC_21

R-0h

INC_20

R-0h

INC_19

R-0h

INC_18

R-0h

INC_17

R-0h

INC_16

R-0h

15

14

13

12

11

10

9

8

INC_15

R-0h

INC_14

R-0h

INC_13

R-0h

INC_12

R-0h

INC_11

R-0h

INC_10

R-0h

INC_9

R-0h

INC_8

R-0h

7

6

5

4

3

2

1

0

INC_7

R-0h

INC_6

R-0h

INC_5

R-0h

INC_4

R-0h

INC_3

R-0h

INC_2

R-0h

INC_1

R-0h

INC_0

R-0h

LEGEND: R = Read only

表8-16. IN_STAT_COMP Register Field Descriptions

Bit

Field

Type

Reset

Description

23

INC_23

R

0h

0h = Input IN23 is below the comparator threshold.

1h = Input IN23 is above the comparator threshold.

22

21

20

19

18

17

16

15

14

13

12

11

INC_22

INC_21

INC_20

INC_19

INC_18

INC_17

INC_16

INC_15

INC_14

INC_13

INC_12

INC_11

R

0h

0h = Input IN22 is below the comparator threshold.

1h = Input IN22 is above the comparator threshold.

0h = Input IN21 is below the comparator threshold.

1h = Input IN21 is above the comparator threshold.

0h = Input IN20 is below the comparator threshold.

1h = Input IN20 is above the comparator threshold.

0h = Input IN19 is below the comparator threshold

1h = Input IN19 is above the comparator threshold

0h = Input IN18 is below the comparator threshold

1h = Input IN18 is above the comparator threshold

0h = Input IN17 is below the comparator threshold

1h = Input IN17 is above the comparator threshold

0h = Input IN16 is below the comparator threshold

1h = Input IN16 is above the comparator threshold

0h = Input IN15 is below the comparator threshold

1h = Input IN15 is above the comparator threshold

0h = Input IN14 is below the comparator threshold

1h = Input IN14 is above the comparator threshold

0h = Input IN13 is below the comparator threshold

1h = Input IN13 is above the comparator threshold

0h = Input IN12 is below the comparator threshold

1h = Input IN12 is above the comparator threshold

0h = Input IN11 is below the comparator threshold

1h = Input IN11 is above the comparator threshold

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表8-16. IN_STAT_COMP Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

10

INC_10

R

0h

0h = Input IN10 is below the comparator threshold

1h = Input IN10 is above the comparator threshold

9

8

7

6

5

4

3

2

1

0

INC_9

INC_8

INC_7

INC_6

INC_5

INC_4

INC_3

INC_2

INC_1

INC_0

R

0h

0h = Input IN9 is below the comparator threshold

1h = Input IN9 is above the comparator threshold

0h = Input IN8 is below the comparator threshold

1h = Input IN8 is above the comparator threshold

0h = Input IN7 is below the comparator threshold

1h = Input IN7 is above the comparator threshold

0h = Input IN6 is below the comparator threshold

1h = Input IN6 is above the comparator threshold

0h = Input IN5 is below the comparator threshold

1h = Input IN5 is above the comparator threshold

0h = Input IN4 is below the comparator threshold

1h = Input IN4 is above the comparator threshold

0h = Input IN3 is below the comparator threshold

1h = Input IN3 is above the comparator threshold

0h = Input IN2 is below the comparator threshold

1h = Input IN2 is above the comparator threshold

0h = Input IN1 is below the comparator threshold

1h = Input IN1 is above the comparator threshold

0h = Input IN0 is below the comparator threshold

1h = Input IN0 is above the comparator threshold

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8.6.6 IN_STAT_ADC0 Register (Offset = 6h) [Reset = 0h]

IN_STAT_ADC0 is shown in 图8-29 and described in 表8-17.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold (for IN0-IN11) when it is

configured as ADC input mode. For IN12-IN17, there are 2 thresholds and the register bits indicate whether the

input is below, above or in-between the 2 thresholds.

图8-29. IN_STAT_ADC0 Register

23

22

21

20

19

18

17

16

INA_17

R-0h

INA_16

R-0h

INA_15

R-0h

INA_14

R-0h

15

14

13

12

11

10

9

8

INA_13

R-0h

INA_12

R-0h

INA_11

R-0h

INA_10

R-0h

INA_9

R-0h

INA_8

R-0h

7

6

5

4

3

2

1

0

INA_7

R-0h

INA_6

R-0h

INA_5

R-0h

INA_4

R-0h

INA_3

R-0h

INA_2

R-0h

INA_1

R-0h

INA_0

R-0h

LEGEND: R = Read only

表8-17. IN_STAT_ADC0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-22

INA_17

R

0h

0h = Input IN17 is below threshold 2A

1h = Input IN17 is below threshold 2B and equal to or above

threshold 2A

2h = Input IN17 is equal to or above threshold 2B

3h = N/A

21-20

19-18

17-16

15-14

INA_16

INA_15

INA_14

INA_13

R

0h

0h = Input IN16 is below threshold 2A

1h = Input IN16 is below threshold 2B and equal to or above

threshold 2A

2h = Input IN16 is equal to or above threshold 2B

3h = N/A

0h = Input IN15 is below threshold 2A

1h = Input IN15 is below threshold 2B and equal to or above

threshold 2A

2h = Input IN15 is equal to or above threshold 2B

3h = N/A

0h = Input IN14 is below threshold 2A

1h = Input IN14 is below threshold 2B and equal to or above

threshold 2A

2h = Input IN14 is equal to or above threshold 2B

3h = N/A

0h = Input IN13 is below threshold 2A

1h = Input IN13 is below threshold 2B and equal to or above

threshold 2A

2h = Input IN13 is equal to or above threshold 2B

3h = N/A

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表8-17. IN_STAT_ADC0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13-12

INA_12

R

0h

0h = Input IN12 is below threshold 2A

1h = Input IN12 is below threshold 2B and equal to or above

threshold 2A

2h = Input IN12 is equal to or above threshold 2B

3h = N/A

11

10

9

INA_11

INA_10

INA_9

INA_8

INA_7

INA_6

INA_5

INA_4

INA_3

INA_2

INA_1

INA_0

R

0h

0h = Input IN11 is below configured threshold

1h = Input IN11 is above configured threshold

0h = Input IN10 is below configured threshold

1h = Input IN10 is above configured threshold

0h = Input IN9 is below configured threshold

1h = Input IN9 is above configured threshold

8

0h = Input IN8 is below configured threshold

1h = Input IN8 is above configured threshold

7

0h = Input IN7 is below configured threshold

1h = Input IN7 is above configured threshold

6

0h = Input IN6 is below configured threshold

1h = Input IN6 is above configured threshold

5

0h = Input IN5 is below configured threshold

1h = Input IN5 is above configured threshold

4

0h = Input IN4 is below configured threshold

1h = Input IN4 is above configured threshold

3

0h = Input IN3 is below configured threshold

1h = Input IN3 is above configured threshold

2

0h = Input IN2 is below configured threshold

1h = Input IN2 is above configured threshold

1

0h = Input IN1 is below configured threshold

1h = Input IN1 is above configured threshold

0

0h = Input IN0 is below configured threshold

1h = Input IN0 is above configured threshold

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8.6.7 IN_STAT_ADC1 Register (Offset = 7h) [Reset = 0h]

IN_STAT_ADC1 is shown in 图8-30 and described in 表8-18.

Return to Summary Table.

This register indicates whether an input is above or below the programmed thresholds 3A, 3B, and 3C when it is

configured as ADC input mode. For IN23, there are 5 thresholds that can be programmed.

图8-30. IN_STAT_ADC1 Register

23

22

21

20

19

18

17

16

15

14

13

12

RESERVED

R-0h

INA_23

R-0h

11

10

9

8

7

6

5

4

3

2

1

0

INA_23

R-0h

INA_22

R-0h

INA_21

R-0h

INA_20

R-0h

INA_19

R-0h

INA_18

R-0h

LEGEND: R = Read only

表8-18. IN_STAT_ADC1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-13

RESERVED

R

0h

Reserved

12-10

INA_23

R

0h

0h = Input IN23 is below threshold 3A

1h = Input IN23 is below threshold 3B and equal to or above

threshold 3A

2h = Input IN23 is below threshold 3C and equal to or above

threshold 3B

3h = Input IN23 is below threshold THRES8 and equal to or above

threshold 3C

4h = Input IN23 is below threshold THRES9 and equal to or above

threshold THRES8

5h = Input IN23 is equal to or above threshold THRES9

9-8

7-6

5-4

INA_22

INA_21

INA_20

R

0h

0h = Input IN22 is below threshold 3A

1h = Input IN22 is below threshold 3B and equal to or above

threshold 3A

2h = Input IN22 is below threshold 3C and equal to or above

threshold 3B

3h = Input IN22 is equal to or above threshold 3C

0h = Input IN21 is below threshold 3A

1h = Input IN21 is below threshold 3B and equal to or above

threshold 3A

2h = Input IN21 is below threshold 3C and equal to or above

threshold 3B

3h = Input IN21 is equal to or above threshold 3C

0h = Input IN20 is below threshold 3A

1h = Input IN20 is below threshold 3B and equal to or above

threshold 3A

2h = Input IN20 is below threshold 3C and equal to or above

threshold 3B

3h = Input IN20 is equal to or above threshold 3C

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表8-18. IN_STAT_ADC1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-2

INA_19

R

0h

0h = Input IN19 is below threshold 3A

1h = Input IN19 is below threshold 3B and equal to or above

threshold 3A

2h = Input IN19 is below threshold 3C and equal to or above

threshold 3B

3h = Input IN19 is equal to or above threshold 3C

1-0

INA_18

R

0h

0h = Input is IN18 is below threshold 3A

1h = Input is IN18 is below threshold 3B and equal to or above

threshold 3A

2h = Input is IN18 is below threshold 3C and equal to or above

threshold 3B

3h = Input is IN18 is equal to or above threshold 3C

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8.6.8 IN_STAT_MATRIX0 Register (Offset = 8h) [Reset = 0h]

IN_STAT_MATRIX0 is shown in 图8-31 and described in 表8-19.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold in the matrix polling mode

for switches connected to IN10-IN13.

图8-31. IN_STAT_MATRIX0 Register

23

22

21

20

19

18

17

16

INMAT_13_IN9 INMAT_13_IN8 INMAT_13_IN7 INMAT_13_IN6 INMAT_13_IN5 INMAT_13_IN4 INMAT_12_IN9 INMAT_12_IN8

R-0h

15

R-0h

14

R-0h

13

R-0h

12

R-0h

11

R-0h

10

R-0h

9

R-0h

8

INMAT_12_IN7 INMAT_12_IN6 INMAT_12_IN5 INMAT_12_IN4 INMAT_11_IN9 INMAT_11_IN8 INMAT_11_IN7 INMAT_11_IN6

R-0h

7

R-0h

6

R-0h

5

R-0h

4

R-0h

3

R-0h

2

R-0h

1

R-0h

0

INMAT_11_IN5 INMAT_11_IN4 INMAT_10_IN9 INMAT_10_IN8 INMAT_10_IN7 INMAT_10_IN6 INMAT_10_IN5 INMAT_10_IN4

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

LEGEND: R = Read only

表8-19. IN_STAT_MATRIX0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23

INMAT_13_IN9

R

0h

0h = Input IN13 is below threshold while IN9 pulled to GND

1h = Input IN13 is above threshold while IN9 pulled to GND

22

21

20

19

18

17

16

15

14

13

12

11

INMAT_13_IN8

INMAT_13_IN7

INMAT_13_IN6

INMAT_13_IN5

INMAT_13_IN4

INMAT_12_IN9

INMAT_12_IN8

INMAT_12_IN7

INMAT_12_IN6

INMAT_12_IN5

INMAT_12_IN4

INMAT_11_IN9

R

0h

0h = Input IN13 is below threshold while IN8 pulled to GND

1h = Input IN13 is above threshold while IN8 pulled to GND

0h = Input IN13 is below threshold while IN7 pulled to GND

1h = Input IN13 is above threshold while IN7 pulled to GND

0h = Input IN13 is below threshold while IN6 pulled to GND

1h = Input IN13 is above threshold while IN6 pulled to GND

0h = Input IN13 is below threshold while IN5 pulled to GND

1h = Input IN13 is above threshold while IN5 pulled to GND

0h = Input IN13 is below threshold while IN4 pulled to GND

1h = Input IN13 is above threshold while IN4 pulled to GND

0h = Input IN12 is below threshold while IN9 pulled to GND

1h = Input IN12 is above threshold while IN9 pulled to GND

0h = Input IN12 is below threshold while IN8 pulled to GND.

1h = Input IN12 is above threshold while IN8 pulled to GND.

0h = Input IN12 is below threshold while IN7 pulled to GND.

1h = Input IN12 is above threshold while IN7 pulled to GND.

0h = Input IN12 is below threshold while IN6 pulled to GND.

1h = Input IN12 is above threshold while IN6 pulled to GND.

0h = Input IN12 is below threshold while IN5 pulled to GND.

1h = Input IN12 is above threshold while IN5 pulled to GND.

0h = Input IN12 is below threshold while IN4 pulled to GND.

1h = Input IN12 is above threshold while IN4 pulled to GND.

0h = Input IN11 is below threshold while IN9 pulled to GND.

1h = Input IN11 is above threshold while IN9 pulled to GND.

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表8-19. IN_STAT_MATRIX0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

10

INMAT_11_IN8

R

0h

0h = Input IN11 is below threshold while IN8 pulled to GND.

1h = Input IN11 is above threshold while IN8 pulled to GND.

9

8

7

6

5

4

3

2

1

0

INMAT_11_IN7

INMAT_11_IN6

INMAT_11_IN5

INMAT_11_IN4

INMAT_10_IN9

INMAT_10_IN8

INMAT_10_IN7

INMAT_10_IN6

INMAT_10_IN5

INMAT_10_IN4

R

0h

0h = Input IN11 is below threshold while IN7 pulled to GND.

1h = Input IN11 is above threshold while IN7 pulled to GND.

0h = Input IN11 is below threshold while IN6 pulled to GND.

1h = Input IN11 is above threshold while IN6 pulled to GND.

0h = Input IN11 is below threshold while IN5 pulled to GND.

1h = Input IN11 is above threshold while IN5 pulled to GND.

0h = Input IN11 is below threshold while IN4 pulled to GND.

1h = Input IN11 is above threshold while IN4 pulled to GND.

0h = Input IN10 is below threshold while IN9 pulled to GND.

1h = Input IN10 is above threshold while IN9 pulled to GND.

0h = Input IN10 is below threshold while IN8 pulled to GND.

1h = Input IN10 is above threshold while IN8 pulled to GND.

0h = Input IN10 is below threshold while IN7 pulled to GND.

1h = Input IN10 is above threshold while IN7 pulled to GND.

0h = Input IN10 is below threshold while IN6 pulled to GND.

1h = Input IN10 is above threshold while IN6 pulled to GND.

0h = Input IN10 is below threshold while IN5 pulled to GND.

1h = Input IN10 is above threshold while IN5 pulled to GND.

0h = Input IN10 is below threshold while IN4 pulled to GND.

1h = Input IN10 is above threshold while IN4 pulled to GND.

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8.6.9 IN_STAT_MATRIX1 Register (Offset = 9h) [Reset = 0h]

IN_STAT_MATRIX1 is shown in 图8-32 and described in 表8-20.

Return to Summary Table.

This register indicates whether an input is below or above the programmed threshold in the matrix polling mode

for switches connected to IN14-IN15. This register also indicates the status of IN0-IN11 with respect to the

common threshold THRES_COM.

图8-32. IN_STAT_MATRIX1 Register

23

22

21

20

19

18

17

16

IN11_COM

R-0h

IN10_COM

R-0h

IN9_COM

R-0h

IN8_COM

R-0h

IN7_COM

R-0h

IN6_COM

R-0h

IN5_COM

R-0h

IN4_COM

R-0h

15

14

13

12

11

10

9

8

IN3_COM

R-0h

IN2_COM

R-0h

IN1_COM

R-0h

IN0_COM

R-0h

INMAT_15_IN9 INMAT_15_IN8 INMAT_15_IN7 INMAT_15_IN6

R-0h

3

R-0h

2

R-0h

1

R-0h

0

7

6

5

4

INMAT_15_IN5 INMAT_15_IN4 INMAT_14_IN9 INMAT_14_IN8 INMAT_14_IN7 INMAT_14_IN6 INMAT_14_IN5 INMAT_14_IN4

R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

LEGEND: R = Read only

表8-20. IN_STAT_MATRIX1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23

IN11_COM

R

0h

0h = Input IN11 below threshold THRES_COM

1h = Input IN11 equal to or above threshold THRES_COM

22

21

20

19

18

17

16

15

14

13

12

IN10_COM

IN9_COM

IN8_COM

IN7_COM

IN6_COM

IN5_COM

IN4_COM

IN3_COM

IN2_COM

IN1_COM

IN0_COM

R

0h

0h = Input IN10 below threshold THRES_COM

1h = Input IN10 equal to or above threshold THRES_COM

0h = Input IN9 below threshold THRES_COM

1h = Input IN9 equal to or above threshold THRES_COM

0h = Input IN8 below threshold THRES_COM

1h = Input IN8 equal to or above threshold THRES_COM

0h = Input IN7 below threshold THRES_COM

1h = Input IN7 equal to or above threshold THRES_COM

0h = Input IN6 below threshold THRES_COM

1h = Input IN6 equal to or above threshold THRES_COM

0h = Input IN5 below threshold THRES_COM

1h = Input IN5 equal to or above threshold THRES_COM

0h = Input IN4 below threshold THRES_COM

1h = Input IN4 equal to or above threshold THRES_COM

0h = Input IN3 below threshold THRES_COM

1h = Input IN3 equal to or above threshold THRES_COM

0h = Input IN2 below threshold THRES_COM

1h = Input IN2 equal to or above threshold THRES_COM

0h = Input IN1 below threshold THRES_COM

1h = Input IN1 equal to or above threshold THRES_COM

0h = Input IN0 below threshold THRES_COM

1h = Input IN0 equal to or above threshold THRES_COM

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表8-20. IN_STAT_MATRIX1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11

INMAT_15_IN9

R

0h

0h = Input IN15 below threshold while IN9 pulled to GND

1h = Input IN15 above threshold while IN9 pulled to GND

10

9

8

7

6

5

4

3

2

1

0

INMAT_15_IN8

INMAT_15_IN7

INMAT_15_IN6

INMAT_15_IN5

INMAT_15_IN4

INMAT_14_IN9

INMAT_14_IN8

INMAT_14_IN7

INMAT_14_IN6

INMAT_14_IN5

INMAT_14_IN4

R

0h

0h = Input IN15 below threshold while IN8 pulled to GND

1h = Input IN15 above threshold while IN8 pulled to GND

0h = Input IN15 below threshold while IN7 pulled to GND

1h = Input IN15 above threshold while IN7 pulled to GND

0h = Input IN15 below threshold while IN6 pulled to GND

1h = Input IN15 above threshold while IN6 pulled to GND

0h = Input IN15 below threshold while IN5 pulled to GND

1h = Input IN15 above threshold while IN5 pulled to GND

0h = Input IN15 below threshold while IN4 pulled to GND

1h = Input IN15 above threshold while IN4 pulled to GND

0h = Input IN14 below threshold while IN9 pulled to GND

1h = Input IN14 above threshold while IN9 pulled to GND

0h = Input IN14 below threshold while IN8 pulled to GND

1h = Input IN14 above threshold while IN8 pulled to GND

0h = Input IN14 below threshold while IN7 pulled to GND

1h = Input IN14 above threshold while IN7 pulled to GND

0h = Input IN14 below threshold while IN6 pulled to GND

1h = Input IN14 above threshold while IN6 pulled to GND

0h = Input IN14 below threshold while IN5 pulled to GND

1h = Input IN14 above threshold while IN5 pulled to GND

0h = Input IN14 below threshold while IN4 pulled to GND

1h = Input IN14 above threshold while IN4 pulled to GND

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8.6.10 ANA_STAT0 Register (Offset = Ah) [Reset = 0h]

ANA_STAT0 is shown in 图8-33 and described in 表8-21.

Return to Summary Table.

图8-33. ANA_STAT0 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN1_ANA

R-0h

IN0_ANA

R-0h

LEGEND: R = Read only

表8-21. ANA_STAT0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN1_ANA

R

0h

10-bits value of IN1

Bit 10: LSB

Bit 19: MSB

9-0

IN0_ANA

10-bits value of IN0

Bit 0: LSB

Bit 9: MSB

8.6.11 ANA_STAT1 Register (Offset = Bh) [Reset = 0h]

ANA_STAT1 is shown in 图8-34 and described in 表8-22.

Return to Summary Table.

图8-34. ANA_STAT1 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN5_ANA

R-0h

IN4_ANA

R-0h

LEGEND: R = Read only

表8-22. ANA_STAT1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN3_ANA

R

0h

10-bits value of IN3

Bit 10: LSB

Bit 19: MSB

9-0

IN2_ANA

10-bits value of IN2

Bit 0: LSB

Bit 9: MSB

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8.6.12 ANA_STAT2 Register (Offset = Ch) [Reset = 0h]

ANA_STAT2 is shown in 图8-35 and described in 表8-23.

Return to Summary Table.

图8-35. ANA_STAT2 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN5_ANA

R-0h

IN4_ANA

R-0h

LEGEND: R = Read only

表8-23. ANA_STAT2 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN5_ANA

R

0h

10-bits value of IN5

Bit 10: LSB

Bit 19: MSB

9-0

IN4_ANA

10-bits value of IN4

Bit 0: LSB

Bit 9: MSB

8.6.13 ANA_STAT3 Register (Offset = Dh) [Reset = 0h]

ANA_STAT3 is shown in 图8-36 and described in 表8-24.

Return to Summary Table.

图8-36. ANA_STAT3 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN7_ANA

R-0h

IN6_ANA

R-0h

LEGEND: R = Read only

表8-24. ANA_STAT3 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN7_ANA

R

0h

10-bits value of IN7

Bit 10: LSB

Bit 19: MSB

9-0

IN6_ANA

10-bits value of IN6

Bit 0: LSB

Bit 9: MSB

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8.6.14 ANA_STAT4 Register (Offset = Eh) [Reset = 0h]

ANA_STAT4 is shown in 图8-37 and described in 表8-25.

Return to Summary Table.

图8-37. ANA_STAT4 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN9_ANA

R-0h

IN8_ANA

R-0h

LEGEND: R = Read only

表8-25. ANA_STAT4 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN9_ANA

R

0h

10-bits value of IN9

Bit 10: LSB

Bit 19: MSB

9-0

IN8_ANA

10-bits value of IN8

Bit 0: LSB

Bit 9: MSB

8.6.15 ANA_STAT5 Register (Offset = Fh) [Reset = 0h]

ANA_STAT5 is shown in 图8-38 and described in 表8-26.

Return to Summary Table.

图8-38. ANA_STAT5 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN11_ANA

R-0h

IN10_ANA

R-0h

LEGEND: R = Read only

表8-26. ANA_STAT5 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN11_ANA

R

0h

10-bits value of IN11

Bit 10: LSB

Bit 19: MSB

9-0

IN10_ANA

10-bits value of IN10

Bit 0: LSB

Bit 9: MSB

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8.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]

ANA_STAT6 is shown in 图8-39 and described in 表8-27.

Return to Summary Table.

图8-39. ANA_STAT6 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN13_ANA

R-0h

IN12_ANA

R-0h

LEGEND: R = Read only

表8-27. ANA_STAT6 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN13_ANA

R

0h

10-bits value of IN13

Bit 10: LSB

Bit 19: MSB

9-0

IN12_ANA

10-bits value of IN12

Bit 0: LSB

Bit 9: MSB

8.6.17 ANA_STAT7 Register (Offset = 11h) [Reset = 0h]

ANA_STAT7 is shown in 图8-40 and described in 表8-28.

Return to Summary Table.

图8-40. ANA_STAT7 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN15_ANA

R-0h

IN14_ANA

R-0h

LEGEND: R = Read only

表8-28. ANA_STAT7 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN15_ANA

R

0h

10-bits value of IN15

Bit 10: LSB

Bit 19: MSB

9-0

IN14_ANA

10-bits value of IN14

Bit 0: LSB

Bit 9: MSB

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8.6.18 ANA_STAT8 Register (Offset = 12h) [Reset = 0h]

ANA_STAT8 is shown in 图8-41 and described in 表8-29.

Return to Summary Table.

图8-41. ANA_STAT8 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN17_ANA

R-0h

IN16_ANA

R-0h

LEGEND: R = Read only

表8-29. ANA_STAT8 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN17_ANA

R

0h

10-bits value of IN17

Bit 10: LSB

Bit 19: MSB

9-0

IN16_ANA

10-bits value of IN16

Bit 0: LSB

Bit 9: MSB

8.6.19 ANA_STAT9 Register (Offset = 13h) [Reset = 0h]

ANA_STAT9 is shown in 图8-42 and described in 表8-30.

Return to Summary Table.

图8-42. ANA_STAT9 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN19_ANA

R-0h

IN18_ANA

R-0h

LEGEND: R = Read only

表8-30. ANA_STAT9 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN19_ANA

R

0h

10-bits value of IN19

Bit 10: LSB

Bit 19: MSB

9-0

IN18_ANA

10-bits value of IN18

Bit 0: LSB

Bit 9: MSB

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8.6.20 ANA_STAT10 Register (Offset = 14h) [Reset = 0h]

ANA_STAT10 is shown in 图8-43 and described in 表8-31.

Return to Summary Table.

图8-43. ANA_STAT10 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN21_ANA

R-0h

IN20_ANA

R-0h

LEGEND: R = Read only

表8-31. ANA_STAT10 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN21_ANA

R

0h

10-bits value of IN21

Bit 10: LSB

Bit 19: MSB

9-0

IN20_ANA

10-bits value of IN20

Bit 0: LSB

Bit 9: MSB

8.6.21 ANA_STAT11 Register (Offset = 15h) [Reset = 0h]

ANA_STAT11 is shown in 图8-44 and described in 表8-32.

Return to Summary Table.

图8-44. ANA_STAT11 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

IN23_ANA

R-0h

IN22_ANA

R-0h

LEGEND: R = Read only

表8-32. ANA_STAT11 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

IN23_ANA

R

0h

10-bits value of IN23

Bit 10: LSB

Bit 19: MSB

9-0

IN22_ANA

10-bits value of IN22

Bit 0: LSB

Bit 9: MSB

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8.6.22 ANA_STAT12 Register (Offset = 16h) [Reset = 0h]

ANA_STAT12 is shown in 图8-45 and described in 表8-33.

Return to Summary Table.

图8-45. ANA_STAT12 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

ADC_SELF_ANA

R-0h

V_S_ANA

R-0h

LEGEND: R = Read only

表8-33. ANA_STAT12 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

ADC_SELF_ANA

R

0h

10-bits value of the ADC self-diagnosis

Bit 10: LSB

Bit 19: MSB

9-0

V_S_ANA

10-bits value of V_Smeasurement

Bit 0: LSB

Bit 9: MSB

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8.6.23 CONFIG Register (Offset = 1Ah) [Reset = 0h]

CONFIG is shown in 图8-46 and described in 表8-34.

Return to Summary Table.

图8-46. CONFIG Register

23

22

21

20

19

18

17

16

VS_RATIO

ADC_DIAG_T WET_D_IN3_E WET_D_IN2_E WET_D_IN1_E WET_D_IN0_E VS_MEAS_EN TW_CUR_DIS_

N

CSI

R/W-0h

15

R/W-0h

14

R/W-0h

13

12

11

10

9

8

DET_FILTER

TW_CUR_DIS_ INT_CONFIG

CSO

TRIGGER

POLL_EN

CRC_T

POLL_ACT_TI

ME

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

7

6

0

POLL_ACT_TIME

R/W-0h

POLL_TIME

R/W-0h

RESET

R/W-0h

LEGEND: R/W = Read/Write

表8-34. CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

23

VS_RATIO

R/W

0h

0h = Use voltage divider factor of 3 for the V_Smeasurement

1h = Use voltage divider factor of 10 for the V_Smeasurement

22

ADC_DIAG_T

R/W

0h

For detailed descriptions for the ADC self-diagnostic feature, refer to

section ADC Self-Diagnostic

0h = Disable ADC self-diagnostic feature

1h = Enable ADC self-diagnostic feature

21

20

19

18

17

WET_D_IN3_EN

WET_D_IN2_EN

WET_D_IN1_EN

WET_D_IN0_EN

VS_MEAS_EN

R/W

0h

0h = Disable wetting current diagnostic for input IN3

1h = Enable wetting current diagnostic for input IN3

0h = Disable wetting current diagnostic for input IN2

1h = Enable wetting current diagnostic for input IN2

0h = Disable wetting current diagnostic for input IN1

1h = Enable wetting current diagnostic for input IN1

0h = Disable wetting current diagnostic for input IN0

1h = Enable wetting current diagnostic for input IN0

For detailed descriptions for the V_Smeasurement, refer to section

VS Measurement.

0h = Disable V_Smeasurement at the end of every polling cycle

1h = Enable V_Smeasurement at the end of every polling cycle

16

TW_CUR_DIS_CSI

DET_FILTER

R/W

0h

0h = Enable wetting current reduction (to 2 mA) for 10 mA and 15

mA settings upon TW event for all inputs enabled with CSI.

1h = Disable wetting current reduction (to 2 mA) for 10 mA and 15

mA settings upon TW event for all inputs enabled with CSI.

15-14

For detailed descriptions for the detection filter, refer to section

Detection Filter.

0h = every sample is valid and taken for threshold evaluation

1h = 2 consecutive and equal samples required to be valid data

2h = 3 consecutive and equal samples required to be valid data

3h = 4 consecutive and equal samples required to be valid data

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表8-34. CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13

TW_CUR_DIS_CSO

INT_CONFIG

TRIGGER

R/W

0h

0h = Enable wetting current reduction (to 2 mA) for 10 mA and 15

mA settings upon TW event for all inputs enabled with CSO.

1h = Disable wetting current reduction (to 2 mA) for 10 mA and 15

mA settings upon TW event for all inputs enabled with CSO.

12

11

R/W

0h

For detailed descriptions for the INT pin assertion scheme, refer to

section Interrupt Generation and /INT Assertion.

0h = INT pin assertion scheme set to static

1h = INT pin assertion scheme set to dynamic

When the TRIGGER bit is set to logic 1, normal device operation

(wetting current activation and polling) starts. To stop device

operation and keep the device in an idle state, de-assert this bit to 0.

After device normal operation is triggered, if at any time the device

setting needs to be re-configured, the microcontroller is required to

first set the bit TRIGGER to logic 0 to stop device operation. Once

the re-configuration is completed, the microcontroller can set the

TRIGGER bit back to logic 1 to re-start device operation. If re-

configuration is done on the fly without first stopping the device

operation, false switch status could be reported and accidental

interrupt might be issued. The following register bits are the

exception and can be configured when TRIGGER bit is set to logic 1:

•

TRIGGER (bit 11 of the CONFIG register)

CRC_T (bit 9 of the CONFIG register)

RESET (bit 0 of the CONFIG register)

The CCP_CFG1 register

0h = Stop TIC12400-Q1 from normal operation.

1h = Trigger TIC12400-Q1 from normal operation.

10

9

POLL_EN

CRC_T

R/W

0h

0h = Polling disabled. Device operates in continuous mode.

1h = Polling enabled and the device operates in one of the polling

modes.

Set this bit to 1 to trigger a CRC calculation on all the configuration

register bits. Once triggered, it is strongly recommended the SPI

controller does not change the content of the configuration registers

until the CRC calculation is completed to avoid erroneous CRC

calculation result. The TIC12400-Q1 sets the CRC_CALC interrupt

bit and asserts the INT pin low when the CRC calculation is

completed. The calculated result will be available in the CRC

register. This bit self-clears back to 0 after CRC calculation is

executed.

0h = no CRC calculation triggered.

1h = trigger CRC calculation.

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表8-34. CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8-5

POLL_ACT_TIME

R/W

0h

0h = 64 μs

1h = 128 μs

2h = 192 μs

3h = 256 μs

4h = 320 μs

5h = 384 μs

6h = 448 μs

7h = 512 μs

8h = 640 μs

9h = 768 μs

Ah = 896 μs

Bh = 1024 μs

Ch = 2048 μs

Dh-15h = 512 μs (most frequently-used setting)

4-1

POLL_TIME

R/W

0h

0h = 2 ms

1h = 4 ms

2h = 8 ms

3h = 16 ms

4h = 32 ms

5h = 48 ms

6h = 64 ms

7h = 128 ms

8h = 256 ms

9h = 512 ms

Ah = 1024 ms

Bh = 2048 ms

Ch = 4096 ms

Dh-15h = 8 ms (most frequently-used setting)

0

RESET

R/W

0h

0h = No reset.

1h = Trigger software reset of the device.

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8.6.24 IN_EN Register (Offset = 1Bh) [Reset = 0h]

IN_EN is shown in 图8-47 and described in 表8-35.

Return to Summary Table.

图8-47. IN_EN Register

23

22

21

20

19

18

17

16

IN_EN_23

R/W-0h

IN_EN_22

R/W-0h

IN_EN_21

R/W-0h

IN_EN_20

R/W-0h

IN_EN_19

R/W-0h

IN_EN_18

R/W-0h

IN_EN_17

R/W-0h

IN_EN_16

R/W-0h

15

14

13

12

11

10

9

8

IN_EN_15

R/W-0h

IN_EN_14

R/W-0h

IN_EN_13

R/W-0h

IN_EN_12

R/W-0h

IN_EN_11

R/W-0h

IN_EN_10

R/W-0h

IN_EN_9

R/W-0h

IN_EN_8

R/W-0h

7

6

5

4

3

2

1

0

IN_EN_7

R/W-0h

IN_EN_6

R/W-0h

IN_EN_5

R/W-0h

IN_EN_4

R/W-0h

IN_EN_3

R/W-0h

IN_EN_2

R/W-0h

IN_EN_1

R/W-0h

IN_EN_0

R/W-0h

LEGEND: R/W = Read/Write

表8-35. IN_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

23

IN_EN_23

R/W

0h

0h = Input channel IN23 disabled. Polling sequence skips this

channel

1h = Input channel IN23 enabled.

22

21

20

19

18

17

16

15

IN_EN_22

IN_EN_21

IN_EN_20

IN_EN_19

IN_EN_18

IN_EN_17

IN_EN_16

IN_EN_15

R/W

0h

0h = Input channel IN22 disabled. Polling sequence skips this

channel

1h = Input channel IN22 enabled.

0h = Input channel IN21 disabled. Polling sequence skips this

channel

1h = Input channel IN21 enabled.

0h = Input channel IN20 disabled. Polling sequence skips this

channel

1h = Input channel IN20 enabled.

0h = Input channel IN19 disabled. Polling sequence skips this

channel

1h = Input channel IN19 enabled.

0h = Input channel IN18 disabled. Polling sequence skips this

channel

1h = Input channel IN18 enabled.

0h = Input channel IN17 disabled. Polling sequence skips this

channel

1h = Input channel IN17 enabled.

0h = Input channel IN16 disabled. Polling sequence skips this

channel

1h = Input channel IN16 enabled.

0h = Input channel IN15 disabled. Polling sequence skips this

channel

1h = Input channel IN15 enabled.

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表8-35. IN_EN Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

14

IN_EN_14

R/W

0h

0h = Input channel IN14 disabled. Polling sequence skips this

channel

1h = Input channel IN14 enabled.

13

12

11

10

IN_EN_13

IN_EN_12

IN_EN_11

IN_EN_10

R/W

0h

0h = Input channel IN13 disabled. Polling sequence skips this

channel

1h = Input channel IN13 enabled.

0h = Input channel IN12 disabled. Polling sequence skips this

channel

1h = Input channel IN12 enabled.

0h = Input channel IN11 disabled. Polling sequence skips this

channel

1h = Input channel IN11 enabled.

0h = Input channel IN10 disabled. Polling sequence skips this

channel

1h = Input channel IN10 enabled.

9

8

7

6

5

4

3

2

1

0

IN_EN_9

IN_EN_8

IN_EN_7

IN_EN_6

IN_EN_5

IN_EN_4

IN_EN_3

IN_EN_2

IN_EN_1

IN_EN_0

R/W

0h

0h = Input channel IN9 disabled. Polling sequence skips this channel

1h = Input channel IN9 enabled.

0h = Input channel IN8 disabled. Polling sequence skips this channel

1h = Input channel IN8 enabled.

0h = Input channel IN7 disabled. Polling sequence skips this channel

1h = Input channel IN7 enabled.

0h = Input channel IN6 disabled. Polling sequence skips this channel

1h = Input channel IN6 enabled.

0h = Input channel IN5 disabled. Polling sequence skips this channel

1h = Input channel IN5 enabled.

0h = Input channel IN4 disabled. Polling sequence skips this channel

1h = Input channel IN4 enabled.

0h = Input channel IN3 disabled. Polling sequence skips this channel

1h = Input channel IN3 enabled.

0h = Input channel IN2 disabled. Polling sequence skips this channel

1h = Input channel IN2 enabled.

0h = Input channel IN1 disabled. Polling sequence skips this channel

1h = Input channel IN1 enabled.

0h = Input channel IN0 disabled. Polling sequence skips this channel

1h = Input channel IN0 enabled.

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8.6.25 CS_SELECT Register (Offset = 1Ch) [Reset = 0h]

CS_SELECT is shown in 图8-48 and described in 表8-36.

Return to Summary Table.

图8-48. CS_SELECT Register

23

22

21

20

19

18

RESERVED

R-0h

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

CS_IN9

R/W-0h

CS_IN8

R/W-0h

CS_IN7

R/W-0h

CS_IN6

R/W-0h

CS_IN5

R/W-0h

CS_IN4

R/W-0h

CS_IN3

R/W-0h

CS_IN2

R/W-0h

CS_IN1

R/W-0h

CS_IN0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-36. CS_SELECT Register Field Descriptions

Bit

Field

Type

Reset

Description

23-10

RESERVED

R

0h

Reserved

9

8

7

6

5

4

3

2

1

0

CS_IN9

CS_IN8

CS_IN7

CS_IN6

CS_IN5

CS_IN4

CS_IN3

CS_IN2

CS_IN1

CS_IN0

R/W

0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

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8.6.26 WC_CFG0 Register (Offset = 1Dh) [Reset = 0h]

WC_CFG0 is shown in 图8-49 and described in 表8-37.

Return to Summary Table.

图8-49. WC_CFG0 Register

23

11

22

21

9

20

8

19

18

17

16

WC_IN8_IN9

R/W-0h

15

3

14

2

13

12

WC_IN11

R/W-0h

10

WC_IN10

R/W-0h

7

WC_IN6_IN7

R/W-0h

6

5

4

1

0

WC_IN5

R/W-0h

WC_IN4

R/W-0h

WC_IN2_IN3

R/W-0h

WC_IN0_IN1

R/W-0h

LEGEND: R/W = Read/Write

表8-37. WC_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-21

WC_IN11

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

20-18

17-15

14-12

11-9

WC_IN10

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

WC_IN8_IN9

WC_IN6_IN7

WC_IN5

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

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表8-37. WC_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8-6

WC_IN4

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

5-3

2-0

WC_IN2_IN3

WC_IN0_IN1

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

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8.6.27 WC_CFG1 Register (Offset = 1Eh) [Reset = 0h]

WC_CFG1 is shown in 图8-50 and described in 表8-38.

Return to Summary Table.

图8-50. WC_CFG1 Register

23

22

21

20

19

18

17

16

15

14

13

12

RESERV AUTO_S AUTO_S

WC_IN23

WC_IN22

WC_IN20_IN21

ED

CALE_DI CALE_DI

S_CSI

S_CSO

R/W-0h

9

R-0h

11

R/W-0h

7

R/W-0h

4

R/W-0h

1

10

8

6

5

3

2

0

WC_IN18_IN19

R/W-0h

WC_IN16_IN17

R/W-0h

WC_IN14_IN15

R/W-0h

WC_IN12_IN13

R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-38. WC_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23

RESERVED

R

0h

Reserved

22

AUTO_SCALE_DIS_CSI R/W

0h

0h = Enable wetting current auto-scaling (to 2 mA) in continuous

mode for 10 mA and 15 mA settings upon switch closure for all

inputs enabled with CSI

1h = Disable wetting current auto-scaling (to 2 mA) in continuous

mode for 10 mA and 15 mA settings upon switch closure for all

inputs enabled with CS

For detailed descriptions for the wetting current auto-scaling, refer to

section Wetting Current Auto-Scaling.

21

AUTO_SCALE_DIS_CSO R/W

0h

0h = Enable wetting current auto-scaling (to 2 mA) in continuous

mode for 10 mA and 15 mA settings upon switch closure for all

inputs enabled with CSO

1h = Disable wetting current auto-scaling (to 2 mA) in continuous

mode for 10 mA and 15 mA settings upon switch closure for all

inputs enabled with CSO

For detailed descriptions for the wetting current auto-scaling, refer to

section Wetting Current Auto-Scaling.

20-18

17-15

WC_IN23

WC_IN22

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

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表8-38. WC_CFG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

14-12

WC_IN20_IN21

WC_IN18_IN19

WC_IN16_IN17

WC_IN14_IN15

WC_IN12_IN13

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

11-9

8-6

5-3

2-0

R/W

0h

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

0h = no wetting current

1h = 1 mA (typical) wetting current

2h = 2 mA (typical) wetting current

3h = 5 mA (typical) wetting current

4h = 10 mA (typical) wetting current

5h-7h = 15 mA (typical) wetting current

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8.6.28 CCP_CFG0 Register (Offset = 1Fh) [Reset = 0h]

CCP_CFG0 is shown in 图8-51 and described in 表8-39.

Return to Summary Table.

图8-51. CCP_CFG0 Register

23

11

22

10

21

20

8

19

18

RESERVED

R-0h

17

16

15

3

14

2

13

1

12

0

9

7

6

5

4

RESERVED

CCP_TIME

WC_CCP WC_CCP WC_CCP WC_CCP

3

2

1

0

R-0h

LEGEND: R/W = Read/Write; R = Read only

表8-39. CCP_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-7

RESERVED

R

0h

Reserved

6-4

CCP_TIME

R/W

0h

Wetting current activation time in CCP mode

0h = 64 μs

1h = 128 μs

2h = 192 μs

3h = 256 μs

4h = 320 μs

5h = 384 μs

6h = 448 μs

7h = 512 μs

3

2

1

0

WC_CCP3

WC_CCP2

WC_CCP1

WC_CCP0

R/W

0h

Wetting current setting for IN18 to IN23 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

Wetting current setting for IN12 to IN17 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

Wetting current setting for IN6 to IN11 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

Wetting current setting for IN0 to IN5 in CCP mode

0h = 10 mA (typical) wetting current

1h = 15 mA (typical) wetting current

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8.6.29 CCP_CFG1 Register (Offset = 20h) [Reset = 0h]

CCP_CFG1 is shown in 图8-52 and described in 表8-40.

Return to Summary Table.

图8-52. CCP_CFG1 Register

23

22

21

20

19

18

17

16

CCP_IN23

R/W-0h

CCP_IN22

R/W-0h

CCP_IN21

R/W-0h

CCP_IN20

R/W-0h

CCP_IN19

R/W-0h

CCP_IN18

R/W-0h

CCP_IN17

R/W-0h

CCP_IN16

R/W-0h

15

14

13

12

11

10

9

8

CCP_IN15

R/W-0h

CCP_IN14

R/W-0h

CCP_IN13

R/W-0h

CCP_IN12

R/W-0h

CCP_IN11

R/W-0h

CCP_IN10

R/W-0h

CCP_IN9

R/W-0h

CCP_IN8

R/W-0h

7

6

5

4

3

2

1

0

CCP_IN7

R/W-0h

CCP_IN6

R/W-0h

CCP_IN5

R/W-0h

CCP_IN4

R/W-0h

CCP_IN3

R/W-0h

CCP_IN2

R/W-0h

CCP_IN1

R/W-0h

CCP_IN0

R/W-0h

LEGEND: R/W = Read/Write

表8-40. CCP_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23

CCP_IN23

R/W

0h

0h = no CCP wetting current

1h = CCP wetting current activated

22

21

20

19

18

17

16

15

14

13

12

11

10

CCP_IN22

CCP_IN21

CCP_IN20

CCP_IN19

CCP_IN18

CCP_IN17

CCP_IN16

CCP_IN15

CCP_IN14

CCP_IN13

CCP_IN12

CCP_IN11

CCP_IN10

R/W

0h

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

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表8-40. CCP_CFG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

9

CCP_IN9

R/W

0h

0h = no CCP wetting current

1h = CCP wetting current activated

8

7

6

5

4

3

2

1

0

CCP_IN8

CCP_IN7

CCP_IN6

CCP_IN5

CCP_IN4

CCP_IN3

CCP_IN2

CCP_IN1

CCP_IN0

R/W

0h

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

0h = no CCP wetting current

1h = CCP wetting current activated

86

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8.6.30 THRES_COMP Register (Offset = 21h) [Reset = 0h]

THRES_COMP is shown in 图8-53 and described in 表8-41.

Return to Summary Table.

图8-53. THRES_COMP Register

23

15

7

22

14

6

21

13

5

20

12

4

19

18

10

17

9

16

8

RESERVED

R-0h

11

RESERVED

R-0h

THRES_COMP_IN20_IN23

R/W-0h

THRES_COMP_IN16_IN19

R/W-0h

3

2

1

0

THRES_COMP_IN12_IN15

R/W-0h

THRES_COMP_IN8_IN11

R/W-0h

THRES_COMP_IN4_IN7

R/W-0h

THRES_COMP_IN0_IN3

R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-41. THRES_COMP Register Field Descriptions

Bit

Field

Type

Reset

Description

23-12

RESERVED

R

0h

Reserved

11-10

THRES_COMP_IN20_IN2 R/W

3

0h

These 2 bits configure the comparator thresholds for input channels

IN20 to IN23.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

9-8

THRES_COMP_IN16_IN1 R/W

9

These 2 bits configure the comparator thresholds for input channels

IN16 to IN19.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

7-6

THRES_COMP_IN12_IN1 R/W

5

These 2 bits configure the comparator thresholds for input channels

IN12 to IN15.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

5-4

THRES_COMP_IN8_IN11 R/W

These 2 bits configure the comparator thresholds for input channels

IN8 to IN11.

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

3-2

THRES_COMP_IN4_IN7 R/W

These 2 bits configure the comparator thresholds for input channels

IN4 to IN7

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

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表8-41. THRES_COMP Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

THRES_COMP_IN0_IN3 R/W

0h

These 2 bits configure the comparator thresholds for input channels

IN0 to IN3

0h = comparator threshold set to 2 V

1h = comparator threshold set to 2.7 V

2h = comparator threshold set to 3 V

3h = comparator threshold set to 4 V

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8.6.31 INT_EN_COMP1 Register (Offset = 22h) [Reset = 0h]

INT_EN_COMP1 is shown in 图8-54 and described in 表8-42.

Return to Summary Table.

图8-54. INT_EN_COMP1 Register

23

INC_EN_11

R/W-0h

22

21

INC_EN_10

R/W-0h

20

19

INC_EN_9

R/W-0h

18

17

INC_EN_8

R/W-0h

16

15

INC_EN_7

R/W-0h

14

13

INC_EN_6

R/W-0h

12

11

10

9

8

7

6

5

4

3

2

1

0

INC_EN_5

R/W-0h

INC_EN_4

R/W-0h

INC_EN_3

R/W-0h

INC_EN_2

R/W-0h

INC_EN_1

R/W-0h

INC_EN_0

R/W-0h

LEGEND: R/W = Read/Write

表8-42. INT_EN_COMP1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-22

INC_EN_11

R/W

0h

0h = no interrupt generation for IN11.

1h = interrupt generation on rising edge above

THRES_COMP_IN8_IN11 for IN11.

2h = interrupt generation on falling edge below

THRES_COMP_IN8_IN11 for IN11.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN8_IN11 for IN11.

21-20

19-18

17-16

15-14

INC_EN_10

INC_EN_9

INC_EN_8

INC_EN_7

R/W

0h

0h = no interrupt generation for IN10

1h = interrupt generation on rising edge above

THRES_COMP_IN8_IN11 for IN10.

2h = interrupt generation on falling edge below

THRES_COMP_IN8_IN11 for IN10.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN8_IN11 for IN10.

0h = no interrupt generation for IN9.

1h = interrupt generation on rising edge above

THRES_COMP_IN8_IN11 for IN9.

2h = interrupt generation on falling edge below

THRES_COMP_IN8_IN11 for IN9.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN8_IN11 for IN9.

0h = no interrupt generation for IN8.

1h = interrupt generation on rising edge above

THRES_COMP_IN8_IN11 for IN8.

2h = interrupt generation on falling edge below

THRES_COMP_IN8_IN11 for IN8.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN8_IN11 for IN8.

0h = no interrupt generation for IN7.

1h = interrupt generation on rising edge above

THRES_COMP_IN4_IN7 for IN7.

2h = interrupt generation on falling edge below

THRES_COMP_IN4_IN7 for IN7.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN4_IN7 for IN7.

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表8-42. INT_EN_COMP1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13-12

INC_EN_6

R/W

0h

0h = no interrupt generation for IN6.

1h = interrupt generation on rising edge above

THRES_COMP_IN4_IN7 for IN6.

2h = interrupt generation on falling edge below

THRES_COMP_IN4_IN7 for IN6.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN4_IN7 for IN6.

11-10

INC_EN_5

INC_EN_4

INC_EN_3

INC_EN_2

INC_EN_1

INC_EN_0

R/W

0h

0h = no interrupt generation for IN5.

1h = interrupt generation on rising edge above

THRES_COMP_IN4_IN7 for IN5.

2h = interrupt generation on falling edge below

THRES_COMP_IN4_IN7 for IN5.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN4_IN7 for IN5.

9-8

0h = no interrupt generation for IN4.

1h = interrupt generation on rising edge above

THRES_COMP_IN4_IN7 for IN4.

2h = interrupt generation on falling edge below

THRES_COMP_IN4_IN7 for IN4.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN4_IN7 for IN4.

7-6

0h = no interrupt generation for IN3.

1h = interrupt generation on rising edge above

THRES_COMP_IN0_IN3 for IN3.

2h = interrupt generation on falling edge below

THRES_COMP_IN0_IN3 for IN3.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN0_IN3 for IN3.

5-4

0h = no interrupt generation for IN2.

1h = interrupt generation on rising edge above

THRES_COMP_IN0_IN3 for IN2.

2h = interrupt generation on falling edge below

THRES_COMP_IN0_IN3 for IN2.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN0_IN3 for IN2.

3-2

0h = no interrupt generation for IN1.

1h = interrupt generation on rising edge above

THRES_COMP_IN0_IN3 for IN1.

2h = interrupt generation on falling edge below

THRES_COMP_IN0_IN3 for IN1.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN0_IN3 for IN1.

1-0

0h = no interrupt generation for IN0.

1h = interrupt generation on rising edge above

THRES_COMP_IN0_IN3 for IN0.

2h = interrupt generation on falling edge below

THRES_COMP_IN0_IN3 for IN0.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN0_IN3 for IN0.

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8.6.32 INT_EN_COMP2 Register (Offset = 23h) [Reset = 0h]

INT_EN_COMP2 is shown in 图8-55 and described in 表8-43.

Return to Summary Table.

图8-55. INT_EN_COMP2 Register

23

INC_EN_23

R/W-0h

22

21

INC_EN_22

R/W-0h

20

19

INC_EN_21

R/W-0h

18

17

INC_EN_20

R/W-0h

16

15

INC_EN_19

R/W-0h

14

13

INC_EN_18

R/W-0h

12

11

10

9

8

7

6

5

4

3

2

1

0

INC_EN_17

R/W-0h

INC_EN_16

R/W-0h

INC_EN_15

R/W-0h

INC_EN_14

R/W-0h

INC_EN_13

R/W-0h

INC_EN_12

R/W-0h

LEGEND: R/W = Read/Write

表8-43. INT_EN_COMP2 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-22

INC_EN_23

R/W

0h

0h = no interrupt generation for IN23.

1h = interrupt generation on rising edge above

THRES_COMP_IN20_IN23 for IN23.

2h = interrupt generation on falling edge below

THRES_COMP_IN20_IN23 for IN23.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN20_IN23 for IN23.

21-20

19-18

17-16

15-14

INC_EN_22

INC_EN_21

INC_EN_20

INC_EN_19

R/W

0h

0h = no interrupt generation for IN22.

1h = interrupt generation on rising edge above

THRES_COMP_IN20_IN23 for IN22.

2h = interrupt generation on falling edge below

THRES_COMP_IN20_IN23 for IN22.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN20_IN23 for IN22.

0h = no interrupt generation for IN21.

1h = interrupt generation on rising edge above

THRES_COMP_IN20_IN23 for IN21.

2h = interrupt generation on falling edge below

THRES_COMP_IN20_IN23 for IN21.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN20_IN23 for IN21.

0h = no interrupt generation for IN20.

1h = interrupt generation on rising edge above

THRES_COMP_IN20_IN23 for IN20.

2h = interrupt generation on falling edge below

THRES_COMP_IN20_IN23 for IN20.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN20_IN23 for IN20.

0h = no interrupt generation for IN19.

1h = interrupt generation on rising edge above

THRES_COMP_IN16_IN19 for IN19.

2h = interrupt generation on falling edge below

THRES_COMP_IN16_IN19 for IN19.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN16_IN19 for IN19.

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表8-43. INT_EN_COMP2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13-12

INC_EN_18

R/W

0h

0h = no interrupt generation for IN18.

1h = interrupt generation on rising edge above

THRES_COMP_IN16_IN19 for IN18.

2h = interrupt generation on falling edge below

THRES_COMP_IN16_IN19 for IN18.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN16_IN19 for IN18.

11-10

INC_EN_17

INC_EN_16

INC_EN_15

INC_EN_14

INC_EN_13

INC_EN_12

R/W

0h

0h = no interrupt generation for IN17.

1h = interrupt generation on rising edge above

THRES_COMP_IN16_IN19 for IN17.

2h = interrupt generation on falling edge below

THRES_COMP_IN16_IN19 for IN17.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN16_IN19 for IN17.

9-8

0h = no interrupt generation for IN16.

1h = interrupt generation on rising edge above

THRES_COMP_IN16_IN19 for IN16.

2h = interrupt generation on falling edge below

THRES_COMP_IN16_IN19 for IN16.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN16_IN19 for IN16.

7-6

0h = no interrupt generation for IN15.

1h = interrupt generation on rising edge above

THRES_COMP_IN12_IN15 for IN15.

2h = interrupt generation on falling edge below

THRES_COMP_IN12_IN15 for IN15.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN12_IN15 for IN15.

5-4

0h = no interrupt generation for IN14.

1h = interrupt generation on rising edge above

THRES_COMP_IN12_IN15 for IN14.

2h = interrupt generation on falling edge below

THRES_COMP_IN12_IN15 for IN14.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN12_IN15 for IN14.

3-2

0h = no interrupt generation for IN13.

1h = interrupt generation on rising edge above

THRES_COMP_IN12_IN15 for IN13.

2h = interrupt generation on falling edge below

THRES_COMP_IN12_IN15 for IN13.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN12_IN15 for IN13.

1-0

0h = no interrupt generation for IN12.

1h = interrupt generation on rising edge above

THRES_COMP_IN12_IN15 for IN12.

2h = interrupt generation on falling edge below

THRES_COMP_IN12_IN15 for IN12.

3h = interrupt generation on falling and rising edge of

THRES_COMP_IN12_IN15 for IN12.

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8.6.33 INT_EN_CFG0 Register (Offset = 24h) [Reset = 0h]

INT_EN_CFG0 is shown in 图8-56 and described in 表8-44.

Return to Summary Table.

图8-56. INT_EN_CFG0 Register

23

15

7

22

14

6

21

20

19

18

10

17

16

RESERVED

R-0h

13

12

11

9

8

RESERVED

R-0h

ADC_DIAG_EN WET_DIAG_EN

VS1_EN

R/W-0h

VS0_EN

R/W-0h

5

4

3

2

1

0

CRC_CALC_E

N

UV_EN

OV_EN

TW_EN

TSD_EN

SSC_EN

PRTY_FAIL_EN SPI_FAIL_EN

R/W-0h

R/W-0h R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-44. INT_EN_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-12

RESERVED

R

0h

Reserved

11

10

9

ADC_DIAG_EN

WET_DIAG_EN

VS1_EN

R/W

0h

0h = INT pin assertion due to ADC error disabled.

1h = INT pin assertion due to ADC error enabled.

0h = INT pin assertion due to wetting current error disabled.

1h = INT pin assertion due to wetting current error enabled.

0h = INT pin assertion due to VS1 threshold crossing disabled.

1h = INT pin assertion due to VS1 threshold crossing enabled.

8

VS0_EN

0h = INT pin assertion due to VS0 threshold crossing disabled.

1h = INT pin assertion due to VS0 threshold crossing enabled.

7

CRC_CALC_EN

UV_EN

0h = INT pin assertion due to CRC calculation completion disabled.

1h = INT pin assertion due to CRC calculation completion enabled.

6

0h = INT pin assertion due to UV event disabled.

1h = INT pin assertion due to UV event enabled.

5

OV_EN

0h = INT pin assertion due to OV event disabled.

1h = INT pin assertion due to OV event enabled.

4

TW_EN

0h = INT pin assertion due to TW event disabled.

1h = INT pin assertion due to TW event enabled.

3

TSD_EN

0h = INT pin assertion due to TSD event disabled.

1h = INT pin assertion due to TSD event enabled.

2

SSC_EN

0h = INT pin assertion due to SSC event disabled.

1h = INT pin assertion due to SSC event enabled.

1

PRTY_FAIL_EN

SPI_FAIL_EN

0h = INT pin assertion due to parity fail event disabled.

1h = INT pin assertion due to parity fail event enabled.

0

0h = INT pin assertion due to SPI fail event disabled.

1h = INT pin assertion due to SPI fail event enabled.

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8.6.34 INT_EN_CFG1 Register (Offset = 25h) [Reset = 0h]

INT_EN_CFG1 is shown in 图8-57 and described in 表8-45.

Return to Summary Table.

图8-57. INT_EN_CFG1 Register

23

11

22

10

21

9

20

8

19

18

17

16

15

3

14

2

13

1

12

IN6_EN

R/W-0h

0

IN11_EN

R/W-0h

IN10_EN

R/W-0h

IN9_EN

R/W-0h

IN8_EN

R/W-0h

IN7_EN

R/W-0h

7

6

5

4

IN5_EN

R/W-0h

IN4_EN

R/W-0h

IN3_EN

R/W-0h

IN2_EN

R/W-0h

IN1_EN

R/W-0h

IN0_EN

R/W-0h

LEGEND: R/W = Read/Write

表8-45. INT_EN_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-22

IN11_EN

R/W

0h

0h = no interrupt generation for IN11.

1h = interrupt generation on rising edge above THRESx for IN11.

2h = interrupt generation on falling edge below THRESx for IN11.

3h = interrupt generation on falling and rising edge of THRESx for

IN11.

21-20

19-18

17-16

15-14

13-12

11-10

IN10_EN

IN9_EN

IN8_EN

IN7_EN

IN6_EN

IN5_EN

R/W

0h

0h = no interrupt generation for IN10.

1h = interrupt generation on rising edge above THRESx for IN10.

2h = interrupt generation on falling edge below THRESx for IN10.

3h = interrupt generation on falling and rising edge of THRESx for

IN10.

0h = no interrupt generation for IN9.

1h = interrupt generation on rising edge above THRESx for IN9.

2h = interrupt generation on falling edge below THRESx for IN9.

3h = interrupt generation on falling and rising edge of THRESx for

IN9.

0h = no interrupt generation for IN8.

1h = interrupt generation on rising edge above THRESx for IN8.

2h = interrupt generation on falling edge below THRESx for IN8.

3h = interrupt generation on falling and rising edge of THRESx for

IN8.

0h = no interrupt generation for IN7.

1h = interrupt generation on rising edge above THRESx for IN7.

2h = interrupt generation on falling edge below THRESx for IN7.

3h = interrupt generation on falling and rising edge of THRESx for

IN7.

0h = no interrupt generation for IN6.

1h = interrupt generation on rising edge above THRESx for IN6.

2h = interrupt generation on falling edge below THRESx for IN6.

3h = interrupt generation on falling and rising edge of THRESx for

IN6.

0h = no interrupt generation for IN5.

1h = interrupt generation on rising edge above THRESx for IN5.

2h = interrupt generation on falling edge below THRESx for IN5.

3h = interrupt generation on falling and rising edge of THRESx for

IN5.

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表8-45. INT_EN_CFG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

9-8

IN4_EN

IN3_EN

IN2_EN

IN1_EN

IN0_EN

R/W

0h

0h = no interrupt generation for IN4.

1h = interrupt generation on rising edge above THRESx for IN4.

2h = interrupt generation on falling edge below THRESx for IN4.

3h = interrupt generation on falling and rising edge of THRESx for

IN4.

7-6

5-4

3-2

1-0

R/W

0h

0h = no interrupt generation for IN3.

1h = interrupt generation on rising edge above THRESx for IN3.

2h = interrupt generation on falling edge below THRESx for IN3.

3h = interrupt generation on falling and rising edge of THRESx for

IN3.

0h = no interrupt generation for IN2.

1h = interrupt generation on rising edge above THRESx for IN2.

2h = interrupt generation on falling edge below THRESx for IN2.

3h = interrupt generation on falling and rising edge of THRESx for

IN2.

0h = no interrupt generation for IN1.

1h = interrupt generation on rising edge above THRESx for IN1.

2h = interrupt generation on falling edge below THRESx for IN1.

3h = interrupt generation on falling and rising edge of THRESx for

IN1.

0h = no interrupt generation for IN0.

1h = interrupt generation on rising edge above THRESx for IN0.

2h = interrupt generation on falling edge below THRESx for IN0.

3h = interrupt generation on falling and rising edge of THRESx for

IN0.

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8.6.35 INT_EN_CFG2 Register (Offset = 26h) [Reset = 0h]

INT_EN_CFG2 is shown in 图8-58 and described in 表8-46.

Return to Summary Table.

图8-58. INT_EN_CFG2 Register

23

11

22

10

21

9

20

8

19

18

17

16

15

3

14

2

13

1

12

0

IN17_EN

R/W-0h

IN16_EN

R/W-0h

IN15_EN

R/W-0h

7

6

5

4

IN14_EN

R/W-0h

IN13_EN

R/W-0h

IN12_EN

R/W-0h

LEGEND: R/W = Read/Write

表8-46. INT_EN_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

IN17_EN

R/W

0h

xx00: no interrupt generation for IN17 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN17.

xx10: interrupt generation on falling edge below THRES2A for IN17.

xx11: interrupt generation on falling and rising edge of THRES2A for

IN17.

00xx: no interrupt generation for IN17 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN17.

10xx: interrupt generation on falling edge below THRES2B for IN17.

11xx: interrupt generation on falling and rising edge of THRES2B for

IN17.

19-16

IN16_EN

R/W

0h

xx00: no interrupt generation for IN16 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN16.

xx10: interrupt generation on falling edge below THRES2A for IN16.

xx11: interrupt generation on falling and rising edge of THRES2A for

IN16.

00xx: no interrupt generation for IN16 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN16.

10xx: interrupt generation on falling edge below THRES2B for IN16.

11xx: interrupt generation on falling and rising edge of THRES2B for

IN16.

15-12

IN15_EN

R/W

0h

xx00: no interrupt generation for IN15 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN15.

xx10: interrupt generation on falling edge below THRES2A for IN15.

xx11: interrupt generation on falling and rising edge of THRES2A for

IN15.

00xx: no interrupt generation for IN15 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN15.

10xx: interrupt generation on falling edge below THRES2B for IN15.

11xx: interrupt generation on falling and rising edge of THRES2B for

IN15.

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表8-46. INT_EN_CFG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11-8

IN14_EN

IN13_EN

IN12_EN

R/W

0h

xx00: no interrupt generation for IN14 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN14.

xx10: interrupt generation on falling edge below THRES2A for IN14.

xx11: interrupt generation on falling and rising edge of THRES2A for

IN14.

00xx: no interrupt generation for IN14 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN14.

10xx: interrupt generation on falling edge below THRES2B for IN14.

11xx: interrupt generation on falling and rising edge of THRES2B for

IN14.

7-4

R/W

0h

xx00: no interrupt generation for IN13 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN13.

xx10: interrupt generation on falling edge below THRES2A for IN13.

xx11: interrupt generation on falling and rising edge of THRES2A for

IN13.

00xx: no interrupt generation for IN13 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN13.

10xx: interrupt generation on falling edge below THRES2B for IN13.

11xx: interrupt generation on falling and rising edge of THRES2B for

IN13.

3-0

R/W

0h

xx00: no interrupt generation for IN12 w.r.t. THRES2A.

xx01: interrupt generation on rising edge above THRES2A for IN12.

xx10: interrupt generation on falling edge below THRES2A for IN12.

xx11: interrupt generation on falling and rising edge of THRES2A for

IN12.

00xx: no interrupt generation for IN12 w.r.t. THRES2B.

01xx: interrupt generation on rising edge above THRES2B for IN12.

10xx: interrupt generation on falling edge below THRES2B for IN12.

11xx: interrupt generation on falling and rising edge of THRES2B for

IN12.

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8.6.36 INT_EN_CFG3 Register (Offset = 27h) [Reset = 0h]

INT_EN_CFG3 is shown in 图8-59 and described in 表8-47.

Return to Summary Table.

图8-59. INT_EN_CFG3 Register

23

11

22

10

21

9

20

8

19

18

17

16

15

3

14

2

13

1

12

0

IN21_EN

R/W-0h

IN20_EN

R/W-0h

7

6

5

4

IN19_EN

R/W-0h

IN18_EN

R/W-0h

LEGEND: R/W = Read/Write

表8-47. INT_EN_CFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-18

IN21_EN

R/W

0h

xxxx00: no interrupt generation for IN21 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for

IN21

xxxx10: interrupt generation on falling edge below THRES3A for

IN21

xxxx11: interrupt generation on falling and rising edge of THRES3A

for IN21

xx00xx: no interrupt generation for IN21 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for

IN21

xx10xx: interrupt generation on falling edge below THRES3B for

IN21

xx11xx: interrupt generation on falling and rising edge of THRES3B

for IN21

00xxxx: no interrupt generation for IN21 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for

IN21

10xxxx: interrupt generation on falling edge below THRES3C for

IN21

11xxxx: interrupt generation on falling and rising edge of THRES3C

for IN21

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表8-47. INT_EN_CFG3 Register Field Descriptions (continued)

Bit

Field

IN20_EN

Type

Reset

Description

17-12

R/W

0h

xxxx00: no interrupt generation for IN20 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for

IN20

xxxx10: interrupt generation on falling edge below THRES3A for

IN20

xxxx11: interrupt generation on falling and rising edge of THRES3A

for IN20

xx00xx: no interrupt generation for IN20 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for

IN20

xx10xx: interrupt generation on falling edge below THRES3B for

IN20

xx11xx: interrupt generation on falling and rising edge of THRES3B

for IN20

00xxxx: no interrupt generation for IN20 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for

IN20

10xxxx: interrupt generation on falling edge below THRES3C for

IN20

11xxxx: interrupt generation on falling and rising edge of THRES3C

for IN20

11-6

IN19_EN

R/W

0h

xxxx00: no interrupt generation for IN19 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for

IN19

xxxx10: interrupt generation on falling edge below THRES3A for

IN19

xxxx11: interrupt generation on falling and rising edge of THRES3A

for IN19

xx00xx: no interrupt generation for IN19 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for

IN19

xx10xx: interrupt generation on falling edge below THRES3B for

IN19

xx11xx: interrupt generation on falling and rising edge of THRES3B

for IN19

00xxxx: no interrupt generation for IN19 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for

IN19

10xxxx: interrupt generation on falling edge below THRES3C for

IN19

11xxxx: interrupt generation on falling and rising edge of THRES3C

for IN19

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表8-47. INT_EN_CFG3 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

IN18_EN

R/W

0h

xxxx00: no interrupt generation for IN18 w.r.t. THRES3A

xxxx01: interrupt generation on rising edge above THRES3A for

IN18

xxxx10: interrupt generation on falling edge below THRES3A for

IN18

xxxx11: interrupt generation on falling and rising edge of THRES3A

for IN18

xx00xx: no interrupt generation for IN18 w.r.t. THRES3B

xx01xx: interrupt generation on rising edge above THRES3B for

IN18

xx10xx: interrupt generation on falling edge below THRES3B for

IN18

xx11xx: interrupt generation on falling and rising edge of THRES3B

for IN18

00xxxx: no interrupt generation for IN18 w.r.t. THRES3C

01xxxx: interrupt generation on rising edge above THRES3C for

IN18

10xxxx: interrupt generation on falling edge below THRES3C for

IN18

11xxxx: interrupt generation on falling and rising edge of THRES3C

for IN18

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8.6.37 INT_EN_CFG4 Register (Offset = 28h) [Reset = 0h]

INT_EN_CFG4 is shown in 图8-60 and described in 表8-48.

Return to Summary Table.

图8-60. INT_EN_CFG4 Register

23

11

22

VS_TH1_EN

R/W-0h

21

20

8

19

18

VS_TH0_EN

R/W-0h

17

16

15

3

14

2

13

1

12

0

IN23_EN

R/W-0h

10

9

7

6

5

4

IN23_EN

R/W-0h

IN22_EN

R/W-0h

LEGEND: R/W = Read/Write

表8-48. INT_EN_CFG4 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

VS_TH1_EN

R/W

0h

xx00: no interrupt generation for V_Sw.r.t. VS1_THRES2A.

xx01: interrupt generation on rising edge above VS1_THRES2A for

V_S.

xx10: interrupt generation on falling edge below VS1_THRES2A for

V_S.

xx11: interrupt generation on falling and rising edge of

VS1_THRES2A for V_S.

00xx: no interrupt generation for V_Sw.r.t. VS1_THRES2B.

01xx: interrupt generation on rising edge above VS1_THRES2B for

V_S.

10xx: interrupt generation on falling edge below VS1_THRES2B for

V_S.

11xx: interrupt generation on falling and rising edge of

VS1_THRES2B for V_S.

19-16

VS_TH0_EN

R/W

0h

xx00: no interrupt generation for V_Sw.r.t. VS0_THRES2A.

xx01: interrupt generation on rising edge above VS0_THRES2A for

V_S.

xx10: interrupt generation on falling edge below VS0_THRES2A for

V_S.

xx11: interrupt generation on falling and rising edge of

VS0_THRES2A for VS.

00xx: no interrupt generation for V_Sw.r.t. VS0_THRES2B.

01xx: interrupt generation on rising edge above VS0_THRES2B for

V_S.

10xx: interrupt generation on falling edge below VS0_THRES2B for

V_S.

11xx: interrupt generation on falling and rising edge of

VS0_THRES2B for V_S.

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表8-48. INT_EN_CFG4 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

15-6

IN23_EN

R/W

0h

xxxxxxxx00: no interrupt generation for IN23 w.r.t. THRES3A.

xxxxxxxx01: interrupt generation on rising edge above THRES3A for

IN23.

xxxxxxxx10: interrupt generation on falling edge below THRES3A for

IN23.

xxxxxxxx11: interrupt generation on falling and rising edge of

THRES3A for IN23.

xxxxxx00xx: no interrupt generation for IN23 w.r.t. THRES3B.

xxxxxx01xx: interrupt generation on rising edge above THRES3B for

IN23.

xxxxxx10xx: interrupt generation on falling edge below THRES3B for

IN23.

xxxxxx11xx: interrupt generation on falling and rising edge of

THRES3B for IN23.

xxxx00xxxx: no interrupt generation for IN23 w.r.t. THRES3C.

xxxx01xxxx: interrupt generation on rising edge above THRES3C for

IN23.

xxxx10xxxx: interrupt generation on falling edge below THRES3C for

IN23.

xxxx11xxxx: interrupt generation on falling and rising edge of

THRES3C for IN23.

xx00xxxxxx: no interrupt generation for IN23 w.r.t. THRES8.

xx01xxxxxx: interrupt generation on rising edge above THRES8 for

IN23.

xx10xxxxxx: interrupt generation on falling edge below THRES8 for

IN23.

xx11xxxxxx: interrupt generation on falling and rising edge of

THRES8 for IN23.

00xxxxxxxx: no interrupt generation for IN23 w.r.t. THRES9.

01xxxxxxxx: interrupt generation on rising edge above THRES9 for

IN23.

10xxxxxxxx: interrupt generation on falling edge below THRES9 for

IN23.

11xxxxxxxx: interrupt generation on falling and rising edge of

THRES9 for IN23.

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表8-48. INT_EN_CFG4 Register Field Descriptions (continued)

Bit

Field

IN22_EN

Type

Reset

Description

5-0

R/W

0h

xxxx00: no interrupt generation for IN22 w.r.t. THRES3A.

xxxx01: interrupt generation on rising edge above THRES3A for

IN22.

xxxx10: interrupt generation on falling edge below THRES3A for

IN22.

xxxx11: interrupt generation on falling and rising edge of THRES3A

for IN22.

xx00xx: no interrupt generation for IN22 w.r.t. THRES3B.

xx01xx: interrupt generation on rising edge above THRES3B for

IN22.

xx10xx: interrupt generation on falling edge below THRES3B for

IN22.

xx11xx: interrupt generation on falling and rising edge of THRES3B

for IN22.

00xxxx: no interrupt generation for IN22 w.r.t. THRES3C.

01xxxx: interrupt generation on rising edge above THRES3C for

IN22.

10xxxx: interrupt generation on falling edge below THRES3C for

IN22.

11xxxx: interrupt generation on falling and rising edge of THRES3C

for IN22.

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8.6.38 THRES_CFG0 Register (Offset = 29h) [Reset = 0h]

THRES_CFG0 is shown in 图8-61 and described in 表8-49.

Return to Summary Table.

图8-61. THRES_CFG0 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

THRES1

R-0h

THRES0

R-0h

LEGEND: R/W = Read/Write; R = Read only

表8-49. THRES_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

THRES1

R/W

0h

10-bits value of threshold 1:

Bit10: LSB

Bit19: MSB

9-0

THRES0

10-bits value of threshold 0

Bit0: LSB

Bit9: MSB

8.6.39 THRES_CFG1 Register (Offset = 2Ah) [Reset = 0h]

THRES_CFG1 is shown in 图8-62 and described in 表8-50.

Return to Summary Table.

图8-62. THRES_CFG1 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

THRES3

R-0h

THRES2

R-0h

LEGEND: R/W = Read/Write; R = Read only

表8-50. THRES_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

THRES3

R/W

0h

10-bits value of threshold 3:

Bit10: LSB

Bit19: MSB

9-0

THRES2

10-bits value of threshold 2

Bit0: LSB

Bit9: MSB

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8.6.40 THRES_CFG2 Register (Offset = 2Bh) [Reset = 0h]

THRES_CFG2 is shown in 图8-63 and described in 表8-51.

Return to Summary Table.

图8-63. THRES_CFG2 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

THRES5

R-0h

THRES4

R-0h

LEGEND: R/W = Read/Write; R = Read only

表8-51. THRES_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

THRES5

R/W

0h

10-bits value of threshold 5:

Bit10: LSB

Bit19: MSB

10-1

THRES4

10-bits value of threshold 4:

Bit0: LSB

Bit9: MSB

8.6.41 THRES_CFG3 Register (Offset = 2Ch) [Reset = X]

THRES_CFG3 is shown in 图8-64 and described in 表8-52.

Return to Summary Table.

图8-64. THRES_CFG3 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

THRES6

R-0h

THRES7

R-0h

LEGEND: R/W = Read/Write; R = Read only

表8-52. THRES_CFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

THRES7

R/W

0h

10-bits value of threshold 7:

Bit10: LSB

Bit19: MSB

9-0

THRES6

10-bits value of threshold 6:

Bit0: LSB

Bit9: MSB

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8.6.42 THRES_CFG4 Register (Offset = 2Dh) [Reset = X]

THRES_CFG4 is shown in 图8-65 and described in 表8-53.

Return to Summary Table.

图8-65. THRES_CFG4 Register

23 22 21 20 19 18 17 16 15 14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R-0h

THRES9

R-0h

THRES8

R-0h

LEGEND: R/W = Read/Write; R = Read only

表8-53. THRES_CFG4 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-20

RESERVED

R

0h

Reserved

19-10

THRES9

R/W

0h

10-bits value of threshold 9:

Bit10: LSB

Bit19: MSB

9-0

THRES8

10-bits value of threshold 8:

Bit0: LSB

Bit9: MSB

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8.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [Reset = 0h]

THRESMAP_CFG0 is shown in 图8-66 and described in 表8-54.

Return to Summary Table.

图8-66. THRESMAP_CFG0 Register

23

11

22

THRESMAP_IN7

R/W-0h

21

9

20

8

19

18

17

16

15

3

14

2

13

THRESMAP_IN4

R/W-0h

12

0

THRESMAP_IN6

THRESMAP_IN5

R/W-0h

7

R/W-0h

4

10

6

5

1

THRESMAP_IN3

R/W-0h

THRESMAP_IN2

R/W-0h

THRESMAP_IN1

R/W-0h

THRESMAP_IN0

R/W-0h

LEGEND: R/W = Read/Write

表8-54. THRESMAP_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-21

THRESMAP_IN7

R/W

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

20-18

17-15

14-12

THRESMAP_IN6

THRESMAP_IN5

THRESMAP_IN4

R/W

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

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表8-54. THRESMAP_CFG0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11-9

THRESMAP_IN3

R/W

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8-6

5-3

2-0

THRESMAP_IN2

THRESMAP_IN1

THRESMAP_IN0

R/W

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

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8.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [Reset = 0h]

THRESMAP_CFG1 is shown in 图8-67 and described in 表8-55.

Return to Summary Table.

图8-67. THRESMAP_CFG1 Register

23

22

21

20

19

18

17

16

15

14

13

12

RESERVED

THRESMAP_IN12_IN17_THRES THRESMAP_IN12_IN17_THRES

2B

R/W-0h

2A

R/W-0h

11

10

9

8

7

6

5

4

3

2

1

0

THRESMAP_IN11

R/W-0h

THRESMAP_IN10

R/W-0h

THRESMAP_IN9

R/W-0h

THRESMAP_IN8

R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-55. THRESMAP_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-18

RESERVED

R

0h

Reserved

17-15

14-12

11-9

THRESMAP_IN12_IN17_ R/W

THRES2B

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

THRESMAP_IN12_IN17_ R/W

THRES2A

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

THRESMAP_IN11

R/W

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

8-6

THRESMAP_IN10

R/W

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

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表8-55. THRESMAP_CFG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-3

THRESMAP_IN9

R/W

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

2-0

THRESMAP_IN8

R/W

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

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8.6.45 THRESMAP_CFG2 Register (Offset = 30h) [Reset = 0h]

THRESMAP_CFG2 is shown in 图8-68 and described in 表8-56.

Return to Summary Table.

图8-68. THRESMAP_CFG2 Register

23

22

RESERVED

R-0h

21

20

19

18

17

16

15

14

13

12

THRESMAP_VS1_THRES2B

R/W-0h

THRESMAP_VS1_THRES2A

R/W-0h

THRESMAP_VS0_THRES2B

R/W-0h

11

10

9

8

7

6

5

4

3

2

1

0

THRESMAP_VS0_THRES2A

THRESMAP_IN18_IN23_THRES THRESMAP_IN18_IN23_THRES THRESMAP_IN18_IN23_THRES

3C

3B

3A

R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-56. THRESMAP_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

23-21

RESERVED

R

0h

Reserved

20-18

17-15

14-12

11-9

THRESMAP_VS1_THRE R/W

S2B

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

THRESMAP_VS1_THRE R/W

S2A

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

THRESMAP_VS0_THRE R/W

S2B

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

THRESMAP_VS0_THRE R/W

S2A

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

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表8-56. THRESMAP_CFG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8-6

THRESMAP_IN18_IN23_ R/W

THRES3C

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

5-3

THRESMAP_IN18_IN23_ R/W

THRES3B

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

2-0

THRESMAP_IN18_IN23_ R/W

THRES3A

0h

0h = THRES0

1h = THRES1

2h = THRES2

3h = THRES3

4h = THRES4

5h = THRES5

6h = THRES6

7h = THRES7

112

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8.6.46 Matrix Register (Offset = 31h) [Reset = 0h]

Matrix is shown in 图8-69 and described in 表8-57.

Return to Summary Table.

图8-69. Matrix Register

23

11

22

10

21

9

20

RESERVED

R-0h

19

7

18

17

16

15

14

2

13

THRES_COM

R/W-0h

1

12

0

IN_COM_EN

R/W-0h

8

6

5

4

3

THRES_COM

R/W-0h

MATRIX

R/W-0h

POLL_ACT_TIME_M

R/W-0h

LEGEND: R/W = Read/Write; R = Read only

表8-57. Matrix Register Field Descriptions

Bit

Field

Type

Reset

Description

23-17

RESERVED

R

0h

Reserved

16-15

IN_COM_EN

R/W

0h

0h = no interrupt generation for w.r.t. threshold THRES_COM

1h = interrupt generation on rising edge above threshold

THRES_COM

2h = interrupt generation on falling edge below threshold

THRES_COM

3h = interrupt generation on falling and rising edge of threshold

THRES_COM

14-5

4-3

THRES_COM

MATRIX

R/W

0h

10-bits value of threshold THRES_COM:

Bit5: LSB

Bit14: MSB

0h = no matrix, regular inputs only

1h = 4×4 matrix

2h = 5×5 matrix

3h = 6×6 matrix

2-0

POLL_ACT_TIME_M

R/W

0h

Polling active time setting for the matrix inputs:

0h = 64 μs

1h = 128 μs

2h = 256 μs

3h = 384 μs

4h = 512 μs

5h = 768 μs

6h = 1024 μs

7h = 1360 μs

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8.6.47 Mode Register (Offset = 32h) [Reset = 0h]

Mode is shown in 图8-70 and described in 表8-58.

Return to Summary Table.

图8-70. Mode Register

23

22

21

20

19

18

17

16

15

14

13

12

M_IN23

R/W-0h

11

M_IN22

R/W-0h

10

M_IN21

R/W-0h

9

M_IN20

R/W-0h

8

M_IN19

R/W-0h

7

M_IN18

R/W-0h

6

M_IN17

R/W-0h

5

M_IN16

R/W-0h

4

M_IN15

R/W-0h

3

M_IN14

R/W-0h

2

M_IN13

R/W-0h

1

M_IN12

R/W-0h

0

M_IN11

R/W-0h

M_IN10

R/W-0h

M_IN9

R/W-0h

M_IN8

R/W-0h

M_IN7

R/W-0h

M_IN6

R/W-0h

M_IN5

R/W-0h

M_IN4

R/W-0h

M_IN3

R/W-0h

M_IN2

R/W-0h

M_IN1

R/W-0h

M_IN0

R/W-0h

LEGEND: R/W = Read/Write

表8-58. Mode Register Field Descriptions

Bit

Field

Type

Reset

Description

23

M_IN23

R/W

0h

0h = comparator mode for IN23

1h = ADC mode for IN23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

M_IN22

M_IN21

M_IN20

M_IN19

M_IN18

M_IN17

M_IN16

M_IN15

M_IN14

M_IN13

M_IN12

M_IN11

M_IN10

M_IN9

R/W

0h

0h = comparator mode for IN22

1h = ADC mode for IN22

0h = comparator mode for IN21

1h = ADC mode for IN21

0h = comparator mode for IN20

1h = ADC mode for IN20

0h = comparator mode for IN19

1h = ADC mode for IN19

0h = comparator mode for IN18

1h = ADC mode for IN18

0h = comparator mode for IN17

1h = ADC mode for IN17

0h = comparator mode for IN16

1h = ADC mode for IN16

0h = comparator mode for IN15

1h = ADC mode for IN15

0h = comparator mode for IN14

1h = ADC mode for IN14

0h = comparator mode for IN13

1h = ADC mode for IN13

0h = comparator mode for IN12

1h = ADC mode for IN12

0h = comparator mode for IN11

1h = ADC mode for IN11

0h = comparator mode for IN10

1h = ADC mode for IN10

0h = comparator mode for IN9

1h = ADC mode for IN9

8

M_IN8

0h = comparator mode for IN8

1h = ADC mode for IN8

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表8-58. Mode Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7

M_IN7

M_IN6

M_IN5

M_IN4

M_IN3

M_IN2

M_IN1

M_IN0

R/W

0h

0h = comparator mode for IN7

1h = ADC mode for IN7

6

5

4

3

2

1

0

R/W

0h

0h = comparator mode for IN6

1h = ADC mode for IN6

0h = comparator mode for IN5

1h = ADC mode for IN5

0h = comparator mode for IN4

1h = ADC mode for IN4

0h = comparator mode for IN3

1h = ADC mode for IN1

0h = comparator mode for IN2

1h = ADC mode for IN0

0h = comparator mode for IN1

1h = ADC mode for IN1

0h = comparator mode for IN0

1h = ADC mode for IN0

8.7 Programming Guidelines

When configuring the TIC12400-Q1, it is critical to follow the programming guideline summarized below (see 表

8-59) to ensure proper behavior of the device:

表8-59. TIC12400-Q1 Programming Guidelines


型号：	TIC12400QDCPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 SPI 和集成 ADC 的汽车类 35V 多开关检测接口 (MSDI) \| DCP \| 38 \| -40 to 125 开关光电二极管
文件：	总137页 (文件大小：3718K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TIC12400QDCPRQ1 [TI]

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