TIOS102 [TI]
具有低残余电压和集成浪涌保护功能的数字传感器输出驱动器;
| 型号： | TIOS102 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低残余电压和集成浪涌保护功能的数字传感器输出驱动器 驱动 传感器 驱动器 |
| 文件： | 总36页 (文件大小：2471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
具有集成浪涌保护功能的小封装TIOS102 和TIOS102x 数字传感器输出驱动器
1 特性
2 应用
• 宽电源运行
• 接近开关
• 电容式和电感式传感器
• 传动器
• 数字输出
– 4.75V 至36V 电源电压（TIOS102、
TIOS1023）
– 7V 至36V 电源电压(TIOS1025)
• PNP、NPN 或推挽可配置输出
• 提供功能安全
3 说明
TIOS102(x) 器件可配置为高侧、低侧或推挽驱动器。
这些器件能够承受高达 1.2kV (500Ω) 的 IEC
61000-4-5 浪涌，并集成反向极性保护功能。
– 有助于进行功能安全系统设计的文档
• 与TIOS101(x) 引脚兼容，并提升了性能
– 在200mA 条件下，残余电压低，为0.5V
（典型值）
– 提供驱动器电流限制能力
– 改善了封装的热性能
– 更低的驱动器压摆率，可减少过冲（最大
750ns）
只需通过一个引脚可编程接口便可轻松连接到电路。可
使用外部电阻器配置输出电流限值。提供了故障报告和
内部保护功能，可应对欠压、过流和过热条件。
封装信息
封装(1)
封装尺寸(2)
器件型号
TIOS102
• 集成保护特性，使系统更加稳健
– 可配置驱动器过流限制：
（50mA 至350mA）
– 在VCC、OUT 和GND 上提供高达65V 的反极
性保护
TIOS1023
TIOS1025
TIOS102
VSON (10)
3mm x 3mm
DSBGA (12)
2.45 mm x 1.7 mm
TIOS1023L
– 过流、过热和UVLO 的故障指示灯
– 支持高感性负载的安全快速消磁
– 工作环境温度范围：-40°C 至125°C
• VCC 和OUT 上集成EMC 保护功能
(1) 如需了解所有可订购器件，请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
– ±8 kV IEC 61000-4-2 ESD 接触放电
– ±4kV IEC 61000-4-4 电气快速瞬变
– ±1.2kV/500Ω IEC 61000-4-5 浪涌
• 能驱动高容性负载
VCC_OUT
VCC
Rev. Polarity
Protection
VOLTAGE
REGULATOR
0.1 µF
100 V
1 µF
10 V
ESD and Surge
10 k
Protection
IN
OUT
GND
Sensor
Front-End
• 静态电源电流小于1.5mA 典型值（禁用驱动器时）
• 集成式LDO 选项可支持高达20mA 的电流
EN
Diagnostics
& Control
Rev. Polarity
Protection
ESD and Surge
Protection
NFAULT
– TIOS1023：3.3V LDO
– TIOS1025：5V LDO
– TIOS1023L (DSBGA)：可选3.3V/5V LDO 输出
• 节省空间的小型封装选项
CUR _ OK
TMP _ OK
PWR _ OK
ILM_ADJ
RSET
– 3mm x 3mm 10 引脚VSON 封装（与TIOS101
引脚兼容）
典型应用图
– 2.45 mm x 1.7 mm DSBGA 封装
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................16
9 Application Information Disclaimer.............................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 18
10 Power Supply Recommendations..............................22
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................24
12.1 接收文档更新通知................................................... 24
12.2 支持资源..................................................................24
12.3 Trademarks.............................................................24
12.4 静电放电警告.......................................................... 24
12.5 术语表..................................................................... 24
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 ESD Ratings - IEC Specifications...............................5
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information....................................................6
6.6 Electrical Characteristics.............................................6
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................9
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagrams....................................... 11
Information.................................................................... 24
13.1 Mechanical Data..................................................... 25
4 Revision History
Changes from Revision A (December 2022) to Revision B (June 2023)
Page
• 删除了器件信息 表中DSBGA 封装的产品预发布 注释...................................................................................... 1
• 将“器件信息”表更改为封装信息 表.................................................................................................................1
• Changed the DRC package images................................................................................................................... 3
• Added the custom images for the YAH (DSBGA) 12-pin package................................................................... 24
Changes from Revision * (February 2022) to Revision A (December 2022)
Page
• 将数据表中的 VSON 封装从预告信息 更改为量产 数据..................................................................................... 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFL4
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TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
5 Pin Configuration and Functions
VCC_OUT
NFAULT
NC
1
2
3
4
5
10
9
NC
VCC_IN
NFAULT
NC
1
2
3
4
5
10
9
NC
VCC
VCC
Thermal
Pad
Thermal
Pad
8
OUT
8
OUT
IN
7
GND
IN
7
GND
EN
6
ILIM_ADJ
EN
6
ILIM_ADJ
Not to scale
Not to scale
图5-1. TIOS1023, TIOS1025
DRC, 10-Pin VSON
(Top View)
图5-2. TIOS102
DRC, 10-Pin VSON
(Top View)
表5-1. Pin Functions (VSON Package)
PIN
NAME
PIN NO
Type
DESCRIPTION
TIOS1023,
TIOS1025
TIOS102
1
2
VCC_IN
VCC_OUT
P
3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option without
LDO.
NFAULT
NFAULT
O
Fault indicator output signal to the microcontroller. Connect this pin via pull-up resistor to
VCC_IN (TIOS102) or VCC_OUT (TIOS1023, TIOS1025)
3
4
NC
IN
NC
IN
-
I
Do not connect to GND. Leave floating
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side
switch. Logic low sets high-side switch. Weak internal pull-up.
5
EN
EN
I
Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-Z.
Weak internal pull-down.
6
7
ILIM_ADJ
GND
ILIM_ADJ
GND
I
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND.
Device ground connection
GND
8
OUT
VCC
NC
OUT
VCC
NC
O
P
-
Driver output
9
Supply voltage (24 V nominal)
10
Do not connect to GND. Leave floating
Connect to GND plane for optimal thermal and electrical performance
Thermal Pad Thermal Pad
—
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TIOS102 TIOS1023 TIOS1025
English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
1
2
3
1
2
3
A
B
C
D
GND
OUT
VCC
A
B
C
D
GND
OUT
VCC
ILIM_ADJ
VSEL
NC
GND
NC
VCC_OUT
NFAULT
ILIM_ADJ
GND
NC
VCC_IN
NFAULT
NC
TX
EN
NC
TX
EN
Not to scale
Not to scale
图5-3. TIOS1023L
YAH, 12-Pin DSBGA
(Top View)
图5-4. TIOS102
YAH, 12-Pin DSBGA
(Top View)
表5-2. Pin Functions (DSBGA)
PIN NAME
PIN NO
Type
DESCRIPTION
TIOS102
TIOS1023L
B3
C3
VCC_IN
VCC_OUT
P
3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option
without LDO.
NFAULT
NFAULT
O
Fault indicator output signal to the microcontroller. Connect this pin via pull-up resistor
to VCC_IN (TIOS102) or VCC_OUT
(TIOS1023, TIOS1025)
D2
D3
B1
TX
EN
TX
EN
I
I
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-
side switch. Logic low sets high-side switch. Weak internal pull-up.
Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-
Z. Weak internal pull-down.
ILIM_ADJ
GND
ILIM_ADJ
GND
I
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND.
Device ground connection
A1,
B2
GND
A2
A3
OUT
VCC
OUT
VCC
O
P
Switch output
Supply voltage (24 V nominal)
D1,
C2
NC
NC
-
Leave floating. Do not connect.
TIOS102: Leave floating. Do not connect
C1
NC
VSEL
I
TIOS1023L: VSEL: Connect to GND for 5V LDO output. Please leave this pin floating
for 3.3V LDO output
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Product Folder Links: TIOS102 TIOS1023 TIOS1025
English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
–70
MAX
65
70
65
6
UNIT
Steady state voltage for VCC and OUT
Supply voltage
V
V
V
V
Transient pulse width < 100 µs for VCC and OUT
Voltage difference
|V(VCC) –V(OUT)
|
Logic supply voltage (TIOS102)
VCC_IN
–0.3
–0.3
min(VCC_IN
+0.3, 6)
Input logic voltage
IN, EN, VSEL, ILIM_ADJ
NFAULT
V
Output current
5
mA
°C
–5
Storage temperature, Tstg
-55
170
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime. All voltages are with reference to the GND pin, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
All pins
All pins
±4000
V
Charged Device Model (CDM), per ANSI/ESDA/JEDEC
JS-002 (2)
±750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
6.3 ESD Ratings - IEC Specifications
VALUE
UNIT
(1)
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
IEC 61000-4-2 ESD (Contact Discharge), VCC, OUT and GND
±8,000
±1,200
±4,000
IEC 61000-4-5, 1.2 µs/50 µs Surge with 500 Ω in series, VCC, OUT and GND (1)
IEC 61000-4-4 EFT (Fast transient or burst), VCC, OUT and GND (1)
V(ESD)
V
(1) Minimum 100-nF capacitor is required between VCC and GND. Minimum 1-µF capacitor is required between VCC_IN/VCC_OUT and
GND.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TIOS102,TIOS1023,
TIO1023L (3.3V output)
4.75
24
36
V
V(VCC)
Supply voltage
TIOS1025, TIOS1023L (5V
output)
7
24
36
V
3.3 V configuration
5 V configuration
3
4.5
0
3.3
5
3.6
5.5
V
V
V(VCC_IN)
Logic level input voltage (TIOS102 only)
RSET
1/tBIT
I(VCC_OUT)
TA
External resistor for CQ current limit
Data rate (Communication mode)
110
250
20
kΩ
kbps
mA
°C
LDO output current (TIOS1023,TIOS1023L, TIOS1025 only)
Operating ambient temperature
125
150
–40
TJ
Junction temperature
°C
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Product Folder Links: TIOS102 TIOS1023 TIOS1025
English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
6.5 Thermal Information
TIOS102,
TIOS1023,
TIOS1025
TIOS102, TIOS1023L
THERMAL METRIC (1)
UNIT
DRC (10 Pins)
YAH (12 Pins)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
45.9
45.9
17.9
0.7
79.3
0.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
19.5
0.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
17.8
4.7
19.4
N/A
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). Typical values are at VVCC = 24 V, VVCC_IN = 3.3 V,
VVCC_OUT = 3.3 V and TA = 25 ℃unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VCC)
EN = LOW, no load
1
1.5
mA
mA
I(VCC)
Quiescent supply current
EN = HIGH, no load
2.1
2.95
LOGIC-LEVEL INPUTS (EN, IN, VSEL)
VIL
Input logic low voltage
Input logic high voltage
Pull-down (EN) resistance
Pull-up (IN) resistance
Pull-up (VSEL) resistance
0.8
V
VIH
2
V
RPD
RPU
RPU
100
200
kΩ
kΩ
kΩ
1000
CONTROL OUTPUTS (NFAULT)
VOL
IOZ
Output logic low voltage
IO = 4 mA
0.5
1
V
Output high impedance leakage
Output in Hi-Z, VO = 0 V or VCC_IN/OUT
µA
–1
DRIVER OUTPUT (OUT)
RDS(ON)
VDS(ON)
RDS(ON)
VDS(ON)
High-side driver on-resistance
2.5
0.5
4.5
0.9
0.5
4.5
0.9
0.5
Ω
V
V
I = 200 mA
I = 100 mA
High-side driver residual voltage
Low-side driver on-resistance
Low-side driver residual voltage
0.25
2.5
Ω
V
V
I = 200 mA
0.5
I = 100 mA
0.25
EN = LOW, IN = LOW, RSET: >=
10 kΩ
IPD
IPU
OUT pull-down current
OUT pull-up current
40
40
50
50
80
80
µA
µA
0 ≤V(OUT)
(V(VCC) - 0.1) V
≤
EN = LOW, IN = HIGH
RSET = 10 kΩ;
V(OUT) = (V(VCC)-3) V or 3 V
300
350
400
mA
RSET = 110 kΩ;
V(OUT) = (V(VCC)-3) V or 3 V
35
500
260
50
70
mA
mA
mA
IO(LIM)
Driver output current limit
RSET = 0 to 5 kΩ; (3)
V(OUT) = (V(VCC)-3) V or 3 V
TJ < T(SDN) or t < 200 µs
(Fast-detect mode) RSET = OPEN(1)
V(OUT) = (V(VCC)-3) V or 3 V
330
400
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFL4
6
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6.6 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted). Typical values are at VVCC = 24 V, VVCC_IN = 3.3 V,
VVCC_OUT = 3.3 V and TA = 25 ℃unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
4.2
6
TYP
MAX
UNIT
PROTECTION CIRCUITS
V(UVLO)
V(UVLO)
VCC under voltage lockout
VCC under voltage lockout
VCC falling; NFAULT = Hi-Z
VCC rising; NFAULT = Hi-Z
VCC falling; NFAULT = Hi-Z
VCC rising; NFAULT = Hi-Z
4.4
4.6
6.3
6.5
V
V
V
V
TIOS102 and 3.3V
LDO version
4.75
6.8
V(UVLO)
VCC under voltage lockout
TIOS1025
VCC under voltage lockout
hysteresis
Rising to falling
threshold
V(UVLO,HYS)
Rising to falling threshold
200
mV
VCC_IN falling; NFAULT = Hi-Z
VCC_IN rising; NFAULT = LOW
2.3
2.5
V
V
VCC_IN under voltage lockout
(No LDO option)
V(UVLO_IN)
V(UVLO_IN,HY VCC_IN under voltage hysteresis
Rising to falling threshold
190
mV
(No LDO option)
S)
T(WRN)
T(SDN)
Thermal warning
125
150
°C
°C
Thermal shutdown
160
14
Die temperature TJ
Hysteresis for thermal shutdown
and warning thresholds
T(HYS)
°C
µA
µA
EN=LOW, IN=x; V(OUT) < V(GND) or V(OUT) > V(VCC), up
to |36 V|
60
EN=LOW, IN=x; V(OUT) < V(GND) or V(OUT) > V(VCC), up
to |55 V|
Leakage current in reverse
polarity
110
IREV
EN = HIGH, IN = LOW; V(OUT to VCC) = 3 V
EN = HIGH, IN = HIGH; V(OUT to GND) = -3 V
640
10
µA
µA
LINEAR REGULATOR (LDO)
5 V LDO version
4.75
3.13
5
5.25
3.46
1.9
V
V
V
V
V(VCC_OUT)
Voltage regulator output
3.3 V LDO version
3.3
5 V LDO
ICC = 20 mA load current
3.3 V LDO
Voltage regulator drop-out voltage
(V(VCC) –V(VCC_OUT)
V(DROP)
REG
)
1.4
Line regulation (dV(VCC_OUT)
dV(VCC))
/
I(VCC_OUT) = 1 mA
1.7
1%
mV/V
Load regulation (dV(VCC_OUT)
/
LREG
V(VCC) = 24 V, I(VCC_OUT) = 100 µA to 20 mA
100 kHz, I(VCC_OUT) = 20 mA
V(VCC_OUT)
)
PSSR
Power Supply Rejection Ratio
40
dB
(1) Current fault indication will be active. Current fault auto recovery will be de-activated.
(2) If operating continuously with this current limit, ensure that the current through the device does not cause the TJ to be greater than
T(SDN) for a given ambient temperature and thermal property of the system. For pulse durations t < 200 µs, the device can source or
sink current of at least 500 mA across the recommended operating conditions.
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Product Folder Links: TIOS102 TIOS1023 TIOS1025
English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
tPLH, tPHL
Driver propagation delay
Driver propagation delay skew. |
600
75
1200
ns
ns
tP(skew)
tPLH - tPHL
|
See 图7-3
RL = 2 kΩ
CL = 5 nF
tPZH, tPZL
tPHZ, tPLZ
tr, tf
Driver enable delay
4
4
µs
µs
ns
ns
µs
µs
Driver disable delay
R(SET) = 10 kΩ
Driver output rise, fall time
Difference in rise and fall time
Current fault blanking time
Current fault indication delay
200
175
700
50
|tr –tf|
tSC
200
tpSC
280
50
Current fault driver re-enable
wait time
tSCEN
15
30
ms
ms
OUT re-enable delay after
UVLO (1)
V(UVLO) rising threshold crossing time to
CQ enable time
t(UVLO)
10
(1) CQ output remains Hi-Z for this time
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFL4
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6.8 Typical Characteristics
3
2.5
2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = -40 C
TA = 25 C
TA = 125 C
1.5
1
0.5
0
EN = High
EN = Low
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
D001
0
25
50
75 100 125 150 175 200 225 250
Load Current (mA)
No load
IN = OPEN
TA = 25°C
图6-2. Residual Voltage vs Load Current: High Side
图6-1. Supply Current vs Supply Voltage
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
800
TA = -40 C
TA = 25 C
TA = 125 C
High-side
Low-side
700
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200 225 250
Load Current (mA)
0
10 20 30 40 50 60 70 80 90 100 110
RSET (k)
图6-3. Residual Voltage vs Load Current: Low Side
图6-4. Current Limit vs RSET
800
700
600
500
400
300
200
100
0
TIOS101
TIOS102
0
10 20 30 40 50 60 70 80 90 100 110
RSET (k)
TA = 25°C
图6-5. Current Limit vs RSET : TIOS102(x) vs TIOS101(x)
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7 Parameter Measurement Information
VCC
R
L
IN
OUT
R
C
L
L
EN
图7-1. Test Circuit for Driver Switching
V
V
OH
OH
80%
80%
50%
IN
OUT
OUT
t
t
PHL
PHL
VOH
50%
20%
20%
OUT
V
V
OL
OL
VOL
t
r
t
f
图7-2. Waveforms for Driver Output Switching Measurements
IN = Low
IN = High
50%
50%
EN
t
EN
t
t
PLZ
t
PLZ
PZH
PHZ
VVCC/2
VOH
80%
50%
50%
OUT
20%
OUT
VOL
VVCC/2
图7-3. Waveforms for Driver Enable or Disable Time Measurements
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8 Detailed Description
8.1 Overview
图 8-1 shows that the device driver output (OUT) can be used in a push-pull, high-side, or low-side configuration
using the enable (EN) and transmit data (IN) input pins. OUT can drive resistive, large capacitive or large
inductive loads.
TIOS102 and TIOS102x devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition,
tolerance to ±65-V transients enables flexibility to choose from a wider range of TVS diodes if an application
requires higher levels of protection. These integrated robustness features will simplify the system-level design by
reducing the external protection circuitry.
These devices implement protection features for over-current, over-voltage and over-temperature conditions.
The devices also provide a current-limit setting of the driver output current using an external resistor.
The TIOS102x devices derive the low voltage supply from the typical 24 V industrial supply via an internal linear
regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
Rev.
Polarity
Protection
VCC
VCC_IN
ESD and
Surge
Protection
IN
OUT
EN
Diagnostics
& Control
Rev. Polarity
Protection
ESD and
Surge
NFAULT
Protection
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
图8-1. Block Diagram, TIOS102
VSEL (YAH package only)
Rev.
Polarity
VOLTAGE
VCC
VCC_OUT
REGULATOR
Protection
ESD and
Surge
Protection
IN
OUT
EN
Diagnostics
& Control
Rev. Polarity
Protection
ESD and
Surge
NFAULT
Protection
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
图8-2. Block Diagram, TIOS102x
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8.3 Feature Description
8.3.1 Current Limit Configuration
The output current can be configured with an external resistor on ILIM_ADJ pin. The highest current limit setting
with an external resistor of 10 kΩ specifies a minimum of 300 mA over the operating temperature and voltage
range.
Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ
pin. However, the current fault indication is still active in this configuration. This feature is useful when driving
large capacitance.
When the ILIM_ADJ pin is shorted to ground, the TIOS102(x) is configured to source or sink a minimum of 500
mA. In this mode, current fault indication is disabled. Output Disable and Auto Recovery feature is also disabled
in this mode. The driver is disabled if the power dissipation in the device causes the junction temperature to
reach T(SDN)
.
表8-1. Current Limitation
OUT Current Limit
NFAULT Indication Due to
Current Fault
Output Disable and Auto
Recovery
ILIM_ADJ Pin Condition
(Min.)
RSET resistor to GND
Variable
(35 mA to 300 mA)
Yes
Yes
(RSET: 10 kΩto 110 kΩ)
Connected to GND (RSET 0 to 5
500 mA
260 mA
No
No
No
kΩ)
OPEN
Yes
8.3.2 Current Fault Detection, Indication and Auto Recovery
If the output current at OUT exceeds the internally set current limit IO(LIM) for a duration longer than tSC, the
NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to
function. The output periodically retries to check if the output is still in the over current condition. In this mode,
the output is switched on for tSC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting
ILIM_ADJ = OPEN or GND. See 表8-3. Toggling EN will clear NFAULT.
8.3.3 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T(WRN), the NFAULT flag is held low indicating a potential over temperature
problem. When the TJ exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the
temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the driver,
subject to the state of the EN and IN pins.
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8.3.4 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T(WRN) or
supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault
conditions clear.
Normal
Operation
CUR_OK = Z
Driver = ON
LDO = ON
Output at Hi-Z
EN*
CUR_OK=Z
Driver = OFF
LDO = ON
N
R
W
T
>
T
E
N
N
*
E
N&
R
W
T
<
Thermal
Warning
CUR_OK = Z
Current
Fault
T
T >T
WRN
CUR_OK = L
Driver = OFF
LDO= ON
TMP_OK = L
Driver= EN/EN*
LDO= ON
Out at I
T < T
WRN
O(LIM) and
Current
Fault Recovery
Thermal
Shutdown
CUR_OK = Z
TMP_OK = L
CUR_OK = L
Driver = ON for t
sc
LDO= ON
Driver = OFF
LDO = ON
NFAULT = [CUR_OK && PWR_OK && TMP_OK]
图8-3. Device State Diagram
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8.3.5 Device Function Tables
表8-2. Driver Function
EN
IN
OUT
COMMENT
L / Open
X
L
Hi-Z
H
Device is in ready-to-receive state
H
H
OUT is sourcing current (high-side drive)
OUT is sinking current (low-side drive)
H / Open
L
表8-3. Current Limit Indicator Function (t > tSC
)
EN
IN
OUT CURRENT
| I(OUT) | > IO(LIM)
| I(OUT) | < IO(LIM)
| I(OUT) | > IO(LIM)
| I(OUT) | < IO(LIM)
X
NFAULT
COMMENT
L
Z
L
Z
Z
OUT current exceeds the set limit for over tSC
Normal operation
H
H / Open
OUT current exceeds the set limit for over tSC
Normal operation
H
L
L / Open
X
Driver is disabled, current limit indicator is inactive
8.3.6 The Integrated Voltage Regulator (LDO)
The TIOS1023 and TIOS1025 each have an integrated linear voltage regulator (LDO) which can supply power to
external components. The voltage regulator is specified for VCC voltages in the range of 7 V to 36 V (TIOS1025)
or in the range of 5 V to 36 V (TIOS102, TIOS1023) with respect to GND. The LDO is capable of delivering up to
20 mA. The LDO output is current limited to 35-mA to limit the inrush current onto VCC_OUT decoupling
capacitors during initial power up.
In the DSBGA (YAH) package, TIOS1023L offers pin-configurable LDO output via VSEL pin. When VSEL is
connected to GND, VCC_OUT is configured to provide a 5-V output. When VSEL is left floating, VCC_OUT
provides a 3.3-V output.
表8-4. LDO Output Configuration via VSEL pin (YAH Package)
VSEL pin connection
VCC_OUT
GND
5 V
Floating
3.3 V
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output.
X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum
capacitance to ensure stability is 1 μF.
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8.3.7 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the
VCC, OUT and GND pins. The maximum voltage between any of the pins may not exceed 65 V DC at any time.
图8-4 and 图8-5 shows all the possible connection combinations.
VCC
OUT
GND
VCC
OUT
GND
DC
RL
DC
RL
TIOS102(x)
TIOS102(x)
Correct
Reverse Polarity Protected
Configuration
Fault Condiꢀons
VCC
OUT
GND
VCC
OUT
GND
DC
DC
RL
TIOS102(x)
TIOS102(x)
RL
Reverse Polarity Protected
Reverse Polarity Protected
Fault Condiꢀons
Fault Condiꢀons
VCC
VCC
OUT
GND
DC
OUT
GND
DC
RL
TIOS102(x)
TIOS102(x)
RL
Reverse Polarity Protected
Reverse Polarity Protected
Fault Condiꢀons
Fault Condiꢀons
图8-4. High-Side Driver Configuration
VCC
OUT
GND
VCC
OUT
DC
DC
TIOS102(x)
TIOS102(x)
RL
RL
GND
Reverse Polarity
Protected
Fault Condi ons
Correct
Configuration
VCC
OUT
GND
VCC
OUT
GND
DC
DC
TIOS102(x)
TIOS102(x)
RL
RL
Reverse Polarity Protected
Fault Condi ons
Reverse Polarity Protected
Fault Condi ons
VCC
OUT
GND
VCC
DC
DC
OUT
GND
TIOS102(x)
TIOS102(x)
RL
RL
Overcurrent Fault
Protected Condi ons
Reverse Polarity Protected
Fault Condi ons
图8-5. Low-Side Driver Configuration
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8.3.8 Integrated Surge Protection and Transient Waveform Tolerance
The VCC and OUT pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC
61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100
nF supply decoupling capacitor between VCC and GND, and 1 µF between VCC_IN/OUT and GND.
External TVS diodes may be required for higher transient protection levels. The system designer should ensure
that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The
device is capable of withstanding up to ±65-V transient pulses < 100 µs.
R
Combination
Wave
Generator
EUT
VCC
OUT
GND
Decoupling
Network
>100nF
1.2/50 - 80/20 µs CWG
R = 500 Ω
图8-6. Surge Test Setup
8.3.9 Power Up Sequence
VCC_IN and VCC domains can be powered up in any sequence. In the event of VCC is powered and VCC_IN is
not, the OUT pin remains in high impedance.
8.3.10 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the VCC voltage falls below V(UVLO). (For the device without the integrated LDO, the
device monitors VCC_IN in addition to VCC. UVLO happens if either supply falls below the threshold.)
As soon as the supply falls below V(UVLO), NFAULT is pulled low, the LDO is turned off and the OUT output is
disabled (Hi-Z). Receiver performance is not specified in this mode.
When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present) and the
LDO will be enabled immediately. The OUT output will be turned on after T(UVLO) delay.
8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch Mode)
Set IN pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side
configuration) on OUT.
8.4.2 PNP Configuration (P-Switch Mode)
Set IN pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on OUT.
8.4.3 Push-Pull Mode
Set EN pin high and toggle IN as control for realizing the function of a push-pull output on OUT. 表 8-5, 表 8-6,
and 表8-7 summarize the pin configurations to accomplish the functional modes.
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表8-5. NPN Mode
EN
L / Open
H
IN
OUT
Hi-Z
H / Open
H / Open
N-Switch
表8-6. PNP Mode
EN
L / Open
H
IN
OUT
Hi-Z
L
L
P-Switch
表8-7. Push-Pull Mode
EN
IN
OUT
Hi-Z
L / Open
X
H / Open
L
H
H
N-Switch
P-Switch
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9 Application Information Disclaimer
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
TIOS102 and TIOS102x are robust 24-V digital drivers for industrial sensors.
9.2 Typical Application
VCC_OUT
VCC
Rev. Polarity
Protection
VOLTAGE
REGULATOR
0.1 µF
100 V
1 µF
10 V
ESD and Surge
Protection
10 k
IN
OUT
GND
Sensor
Front-End
EN
Diagnostics
& Control
Rev. Polarity
Protection
ESD and Surge
Protection
NFAULT
CUR _ OK
TMP _ OK
PWR _ OK
ILM_ADJ
RSET
图9-1. Typical Application Schematic
9.2.1 Design Requirements
表9-1 shows recommended components for a typical system design.
表9-1. Design Parameters
PARAMETERS
Design Requirement
TIOS102(x) Specification
Input voltage range (VCC)
24 V, 30 V (max)
7 V to 36 V (TIOS1025)
Output current (OUT)
200 mA
5 V
Choose 250 mA limit with RSET = 27 kΩ
Choose TIOS1025; VCC_OUT = 5 V
IVCC_OUT: Up to 20 mA
Output voltage (VCC_OUT), Pick TIOS1025
Maximum LDO output current (IVCC(OUT)
)
5 mA
Pull-up resistors for NFAULT
10 kΩ
10 kΩ
VCC decoupling capacitor
LDO output capacitor
0.1 µF / 100 V
1 µF / 10 V
0.1 µF / 100 V
1 µF / 10 V
TIOS102(x) can support up to TA of 125 °C if TJ <
T(SDN)
Maximum Ambient Temperature, TA
105°C
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9.2.2 Detailed Design Procedure
9.2.2.1 最高结温检查
对于200mA 电流限制：
• kΩ驱动器输出电流限制、I O (LIM)= 250mA (允许电流限制容差)；R SET = 27 μA
• 电流为250mA 时、高侧开关上的最大压降为VDS (on) = 1.1V
这会导致功耗为：
PD = V
× I = 1.1 V × 250 mA) = 275 mW
O LIM
(1)
(2)
(3)
(4)
(5)
OP
DS ON
对于5mA LDO 电流输出、
PD
= V
− V
× I
= 30 − 5 V × 5 mA) = 125 mW
LDO
L +
VCC
OUT
VCC_OUT
总功率耗散、
PD = PD
+ PD = 275 mW + 125 mW = 400 mW
OP
LDO
将该值与结至环境热阻θJA = 45.9°C/W 相乘(摘自热性能信息表)以获得结温TJ 和环境温度TA 之间的差值
：
℃
∆ T = T − T = PD × θ = 400 mW × 45.9
= 18.36 ℃
W
J
A
JA
将此值添加到TA = 105°C 的最高环境温度中、以接收最终结温：
℃
T = T + ∆ T = T + PD × θ = 105 ℃ + 400 mW × 45.9
= 105 ℃ + 18.36 ℃ = 123.36 ℃
W
J
A)
A)
JA
只要 TJ 低于150°C 的建议最大值、就不会发生热关断。然而、结温更接近 TWRn 、并且如果结温上升至高于
TWRn、则可能会生成热警告。
请注意、可能需要对整个系统进行建模、以预测较小PCB 和/或外壳中无气流的结温。
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the OUT output. Assuming a pure capacitive load
without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault
can be calculated as:
[I
x t
]
SC
O LIM
(
)
C
=
LOAD
V
VCC
(
)
(6)
To drive higher capacitive loads and avoid overcurrent condition disabling the driver, it is recommended to leave
ILIM_ADJ pin floating. With ILIM_ADJ floating, TIOS102(x) indicates overcurrent fault without blanking time
delay (tSC) but does not disable the driver. Another approach is to drive high capacitive loads with a series
resistor between the output and the load to avoid overcurrent condition. Capacitive loads can be connected to
GND or VCC
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9.2.2.3 Driving Inductive Loads
The TIOS102(x) family is capable of magnetizing and demagnetizing large inductive loads. These devices
contain internal circuitry that enables fast demagnetization when configured as either P-switch or N-switch mode.
In P-switch configuration, the load inductor L is magnetized when the OUT pin is driven high. When the PNP is
turned off, there is a significant amount of negative inductive kick back at the OUT pin. This voltage is clamped
internally at about -15 V.
Similarly, in N-switch configuration, the load inductor L is magnetized when the OUT pin is driven low. When the
NPN is turned off, there is a significant amount of positive inductive kick back at the OUT pin. This voltage is
clamped internally at about 15 V.
The equivalent protection circuits are shown in 图9-2 and 图9-3. The minimum value of the resistive load R can
be calculated as:
V
VCC
(
)
R =
I
O(LIM)
(7)
spacer
Rev.
Polarity
Protection
Rev.
Polarity
Protection
VCC
OUT
VCC
OUT
ESD and
Surge
Protection
ESD and
Surge
Protection
R
Rev. Polarity
Protection
Rev. Polarity
Protection
L
L
ESD and
Surge
ESD and
Surge
R
Protection
Protection
GND
GND
图9-2. PNP Mode
图9-3. NPN Mode
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9.2.3 Application Curves
Time 10 ms/div
Time 10 ms/div
图9-5. OUT In Current Fault Auto Recovery, High
图9-4. OUT In Current Fault Auto Recovery, Low
Side Mode
Side Mode
VCC = 36 V
VCC = 36 V
L = 1.5 H RL = 360 Ω
L = 1.5 H RL = 360 Ω
TA = 25 °C
TA = 25 °C
RSET = 10 kΩ
RSET = 10 kΩ
图9-6. OUT Driving Inductive Load, High Side
图9-7. OUT Driving Inductive Load, Low Side Mode
Mode (PNP)
(NPN)
NFAULT indicated for the duration of charging and discharging of the capacitor but driver is not disabled when ILIM_ADJ is floating.
VCC = 24 V
TA = 25 °C
CL = 20 uF RL = 100 Ω
RSET = 1 MΩ(ILIM_ADJ
Floating)
图9-8. OUT Driving Capacitive Load, Push-Pull Mode
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10 Power Supply Recommendations
The TIOS102 and TIOS102x are designed to operate from a 24-V nominal supply at VCC, but can operate from
supply voltage range of 7 V to 36 V (TIOS1025) or 4.75 V to 36 V (TIOS102, TIOS1023). This supply should be
buffered with at least a 100-nF/100-V capacitor.
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11 Layout
11.1 Layout Guidelines
• Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as GND, layer 3 for the 24-V supply plane (VCC), and layer 4 for the regulated output supply
(VCC_IN/OUT).
• Connect the thermal pad to GND with maximum amount of thermal vias for best thermal performance.
• Use entire planes for VCC, VCC_IN/OUT and GND to assure minimum inductance.
• The VCC terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor with a
minimum value of 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending on
max sensor supply fault rating) and an X5R or X7R dielectric.
• •The optimum placement of the capacitor is closest to the VCC and GND terminals to reduce supply drops
during large supply current loads. See 图11-1 for a PCB layout example.
• Connect all open-drain control outputs via 10 kΩpull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
• Connect the RSET resistor between ILIM_ADJ and GND.
• Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, 1 μF, ceramic decoupling
capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
11.2 Layout Example
VIA to Layer 2: Power Ground Plane (VCC)
VIA to Layer 3: 24V Supply Plane (GND)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
1uF/10V
V
100nF/
50V
C
C
_
I
N
/
O
U
NC
T
VCC
NFAULT
VCC
NC
OUT
GND
OUT
GND
IN
EN
Use Multiple Vias for
VCC and GND
Exposed Thermal
Pad Area
RSET
图11-1. Layout Example
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English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFL4
24
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TIOS102, TIOS1023, TIOS1025
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13.1 Mechanical Data
PACKAGE OUTLINE
YAH0012-C01
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.4 MAX
SEATING PLANE
0.05 C
0.17
0.11
1
TYP
SYMM
D
C
SYMM
1.5
TYP
D: Max = 2.47 mm, Min = 2.43 mm
E: Max = 1.72 mm, Min = 1.68 mm
B
A
0.5
TYP
0.25
12X
2
1
3
0.21
0.015
C A B
0.5 TYP
4227086/A 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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Product Folder Links: TIOS102 TIOS1023 TIOS1025
English Data Sheet: SLLSFL4
TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
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EXAMPLE BOARD LAYOUT
YAH0012-C01
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
12X ( 0.23)
1
2
3
A
(0.5) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
( 0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4227086/A 09/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFL4
26
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TIOS102, TIOS1023, TIOS1025
ZHCSMU4B –FEBRUARY 2022 –REVISED JUNE 2023
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EXAMPLE STENCIL DESIGN
YAH0012-C01
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
3
12X ( 0.25)
1
2
A
(0.5) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 30X
4227086/A 09/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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Product Folder Links: TIOS102 TIOS1023 TIOS1025
English Data Sheet: SLLSFL4
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TIOS1023DRCR
TIOS1023LYAHR
TIOS1025DRCR
TIOS102DRCR
TIOS102YAHR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
DSBGA
VSON
DRC
YAH
DRC
DRC
YAH
10
12
10
10
12
5000 RoHS & Green
1500 RoHS & Green
5000 RoHS & Green
5000 RoHS & Green
1500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1023
Samples
Samples
Samples
Samples
Samples
SNAGCU
NIPDAU
NIPDAU
SNAGCU
T102L
1025
102
VSON
DSBGA
TS102
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TIOS1023DRCR
TIOS1023LYAHR
TIOS1025DRCR
TIOS102DRCR
TIOS102YAHR
VSON
DSBGA
VSON
DRC
YAH
DRC
DRC
YAH
10
12
10
10
12
5000
1500
5000
5000
1500
330.0
180.0
330.0
330.0
180.0
12.4
8.4
3.3
1.88
3.3
3.3
2.63
3.3
1.1
0.53
1.1
8.0
4.0
8.0
8.0
4.0
12.0
8.0
Q2
Q1
Q2
Q2
Q1
12.4
12.4
8.4
12.0
12.0
8.0
VSON
3.3
3.3
1.1
DSBGA
1.88
2.63
0.53
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TIOS1023DRCR
TIOS1023LYAHR
TIOS1025DRCR
TIOS102DRCR
TIOS102YAHR
VSON
DSBGA
VSON
DRC
YAH
DRC
DRC
YAH
10
12
10
10
12
5000
1500
5000
5000
1500
367.0
182.0
367.0
367.0
182.0
367.0
182.0
367.0
367.0
182.0
35.0
20.0
35.0
35.0
20.0
VSON
DSBGA
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010V
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4
2.2
10
1
8X 0.5
0.3
0.2
10X
SYMM
10X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
4226575/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010V
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
SYMM
11
(3.4)
(2.3)
(0.9)
8X (0.5)
6
5
(R0.05) TYP
(0.2) TYP
VIA
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226575/A 02/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010V
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.51)
(0.5)
SYMM
EXPOSED METAL
TYP
10X (0.6)
1
10
(1.53)
2X
(1.02)
10X (0.24)
11
SYMM
(0.61)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226575/A 02/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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