TL032CDRG4 [TI]
ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS; 增强型JFET低功耗低偏移运算放大器
| 型号： | TL032CDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS |
| 文件： | 总68页 (文件大小：1471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
Direct Upgrades for the TL06x Low-Power
BiFETs
Higher Slew Rate and Bandwidth Without
Increased Power Consumption
Low Power Consumption . . .
6.5 mW/Channel Typ
Available in TSSOP for Small Form-Factor
Designs
On-Chip Offset-Voltage Trimming for
Improved DC Performance
(1.5 mV, TL031A)
description
The TL03x series of JFET-input operational amplifiers offer improved dc and ac characteristics over the TL06x
family of low-power BiFET operational amplifiers. On-chip zener trimming of offset voltage yields precision
grades as low as 1.5 mV (TL031A) for greater accuracy in dc-coupled applications. The Texas Instruments
improved BiFET process and optimized designs also yield improved bandwidths and slew rates without
increased power consumption. The TL03x devices are pin-compatible with the TL06x and can be used to
upgrade existing circuits or for optimal performance in new designs.
BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors without
sacrificing the output drive associated with bipolar amplifiers. This higher input impedance makes the TL3x
amplifiers better suited for interfacing with high-impedance sensors or very low-level ac signals. These devices
also feature inherently better ac response than bipolar or CMOS devices having comparable power
consumption.
The TL03x family has been optimized for micropower operation, while improving on the performance of the
TL06x series. Designers requiring significantly faster ac response should consider the Excalibur TLE206x
family of low-power BiFET operational amplifiers.
Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to
observe common-mode input-voltage limits and output swing when operating from a single supply. DC biasing
of the input signal is required, and loads should be terminated to a virtual-ground node at midsupply. The TI
TLE2426 integrated virtual-ground generator is useful when operating BiFET amplifiers from single supplies.
The TL03x devices are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply
systems, the TI LinCMOS families of operational amplifiers (TLC prefix) are recommended. When moving from
BiFET to CMOS amplifiers, particular attention should be paid to slew rate, bandwidth requirements, and output
loading.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from –40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excalibur is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031x, TL031Ax
D, JG, OR P PACKAGE
(TOP VIEW)
TL032x, TL032Ax
D, JG, OR P PACKAGE
(TOP VIEW)
TL034x, TL034Ax
D, J, N, OR PW PACKAGE
(TOP VIEW)
OFFSET N1
IN–
NC
V
OUT
1OUT
1IN–
1IN+
V
CC+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
4OUT
4IN–
4IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
2OUT
2IN–
2IN+
CC+
IN+
V
OFFSET N2
V
V
V
CC–
CC –
CC+
CC–
2IN+
2IN–
3IN+
3IN–
3OUT
2OUT
8
TL031M, TL031AM
FK PACKAGE
(TOP VIEW)
TL032M, TL032AM
FK PACKAGE
(TOP VIEW)
TL034M, TL034AM
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
3
2
1
20 19
18
3
2
1
20 19
18 NC
NC
NC
1IN–
NC
1IN+
NC
4IN+
NC
4
5
6
7
8
NC
IN–
NC
IN+
NC
4
5
6
7
8
4
5
6
7
8
2OUT
NC
17
16
15
14
17
16
15
14
17
16
15
14
V
CC+
V
V
NC
CC+
NC
CC–
2IN–
NC
1IN+
NC
NC
OUT
NC
2IN+
3IN+
9 10 11 12 13
9 10 11 12 13
9 10 11 12 13
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
AVAILABLE OPTIONS
PACKAGED DEVICES
V
MAX
CHIP
CARRIER
(FK)
CERAMIC
CERAMIC
DIP
PLASTIC
PLASTIC
DIP
IO
SMALL
OUTLINE
(D)
T
A
TSSOP
(PW)
AT 25°C
DIP
(J)
DIP
(N)
(JG)
(P)
TL031ACD
TL032ACD
TL031ACP
TL032ACP
0.8 mV
1.5 mV
—
—
—
—
—
—
—
—
—
TL031CD
TL032CD
TL034ACD
0°C to 70°C
TL031CP
TL032CP
TL034ACN
4 mV
TL034CD
—
—
—
—
—
—
TL034CN
—
TL034CPW
TL031AID
TL032AID
TL031AIP
TL032AIP
0.8 mV
—
—
TL031ID
TL032ID
TL034AID
–40°C to 85°C
TL031IP
TL032IP
1.5 mV
—
—
—
—
—
TL034AIN
—
4 mV
TL034ID
—
—
TL034IN
—
—
—
TL031AMD TL031AMFK
TL032AMD TL032AMFK
TL031AMJG
TL032AMJG
TL031AMP
TL032AMP
0.8 mV
—
TL031MD
TL032MD
TL034AMD TL034AMFK
TL031MFK
TL032MFK
–55°C to 125°C
TL031MJG
TL032MJG
TL031MP
TL032MP
1.5 mV
4 mV
TL034AMJ
TL034MJ
TL034AMN
TL034MN
—
—
TL034MD TL034MFK
—
—
The D and PW packages are available taped and reeled and are indicated by adding an R suffix to device type (e.g., TL034CDR or TL034CPWR).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
symbol (each amplifier)
IN–
IN+
–
+
OUT
CC+
equivalent schematic (each amplifier)
V
Q5
Q14
Q2
Q3
D1
R4
Q6
Q11
R7
IN+
OUT
Q8
IN–
Q10
JF1 JF2
Q17
R3
Q15
R6
C1
Q12
JF3
R8
JF4
Q1
Q4
Q9
OFFSET N1
OFFSET N2
See Note A
Q7
Q16
R1
R2
R5
Q13
V
CC–
NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL031, TL031A.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1): V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V
CC+
CC–
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
ID
Input voltage, V (any input) (see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
I
Input current, I (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA
I
Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA
CC+
CC–
Total current out of V
Duration of short-circuit current at (or below) 25°C (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Package thermal impedance, θ (see Note 5): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
D package (14 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Lead temperature 1,6 mm (1 /16 inch) from case for 10 seconds: D, N, P, or PW package . . . . . . . . . 260°C
Lead temperature 1,6 mm (1 /16 inch) from case for 60 seconds: J or JG package . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V
and V
.
CC+
CC–
2. Differential voltages are at IN+ with respect to IN–.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING
A
FK
J
1375 mW
11.0 mW/°C
11.0 mW/°C
8.4 mW/°C
880 mW
880 mW
672 mW
715 mW
715 mW
546 mW
275 mW
275 mW
210 mW
1375 mW
JG
1050 mW
recommended operating conditions
C SUFFIX
I SUFFIX
M SUFFIX
UNIT
V
MIN
±5
MAX
±15
4
MIN
±5
MAX
±15
4
MIN
±5
MAX
V
V
Supply voltage
±15
4
CC±
V
V
= ±5 V
–1.5
–11.5
0
–1.5
–1.5
CC±
Common-mode input voltage
Operating free-air temperature
V
IC
= ±15 V
14 –11.5
70 –40
14 –11.5
85 –55
14
CC±
T
A
125
°C
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031C and TL031AC electrical characteristics at specified free-air temperature
TL031C, TL031AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.5
MIN
MAX
1.5
25°C
Full range
25°C
0.54
0.5
TL031C
V
V
R
= 0,
O
†
4.5
2.5
V
IO
Input offset voltage
mV
= 0,
IC
0.41
2.8
0.34
0.8
= 50 Ω
S
TL031AC
TL031C
†
Full range
3.8
1.8
25°C to
70°C
7.1
7.1
5.9
5.9
V
V
R
= 0,
=0,
= 50 Ω
O
IC
Temperature coefficient of
input offset voltage
µV/°C
V
IO
25°C to
70°C
S
TL031AC
25
V
V
R
= 0,
=0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
70°C
25°C
70°C
1
9
100
200
200
400
1
12
2
100
200
200
400
V
= 0, V = 0
IC
O
I
I
Input offset current
Input bias current
pA
pA
IO
See Figure 5
2
V
O
= 0, V = 0
IC
IB
See Figure 5
50
–3.4
80
–1.5
–11.5
–13.4
to 14 to 15.4
25°C
to 4 to 5.4
Common-mode input
voltage range
V
V
ICR
–1.5
to 4
–11.5
to 14
†
Full range
25°C
0°C
3
3
4.3
4.2
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
70°C
25°C
0°C
3
4.3
13
14
–3
–3
–3
4
–4.2
–4.1
–4.2
12
–12.5
–12.5
–12.5
5
–13.9
–13.9
–14
Maximum negative peak
output voltage swing
OM–
70°C
25°C
0°C
14.3
13.5
15.2
Large-signal differential
A
VD
3
11.1
13.3
4
V/mV
§
voltage amplification
70°C
25°C
25°C
25°C
0°C
4
5
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
5
87
87
87
96
96
96
4
94
94
94
96
96
96
pF
i
70
70
70
75
75
75
75
75
75
75
75
75
Common-mode
rejection ratio
V
V
min,
IC = ICR
CMRR
dB
dB
V
= 0, R = 50 Ω
O
O
S
70°C
25°C
0°C
Supply-voltage
rejection ratio
k
V
= 0, R = 50 Ω
S
SVR
(∆V
/∆V )
CC±
IO
70°C
†
‡
Full range is 0°C to 70°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = ±2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031C and TL031AC electrical characteristics at specified free-air temperature (continued)
TL031C, TL031AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
mW
µA
T
CC±
TYP
CC±
MIN
A
MIN
MAX
2.5
TYP
6.5
MAX
25°C
1.9
1.8
8.4
8.4
P
D
Total power dissipation
Supply current
V
V
= 0,
= 0,
No load
No load
0°C
70°C
25°C
0°C
2.5
6.3
O
1.9
2.5
6.3
8.4
192
184
189
250
250
250
217
211
210
280
280
280
I
CC
O
70°C
TL031C and TL031AC operating characteristics at specified free-air temperature
TL031C, TL031AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
V/µs
V/µs
ns
T
CC±
TYP
CC±
A
MIN
MAX
MIN
1.5
1
TYP
2.9
2.6
3.2
5.1
5
MAX
25°C
0°C
2
1.8
2.2
3.9
3.7
4
R
= 10 kΩ, C = 100 pF
Positive slew rate at
L
L
SR+
†
See Figure 1
unity gain
70°C
25°C
0°C
1.5
1.5
1.5
1.5
R
= 10 kΩ, C = 100 pF
L
See Figure 1
Negative slew rate at
L
SR–
†
unity gain
70°C
25°C
0°C
5
138
134
150
138
134
150
132
127
142
132
127
142
5%
4%
6%
61
V
R
= ±10 mV,
I(PP)
t
r
Rise time
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
70°C
25°C
0°C
V
R
= ±10 mV,
I(PP)
t
f
Fall time
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
70°C
25°C
0°C
11%
10%
12%
61
V
= ±10 mV,
I(PP)
Overshoot factor
RL = 10 kΩ, C = 100 pF
L
See Figures 1 and 2
70°C
f = 10 Hz
TL031C
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
41
41
R
= 20 Ω
See Figure 3
Equivalent input
noise voltage
S
V
n
nV/√Hz
61
61
TL031AC
25°C
25°C
41
41
60
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
0°C
1
1
1.1
1.1
1
V = 10 mV
I
B
1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
70°C
25°C
0°C
1
61°
61°
60°
65°
65°
64°
V = 10 mV
I
L
R
= 10 kΩ, C = 25 pF
φ
m
Phase margin at unity gain
L
See Figure 4
70°C
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031I and TL031AI electrical characteristics at specified free-air temperature
TL031I, TL031AI
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.5
MIN
MAX
1.5
25°C
Full range
25°C
0.54
0.41
0.5
TL031I
= 0,
= 0,
V
V
R
†
O
IC
S
5.3
3.3
V
IO
Input offset voltage
mV
2.8
0.34
0.8
= 50 Ω
TL031AI
TL031I
†
Full range
4.6
2.6
25°C to
85°C
6.5
6.5
6.2
6.2
V
V
R
= 0,
Temperature coefficient
of
input offset voltage
O
IC
µV/°C
= 0,
= 50 Ω
V
IO
25°C to
85°C
S
TL031AI
25
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
85°C
25°C
85°C
1
0.02
2
100
0.45
200
0.9
1
0.02
2
100
0.45
200
0.9
pA
nA
pA
nA
V
= 0, V = 0
IC
O
I
I
Input offset current
Input bias current
IO
See Figure 5
V
O
= 0, V = 0
IC
IB
See Figure 5
0.2
0.2
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
ICR
V
–1.5
to 4
–11.5
to 14
†
Full range
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
25°C
25°C
–40°C
85°C
25°C
–40°C
85°C
3
3
4.3
4.1
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
3
4.4
13
14
–3
–3
–3
4
–4.2
–4.1
–4.2
12
–12.5
–12.5
–12.5
5
–13.9
–13.8
–14
Maximum negative peak
output voltage swing
OM–
14.3
11.6
15.3
Large-signal differential
A
VD
3
8.4
4
V/mV
§
voltage amplification
4
13.5
5
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
5
87
87
87
96
96
96
4
94
94
94
96
96
96
pF
i
70
70
70
75
75
75
75
75
75
75
75
75
Common-mode
rejection ratio
V
V
min,
IC = ICR
CMRR
dB
dB
V
= 0, R = 50 Ω
O
O
S
Supply-voltage
rejection ratio
k
V
= 0,
R = 50 Ω
S
SVR
(∆V
/∆V )
CC±
IO
†
‡
Full range is –40°C to 85°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
At V
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
= ±5 V, V = ±2.3 V; at V = ±15 V, V = ±10 V
CC±
O
CC± O
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031I and TL031AI electrical characteristics at specified free-air temperature (continued)
TL031I, TL031AI
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
mW
µA
T
CC±
TYP
CC±
MIN
A
MIN
MAX
2.5
TYP
6.5
MAX
25°C
1.9
1.4
8.4
8.4
P
D
Total power dissipation
Supply current
V
V
= 0,
= 0,
No load
No load
–40°C
85°C
25°C
–40°C
85°C
2.5
5.4
O
1.9
2.5
6.2
8.4
192
144
189
250
250
250
217
181
207
280
280
280
I
CC
O
TL031I and TL031AI operating characteristics at specified free-air temperature
TL031I, TL031AI
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
2.9
2.1
3.3
5.1
4.8
4.9
132
123
146
132
123
146
5%
5%
7%
61
MAX
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
2
1.6
R
= 10 kΩ, C = 100 pF
Positive slew rate at
L
L
SR+
†
See Figure 1
unity gain
2.3
1.5
1.5
1.5
1.5
3.9
Negative slew rate at unity
R = 10 kΩ, C = 100 pF
L L
See Figure 1
SR–
3.3
†
gain
4.1
138
132
154
138
132
154
V
R
= ±10 mV,
I(PP)
t
r
Rise time
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
V
R
= ±10 mV,
I(PP)
t
f
Fall time
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
11%
12%
13%
61
V
R
= ±10 mV,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
L
L
See Figures 1 and 2
f = 10 Hz
TL031I
25°C
25°C
25°C
Equivalent
input
noise voltage
f = 1 kHz
f = 10 Hz
f = 1 kHz
41
41
R
= 20 Ω
See Figure 3
S
V
n
nV/√Hz
61
61
TL031AI
41
41
60
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
–40°C
85°C
1
1
1.1
1.1
1
V = 10 mV
I
B
1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
0.9
61°
60°
60°
25°C
65°
65°
64°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
L
φ
m
Phase margin at unity gain
–40°C
85°C
See Figure 4
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031M and TL031AM electrical characteristics at specified free-air temperature
TL031M, TL031AM
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.5
MIN
MAX
1.5
25°C
Full range
25°C
0.54
0.5
TL031M
= 0,
= 0,
V
V
R
†
O
IC
6.5
4.5
V
IO
Input offset voltage
mV
0.41
2.8
0.34
0.8
= 50 Ω
S
TL031AM
†
Full range
5.8
3.8
25°C to
125°C
TL031M
5.1
5.1
4.3
4.3
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Temperature coefficient of
input offset voltage
µV/°C
V
IO
25°C to
125°C
TL031AM
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
125°C
25°C
1
0.2
2
100
10
1
0.2
2
100
10
pA
nA
pA
nA
V
= 0, V = 0
IC
O
I
I
Input offset current
Input bias current
IO
See Figure 5
200
20
200
20
V
O
= 0, V = 0
IC
IB
See Figure 5
125°C
7
8
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
ICR
V
–1.5
to 4
–11.5
to 14
†
Full range
25°C
–55°C
125°C
25°C
3
3
4.3
4.1
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
3
4.4
13
14
–3
–3
–3
4
–4.2
–4
–12.5
–12.5
–12.5
5
–13.9
–13.8
–14
14.3
10.4
15
Maximum negative peak
output voltage swing
–55°C
125°C
25°C
OM–
–4.3
12
Large-signal differential
A
VD
–55°C
125°C
25°C
3
7.1
4
V/mV
§
voltage amplification
3
12.9
4
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
25°C
5
87
87
87
96
96
96
4
94
94
94
96
95
96
pF
i
25°C
70
70
70
75
75
75
75
70
70
75
75
75
Common-mode
rejection ratio
V
V
= V
min,
IC
O
ICR
= 0, R = 50 Ω
CMRR
–55°C
125°C
25°C
dB
dB
S
Supply-voltage
rejection ratio
k
V
= 0,
= 0,
R = 50 Ω
S
–55°C
125°C
25°C
SVR
O
O
(∆V
/∆V )
CC±
IO
1.9
1.1
1.8
2.5
2.5
2.5
6.5
4.7
5.8
8.4
8.4
8.4
P
Total power dissipation
V
No load
–55°C
125°C
mW
D
†
‡
Full range is –55°C to 125°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = ±2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL031M and TL031AM electrical characteristics at specified free-air temperature (continued)
TL031M, TL031AM
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
T
CC±
TYP
CC±
MIN
A
MIN
MAX
250
250
250
TYP
217
156
197
MAX
25°C
192
114
178
280
280
280
I
Supply current
V
O
= 0,
No load
–55°C
125°C
µA
CC
TL031M and TL031AM operating characteristics at specified free-air temperature
TL031M, TL031AM
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
2.9
1.9
3.5
5.1
4.6
4.7
132
123
158
132
123
158
5%
6%
8%
61
MAX
25°C
–55°C
125°C
25°C
2
1.4
R
= 10 kΩ, C = 100 pF
Positive slew rate at
L
L
SR+
†
See Figure 1
unity gain
2.4
1
3.9
1.5
1
R
= 10 kΩ, C = 100 pF
L
See Figure 1
Negative slew rate at
L
SR–
–55°C
125°C
25°C
3.2
†
unity gain
4.1
1
138
142
166
138
142
166
V
R
= ±10 mV,
I(PP)
t
r
Rise time
–55°C
125°C
25°C
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
V
R
= ±10 mV,
I(PP)
t
f
Fall time
–55°C
125°C
25°C
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
11%
16%
14%
61
V
R
= ±10 mV,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
–55°C
125°C
L
L
See Figures 1 and 2
f = 10 Hz
TL031M
25°C
25°C
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
41
41
Equivalent input
noise voltage
R = 20 Ω
S
See Figure 3
V
n
nV/√Hz
61
61
TL031AM
41
41
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
–55°C
125°C
25°C
1
1
1.1
1.1
0.9
65°
64°
62°
V = 10 mV,
I
B
1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
0.9
61°
57°
59°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
φ
m
Phase margin at unity gain
–55°C
125°C
L
See Figure 4
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL032C and TL032AC electrical characteristics at specified free-air temperature
TL032C, TL032AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.5
MIN
MAX
1.5
25°C
Full range
25°C
0.69
0.57
TL032C
= 0,
V
V
R
†
O
4.5
2.5
V
IO
Input offset voltage
mV
= 0,
= 50 Ω
IC
0.53
2.8
0.39
0.8
S
TL032AC
†
Full range
3.8
1.8
25°C to
70°C
TL032C
11.5
11.5
10.8
10.8
V
= 0,
= 0,
= 50 Ω
Temperature
coefficient of input
offset voltage
O
V
µV/°C
V
IC
IO
25°C to
70°C
R
TL032AC
25
S
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
70°C
25°C
70°C
1
9
100
200
200
400
1
12
2
100
200
200
400
V
= 0,
V
V
= 0
= 0
O
IC
I
I
Input offset current
Input bias current
pA
pA
IO
See Figure 5
2
V
O
= 0,
IC
IB
See Figure 5
50
80
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
ICR
V
–1.5
to 4
–11.5
to 14
†
Full range
25°C
0°C
3
3
4.3
4.2
13
13
14
14
Maximum positive
peak output voltage
swing
V
V
A
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
70°C
25°C
0°C
3
4.3
13
14
–3
–3
–3
4
–4.2
–4.1
–4.2
12
–12.5
–12.5
–12.5
5
–13.9
–13.9
–14
Maximum negative
peak output voltage
swing
OM–
70°C
25°C
0°C
14.3
13.5
15.2
Large-signal
3
11.1
13.3
4
V/mV
differential voltage
VD
§
amplification
70°C
25°C
25°C
25°C
0°C
4
5
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
5
87
87
87
96
96
96
14
94
94
94
96
96
96
pF
i
70
70
70
75
75
75
75
75
75
75
75
75
Common-mode
rejection ratio
V
IC
V
O
= V
min,
ICR
= 0, R = 50 Ω
CMRR
dB
dB
S
70°C
25°C
0°C
Supply-voltage
rejection ratio
V
= ±5 V to ±15 V,
CC±
= 0, R = 50 Ω
k
SVR
V
O
S
(∆V
/∆V )
CC±
IO
70°C
†
‡
Full range is 0°C to 70°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = 2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL032C and TL032AC electrical characteristics at specified free-air temperature (continued)
TL032C, TL032AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
T
CC±
TYP
CC±
MIN
A
MIN
MAX
5
TYP
13
MAX
25°C
3.8
3.7
17
17
Total power dissipation
(two amplifiers)
P
D
V
V
= 0,
= 0,
No load
No load
0°C
70°C
0°C
5
12.7
12.6
422
420
120
mW
O
3.8
5
17
368
378
120
500
500
560
560
Supply current
(two amplifiers)
I
µA
CC
O
70°C
25°C
V /V
O1 O2
Crosstalk attenuation
A
VD
= 100 dB
dB
TL032C and TL032AC operating characteristics at specified free-air temperature
TL032C, TL032AC
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC
±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
2.9
2.6
3.2
5.1
5
MAX
25°C
0°C
1.2
1.8
2.2
3.9
3.7
4
R
= 10 kΩ, C = 100 pF
Positive slew rate at unity
L
L
SR+
†
See Figure 1
gain
70°C
25°C
0°C
1.5
1.5
1.5
1.5
R
= 10 kΩ, C = 100 pF
L
See Figure 1
Negative slew rate at unity
L
SR–
†
gain
70°C
25°C
0°C
5
138
134
150
138
134
150
132
127
142
132
127
142
5%
4%
6%
49
V
R
= ±10 V,
I(PP)
t
r
Rise time
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
70°C
25°C
0°C
V
R
= ±10 V,
I(PP)
t
f
Fall time
ns
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
70°C
25°C
0°C
11%
10%
12%
49
V
R
= ±10 V,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
L
L
See Figures 1 and 2
70°C
f = 10 Hz
TL032C
25°C
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
41
41
R
= 20 Ω
See Figure 3
Equivalent input
noise voltage
S
V
n
nV/√Hz
49
49
TL032AC
41
41
60
I
Equivalent input noise current
Unity-gain bandwidth
f = 1 kHz
25°C
25°C
0°C
0.003
1
0.003
1.1
1.1
1
pA/√Hz
n
V = 10 mV,
I
L
B
1
1
MHz
R
= 10 kΩ, C = 25 pF
L
See Figure 4
70°C
25°C
0°C
1
61°
61°
60°
65°
65°
64°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
φ
Phase margin at unity gain
L
m
See Figure 4
70°C
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL032I and TL032AI electrical characteristics at specified free-air temperature
TL032I, TL032AI
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.5
MIN
MAX
1.5
25°C
Full range
25°C
0.69
0.53
0.57
TL032I
= 0,
= 0,
V
V
R
†
O
IC
5.3
3.3
V
IO
Input offset voltage
mV
2.8
0.39
0.8
= 50 Ω
S
TL032AI
†
Full range
4.6
2.6
25°C to
85°C
TL032I
11.4
11.4
10.8
10.8
V
= 0,
= 0,
= 50 Ω
Temperature
coefficient of input
offset voltage
O
V
µV/°C
V
IC
IO
25°C to
85°C
R
TL032AI
25
S
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
85°C
25°C
85°C
1
0.02
2
100
0.45
200
0.9
1
0.02
2
100
0.45
200
0.9
pA
nA
pA
nA
V
= 0,
V
V
= 0
= 0
O
IC
I
I
Input offset current
Input bias current
IO
See Figure 5
V
O
= 0,
IC
IB
See Figure 5
0.2
0.3
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
V
V
ICR
–1.5
to 4
–11.5
to 14
†
Full range
25°C
–40°C
85°C
25°C
–40°C
85°C
–40°C
85°C
25°C
25°C
25°C
–40°C
85°C
25°C
–40°C
85°C
3
3
4.3
4.2
13
13
14
14
Maximum positive
peak output voltage
swing
V
V
R
= 10 kΩ
OM+
L
3
4.4
13
14
–3
–3
–3
3
–4.2
–4.1
–4.2
8.4
–12.5
–12.5
–12.5
4
–13.9
–13.8
–14
Maximum negative
peak output voltage
swing
R
R
= 10 kΩ
= 10 kΩ
V
OM–
L
L
11.6
15.3
Large-signal differential
A
VD
V/mV
§
voltage amplification
4
13.5
5
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
5
87
87
87
96
96
96
4
94
94
94
96
96
96
pF
i
70
70
70
75
75
75
75
75
75
75
75
75
Common-mode
rejection ratio
V
IC
V
O
= V
min,
ICR
= 0, R = 50 Ω
CMRR
dB
dB
S
Supply-voltage
rejection ratio
V
V
= ±5 V to ±15 V,
CC±
O
k
SVR
= 0, R = 50 Ω
S
(∆V
/∆V )
CC±
IO
†
‡
Full range is –40°C to 85°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = 2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL032I and TL032AI electrical characteristics at specified free-air temperature (continued)
TL032I, TL032AI
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
13
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
5
MIN
MAX
17
25°C
3.8
2.9
Total power
dissipation
(two amplifiers)
P
D
V
V
= 0,
= 0,
No load
No load
–40°C
85°C
25°C
–40°C
85°C
5
10.9
12.4
434
17
mW
O
3.7
5
17
384
288
372
500
500
500
560
560
560
Supply current
(two amplifiers)
I
362
µA
CC
O
414
Crosstalk
attenuation
V /V
O1 O2
A
VD
= 100 dB
25°C
120
120
dB
TL032I and TL032AI operating characteristics at specified free-air temperature
TL032I, TL032AI
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
2.9
2.1
3.3
5.1
4.8
4.9
132
123
146
132
123
146
5%
5%
7%
49
MAX
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
2
1.6
Positive slew rate at unity
SR+
R
R
= 10 kΩ, C = 100 pF
L
L
†
gain
2.3
1.5
1.5
1.5
1.5
3.9
Negative slew rate at unity
SR–
= 10 kΩ, C = 100 pF
3.3
L
L
†
gain
4.1
138
132
154
138
132
154
V
R
= ±10 V,
I(PP)
t
r
Rise time
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
V
R
= ±10 V,
I(PP)
t
f
Fall time
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
11%
12%
13%
49
V
R
= ±10 V,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
L
L
See Figures 1 and 2
f = 10 Hz
TL032I
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
41
41
R
= 20 Ω
See Figure 3
Equivalent input
noise voltage
S
V
n
nV/√Hz
49
49
TL032AI
25°C
25°C
41
41
60
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
–40°C
85°C
1
1
1.1
1.1
1
V = 10 mV,
I
B
1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
0.9
61°
61°
60°
25°C
65°
65°
64°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
φ
m
Phase margin at unity gain
–40°C
85°C
L
See Figure 4
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL032M and TL032AM electrical characteristics at specified free-air temperature
TL032M, TL032AM
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.5
MIN
MAX
1.5
25°C
Full range
25°C
0.69
0.53
0.57
TL032M
= 0,
= 0,
V
V
R
†
O
IC
6.5
4.5
V
IO
Input offset voltage
mV
2.8
0.39
0.8
= 50 Ω
S
TL032AM
†
Full range
5.8
3.8
25°C to
125°C
TL032M
9.7
9.7
9.7
9.7
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Temperature coefficient
of input offset voltage
µV/°C
V
IO
25°C to
125°C
TL032AM
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
125°C
25°C
1
0.2
2
100
10
1
0.2
2
100
10
pA
nA
pA
nA
V
= 0,
V
V
= 0
= 0
O
IC
I
I
Input offset current
Input bias current
IO
See Figure 5
200
20
200
20
V
O
= 0,
IC
IB
See Figure 5
125°C
7
8
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
ICR
V
–1.5
to 4
–11.5
to 14
†
Full range
25°C
–55°C
125°C
25°C
3
3
4.3
4.1
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
3
4.4
13
14
–3
–3
–3
4
–4.2
–4
–12.5
–12.5
–12.5
5
–13.9
–13.8
–14
14.3
10.4
15
Maximum negative peak
output voltage swing
–55°C
125°C
25°C
OM–
–4.3
12
Large-signal differential
A
VD
–55°C
125°C
25°C
3
7.1
4
V/mV
§
voltage amplification
3
12.9
4
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
25°C
5
87
87
87
96
95
96
4
94
94
94
96
95
96
pF
i
25°C
70
70
70
75
75
75
75
70
70
75
75
75
Common-mode rejection
ratio
V
V
= V
min,
IC
O
ICR
= 0, R = 50 Ω
CMRR
–55°C
125°C
25°C
dB
dB
S
Supply-voltage
rejection ratio
V
V
= ±5 V to ±15 V,
= 0, R = 50 Ω
CC±
O
k
–55°C
125°C
SVR
S
(∆V
/∆V )
CC±
IO
†
‡
Full range is –55°C to 125°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = 2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL032M and TL032AM electrical characteristics at specified free-air temperature (continued)
TL032M, TL032AM
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
T
CC±
TYP
CC±
MIN
A
MIN
MAX
5
TYP
13
MAX
25°C
3.8
2.3
17
17
Total power dissipation
(two amplifiers)
P
D
V
V
= 0,
= 0,
No load
No load
–55°C
125°C
25°C
5
9.4
mW
O
V
O
= 0,
3.6
5
11.8
434
312
394
120
17
384
228
356
120
500
500
500
560
560
560
Supply current
(two amplifiers)
I
–55°C
125°C
25°C
µA
CC
O
V /V
O1 O2
Crosstalk attenuation
A
= 100 dB
dB
VD
TL032M and TL032AM operating characteristics at specified free-air temperature
TL032M, TL032AM
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
2.9
1.9
3.5
5.1
4.6
4.7
132
123
58
MAX
25°C
–55°C
125°C
25°C
2
1.4
R
= 10 kΩ, C = 100 pF
Positive slew rate at unity
L
L
SR+
†
gain
See and Figure 1
2.4
1
3.9
1.5
1
R
= 10 kΩ, C = 100 pF
L
See and Figure 1
Negative slew rate at unity
L
SR–
–55°C
125°C
25°C
3.2
†
gain
4.1
1
138
142
166
138
142
166
V
R
= ±10 V,
I(PP)
t
r
Rise time
–55°C
125°C
25°C
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
132
123
158
5%
6%
8%
49
V
R
= ±10 V,
I(PP)
t
f
Fall time
–55°C
125°C
25°C
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
11%
16%
14%
49
V
R
= ±10 V,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
–55°C
125°C
L
L
See Figures 1 and 2
f = 10 Hz
TL032M
25°C
Equivalent
f = 1 kHz
f = 10 Hz
f = 1 kHz
41
41
R
= 20 Ω
See Figure 3
S
V
n
input noise
nV/√Hz
49
49
voltage
TL032AM
25°C
25°C
41
41
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
–55°C
125°C
25°C
1
1
1.1
1.1
0.9
65°
64°
62°
V = 10 mV,
I
B1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
0.9
61°
57°
59°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
L
φ
m
Phase margin at unity gain
–55°C
125°C
See Figure 4
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL034C and TL034AC electrical characteristics at specified free-air temperature
TL034C, TL034AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
6
MIN
MAX
4
25°C
Full range
25°C
0.91
0.7
0.79
TL034C
= 0,
= 0,
V
V
R
†
O
IC
8.2
3.5
5.7
6.2
1.5
3.7
V
IO
Input offset voltage
mV
0.58
= 50 Ω
S
TL034AC
†
Full range
25°C to
70°C
TL034C
11.6
11.6
12
12
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Temperature coefficient
of input offset voltage
µV/°C
V
IO
25°C to
70°C
TL034AC
25
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
70°C
25°C
70°C
1
9
100
200
200
400
1
12
2
100
200
200
400
V
= 0, V = 0
IC
O
I
I
Input offset current
Input bias current
pA
pA
IO
See Figure 5
2
V
O
= 0, V = 0
IC
IB
See Figure 5
50
–3.4
80
–1.5
–11.5
–13.4
to 14 to 15.4
25°C
to 4 to 5.4
Common-mode input
voltage range
V
V
ICR
–1.5
to 4
–11.5
to 14
†
Full range
25°C
0°C
3
3
4.3
4.2
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
70°C
25°C
0°C
3
4.3
13
14
–3
–3
–3
4
–4.2
–4.1
–4.2
12
–12.5
–12.5
–12.5
5
–13.9
–13.9
–14
Maximum negative peak
output voltage swing
OM–
70°C
25°C
0°C
14.3
13.5
15.2
Large-signal differential
A
VD
3
11.1
13.3
4
V/mV
§
voltage amplification
70°C
25°C
25°C
25°C
0°C
4
5
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
5
87
87
87
96
96
96
14
94
94
94
96
96
96
pF
i
70
70
70
75
75
75
75
75
75
75
75
75
V
V
R
= V
= 0,
min,
ICR
IC
O
Common-mode
rejection ratio
CMRR
dB
dB
= 50 Ω
S
70°C
25°C
0°C
Supply-voltage
rejection ratio
k
V
O
= 0, R = 50 Ω
S
SVR
(∆V
/∆V )
CC±
IO
70°C
†
‡
Full range is 0°C to 70°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = ±2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL034C and TL034AC electrical characteristics at specified free-air temperature (continued)
TL034C, TL034AC
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
26
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
10
10
10
1
MIN
MAX
34
25°C
7.7
7.4
7.6
Total power dissipation
(two amplifiers)
P
D
V
V
= 0, No load
= 0, No load
0°C
70°C
25°C
0°C
25.3
25.2
0.87
0.85
0.84
120
34
mW
O
34
0.77
0.74
0.76
120
1.12
1.12
1.12
Supply current (four
amplifiers)
I
1
mA
dB
CC
O
70°C
25°C
1
V /V
O1 O2
Crosstalk attenuation
A
= 100
VD
TL034C and TL034AC operating characteristics at specified free-air temperature
TL034C, TL034AC
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC
±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
MAX
25°C
0°C
2
1.8
2.2
3.9
3.7
4
2.9
2.6
3.2
5.1
5
R
= 10 kΩ, C = 100 pF
Positive slew rate at unity
L
L
SR+
†
See Figure 1
gain
70°C
25°C
0°C
1.5
1.5
1.5
1.5
R
= 10 kΩ, C = 100 pF
L
See Figure 1
Negative slew rate at unity
L
SR–
†
gain
70°C
25°C
0°C
5
138
134
150
138
134
150
132
127
142
132
127
142
5%
4%
6%
83
V
R
= ±10 V,
I(PP)
t
r
Rise time
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
70°C
25°C
0°C
V
R
= ±10 V,
I(PP)
t
f
Fall time
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
70°C
25°C
0°C
11%
10%
12%
83
V
R
= ±10 V,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
L
L
See Figures 1 and 2
70°C
f = 10 Hz
TL034C
25°C
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
43
43
R
= 20 Ω
See Figure 3
Equivalent input
noise voltage
S
V
n
nV/√Hz
83
83
TL034AC
43
43
60
I
Equivalent input noise current
Unity-gain bandwidth
f = 1 kHz
25°C
25°C
0°C
0.003
1
0.003
1.1
1.1
1
pA/√Hz
n
V = 10 mV
I
L
B
1
1
MHz
R
= 10 kΩ, C = 25 pF
L
See Figure 4
70°C
25°C
0°C
1
61°
61°
60°
65°
65°
64°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
φ
Phase margin at unity gain
L
m
See Figure 4
70°C
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL034I and TL034AI electrical characteristics at specified free-air temperature
TL034I, TL034AI
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.6
MIN
MAX
4
25°C
Full range
25°C
0.91
0.7
0.79
TL034I
= 0,
= 0,
V
V
R
†
O
IC
9.3
7.3
1.5
4.8
V
IO
Input offset voltage
mV
3.5
0.58
= 50 Ω
S
TL034AI
†
Full range
6.8
25°C to
85°C
TL034I
11.5
11.5
11.6
11.6
V
= 0,
R
= 0, V
IC
O
Temperature coefficient
of input offset voltage
µV/°C
V
IO
25°C to
85°C
= 50 Ω
TL034AI
25
S
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
85°C
25°C
85°C
1
0.02
2
100
0.45
200
0.9
1
0.02
2
100
0.45
200
0.9
pA
nA
pA
nA
V
= 0, V = 0
IC
O
I
I
Input offset current
Input bias current
IO
See Figure 5
V
O
= 0, V = 0
IC
IB
See Figure 5
0.2
0.3
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
V
V
ICR
–1.5
to 4
–11.5
to 14
†
Full range
25°C
–40°C
85°C
25°C
–40°C
85°C
–40°C
85°C
25°C
25°C
25°C
–40°C
85°C
25°C
–40°C
85°C
3
3
4.3
4.1
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
= 10 kΩ
OM+
L
3
4.4
13
14
–3
–3
–3
4
–4.2
–4.1
–4.2
12
–12.5
–12.5
–12.5
5
–13.9
–13.8
–14
Maximum negative
peak
output voltage swing
R
R
= 10 kΩ
= 10 kΩ
V
OM–
L
L
14.3
11.6
Large-signal differential
A
VD
V/mV
§
voltage amplification
3
8.4
4
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
5
87
87
87
96
96
96
4
94
94
94
96
96
96
pF
i
70
70
70
75
75
75
75
75
75
75
75
75
V
V
R
= V
= 0,
min,
ICR
IC
O
Common-mode
rejection ratio
CMRR
dB
dB
= 50 Ω
S
Supply-voltage
rejection ratio
k
V
O
= 0, R = 50 Ω
S
SVR
(∆V
/ ∆V )
CC±
IO
†
‡
Full range is –40°C to 85°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = ±2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL034I and TL034AI electrical characteristics at specified free-air temperature (continued)
TL034I, TL034AI
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
UNIT
T
CC±
TYP
CC±
MIN
A
MIN
MAX
10
10
10
1
TYP
26
MAX
25°C
7.7
5.8
7.4
34
34
Total power dissipation
(four amplifiers)
P
D
V
= 0, No load
= 0, No load
–40°C
85°C
25°C
–40°C
85°C
25°C
21.7
24.8
0.87
0.72
0.83
120
mW
O
O
34
0.77
0.58
0.74
120
1.12
1.12
1.12
Supply current
(four amplifiers)
I
V
1
mA
dB
CC
1
V /V
O1 O2
Crosstalk attenuation
A
VD
= 100
TL034I and TL034AI operating characteristics
TL034I, TL034AI
= ±5 V V = ±15 V
CC±
PARAMETER
TEST CONDITIONS
T
V
UNIT
V/µs
V/µs
ns
A
CC±
MIN
TYP
MAX
MIN
1.5
1
TYP
2.9
2.1
3.3
5.1
4.8
4.9
132
123
146
132
123
146
5%
5%
7%
83
MAX
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
25°C
–40°C
85°C
2
R
= 10 kΩ, C = 100 pF
Positive slew rate at unity
L
L
SR+
1.6
2.3
3.9
3.3
4.1
138
132
154
138
132
154
11%
12%
13%
83
†
gain
See Figure 1
1.5
1.5
1.5
1.5
R
= 10 kΩ, C = 100 pF
L
See Figure 1
Negative slew rate at unity
L
SR–
†
gain
V
R
= ±10 V,
I(PP)
t
r
Rise time
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
V
R
= ±10 V,
I(PP)
t
f
Fall time
ns
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
V
R
= ±10 V,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
L
L
See Figures 1 and 2
f = 10 Hz
TL034I
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
43
43
R
= 20 Ω
See Figure 3
Equivalent input
noise voltage
TL034AI
S
V
n
nV/√Hz
83
83
25°C
25°C
43
43
60
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
–40°C
85°C
1
1
1.1
1.1
1
V = 10 mV,
I
B
1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
0.9
61°
61°
60°
25°C
65°
65°
64°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
L
φ
m
Phase margin at unity gain
–40°C
85°C
See Figure 4
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL034M and TL034AM electrical characteristics at specified free-air temperature
TL034M, TL034AM
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
3.6
11
MIN
MAX
4
25°C
Full range
25°C
0.91
0.7
0.78
TL034M
V
V
R
= 0,
O
†
9
V
IO
Input offset voltage
mV
= 0,
IC
3.5
8.5
0.58
1.5
6.5
= 50 Ω
S
TL034AM
†
Full range
25°C to
125°C
TL034M
10.6
10.6
10.9
10.9
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Temperature coefficient of
input offset voltage
µV/°C
V
IO
25°C to
125°C
TL034AM
V
V
R
= 0,
= 0,
= 50 Ω
O
IC
S
Input offset voltage
long-term drift
25°C
0.04
0.04
µV/mo
‡
25°C
125°C
25°C
1
0.2
2
100
10
1
0.2
2
100
10
pA
nA
pA
nA
V
= 0, V = 0
IC
O
I
I
Input offset current
Input bias current
IO
See Figure 5
200
20
200
20
V
O
= 0, V = 0
IC
IB
See Figure 5
125°C
7
8
–1.5
to 4 to 5.4
–3.4
–11.5
to 14 to 15.4
–13.4
25°C
Common-mode input
voltage range
V
ICR
V
–1.5
to 4
–11.5
to 14
†
Full range
25°C
–55°C
125°C
25°C
3
3
4.3
4.1
13
13
14
14
Maximum positive peak
output voltage swing
V
V
R
R
R
= 10 kΩ
= 10 kΩ
= 10 kΩ
V
V
OM+
L
L
L
3
4.4
13
14
–3
–3
–3
4
–4.2
–4
–12.5
–12.5
–12.5
5
–13.9
–13.8
–14
14.3
10.4
15
Maximum negative peak
output voltage swing
–55°C
125°C
25°C
OM–
–4.3
12
Large-signal differential
A
VD
–55°C
125°C
25°C
3
7.1
4
V/mV
§
voltage amplification
3
12.9
4
12
10
12
10
r
Input resistance
Ω
i
c
Input capacitance
25°C
5
87
87
87
96
95
96
4
94
94
94
96
95
96
pF
i
25°C
70
70
70
75
75
75
75
70
70
75
75
75
Common-mode
rejection ratio
V
V
= V
min,
IC
O
ICR
= 0, R = 50 Ω
CMRR
–55°C
125°C
25°C
dB
dB
S
Supply-voltage
rejection ratio
k
V
O
= 0, R = 50 Ω
–55°C
125°C
SVR
S
(∆V
/∆V )
CC±
IO
†
‡
Full range is –55°C to 125°C.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated to
A
T
= 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
§
At V
CC±
= ±5 V, V = ±2.3 V; at V = ±15 V, V = ±10 V
CC± O
O
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TL034M and TL034AM electrical characteristics at specified free-air temperature (continued)
TL034M, TL034AM
PARAMETER
TEST CONDITIONS
V
= ±5 V
V
= ±15 V
TYP
26
UNIT
T
CC±
TYP
CC±
A
MIN
MAX
10
MIN
MAX
34
25°C
7.7
4.6
7.1
Total power dissipation
(two amplifiers)
P
D
V
V
= 0,
= 0,
No load
No load
–55°C
125°C
25°C
12
18.7
23.6
0.87
0.62
0.79
120
45
mW
O
12
45
0.77
0.46
0.71
120
1
1.12
1.5
1.5
Supply current
(two amplifiers)
I
–55°C
125°C
25°C
1.2
1.2
mA
dB
CC
O
V /V
O1 O2
Crosstalk attenuation
A
= 100
VD
TL034M and TL034AM operating characteristics at specified free-air temperature
TL034M, TL034AM
PARAMETER
TEST CONDITIONS
T
V
= ±5 V
V = ±15 V
CC±
UNIT
V/µs
V/µs
ns
A
CC±
TYP
MIN
MAX
MIN
1.5
1
TYP
2.9
1.9
3.5
5.1
4.6
4.7
132
123
58
MAX
25°C
–55°C
125°C
25°C
2
1.4
R
= 10 kΩ, C = 100 pF
Positive slew rate at unity
L
L
SR+
†
gain
See Figure 1
2.4
1
3.9
1.5
1
R
= 10 kΩ, C = 100 pF
L
See Figure 1
Negative slew rate at unity
L
SR–
–55°C
125°C
25°C
3.2
†
gain
4.1
1
138
142
166
138
142
166
V
R
= ±10 V,
I(PP)
t
r
Rise time
–55°C
125°C
25°C
= 10 kΩ, C = 100 pF
L
L
See Figures 1 and 2
132
123
158
5%
6%
8%
83
V
R
= ±10 V,
I(PP)
t
f
Fall time
–55°C
125°C
25°C
ns
= 10 kΩ, C = 100 pF
L
L
See Figure 1
11%
16%
14%
83
V
R
= ±10 V,
I(PP)
= 10 kΩ, C = 100 pF
Overshoot factor
–55°C
125°C
L
L
See Figures 1 and 2
f = 10 Hz
TL034M
25°C
f = 1 kHz
f = 10 Hz
f = 1 kHz
43
43
Equivalent input
noise voltage
TL034AM
R = 20 Ω
S
See Figure 3
V
n
nV/√Hz
83
83
25°C
25°C
43
43
Equivalent input noise
current
I
n
f = 1 kHz
0.003
0.003
pA/√Hz
25°C
–55°C
125°C
25°C
1
1
1.1
1.1
0.9
65°
64°
62°
V = 10 mV,
I
B1
Unity-gain bandwidth
MHz
R
= 10 kΩ, C = 25 pF
L
L
See Figure 4
0.9
61°
57°
59°
V = 10 mV,
I
L
R
= 10 kΩ, C = 25 pF
L
φ
m
Phase margin at unity gain
–55°C
125°C
See Figure 4
†
For V
= ±5 V, V
= ±1 V; for V
CC±
= ±15 V, V
= ±5 V
I(PP)
CC±
I(PP)
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
V
CC+
–
Overshoot
V
O
+
V
I
90%
V
CC–
C
L
R
L
(see Note A)
10%
t
NOTE A: C includes fixture capacitance.
L
r
Figure 1. Slew-Rate and Overshoot Test Circuit
Figure 2. Rise Time and Overshoot Waveform
10 kΩ
V
–
CC+
10 kΩ
V
I
V
L
+
O
100 Ω
V
CC+
–
V
CC–
V
O
C
L
R
(see Note A)
V
CC–
R
R
S
S
NOTE A: C includes fixture capacitance.
L
Figure 4. Unity-Gain Bandwidth and
Phase-Margin Test Circuit
Figure 3. Noise-Voltage Test Circuit
V
CC+
Ground Shield
–
+
V
CC–
Picoammeters
Figure 5. Input-Bias and Offset-Current Test Circuit
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
typical values
Typical values presented in this data sheet represent the median (50% point) of device parametric performance.
input bias and offset current
At the picoampere bias current level typical of the TL03x and TL03xA, accurate measurement of the bias current
becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can
exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses
a two-step process. The socket leakage is measured using picoammeters with bias voltages applied but with
no device in the socket. The device is then inserted into the socket and a second test that measures both the
socket leakage and the device input bias current is performed. The two measurements are then subtracted
algebraically to determine the bias current of the device.
noise
With the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage density
is performed at f = 1 kHz, unless otherwise noted.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
6–11
12–14
15
Distribution of TL03x input offset voltage
Distribution of TL03x input offset-voltage temperature coefficient
Input bias current vs Common-mode input voltage
Input bias current and input offset current vs Free-air temperature
Common-mode input voltage vs Supply voltage
Common-mode input voltage vs Free-air temperature
Output voltage vs Differential input voltage
16
17
18
19, 20
21
Maximum peak output voltage vs Supply voltage
Maximum peak-to-peak output voltage vs Frequency
Maximum peak output voltage vs Output current
Maximum peak output voltage vs Free-air temperature
Large-signal differential voltage amplification vs Load resistance
Large-signal differential voltage amplification and Phase shift vs Frequency
Large-signal differential voltage amplification vs Free-air temperature
Output impedance vs Frequency
22
23, 24
25, 26
27
28
29
30
Common-mode rejection ratio vs Frequency
31, 32
33
Common-mode rejection ratio vs Free-air temperature
Supply-voltage rejection ratio vs Free-air temperature
Short-circuit output current vs Supply voltage
34
35
Short-circuit output current vs Time
36
Short-circuit output current vs Free-air temperature
Equivalent input noise voltage vs Frequency (TL031 and TL031A)
Equivalent input noise voltage vs Frequency (TL032 and TL032A)
Equivalent input noise voltage vs Frequency (TL034 and TL034A)
Supply current vs Supply voltage (TL031 and TL031A)
Supply current vs Supply voltage (TL032 and TL032A)
Supply current vs Supply voltage (TL034 and TL034A)
Supply current vs Free-air temperature (TL031 and TL031A)
Supply current vs Free-air temperature (TL032 and TL032A)
Supply current vs Free-air temperature (TL034 and TL034A)
Slew rate vs Load resistance
37
38
39
40
41
42
43
44
45
46
47, 48
49, 50
51
Slew rate vs Free-air temperature
Overshoot factor vs Load capacitance
Total harmonic distortion vs Frequency
52
Unity-gain bandwidth vs Supply voltage
53
Unity-gain bandwidth vs Free-air temperature
54
Phase margin vs Supply voltage
55
Phase margin vs Load capacitance
56
Phase margin vs Free-air temperature
57
Voltage-follower small-signal pulse response
58
Voltage-follower large-signal pulse response
59, 60
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TL031
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TL031A
INPUT OFFSET VOLTAGE
14
12
10
8
16
14
12
10
8
1681 Units Tested From 1 Wafer Lot
1433 Units Tested From 1 Wafer Lot
V
T
A
= ±15 V
CC±
= 25°C
V
T
A
= ±15 V
CC±
= 25°C
P Package
P Package
6
6
4
4
2
2
0
0
–1.2
–0.6
0
0.6
1.2
–900
–600
–300
0
300
600
900
V
IO
– Input Offset Voltage – mV
V
IO
– Input Offset Voltage – µV
Figure 6
Figure 7
DISTRIBUTION OF TL032A
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TL032
INPUT OFFSET VOLTAGE
15
12
9
12
1321 Amplifiers Tested From 1 Wafer Lot
1681 Amplifiers Tested From 1 Wafer Lot
V
T
= ±15 V
V
T
= ±15 V
CC±
= 25°C
CC±
= 25°C
A
A
P Package
P Package
9
6
6
3
0
3
0
–900
–1.2
–0.6
0
0.6
1.2
–600
–300
0
300
600
900
V
IO
– Input Offset Voltage – mV
V
IO
– Input Offset Voltage – µV
Figure 8
Figure 9
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TL034
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TL034A
INPUT OFFSET VOLTAGE
12
9
15
12
9
1716 Amplifiers Tested From 3 Wafer Lots
1681 Amplifiers Tested From 1 Wafer Lot
V
= ±15 V
V
= ±15 V
CC±
= 25°C
CC±
= 25°C
T
A
T
A
N Package
D Package
6
6
3
3
0
0
–1.8
–1.2
–0.6
0
0.6
1.2
–1.2
0.6
0
0.6
1.2
1.8
V
IO
– Input Offset Voltage – mV
V
IO
– Input Offset Voltage – mV
Figure 10
Figure 11
DISTRIBUTION OF TL031
INPUT OFFSET-VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TL032
INPUT OFFSET-VOLTAGE
TEMPERATURE COEFFICIENT
24
18
12
6
76 Units Tested From 1 Wafer Lot
30
160 Amplifiers Tested From 2 Wafer Lots
V
T
A
= ±15 V
CC±
= 25°C to 125°C
V
T
A
= ±15 V
CC±
= 25°C to 125°C
P Package
25
20
15
10
5
P Package
0
0
–40 –30 –20 –10
0
10
20
30
40
–30
–20
–10
0
10
20
30
V
V
IO – Input Offset-Voltage Temperature Coefficient – µV/°C
IO – Temperature Coefficient – µV/°C
Figure 12
Figure 13
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TL034
INPUT OFFSET-VOLTAGE
TEMPERATURE COEFFICIENT
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
30
25
20
15
10
5
10
5
160 Amplifiers Tested From 2 Wafer Lots
V
T
A
= ±15 V
CC±
= 25°C
V
T
= ±15 V
CC±
= 25°C to 125°C
A
D Package
0
–5
0
–10
–40 –30 –20 –10
0
10
20
30
40
–15
–10
–5
0
5
10
15
V
V
IC
– Common-Mode Input Voltage – V
– Temperature Coefficient – µV/°C
IO
Figure 14
Figure 15
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
COMMON-MODE INPUT VOLTAGE
†
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
16
12
8
10
1
T
A
= 25°C
V
V
V
= ±15 V
CC±
= 0
= 0
O
IC
Positive Limit
4
I
IB
0
0.1
–4
–8
–12
–16
Negative Limit
I
IO
0.01
0.001
25
45
65
85
105
125
0
2
4
6
8
10
12
14
16
T
A
– Free-Air Temperature – °C
|V | – Supply Voltage – V
CC±
Figure 16
Figure 17
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
†
COMMON-MODE INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
20
15
10
5
1.5
1
R
R
= 1 kΩ
= 2 kΩ
V
CC±
= ±15 V
L
L
R
= 5 kΩ
= 10 kΩ
Positive Limit
L
R
L
L
R
= 20 kΩ
0.5
0
0
V
T
A
= ±5 V
= 25°C
CC±
–5
–10
–0.5
R
R
R
= 20 kΩ
= 10 kΩ
= 5 kΩ
L
L
L
–1
R
R
= 2 kΩ
= 1 kΩ
L
L
–15
–20
Negative Limit
25 50
–1.5
–5 –4 –3 –2 –1
0
1
2
3
4
5
–75 –50 –25
0
75
100 125
T
A
– Free-Air Temperature –°C
V
ID
– Differential Input Voltage – V
Figure 18
Figure 19
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
1.5
16
12
8
R
= 5 kΩ
L
V
T
= ±15 V
CC±
= 25°C
R
= 10 kΩ
= 20 kΩ
= 50 kΩ
R
T
= 10 kΩ
L
A
L
L
L
A
= 25°C
R
R
1
V
OM+
0.5
4
0
0
–4
–8
–12
–16
–0.5
V
OM–
R
R
R
R
= 50 kΩ
= 20 kΩ
= 10 kΩ
= 5 kΩ
L
L
L
L
–1
–1.5
15
–15
–10
–5
0
5
10
0
2
4
6
8
10
12
14
16
V
ID
– Differential Input Voltage – V
|V | – Supply Voltage – V
CC±
Figure 20
Figure 21
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
†
MAXIMUM PEAK OUTPUT VOLTAGE
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
FREQUENCY
5
4
3
2
1
0
30
25
20
15
10
5
V
T
= ±5 V
CC±
= 25°C
R
= 10 kΩ
L
V
= ±15 V
A
CC±
V
OM+
V
OM–
T
A
= –55°C
T
= 125°C
A
V
= ±5 V
CC±
0
0
5
10
15
20
1 k
10 k
100 k
1 M
f – Frequency – Hz
|I | – Output Current – mA
O
Figure 22
Figure 23
†
MAXIMUM PEAK OUTPUT VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
OUTPUT CURRENT
5
16
V
T
= ±15 V
CC±
4
3
= 25°C
14
12
10
8
V
A
OM+
2
V
OM–
1
V
R
= ±5 V
= 10 kΩ
CC±
L
0
V
OM+
–1
–2
–3
–4
–5
6
4
V
OM–
2
0
0
–75 –50 –25
0
25
50
75
100 125
5
10
15
20
25
30
|I | – Output Current – mA
O
T
A
– Free-Air Temperature – °C
Figure 24
Figure 25
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
†
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOAD RESISTANCE
16
12
8
40
35
30
25
20
15
10
5
V
T
A
= ±1 V
= 25°C
O
V
OM+
V
= ±15 V
= ±5 V
CC±
4
V
R
= ±15 V
CC±
= 10 kΩ
0
L
V
CC±
–4
–8
–12
–16
V
OM–
0
–75 –50 –25
0
25
50
75
100 125
10 k
100 k
1 M
T
A
– Free-Air Temperature –°C
R
– Load Resistance – Ω
L
Figure 26
Figure 27
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
100 k
10 k
1 k
0°
V
= ±15 V
CC±
R
C
= 10 kΩ
= 25 pF
L
L
30°
60°
90°
120°
T
A
= 25°C
A
VD
100
10
Phase Shift
1
150°
180°
0.1
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
Figure 28
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
†
OUTPUT IMPEDANCE
vs
VOLTAGE AMPLIFICATION
vs
FREQUENCY
FREE-AIR TEMPERATURE
50
10
200
R
= 10 kΩ
L
A
= 100
VD
100
80
V
CC±
= ±15 V
60
V
CC±
= ±5 V
A
VD
= 10
= 1
40
A
VD
20
10
V
= ±15 V
(open loop) ≈ 250 Ω
= 25°C
CC±
r
T
o
A
1
–75 –50 –25
0
25
50
75
100 125
1 k
10 k
100 k
T
A
– Free-Air Temperature – °C
f – Frequency – Hz
Figure 29
Figure 30
COMMON-MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
100
V
T
= ±5 V
V
T
= ±15 V
CC±
= 25°C
CC±
= 25°C
90
80
70
60
50
40
30
20
10
0
A
A
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 31
Figure 32
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
†
†
SUPPLY-VOLTAGE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
100
98
96
94
92
90
95
90
85
80
75
V
= ±5 V to ±15 V
CC±
V
= ±15 V
= ±5 V
CC±
CC±
V
V
IC
= V
min
ICR
–75 –50 –25
0
25
50
75
100 125
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 33
Figure 34
SHORT-CIRCUIT OUTPUT CURRENT
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
SUPPLY VOLTAGE
TIME
30
20
30
20
V
T
= 0
= 25°C
O
A
V
ID
= 100 mV
V
ID
= 100 mV
10
10
0
V
ID
= –100 mV
0
–10
–20
–30
V
= –100 mV
ID
–10
–20
V
T
A
= ±15 V
= 25°C
CC±
0
2
4
|V
6
8
10
12
14
16
0
5
10
15
t – Time – s
20
25
30
| – Supply Voltage – V
CC±
Figure 35
Figure 36
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
TL031 and TL031A
EQUIVALENT INPUT NOISE VOLTAGE
†
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
25
20
70
60
V
= ±15 V
V
R
= ±15 V
CC±
CC±
= 20 Ω
S
T
= 25°C
A
15
See Figure 3
V
V
= 100 mV
V
CC±
= ±5 V
ID
10
5
0
= –100 mV
ID
V
= ±5 V
CC±
–5
50
40
–10
–15
–20
–25
V
CC±
= ±15 V
V
O
= 0
10
100
1 k
10 k
100 k
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
f – Frequency – Hz
Figure 37
Figure 38
TL034 and TL034A
TL032 and TL032A
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
90
80
60
50
V
= ±15 V
V
= ±15 V
CC±
= 20 Ω
CC±
= 20 Ω
R
T
R
T
S
S
= 25°C
= 25°C
A
A
See Figure 3
See Figure 3
70
60
40
30
50
40
10
100
1 k
10 k
100 k
10
100
1 k
10 k
11 k
f – Frequency – Hz
f – Frequency – Hz
Figure 39
Figure 40
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
TL031 and TL031A
†
TL032 and TL032A
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
†
SUPPLY VOLTAGE
250
200
SUPPLY VOLTAGE
500
400
300
200
100
0
V
= 0
O
V
= 0
No Load
O
No Load
T
= 25°C
A
T
A
= 25°C
150
100
50
T
= 125°C
= –55°C
A
T
A
= 125°C
= –55°C
T
A
T
A
0
0
2
4
6
8
10
12
14
16
0
2
4
|V
6
8
10
12
14
16
|V
CC±
| – Supply Voltage – V
| – Supply Voltage – V
CC±
Figure 41
Figure 42
TL031 and TL031A
SUPPLY CURRENT
vs
TL034 and TL034A
SUPPLY CURRENT
vs
†
†
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1000
800
600
400
250
200
150
100
V
= 0
V
= 0
O
O
V
= ±15 V
= ±5 V
CC±
CC±
No Load
No Load
V
T
= 25°C
A
T
= 125°C
= –55°C
A
T
A
200
0
50
0
–75 –50 –25
0
25
50
75
100
125
0
2
4
6
8
10
12
14
16
|V | – Supply Voltage – V
CC±
T
A
– Free-Air Temperature – °C
Figure 43
Figure 44
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
TL034 and TL034A
SUPPLY CURRENT
vs
TL032 and TL032A
SUPPLY CURRENT
vs
†
†
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1000
800
600
400
200
0
500
400
300
200
100
0
V
= 0
O
V
= ±15 V
= ±5 V
V
= 0
CC±
CC±
O
No Load
V
= ±15 V
CC±
No Load
V
V
= ±5 V
CC±
–75 –50 –25
0
25
50
75
100 125
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 45
Figure 46
SLEW RATE
vs
SLEW RATE
vs
LOAD RESISTANCE
LOAD RESISTANCE
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
C
= ±5 V
= 100 pF
= 25°C
CC±
L
SR–
T
A
See Figure 1
SR–
SR+
SR+
V
C
= ±15 V
= 100 pF
= 25°C
CC±
L
T
A
See Figure 1
1
10
100
1
10
100
R
– Load Resistance – kΩ
R
– Load Resistance – kΩ
L
L
Figure 47
Figure 48
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
†
†
SLEW RATE
vs
SLEW RATE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
R
C
= ±5 V
= 10 kΩ
= 100 pF
CC±
L
L
SR–
See Figure 1
SR–
SR+
SR+
V
R
C
= ±15 V
= 10 kΩ
= 100 pF
CC±
L
L
See Figure 1
–75 –50 –25
0
25
50
75
100 125
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 49
Figure 50
OVERSHOOT FACTOR
vs
LOAD CAPACITANCE
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
60
50
40
30
20
10
0
0.5
0.4
V
R
= ±10 mV
I(PP)
= 10 kΩ
V
A
= ±15 V
CC±
= 1
L
VD
T
= 25°C
A
V
T
= 6 V
O(rms)
= 25°C
See Figure 1
A
0.3
0.2
V
= ±5 V
CC±
V
CC±
= ±15 V
0.1
100
0
50
100
150
200
250
1 k
10 k
100 k
C
– Load Capacitance – pF
f – Frequency – Hz
L
Figure 51
Figure 52
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
†
UNITY-GAIN BANDWIDTH
vs
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.05
1.0
V = 10 mV
I
V = 10 mV
I
R
C
= 10 kΩ
= 25 pF
L
L
R
C
= 10 kΩ
= 25 pF
= 25°C
L
L
See Figure 4
T
A
V
= ±15 V
See Figure 4
CC+
V
= ±5 V
CC±
0.95
0.9
–75 –50 –25
0
25
50
75 100 125
0
2
4
6
8
10
12
14
16
|V |– Supply Voltage – V
CC±
T
A
– Free-Air Temperature – °C
Figure 53
Figure 54
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
SUPPLY VOLTAGE
70°
68°
66°
64°
62°
60°
58°
56°
54°
52°
50°
V = 10 mV
I
R
= 10 kΩ
T = 25°C
A
L
65°
63°
V
= ±15 V
CC±
V = 10 mV
I
R
C
= 10 kΩ
= 25 pF
= 25°C
See Figure 4
See Note A
L
L
T
A
See Figure 4
61°
59°
57°
V
CC±
= ±5 V
0
10 20 30 40 50 60 70 80 90 100
– Load Capacitance – pF
C
L
0
2
4
6
8
10
12
14
16
NOTE A: Values of phase margin below a load capacitance of 25 pF
were estimated.
|V | – Supply Voltage – V
CC±
Figure 55
Figure 56
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
TYPICAL CHARACTERISTICS
†
PHASE MARGIN
vs
VOLTAGE-FOLLOWER
SMALL-SIGNAL
FREE-AIR TEMPERATURE
PULSE RESPONSE
67°
65°
63°
61°
59°
57°
55°
16
12
8
V
= ±15 V
CC±
V
= ±15 V
CC±
R
C
= 10 kΩ
= 100 pF
= 25°C
L
L
T
A
See Figure 1
4
V
= ±5 V
CC±
0
–4
–8
–12
–16
V = 10 mV
I
L
L
R
C
= 10 kΩ
= 25 pF
See Figure 4
–75 –50 –25
0
25
50
75
100 125
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
T
A
– Free-Air Temperature –°C
t – Time – µs
Figure 57
Figure 58
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
2
8
6
1
0
4
2
V
R
= ±5 V
= 10 kΩ
CC±
L
V
= ±15 V
CC±
0
R
C
= 10 kΩ
= 100 pF
= 25°C
C
T
= 100 pF
= 25°C
L
L
L
A
–2
T
See Figure 1
A
See Figure 1
–1
–2
–4
–6
–8
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10 12 14 16 18
t – Time – µs
t – Time – µs
Figure 59
Figure 60
†
Data at high and low temperatures are applicable only within the recommended operating free-air temperature ranges of the various devices.
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
input characteristics
The TL03x and TL03xA are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction.
Due to of the extremely high input impedance and resulting low bias-current requirements, the TL03x and
TL03xA are well suited for low-level signal processing; however, leakage currents on printed circuit boards and
socketseasilycanexceedbias-currentrequirementsandcausedegradationinsystemperformance. Itisagood
practice to include guard rings around inputs (see Figure 61). These guard rings should be driven from a
low-impedance source at the same voltage level as the common-mode input.
Unused amplifiers should be connected as grounded unity-gain followers to avoid oscillation.
V
I
+
V
O
–
V
I
–
V
O
+
–
V
O
+
V
I
(a) NONINVERTING AMPLIFIER
(b) INVERTING AMPLIFIER
(c) UNITY-GAIN AMPLIFIER
Figure 61. Use of Guard Rings
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
output characteristics
All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance.
The TL03x and TL03xA drive higher capacitive loads; however, as the load capacitance increases, the resulting
response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation. The value of
the load capacitance at which oscillation occurs varies with production lots. If an application appears to be
sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate
the problem (see Figure 63). Capacitive loads of 1000 pF and larger can be driven if enough resistance is added
in series with the output (see Figure 62).
(a) C = 100 pF, R = 0
(b) C = 300 pF, R = 0
(c) C = 350 pF, R = 0
L
L
L
(d) C = 1000 pF, R = 0
(e) C = 1000 pF, R = 50 Ω
(f) C = 1000 pF, R = 2 kΩ
L
L
L
Figure 62. Effect of Capacitive Loads
15 V
–
R
V
O
5 V
+
–5 V
– 15 V
C
L
10 kΩ
(see Note A)
NOTE A: C includes fixture capacitance.
L
Figure 63. Test Circuit for Output Characteristics
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
high-Q notch filter
In general, Texas Instruments enhanced-JFET operational amplifiers serve as excellent filters. The circuit in
Figure 64 provides a narrow notch at a specific frequency. Notch filters are designed to eliminate frequencies
that are interfering with the operation of an application. For this filter, the center frequency can be calculated as:
1
f
O
2
R1 C1
With the resistors and capacitors shown in Figure 64, the center frequency is 1 kHz. C1 = C3 = C2 + 2 and
R1 = R3 = 2 × R2. The center frequency can be modified by varying these values. When adjusting the center
frequency, ensure that the operational amplifier has sufficient gain at the frequency required.
15 V
–
R1
R3
V
O
+
V
I
TL03x
1.5 MΩ
1.5 MΩ
–15 V
C2
220 pF
R3
C1
750 kΩ
C3
110 pF
110 pF
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
0.2 0.4 0.6 0.8
1
0.2 0.4 0.6 0.8
2
f – Frequency – kHz
Figure 64. High-Q Notch Filter
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
transimpedance amplifier
The low-power precision TL03x allows accurate measurement of low currents. The high input impedance and
low offset voltage of the TL03xA greatly simplify the design of a transimpedance amplifier. At room temperature,
this design achieves 10-bit accuracy with an error of less than 1/2 LSB.
Assuming that R2 is much less than R1 and ignoring error terms, the output voltage can be expressed as:
R1 R2
V
–I
R
IN
F
O
R2
Using the resistor values shown in the schematic for a 1-nA input current, the output voltage equals –0.1 V. If
theV limitfortheTL03xAismeasuredat±12V, themaximuminputcurrentfortheseresistorvaluesis±120 nA.
O
Similarly, one LSB on a 10-bit scale corresponds to 12 mV of output voltage, or 120 pA of input current.
The following equation shows the effect of input offset voltage and input bias current on the output voltage:
R1 R2
V
– V
R
I
I
O
IO
F IO
IB
R2
If the application requires input protection for the transimpedance amplifier, do not use standard PN diodes.
Instead, use low-leakage Siliconix SN4117 JFETs (or equivalent) connected as diodes across the TL03xA
inputs (see Figure 65).
As with all precision applications, special care must be taken to eliminate external sources of leakage and
interference. Other precautions include using high-quality insulation, cleaning insulating surfaces to remove
fluxes and other residue, and enclosing the application within a protective box.
R
F
10 MΩ
15 V
TL03xA
+
Input Current
V
O
–
R1 90 kΩ
–15 V
SN4117
R2
10 kΩ
Figure 65. Transimpedance Amplifier
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
4-mA to 20-mA current loops
Often, information from an analog sensor must be sent over a distance to the receiving circuitry. For many
applications, the most feasible method involves converting voltage information to a current before transmission.
Thefollowing circuits give two variations of low-power current loops. The circuit in Figure 66 requires three wires
from the transmitting to receiving circuitry, while the second variation in Figure 67 requires only two wires, but
includes an extra integrated circuit. Both circuits benefit from the high input impedance of the TL03xA because
many inexpensive sensors do not have low output impedance.
Assuming that the voltage at the noninverting input of the TL03xA is zero, the following equation determines
the output current:
R3
R3
I
V
5V
0.16
V
4mA
O
I
I
R1
R
R2
R
S
S
The circuits presently provide 4-mA to 20-mA output current for an input voltage of 0 to 100 mV. By modifying
R1, R2, and R3, the input voltage range or the output current range can be adjusted.
Including the offset voltage of the operational amplifier in the above equation clearly illustrates why the low offset
TL03xA was chosen:
R3
R3
R3
R3
R1
I
V
5V
V
O
I
I
R1
R1
R
R2
4mA – 0.17
R
R
R2
R
R
S
S
S
S
S
0.16
V
I
V
I
For example, an offset voltage of 1 mV decreases the output current by 0.17 mA.
Due to the low power consumption of the TL03xA, both circuits have at least 2 mA available to drive the actual
sensor from the 5-V reference node.
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
V
CC+
= 10 V
100 kΩ
100 kΩ
R6
R7
TL431
5 V Ref
R2
1 MΩ
–
R5
R1
5 kΩ
2N3904
1N4148
+
V
I
3.3 kΩ
TL03xA
V
EE
= –5 V
R4
R3 80 kΩ
5 kΩ
R
S
I
O
Signal Common
100 Ω
R
50 Ω
L
Figure 66. Three-Wire 4-mA to 20-mA Current Loop
V
CC+
= 10 V
IN
OUT
LT1019-5
GND
5 V Ref
8
2
3
4
R2 1 MΩ
LTC1044
5
10 µF
–
R5
10 µF
R1
+
2N3904
V
I
3.3 kΩ
5 kΩ
TL03xA
R4 5 kΩ
R3 80 kΩ
1N4148
R
S
I
O
Signal Common
100 Ω
R
50 Ω
L
Figure 67. Two-Wire 4-mA to 20-mA Current Loop
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
low-level light-detector preamplifier
Applications that need to detect small currents require high input-impedance operational amplifiers; otherwise,
the bias currents of the operational amplifier camouflage the current being monitored. Phototransistors provide
a current that is proportional to the light reaching the transistor. The TL03x allows even the small currents
resulting from low-level light to be detected.
In Figure 68, if there is no light, the phototransistor is off and the output is high. As light is detected, the
operational amplifier output begins pulling low. Adjusting R4 both compensates for offset voltage of the amplifier
and adjusts the point of light detection by the amplifier.
15 V
R6
10 kΩ
R1
10 kΩ
TL03x
+
R3 10 kΩ
C1
100 pF
V
O
–
R7
R4
10 kΩ
TIL601
10 kΩ
R5 10 kΩ
R2
5 kΩ
–15 V
Figure 68. Low-Level Light-Detector Preamplifier
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
audio-distribution amplifier
This audio-distribution amplifier (see Figure 69) feeds the input signal to three separate output channels. U1A
amplifies the input signal with a gain of 10, while U1B, U1C, and U1D serve as buffers to the output channels.
The gain response of this circuit is very flat from 20 Hz to 20 kHz. The TL03x allows quick response to the input
signal while maintaining low power consumption.
R4
1 MΩ
U1B
–
V
V
OA
OB
CC+
+
C1
1 µF
–
V
I
+
U1C
U1D
U1A
–
V
R1
100 kΩ
R2
+
100 kΩ
V
CC+
R5
10 kΩ
–
C2
100 µF
R3
V
OC
100 kΩ
+
NOTE A: U1A through U1D = TL03x; V
CC+
= 5 V
Figure 69. Audio-Distribution Amplifier Circuit
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL03x, TL03xA
ENHANCED-JFET LOW-POWER LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS180C – FEBRUARY 1997 – REVISED DECEMBER 2001
APPLICATION INFORMATION
instrumentation amplifier with linear gain adjust
The low offset voltage and low power consumption of the TL03x provide an accurate but inexpensive
instrumentation amplifier (see Figure 70). This particular configuration offers the advantage that the gain can
be linearly set by one resistor:
R6
V
=
× (V – V )
B A
O
R5
Adjusting R6 varies the gain. The value of R6 always should be greater than, or equal to, the value of R5 to
ensure stability. The disadvantage of this instrumentation amplifier topology is the high degree of CMRR
degradation resulting from mismatches between R1, R2, R3, and R4. For this reason, these four resistors
should be 0.1%-tolerance resistors.
V
CC+
R1
R3
10 kΩ
0.1%
10 kΩ
0.1%
–
V
A
+
U1A
U1C
–
V
O
+
R5
100 kΩ
R6
1 MΩ
U1B
U1D
–
–
V
B
+
+
R2
R4
R7
100 kΩ
10 kΩ
0.1%
10 kΩ
0.1%
V
CC–
NOTE A: U1A through U1D = TL03x; V
CC±
= ±15 V
Figure 70. Instrumentation Amplifier With Linear Gain-Adjust Circuit
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
microcontroller.ti.com
www.ti.com/lpw
Low Power
Wireless
Telephony
www.ti.com/telephony
Video & Imaging
Wireless
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
SOIC
PDIP
SOIC
PDIP
SOIC
Drawing
5962-9086102Q2A
TL031ACD
TL031ACP
TL031AID
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
FK
D
20
8
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
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P
8
D
8
TL031AIP
P
8
TL031CD
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL031CDE4
TL031CDG4
TL031CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
D
D
P
P
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL031CDRE4
TL031CDRG4
TL031CP
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL031CPE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL031CPWLE
TL031ID
OBSOLETE TSSOP
PW
D
8
8
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL031IDE4
TL031IDG4
TL031IP
D
D
P
P
D
D
D
D
D
D
P
P
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL031IPE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL032ACD
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032ACDE4
TL032ACDG4
TL032ACDR
TL032ACDRE4
TL032ACDRG4
TL032ACP
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL032ACPE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
TL032AID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032AIDE4
TL032AIDG4
TL032AIDR
TL032AIDRE4
TL032AIDRG4
TL032AIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL032AIPE4
TL032CD
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032CDE4
TL032CDG4
TL032CDR
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032CDRE4
TL032CDRG4
TL032CP
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL032CPE4
TL032CPSR
TL032CPSRE4
TL032CPSRG4
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
PS
PS
PS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032CPWLE
TL032ID
OBSOLETE TSSOP
PW
D
8
8
TBD
Call TI
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ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032IDE4
TL032IDG4
TL032IDR
D
D
D
D
D
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL032IDRE4
TL032IDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
TL032IP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL032IPE4
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL032MFKB
TL032MJGB
TL034ACD
OBSOLETE
OBSOLETE
ACTIVE
LCCC
CDIP
SOIC
FK
JG
D
20
8
TBD
TBD
Call TI
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14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034ACDE4
TL034ACDG4
TL034ACDR
TL034ACDRE4
TL034ACDRG4
TL034ACN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
N
N
D
D
D
D
D
D
N
N
D
D
D
D
D
D
N
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL034ACNE4
TL034AID
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034AIDE4
TL034AIDG4
TL034AIDR
TL034AIDRE4
TL034AIDRG4
TL034AIN
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL034AINE4
TL034CD
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034CDE4
TL034CDG4
TL034CDR
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034CDRE4
TL034CDRG4
TL034CN
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
CU NIPDAU N / A for Pkg Type
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
(RoHS)
TL034CNE4
TL034CNSR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SO
N
14
14
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034CNSRE4
TL034CNSRG4
TL034CPW
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034CPWE4
TL034CPWG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034CPWLE
TL034CPWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034CPWRE4
TL034CPWRG4
TL034ID
PW
PW
D
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034IDE4
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034IDG4
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL034IDR
TL034IN
OBSOLETE
ACTIVE
SOIC
PDIP
D
N
14
14
TBD
Call TI
Call TI
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL034INE4
ACTIVE
PDIP
N
14
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL034MD
TL034MFKB
TL034MJB
TL034MN
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
SOIC
LCCC
CDIP
PDIP
D
FK
J
14
20
14
14
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
330
330
330
330
(mm)
12
12
12
12
16
12
16
16
16
16
12
TL031CDR
TL032ACDR
TL032AIDR
TL032CDR
TL032CPSR
TL032IDR
D
D
8
8
SITE 27
SITE 27
SITE 27
SITE 27
SITE 41
SITE 27
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
6.4
6.4
6.4
6.4
8.2
6.4
6.5
6.5
6.5
8.2
7.0
5.2
5.2
5.2
5.2
6.6
5.2
9.0
9.0
9.0
10.5
5.6
2.1
2.1
2.1
2.1
2.5
2.1
2.1
2.1
2.1
2.5
1.6
8
8
12
12
12
12
16
12
16
16
16
16
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
8
8
D
8
8
PS
D
8
12
8
8
TL034ACDR
TL034AIDR
TL034CDR
TL034CNSR
TL034CPWR
D
14
14
14
14
14
8
D
8
D
8
NS
PW
12
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TL031CDR
TL032ACDR
TL032AIDR
TL032CDR
TL032CPSR
TL032IDR
D
D
8
8
SITE 27
SITE 27
SITE 27
SITE 27
SITE 41
SITE 27
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
342.9
342.9
342.9
342.9
346.0
342.9
346.0
346.0
346.0
346.0
346.0
338.1
338.1
338.1
338.1
346.0
338.1
346.0
346.0
346.0
346.0
346.0
20.64
20.64
20.64
20.64
33.0
D
8
D
8
PS
D
8
8
20.64
33.0
TL034ACDR
TL034AIDR
TL034CDR
TL034CNSR
TL034CPWR
D
14
14
14
14
14
D
33.0
D
33.0
NS
PW
33.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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