TL06XX [TI]
TL06xx Low-Power JFET-Input Operational Amplifiers;
| 型号： | TL06XX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TL06xx Low-Power JFET-Input Operational Amplifiers |
| 文件： | 总52页 (文件大小：2592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
TL06xx Low-Power JFET-Input Operational Amplifiers
1 Features
2 Applications
1
•
•
•
Very Low Power Consumption
•
•
•
•
Tablets
Typical Supply Current: 200 μA (Per Amplifier)
White goods
Personal electronics
Computers
Wide Common-Mode and Differential Voltage
Ranges
•
•
Low Input Bias and Offset Currents
3 Description
Common-Mode Input Voltage Range
Includes VCC+
The JFET-input operational amplifiers of the TL06x
series are designed as low-power versions of the
TL08x series amplifiers. They feature high input
impedance, wide bandwidth, high slew rate, and low
input offset and input bias currents. The TL06x series
features the same terminal assignments as the TL07x
and TL08x series.
•
•
•
•
•
•
Output Short-Circuit Protection
High Input Impedance: JFET-Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate: 3.5 V/μs Typical
Device Information(1)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
PART NUMBER
TL06xxD
PACKAGE
BODY SIZE (NOM)
8.65 mm × 3.91 mm
19.56 mm × 6.92 mm
19.30 mm × 6.35 mm
10.30 mm × 5.30 mm
5.00 mm × 4.40 mm
SOIC (14)
TL06xxJ
CDIP (14)
PDIP (14)
SO (14)
TL06xxN
TL06xxNS
TL06xxPW
TSSOP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Schematic Symbol
+
−
IN+
IN−
OUT
OFFSET N1
OFFSET N2
Offset Null/Compensation
TL061 Only
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
www.ti.com
Table of Contents
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
9.2 Typical Applications ................................................ 16
9.3 System Examples ................................................... 17
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information - 8 Pins..................................... 5
6.5 Thermal Information - 14 Pins................................... 5
6.6 Thermal Information - 20 Pins................................... 6
6.7 Electrical Characteristics for TL06xC and TL06xxC . 6
6.8 Electrical Characteristics for TL06xxC and TL06xI... 7
6.9 Electrical Characteristics for TL06xM and TL064M .. 7
6.10 Operating Characteristics........................................ 8
6.11 Typical Characteristics............................................ 9
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
9
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Examples................................................... 20
12 Device and Documentation Support ................. 21
12.1 Documentation Support ........................................ 21
12.2 Related Links ........................................................ 21
12.3 Community Resources.......................................... 21
12.4 Trademarks........................................................... 21
12.5 Electrostatic Discharge Caution............................ 21
12.6 Glossary................................................................ 21
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (January 2014) to Revision L
Page
•
•
Added Applications................................................................................................................................................................. 1
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision J (September 2004) to Revision K
Page
•
•
•
Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
Deleted Ordering Information table. ....................................................................................................................................... 1
Updated Features with Military Disclaimer. ............................................................................................................................ 1
2
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Copyright © 1978–2015, Texas Instruments Incorporated
Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
5 Pin Configuration and Functions
TL061x D, P, and PS Package
8-Pin SOIC, PDIP, and SO
Top View
TL062 FK Package
20-Pin LCCC
Top View
OFFSET N1
IN−
1
2
3
4
NC
V
8
7
6
5
CC+
IN+
OUT
3
2
1
20 19
18
V
OFFSET N2
CC−
NC
4
5
6
7
8
NC
1IN−
NC
2OUT
NC
17
16
15
TL062x D, JG, P, PS, and PW Package
8-Pin SOIC, CDIP, PDIP, SO, and TSSOP
Top View
2IN−
1IN+
NC
14 NC
9 10 11 12 13
1OUT
1IN−
1IN+
1
2
3
4
8
7
6
5
V
CC+
2OUT
2IN−
2IN+
V
CC−
TL064 FK Package
20-Pin LCCC
Top View
TL064x D, J, N, NS, PW, and W Package
14-Pin SOIC, CDIP, PDIP, SO, TSSOP and CFP
Top View
3
2
1
20 19
18
1OUT
1IN−
1IN+
1
2
3
4
5
6
7
14 4OUT
13
12 4IN+
4IN+
NC
4
5
6
7
8
1IN+
NC
4IN−
17
16
15
14
V
V
CC−
CC+
V
11
10
9
V
CC−
CC+
NC
NC
2IN+
2IN−
3IN+
3IN−
3OUT
3IN+
2IN+
9 10 11 12 13
8
2OUT
Pin Functions
PIN
TL061
TL062
TL064
TYPE
DESCRIPTION
NAME
D, JG, P,
PS, PW
D, J, N, NS,
PW, W
D, P, PS
FK
FK
1IN–
1IN+
1OUT
2IN–
2IN+
2OUT
3IN–
3IN+
3OUT
4IN–
4IN+
4OUT
IN–
—
—
—
—
—
—
—
—
—
—
—
—
2
2
3
5
2
3
3
4
I
I
Negative input
7
Positive input
Output
1
2
1
2
O
I
6
15
12
17
—
—
—
—
—
—
—
6
9
Negative input
Positive input
Output
5
5
8
I
7
7
10
13
14
12
19
18
20
—
O
I
—
—
—
—
—
—
—
9
Negative input
Positive input
Output
10
8
I
O
I
13
12
14
—
Negative input
Positive input
Output
I
O
I
Negative input
Copyright © 1978–2015, Texas Instruments Incorporated
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TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
www.ti.com
Pin Functions (continued)
PIN
TL061
D, P, PS
3
TL062
TL064
D, J, N, NS,
PW, W
TYPE
DESCRIPTION
NAME
D, JG, P,
PS, PW
FK
FK
IN+
—
—
1
—
—
I
Positive input
1
5
3
4
6
8
7
9
NC
8
—
—
—
Do not connect
11
13
14
16
18
19
—
—
—
10
20
11
15
17
OFFSET N1
OFFSET N2
OUT
1
5
6
4
7
—
—
—
4
—
—
—
11
4
—
—
—
16
6
—
—
O
Input offset adjustment
Input offset adjustment
Output
VCC–
—
—
Power supply
VCC+
8
Power supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
18
UNIT
VCC+
Supply voltage(2)
VCC–
V
–18
±30
±15
VID
VI
Differential input voltage(3)
Input voltage(2)(4)
V
V
Duration of output short circuit(5)
Operating virtual junction temperature
Case temperature for 60 seconds
Unlimited
TJ
150
260
°C
°C
FK package
Lead temperature 1.6 mm (1/16 inch) from
case for 60 seconds
J, JG, U, or W package
300
°C
Lead temperature 1.6 mm (1/16 inch) from
case for 10 seconds
D, N, NS, P, PS, or PW package
260
150
°C
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−
.
(3) Differential voltages are at IN+, with respect to IN−.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
4
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Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
15
UNIT
VCC+
VCC–
VCM
Supply voltage
5
V
V
V
Supply voltage
–5
–15
Common-mode voltage
VCC– + 4 VCC+ – 4
TL06xM
TL06xQ
TL06xI
–55
–40
–40
0
125
125
85
TA
Ambient temperature
°C
TL06xC
70
6.4 Thermal Information - 8 Pins
THERMAL METRIC(1)
TL06xx
PS (SO)
8 PINS
D (SOIC)
8 PINS
P (PDIP)
8 PINS
PW (TSSOP) JG (CDIP)
UNIT
8 PINS
8 PINS
RθJ Junction-to-ambient thermal
A
97
85
95
149
—
°C/W
°C/W
resistance(2)(3)
RθJ
C(to
Junction-to-case (top) thermal
—
—
—
—
14.5
resistance(4)(5)
p)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(5) The package thermal impedance is calculated in accordance with MIL-STD-883.
6.5 Thermal Information - 14 Pins
TL06xx
D (SOIC)
N (PDIP)
NS (SO)
PS (SO)
PW
(TSSOP)
J (CDIP)
W (CFP)
THERMAL METRIC(1)
UNIT
14 PINS
14 PINS
14 PINS
8 PINS
14 PINS
14 PINS
14 PINS
RθJ Junction-to-ambient thermal
A
113
86
80
76
95
—
—
°C/W
°C/W
resistance(2)(3)
RθJ
C(to
Junction-to-case (top) thermal
—
—
—
—
—
15.05
14.65
resistance(2)(3)
p)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with MIL-STD-883.
Copyright © 1978–2015, Texas Instruments Incorporated
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TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
www.ti.com
6.6 Thermal Information - 20 Pins
TL06xx
FK (LCCC)
20 PINS
—
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top) Junction-to-case (top) thermal resistance(4)(5)
Junction-to-ambient thermal resistance(2)(3)
°C/W
°C/W
5.61
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(5) The package thermal impedance is calculated in accordance with MIL-STD-883.
6.7 Electrical Characteristics for TL06xC and TL06xxC
VCC± = ±15 V (unless otherwise noted)
TL061AC, TL062AC,
TL061C, TL062C, TL064C
TEST CONDITIONS(1)
UNIT
TL064AC
PARAMETER
MIN
TYP
MAX
15
MIN
TYP
MAX
6
TA = 25°C
3
3
VIO
αVIO
IIO
Input offset voltage
VO = 0, RS = 50 Ω
mV
TA = Full range
20
7.5
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω, TA = Full range
10
5
10
5
μV/°C
TA = 25°C
VO = 0
200
5
100
3
pA
nA
pA
nA
Input offset current
Input bias current(2)
TA = Full range
TA = 25°C
VO = 0
30
400
10
30
200
7
IIB
TA = Full range
–12
to
15
–12
to
15
Common-mode input
voltage range
VICR
TA = 25°C
±11
±11
V
RL = 10 kΩ, TA = 25°C
±10
±10
3
±13.5
6
±10
±10
4
±13.5
6
Maximum peak output
voltage swing
VOM
V
RL ≥ 10 kΩ, TA = Full range
TA = 25°C
Large-signal differential
voltage amplification
VO = ±10 V,
L ≥ 2 kΩ
AVD
V/mV
R
TA = Full range
3
4
B1
ri
Unity-gain bandwidth
Input resistance
RL = 10 kΩ, TA = 25°C
1
1
MHz
1012
1012
TA = 25°C
Ω
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω, TA = 25°C
CMRR
kSVR
70
70
86
95
6
80
80
86
95
6
dB
dB
Supply-voltage
rejection ratio
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω, TA = 25°C
(ΔVCC±/ΔVIO
)
Total power dissipation
(each amplifier)
PD
VO = 0, No load, TA = 25°C
7.5
7.5
mW
Supply current
(each amplifier)
ICC
VO = 0, No load, TA = 25°C
AVD = 100, TA = 25°C
200
120
250
200
120
250
µA
dB
VO1/VO2 Crosstalk attenuation
(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full
range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.
(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
6
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Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B
TL061, TL061A, TL061B
TL062, TL062A, TL062B, TL064, TL064A, TL064B
www.ti.com
SLOS078L –NOVEMBER 1978–REVISED MAY 2015
6.8 Electrical Characteristics for TL06xxC and TL06xI
VCC± = ±15 V (unless otherwise noted)
TL061BC, TL062BC,
TL061I, TL062I, TL064I
PARAMETER
TEST CONDITIONS(1)
UNIT
TL064BC
MIN
TYP
MAX
MIN
TYP
MAX
TA = 25°C
2
3
5
3
6
9
VIO
αVIO
IIO
Input offset voltage
VO = 0, RS = 50 Ω
mV
TA = Full range
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω, TA = Full range
10
5
10
5
μV/°C
TA = 25°C
VO = 0
100
3
100
10
pA
nA
pA
nA
Input offset current
Input bias current(2)
TA = Full range
TA = 25°C
VO = 0
30
200
7
30
200
20
IIB
TA = Full range
–12
to
15
–12
to
15
Common-mode input
voltage range
VICR
TA = 25°C
±11
±11
V
RL = 10 kΩ, TA = 25°C
±10
±10
4
±13.5
6
±10
±10
4
±13.5
6
Maximum peak output
voltage swing
VOM
V
RL ≥ 10 kΩ, TA = Full range
TA = 25°C
Large-signal differential
voltage amplification
VO = ±10 V,
L ≥ 2 kΩ
AVD
V/mV
R
TA = Full range
4
4
B1
ri
Unity-gain bandwidth
Input resistance
RL = 10 kΩ, TA = 25°C
1
1
MHz
1012
1012
TA = 25°C
Ω
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω, TA = 25°C
CMRR
kSVR
80
80
86
95
6
80
80
86
95
6
dB
dB
Supply-voltage
rejection ratio
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω, TA = 25°C
(ΔVCC±/ΔVIO
)
Total power dissipation
(each amplifier)
PD
VO = 0, No load, TA = 25°C
7.5
7.5
mW
Supply current
(each amplifier)
ICC
VO = 0, No load, TA = 25°C
AVD = 100, TA = 25°C
200
120
250
200
120
250
µA
dB
VO1/VO2 Crosstalk attenuation
(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full
range for TA is 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.
(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
6.9 Electrical Characteristics for TL06xM and TL064M
VCC± = ±15 V (unless otherwise noted)
TL061M, TL062M
TL064M
TYP
3
PARAMETER
TEST CONDITIONS(1)
UNIT
MIN
TYP
MAX
MIN
MAX
TA = 25°C
3
6
9
VIO
Input offset voltage
VO = 0, RS = 50 Ω
mV
TA = –55°C to
125°C
9
15
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω,
TA = –55°C to 125°C
αVIO
10
5
10
5
μV/°C
TA = 25°C
TA = –55°C
TA = 125°C
TA = 25°C
TA = –55°C
TA = 125°C
100
20(2)
20
100
20(2)
20
pA
IIO
Input offset current
Input bias current(3)
VO = 0
nA
pA
nA
30
200
50(2)
50
30
200
50(2)
50
IIB
VO = 0
–12
to
15
–12
to
15
Common-mode input
voltage range
VICR
TA = 25°C
±11
±11
V
(1) All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified.
(2) This parameter is not production tested.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
Copyright © 1978–2015, Texas Instruments Incorporated
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TL061, TL061A, TL061B
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SLOS078L –NOVEMBER 1978–REVISED MAY 2015
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Electrical Characteristics for TL06xM and TL064M (continued)
VCC± = ±15 V (unless otherwise noted)
TL061M, TL062M
TL064M
TYP
PARAMETER
TEST CONDITIONS(1)
UNIT
MIN
±10
±10
4
TYP
MAX
MIN
±10
±10
4
MAX
RL = 10 kΩ, TA = 25°C
±13.5
±13.5
Maximum peak output
voltage swing
VOM
V
R
L ≥ 10 kΩ, TA = –55°C to 125°C
TA = 25°C
6
6
Large-signal differential
voltage amplification
VO = ±10 V,
L ≥ 2 kΩ
AVD
V/mV
TA = –55°C to
125°C
R
4
4
B1
ri
Unity-gain bandwidth
Input resistance
RL = 10 kΩ, TA = 25°C
MHz
1012
86
1012
86
TA = 25°C
Ω
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω, TA = 25°C
CMRR
kSVR
80
80
80
80
dB
dB
Supply-voltage
rejection ratio
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω, TA = 25°C
95
6
95
6
(ΔVCC±/ΔVIO
)
Total power dissipation
(each amplifier)
PD
VO = 0, No load, TA = 25°C
7.5
7.5
mW
Supply current
(each amplifier)
ICC
VO = 0, No load, TA = 25°C
AVD = 100, TA = 25°C
200
120
250
200
120
250
µA
dB
VO1/VO2 Crosstalk attenuation
6.10 Operating Characteristics
VCC± = ±15 V, TA= 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V/μs
μs
VI = 10 V,
RL = 10 kΩ,
CL = 100 pF,
see Figure 16
SR
tr
Slew rate at unity gain(1)
1.5
3.5
Rise-time
0.2
10%
42
VI = 20 V,
RL = 10 kΩ,
CL = 100 pF,
see Figure 16
Overshoot factor
Vn
Equivalent input noise voltage
RS = 20 Ω
f = 1 kHz
nV/√Hz
(1) Slew rate at –55°C to 125°C is 0.7 V/μs min.
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6.11 Typical Characteristics
Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the
various devices.
Table 1. Table of Graphs
FIGURE
Maximum peak output voltage versus Supply voltage
Maximum peak output voltage versus Free-air temperature
Maximum peak output voltage versus Load resistance
Maximum peak output voltage versus Frequency
Differential voltage amplification versus Free-air temperature
Large-signal differential voltage amplification versus Frequency
Phase shift versus Frequency
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 11
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Supply current versus Supply voltage
Supply current versus Free-air temperature
Total power dissipation versus Free-air temperature
Common-mode rejection ratio versus Free-air temperature
Normalized unity-gain bandwidth versus Free-air temperature
Normalized slew rate versus Free-air temperature
Normalized phase shift versus Free-air temperature
Input bias current versus Free-air temperature
Voltage-follower large-signal pulse response versus Time
Output voltage versus Elapsed time
Equivalent input noise voltage versus Frequency
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15
12.5
10
15
R
T
= 10 kΩ
= 25°C
L
12.5
10
A
See Figure 2
7.5
5
7.5
5
2.5
0
2.5
0
V
=
= 10 kΩ
15 V
CC
R
L
See Figure 2
0
2
4
6
8
10
12
14
16
−75 −50 −25
0
25
50
75
100 125
|V
CC
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 1. Maximum Peak Output Voltage vs Supply Voltage
Figure 2. Maximum Peak Output Voltage vs Free-Air
Temperature
15
V
CC
=
15 V
V
T
=
15 V
CC
R
T
= 10 kΩ
= 25°C
L
= 25°C
A
A
12.5
10
12.5
10
See Figure 2
See Figure 2
V
CC
=
12 V
7.5
5
7.5
5
V
CC
=
5 V
2.5
0
2.5
0
1 k
10 k
100 k
1 M
10 M
100
200
400 700 1 k
2 k
4 k 7 k 10 k
f − Frequency − Hz
R
− Load Resistance − Ω
L
Figure 4. Maximum Peak Output Voltage vs Frequency
Figure 3. Maximum Peak Output Voltage vs Load
Resistance
100
10
V
=
15 V
CC
V
=
15 V
CC
R
= 10 kΩ
L
R
R
T
= 0
7
4
ext
0°
= 10 kΩ
= 25°C
10
1
L
A
Phase Shift
(right scale)
45°
90°
135°
180°
0.1
2
A
VD
(left scale)
0.01
0.001
1
1
10
100
1 k
10 k 100 k 1 M 10 M
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 5. Differential Voltage Amplification vs Free-Air
Temperature
Figure 6. Large-Signal Differential Voltage Amplification and
Phase Shift vs Frequency
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250
200
250
T
= 25°C
A
No Signal
No Load
200
150
100
150
100
50
50
V
= 15 V
CC
No Signal
No Load
0
0
−75
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
|V
CC
| − Supply Voltage − V
Figure 8. Supply Current vs Free-Air Temperature
Figure 7. Supply Current vs Supply Voltage
87
30
V
CC
=
15 V
R
= 10 kΩ
L
86
85
84
83
25
TL064
V
= 15 V
CC
No Signal
20
15
No Load
TL062
TL061
10
5
82
81
0
−75 −50 −25
0
25
50
75 100 125
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 10. All Except TL06_C Common-Mode Rejection
Ratio vs Free-Air Temperature
Figure 9. Total Power Dissipation vs Free-Air Temperature
100
1.03
1.02
1.3
1.2
V
CC
= 15 V
40
Unity-Gain Bandwidth
(left scale)
Phase Shift
(right scale)
10
4
1.01
1.1
1
Slew Rate
(left scale)
1
1
0.4
0.99
0.9
0.1
V
R
=
15 V
CC
0.98
0.97
0.8
0.7
0.04
= 10 kΩ
L
f = B1 for Phase Shift
0.01
−50
−25
0
− Free-Air Temperature − °C
A
25
50
75
100
125
−75 −50 −25
0
25
50
75
100 125
T
T
A
− Free-Air Temperature − °C
Figure 12. Input Bias Current vs Free-Air Temperature
Figure 11. Normalized Unity-Gain Bandwidth, Slew Rate,
and Phase Shift vs Free-Air Temperature
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6
28
24
20
Input
Overshoot
4
2
16
12
8
0
Output
−2
V
CC
= 15 V
4
R
C
T
= 10 kΩ
= 100 pF
= 25°C
10%
L
L
V
= 15 V
−4
−6
CC
0
R
T
= 10 kΩ
= 25°C
L
A
t
r
A
−4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
2
4
6
8
10
t − Elapsed Time − µs
t − Time − µs
Figure 14. Output Voltage vs Elapsed Time
Figure 13. Voltage-Follower Large-Signal Pulse Response
vs Time
100
V
= 15 V
CC
S
R
= 20 Ω
90
T
A
= 25°C
80
70
60
50
40
30
20
10
0
10
40 100
400 1 k
4 k 10 k
40 k 100 k
f − Frequency − Hz
Figure 15. Equivalent Input Noise Voltage vs Frequency
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7 Parameter Measurement Information
−
+
OUT
V
I
R = 2 kΩ
L
C = 100 pF
L
Figure 16. Unity-Gain Amplifier
10 kΩ
1 kΩ
−
+
V
I
OUT
R
L
C = 100 pF
L
Figure 17. Gain-of-10 Inverting Amplifier
−
IN−
TL061
+
OUT
N2
IN+
N1
100 kΩ
1.5 kΩ
V
CC−
Figure 18. Input Offset-Voltage Null Circuit
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8 Detailed Description
8.1 Overview
The JFET-input operational amplifiers of the TL06x series are designed as low-power versions of the TL08x
series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset and
input bias currents. The TL06x series features the same terminal assignments as the TL07x and TL08x series.
Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar
transistors in an integrated circuit.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for
operation from −40°C to 85°C, and the M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
8.2 Functional Block Diagram
V
CC+
IN+
50 Ω
IN−
100 Ω
C1
OFFSET N1
OFFSET N2
OUT
V
CC−
TL061 Only
C1 = 10 pF on TL061, TL062, and TL064
Component values shown are nominal.
8.3 Feature Description
8.3.1 Common-Mode Rejection Ratio
The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted
input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to
the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers
are designed to have it as high as possible. The CMRR of this device is 86 dB.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. These devices have a 3.5-V/μs slew rate.
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8.4 Device Functional Modes
These devices are powered on when the supply is connected. This device can be operated as a single supply
operational amplifier or dual supply amplifier depending on the application.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TL06x series of operational amplifiers can be used in countless applications. The few applications in this
section show principles used in all applications of these parts.
9.2 Typical Applications
9.2.1 Inverting Amplifier Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes
negative voltages positive.
RF
Vsup+
RI
VOUT
+
VIN
Vsup-
Figure 19. Schematic for Inverting Amplifier Application
9.2.1.1 Design Requirements
The supply voltage must be chosen such that it is larger than the input voltage range and output range. For
instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to
accommodate this application.
9.2.1.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
(1)
(2)
Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw
too much current. This example will choose 10 kΩ for RI which means 36 kΩ will be used for RF. This was
determined by Equation 3.
(3)
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Typical Applications (continued)
9.2.1.3 Application Curve
2
1.5
1
VIN
VOUT
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 20. Input and Output Voltages of the Inverting Amplifier
9.3 System Examples
9.3.1 General Applications
R
= 100 kΩ
V
CC+
F
−
10 kΩ
0.1%
10 kΩ
0.1%
TL064
+
15 V
100 kΩ
V
CC+
Input A
3.3 kΩ
Output
−
−
V
CC−
TL061
+
Output
TL064
+
100 kΩ
1 kΩ
C
= 3.3 µF
F
V
CC+
1 MΩ
V
CC+
V
−15 V
CC−
−
+
Input B
+
100 kΩ
TL064
TL064
100 kΩ
10 kΩ
0.1%
10 kΩ
0.1%
3.3 kΩ
−
9.1 kΩ
1
V
CC−
V
CC−
f =
2π ´RF ´CF
Figure 21. Instrumentation Amplifier
Figure 22. 0.5-Hz Square-Wave Oscillator
V
V
CC+
CC+
CC+
−
CC+
1 MΩ
Output A
Output B
Output C
TL064
+
−
V
CC+
−
TL061
+
R1
C3
V
Input
Output
1 µF
−
TL064
+
R2
Input
TL064
+
V
CC−
100 kΩ
100 kΩ
V
CC+
V
−
R1= R2 = 2´R3 = 1.5 MΩ
100 µF
R3
C2
100 kΩ
TL064
+
C3
C1
C1= C2 =
= 110 pF
2
1
fO
=
= 1 kHz
2π ´R1´C1
Figure 23. High-Q Notch Filter
Figure 24. Audio-Distribution Amplifier
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System Examples (continued)
15 V
V
CC+
10 kΩ
10 kΩ
10 kΩ
0.1 µF
10 kΩ
10 kΩ
+
1 MΩ
−
TIL601
100 pF
Output
TL061
10 kΩ
TL061
+
Output
−
50 Ω
10 kΩ
N2
10 kΩ
5 kΩ
N1
10 kΩ
0.1 µF
250 kΩ
−15 V
Figure 25. Low-Level Light Detector Preamplifier
Figure 26. AC Amplifier
10 kΩ
100 kΩ
1 kΩ
IN+
+
0.1 µF
47 kΩ
0.06 µF
0.06 µF
1 µF
TL062
−
Output
+
TL061
−
10 kΩ
1.2 MΩ
100 kΩ
100 kΩ
1 kΩ
0.002 µF
50 kΩ
2.7 kΩ
270 Ω
10 kΩ
100 kΩ
0.003 µF 0.001 µF
100 kΩ
+
50 kΩ
0.02 µF
20 µF
1 kΩ
100 kΩ
−
TL062
+
IN−
Figure 27. Microphone Preamplifier With Tone
Control
Figure 28. Instrumentation Amplifier
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System Examples (continued)
IC PREAMPLIFIER RESPONSE CHARACTERISTICS
25
20
Max Bass
Max
Treble
V
T
=
15 V
CC
15
= 25°C
A
10
5
0
−5
−10
−15
−20
−25
Min
Min Bass
20 40
Treble
100 200 400
1 k 2 k 4 k 10 k 20 k
f − Frequency − Hz
220 kΩ
0.00375 µF
0.003 µF
10 kΩ
0.03 µF
0.01 µF
27 kΩ
MIN
MIN
100 kΩ
100 kΩ
Bass
MAX
V
+
V
CC+
CC+
Treble
MAX
10 kΩ 3.3 kΩ
+
100 Ω
Input
0.03 µF
1 µF
TL062
−
TL062
−
Output
V
CC−
V
CC−
0.003 µF
100 Ω
10 kΩ
Balance
10 pF
10 pF
+
75 µF
5 kΩ
Gain
47 kΩ
+
68 kΩ
50 pF
47 µF
Figure 29. IC Preamplifier
10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single supply, or outside the range of ±18 V for
a dual supply can permanently damage the device (see the Absolute Maximum
Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Examples.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Examples
RIN
RG
VIN
+
VOUT
RF
Figure 30. Operational Amplifier Schematic for Noninverting Configuration
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
VS+
NC
IN1í
IN1+
VCCí
NC
VCC+
OUT
NC
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS-
(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 31. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Circuit Board Layout Techniques, SLOA089
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TL061
TL061A
TL061B
TL062
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
TL062A
TL062B
TL064
TL064A
TL064B
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
81023022A
8102302PA
81023032A
8102303CA
8102303DA
TL061ACD
TL061ACDE4
TL061ACDR
TL061ACP
TL061BCP
TL061BCPE4
TL061CD
ACTIVE
LCCC
CDIP
LCCC
CDIP
CFP
FK
JG
FK
J
20
8
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
0 to 70
81023022A
TL062MFKB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
1
SNPB
POST-PLATE
SNPB
8102302PA
TL062M
20
14
14
8
1
81023032A
TL064MFKB
1
8102303CA
TL064MJB
W
D
1
Call TI
8102303DA
TL064MWB
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
SOIC
SOIC
PDIP
SO
75
75
2500
50
50
50
75
2500
50
2000
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
061AC
D
8
Green (RoHS
& no Sb/Br)
0 to 70
061AC
D
8
Green (RoHS
& no Sb/Br)
0 to 70
061AC
P
8
Green (RoHS
& no Sb/Br)
0 to 70
TL061ACP
TL061BCP
TL061BCP
TL061C
TL061C
TL061CP
T061
P
8
Green (RoHS
& no Sb/Br)
0 to 70
P
8
Green (RoHS
& no Sb/Br)
0 to 70
D
8
Green (RoHS
& no Sb/Br)
0 to 70
TL061CDR
TL061CP
D
8
Green (RoHS
& no Sb/Br)
0 to 70
P
8
Green (RoHS
& no Sb/Br)
0 to 70
TL061CPSR
TL061ID
PS
D
8
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
8
Green (RoHS
& no Sb/Br)
-40 to 85
TL061I
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
2500
50
(1)
(2)
(3)
(4/5)
(6)
TL061IDR
TL061IDRG4
TL061IP
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL061I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL061I
P
Green (RoHS
& no Sb/Br)
TL061IP
TL061IP
062AC
TL061IPE4
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
TL062ACD
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TL062ACDE4
TL062ACDR
TL062ACDRE4
TL062ACDRG4
TL062ACP
D
75
Green (RoHS
& no Sb/Br)
062AC
D
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
062AC
D
Green (RoHS
& no Sb/Br)
062AC
D
Green (RoHS
& no Sb/Br)
062AC
P
Green (RoHS
& no Sb/Br)
TL062ACP
T062A
TL062ACPSR
TL062ACPSRG4
TL062BCD
PS
PS
D
2000
2000
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SO
Green (RoHS
& no Sb/Br)
T062A
SOIC
SOIC
SOIC
PDIP
PDIP
Green (RoHS
& no Sb/Br)
062BC
TL062BCDG4
TL062BCDR
TL062BCP
D
75
Green (RoHS
& no Sb/Br)
062BC
D
2500
50
Green (RoHS
& no Sb/Br)
062BC
P
Green (RoHS
& no Sb/Br)
TL062BCP
TL062BCP
TL062BCPE4
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL062CD
TL062CDE4
TL062CDR
TL062CDRE4
TL062CDRG4
TL062CP
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TL062C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL062C
TL062C
TL062C
TL062C
TL062CP
TL062CP
T062
D
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Green (RoHS
& no Sb/Br)
TL062CPE4
TL062CPS
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
PS
PS
PW
PW
PW
PW
D
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TL062CPSR
TL062CPW
TL062CPWG4
TL062CPWR
TL062CPWRG4
TL062ID
SO
2000
150
Green (RoHS
& no Sb/Br)
T062
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
T062
150
Green (RoHS
& no Sb/Br)
T062
2000
2000
75
Green (RoHS
& no Sb/Br)
T062
Green (RoHS
& no Sb/Br)
T062
Green (RoHS
& no Sb/Br)
TL062I
TL062I
TL062I
TL062I
TL062IDG4
TL062IDR
D
75
Green (RoHS
& no Sb/Br)
D
2500
2500
Green (RoHS
& no Sb/Br)
TL062IDRG4
D
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL062IP
TL062IPE4
ACTIVE
PDIP
PDIP
P
8
8
50
Green (RoHS
& no Sb/Br)
NIPDAU
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
TL062IP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
P
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
TL062IP
Z062
TL062IPWR
TL062IPWRG4
TL062MFKB
TSSOP
TSSOP
LCCC
PW
PW
FK
8
2000
2000
1
Green (RoHS
& no Sb/Br)
8
Green (RoHS
& no Sb/Br)
NIPDAU
Z062
20
TBD
POST-PLATE
81023022A
TL062MFKB
TL062MJG
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL062MJG
TL062MJGB
8102302PA
TL062M
TL064ACD
TL064ACDR
TL064ACDRE4
TL064ACN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
D
D
N
D
D
D
N
N
D
D
14
14
14
14
14
14
14
14
14
14
14
50
2500
2500
25
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL064AC
TL064AC
TL064AC
TL064ACN
TL064BC
TL064BC
TL064BC
TL064BCN
TL064BCN
TL064C
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL064BCD
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TL064BCDG4
TL064BCDR
TL064BCN
50
Green (RoHS
& no Sb/Br)
2500
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL064BCNE4
TL064CD
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TL064CDE4
50
Green (RoHS
& no Sb/Br)
TL064C
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
2500
25
(1)
(2)
(3)
(4/5)
(6)
TL064CDR
TL064CDRE4
TL064CN
ACTIVE
SOIC
SOIC
PDIP
SO
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
20
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
TL064C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU | SN
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
POST-PLATE
TL064C
TL064CN
TL064
N
Green (RoHS
& no Sb/Br)
0 to 70
TL064CNSR
TL064CPW
TL064CPWE4
TL064CPWG4
TL064CPWR
TL064ID
NS
PW
PW
PW
PW
D
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
Green (RoHS
& no Sb/Br)
0 to 70
T064
90
Green (RoHS
& no Sb/Br)
0 to 70
T064
90
Green (RoHS
& no Sb/Br)
0 to 70
T064
2000
50
Green (RoHS
& no Sb/Br)
0 to 70
T064
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
TL064I
TL064I
TL064I
TL064I
TL064IN
TL064IN
TL064I
TL064I
Z064
TL064IDG4
TL064IDR
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
25
Green (RoHS
& no Sb/Br)
TL064IDRG4
TL064IN
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TL064INE4
TL064INS
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
NS
NS
PW
FK
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TL064INSR
TL064IPWR
TL064MFKB
SO
2000
2000
1
Green (RoHS
& no Sb/Br)
TSSOP
LCCC
Green (RoHS
& no Sb/Br)
TBD
81023032A
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL064MFKB
TL064MJ
ACTIVE
ACTIVE
CDIP
CDIP
J
J
14
14
1
1
TBD
TBD
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL064MJ
TL064MJB
8102303CA
TL064MJB
TL064MWB
ACTIVE
CFP
W
14
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
8102303DA
TL064MWB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL062, TL062M, TL064, TL064M :
Catalog: TL062, TL064
•
Military: TL062M, TL064M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL061ACDR
TL061CDR
TL061CDR
TL061IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
TSSOP
SOIC
SOIC
TSSOP
SOIC
SOIC
SOIC
TSSOP
D
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2000
2500
2500
2000
2500
2500
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
16.4
16.4
12.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
7.0
7.0
6.4
6.4
7.0
6.5
6.5
6.5
6.9
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
3.6
3.6
5.2
5.2
3.6
9.0
9.0
9.0
5.6
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
1.6
1.6
2.1
2.1
1.6
2.1
2.1
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
8
D
8
TL061IDR
D
8
TL062ACDR
TL062BCDR
TL062CDR
TL062CDR
TL062CPWR
TL062CPWRG4
TL062IDR
D
8
D
8
D
8
D
8
PW
PW
D
8
8
8
TL062IDR
D
8
TL062IPWR
TL064ACDR
TL064BCDR
TL064CDR
TL064CPWR
PW
D
8
14
14
14
14
D
D
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL064IDR
TL064IDRG4
TL064INSR
TL064IPWR
SOIC
SOIC
SO
D
D
14
14
14
14
2500
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
12.4
6.5
6.5
8.2
6.9
9.0
9.0
2.1
2.1
2.5
1.6
8.0
8.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
NS
PW
10.5
5.6
12.0
8.0
TSSOP
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL061ACDR
TL061CDR
TL061CDR
TL061IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
TSSOP
SOIC
SOIC
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2000
2500
2500
340.5
340.5
367.0
340.5
367.0
340.5
340.5
340.5
367.0
367.0
367.0
367.0
340.5
338.1
338.1
367.0
338.1
367.0
338.1
338.1
338.1
367.0
367.0
367.0
367.0
338.1
20.6
20.6
35.0
20.6
35.0
20.6
20.6
20.6
35.0
35.0
35.0
35.0
20.6
D
D
TL061IDR
D
TL062ACDR
TL062BCDR
TL062CDR
TL062CDR
TL062CPWR
TL062CPWRG4
TL062IDR
D
D
D
D
PW
PW
D
TL062IDR
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL062IPWR
TL064ACDR
TL064BCDR
TL064CDR
TL064CPWR
TL064IDR
TSSOP
SOIC
SOIC
SOIC
TSSOP
SOIC
SOIC
SO
PW
D
8
2000
2500
2500
2500
2000
2500
2500
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
38.0
38.0
38.0
35.0
38.0
38.0
38.0
35.0
14
14
14
14
14
14
14
14
D
D
PW
D
TL064IDRG4
TL064INSR
TL064IPWR
D
NS
PW
TSSOP
Pack Materials-Page 3
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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