TL07XX [TI]
TL07xx Low-Noise JFET-Input Operational Amplifiers;
| 型号： | TL07XX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TL07xx Low-Noise JFET-Input Operational Amplifiers |
| 文件： | 总69页 (文件大小：2872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
TL07xx Low-Noise JFET-Input Operational Amplifiers
1 Features
3 Description
The TL07xx JFET-input operational amplifiers
1
•
•
Low Power Consumption
incorporate well-matched, high-voltage JFET and
bipolar transistors in a monolithic integrated circuit.
The devices feature high slew rates, low-input bias
and offset currents, and low offset-voltage
temperature coefficient. The low harmonic distortion
and low noise make the TL07x series ideally suited
for high-fidelity and audio pre-amplifier applications.
The TL071 device has offset pins to support external
input offset correction.
Wide Common-Mode and Differential Voltage
Ranges
•
•
•
•
Low Input Bias and Offset Currents
Output Short-Circuit Protection
Low Total Harmonic Distortion: 0.003% (Typical)
Low Noise
Vn = 18 nV/√Hz (Typical) at f = 1 kHz
•
•
•
•
•
High-Input Impedance: JFET Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
8.65 mm × 3.91 mm
4.90 mm x 3.90 mm
9.59 mm x 6.67 mm
19.56 mm × 6.92 mm
9.59 mm x 6.35 mm
6.20 mm x 5.30 mm
19.3 mm × 6.35 mm
10.30 mm × 5.30 mm
4.40 mm x 3.00 mm
5.00 mm × 4.40 mm
SOIC (14)
TL07xxD
High Slew Rate: 13 V/μs (Typical)
SOIC (8)
CDIP (8)
CDIP (14)
PDIP (8)
SO (8)
Common-Mode Input Voltage Range
Includes VCC+
TL07xxJG
TL074xJ
TL07xxP
2 Applications
TL07xxPS
TL074xN
TL074xNS
TL07xxPW
TL074xPW
•
•
Motor Integrated Systems: UPS
PDIP (14)
SO (14)
Drives and Control Solutions: AC Inverter and VF
Drives
TSSOP (8)
TSSOP (14)
•
•
•
•
Renewables: Solar Inverters
Pro Audio Mixers
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DLP Front Projection System
Oscilloscopes
Logic Symbols
TL071
TL072 (each amplifier)
TL074 (each amplifier)
OFFSET N1
IN+
+
−
IN+
IN−
+
−
OUT
OUT
IN−
Copyright © 2017, Texas Instruments Incorporated
OFFSET N2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
www.ti.com
Table of Contents
TL07xBC, TL07xI ..................................................... 19
6.18 Typical Characteristics.......................................... 20
6.1 Parameter Measurement Information ..................... 25
Detailed Description ............................................ 26
7.1 Overview ................................................................. 26
7.2 Functional Block Diagram ....................................... 26
7.3 Feature Description................................................. 27
7.4 Device Functional Modes........................................ 27
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application .................................................. 28
8.3 Unity Gain Buffer..................................................... 29
8.4 System Examples ................................................... 30
Power Supply Recommendations...................... 32
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications....................................................... 10
6.1 Absolute Maximum Ratings .................................... 10
6.2 ESD Ratings............................................................ 10
6.3 Recommended Operating Conditions..................... 10
6.4 Thermal Information: TL071x.................................. 11
6.5 Thermal Information: TL072x.................................. 11
6.6 Thermal Information: TL072x (cont.)....................... 11
6.7 Thermal Information: TL074x.................................. 11
6.8 Thermal Information: TL074x (cont)........................ 12
6.9 Thermal Information: TL074x (cont)........................ 12
7
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1 Documentation Support ........................................ 34
11.2 Related Links ........................................................ 34
11.3 Community Resources.......................................... 34
11.4 Trademarks........................................................... 34
11.5 Electrostatic Discharge Caution............................ 34
11.6 Glossary................................................................ 34
6.10 Electrical Characteristics: TL071C, TL072C,
TL074C .................................................................... 13
6.11 Electrical Characteristics: TL071AC, TL072AC,
TL074AC.................................................................. 14
6.12 Electrical Characteristics: TL071BC, TL072BC,
TL074BC.................................................................. 15
6.13 Electrical Characteristics: TL071I, TL072I,
TL074I...................................................................... 16
6.14 Electrical Characteristics: TL071M, TL072M ........ 17
6.15 Electrical Characteristics: TL074M ....................... 18
6.16 Switching Characteristics: TL07xM....................... 19
6.17 Switching Characteristics: TL07xC, TL07xAC,
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (February 2014) to Revision N
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated data sheet text to latest documentation and translation standards ......................................................................... 1
Added TL072M and TL074M devices to data sheet ............................................................................................................. 1
Rewrote text in Description section ....................................................................................................................................... 1
Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table .................................................. 1
Deleted 20-pin LCCC package from Device Information table ............................................................................................. 1
Added 2017 copyright statement to front page schematic ..................................................................................................... 1
Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ........................ 4
Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................................... 5
Deleted differential input voltage parameter from Absolute Maximum Ratings table ......................................................... 10
Deleted table notes from Absolute Maximum Ratings table ............................................................................................... 10
Added new table note to Absolute Maximum Ratings table ................................................................................................ 10
Changed minimum supply voltage value from –18 V to –0.3 V in Absolute Maximum Ratings table ................................. 10
Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table ............................................... 10
Changed minimum input voltage value from –15 V to VCC– – 0.3 V in Absolute Maximum Ratings table........................... 10
Changed maximum input voltage from 15 V to VCC– + 36 V in Absolute Maximum Ratings table....................................... 10
Added input clamp current parameter to Absolute Maximum Ratings table ....................................................................... 10
Changed common-mode voltage maximum value from VCC+ – 4 V to VCC+ in the Recommended Operating
Conditions table.................................................................................................................................................................... 10
2
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Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
www.ti.com
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
Revision History (continued)
•
Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and
TL07xBC .............................................................................................................................................................................. 10
•
•
•
•
•
•
•
•
Added TL07xI operating free-air temperature minimum value of –40°C to Recommended Operating Conditions table ... 10
Added U (CFP) package thermal values to Thermal Information: TL072x (cont.) table ...................................................... 11
Added W (CFP) package thermal values to Thermal Information: TL074x (cont.) table ..................................................... 12
Added Figure 20 to Table 1 ................................................................................................................................................. 20
Added Figure 20 to Typical Characteristics section ............................................................................................................. 24
Added second Typical Application section application curves ............................................................................................ 29
Reformatted document references in Layout Guidelines section ........................................................................................ 32
Updated formatting of document reference in Related Documentation section .................................................................. 34
Changes from Revision L (February 2014) to Revision M
Page
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section ........................................................................................................................................................... 1
•
Moved Typical Characteristics into Specifications section. ................................................................................................. 20
Changes from Revision K (January 2014) to Revision L
Page
•
•
•
Moved Tstg to Handling Ratings table .................................................................................................................................. 10
Added Device and Documentation Support section............................................................................................................. 34
Added Mechanical, Packaging, and Orderable Information section..................................................................................... 34
Changes from Revision J (March 2005) to Revision K
Page
•
•
Updated document to new TI datasheet format - no specification changes. ......................................................................... 1
Added ESD warning ............................................................................................................................................................. 34
Copyright © 1978–2017, Texas Instruments Incorporated
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3
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
www.ti.com
5 Pin Configuration and Functions
TL071x D, P, and PS Package
8-Pin SOIC, PDIP, SO
Top View
OFFSET N1
INœ
1
2
3
4
8
7
6
5
NC
VCC+
IN+
OUT
VCCœ
OFFSET N2
Not to scale
NC- no internal connection
Pin Functions: TL071x
PIN
I/O
DESCRIPTION
NAME
IN–
NO.
2
I
Inverting input
IN+
3
I
Noninverting input
Do not connect
Input offset adjustment
Input offset adjustment
Output
NC
8
—
—
—
O
—
—
OFFSET N1
OFFSET N2
OUT
1
5
6
VCC–
VCC+
4
Power supply
7
Power supply
4
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Copyright © 1978–2017, Texas Instruments Incorporated
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
www.ti.com
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
TL072x D, JG, P, PS and PW Package
8-Pin SOIC, CDIP, PDIP, SO
Top View
1OUT
1INœ
1
2
3
4
8
7
6
5
VCC+
2OUT
2INœ
1IN+
VCCœ
2IN+
Not to scale
Pin Functions: TL072x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
2
I
I
Inverting input
Noninverting input
Output
1IN+
3
1OUT
2IN–
1
O
I
6
Inverting input
Noninverting input
Output
2IN+
5
I
2OUT
VCC–
VCC+
7
O
—
—
4
Power supply
Power supply
8
Copyright © 1978–2017, Texas Instruments Incorporated
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5
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
www.ti.com
TL072x U Package
10-Pin CFP
Top View
NC
1OUT
1INœ
1
2
3
4
5
10
9
NC
VCC+
2OUT
2INœ
2IN+
8
1IN+
7
VCCœ
6
Not to scale
NC- no internal connection
Pin Functions: TL072x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
3
I
I
Inverting input
1IN+
4
Noninverting input
Output
1OUT
2IN–
2
O
I
7
Inverting input
Noninverting input
Output
2IN+
6
8
I
2OUT
NC
O
—
—
—
1, 10
5
Do not connect
Power supply
Power supply
VCC–
VCC+
9
6
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Copyright © 1978–2017, Texas Instruments Incorporated
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
www.ti.com
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
TL072 FK Package
20-Pin LCCC
Top View
NC
1INœ
NC
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
1IN+
NC
2INœ
NC
Not to scale
NC- no internal connection
Pin Functions: TL072x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
5
I
I
Inverting input
Noninverting input
Output
1IN+
7
1OUT
2IN–
2
O
I
15
12
17
Inverting input
Noninverting input
Output
2IN+
I
2OUT
O
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
NC
—
Do not connect
VCC–
VCC+
10
20
—
—
Power supply
Power supply
Copyright © 1978–2017, Texas Instruments Incorporated
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7
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
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TL074 D, N, NS, PW, J, and W Packages
14-Pin SOIC, PDIP, SO, TSSOP, CDIP and CFP
Top View
1OUT
1INœ
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4INœ
1IN+
4IN+
VCC+
2IN+
VCCœ
3IN+
2INœ
3INœ
2OUT
8
3OUT
Not to scale
Pin Functions: TL074x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
2
I
I
Inverting input
1IN+
1OUT
2IN–
3
Noninverting input
Output
1
O
I
6
Inverting input
Noninverting input
Output
2IN+
2OUT
3IN–
5
I
7
O
I
9
Inverting input
Noninverting input
Output
3IN+
3OUT
4IN–
10
8
I
O
I
13
12
14
11
4
Inverting input
Noninverting input
Output
4IN+
4OUT
VCC–
VCC+
I
O
—
—
Power supply
Power supply
8
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Copyright © 1978–2017, Texas Instruments Incorporated
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
TL074 FK Package
20-Pin LCCC
Top View
1IN+
NC
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC+
NC
VCCœ
NC
2IN+
3IN+
Not to scale
NC- no internal connection
Pin Functions: TL074x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
3
I
I
Inverting input
Noninverting input
Output
1IN+
4
1OUT
2IN–
2
O
I
9
Inverting input
Noninverting input
Output
2IN+
8
I
2OUT
3IN–
10
13
14
12
19
18
20
O
I
Inverting input
Noninverting input
Output
3IN+
I
3OUT
4IN–
O
I
Inverting input
Noninverting input
Output
4IN+
I
4OUT
O
1, 5, 7, 11,
15, 17
NC
—
Do not connect
VCC–
VCC+
16
6
—
—
Power supply
Power supply
Copyright © 1978–2017, Texas Instruments Incorporated
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Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B TL072M TL074M
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B, TL072M, TL074M
SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
MAX
36
UNIT
V
VCC+ - VCC– Supply voltage
(2)
VI
Input voltage
VCC– – 0.3
VCC– + 36
–50
V
IIK
Input clamp current
mA
Duration of output short circuit(3)
Operating virtual junction temperature
Case temperature for 60 seconds - FK package
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds
Storage temperature
Unlimited
TJ
150
260
300
150
°C
°C
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Differential voltage only limited by input voltage.
(3) The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the dissipation
rating is not exceeded.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
15
UNIT
(1)
VCC+
VCC–
VCM
Supply voltage
Supply voltage
5
–5
V
V
V
(1)
–15
VCC+
125
125
85
Common-mode voltage
VCC– + 4
–55
TL07xM
TL08xQ
–40
TA
Operating free-air temperature
°C
TL07xI
–40
TL07xAC, TL07xBC, TL07xC
0
70
(1) VCC+ and VCC– are not required to be of equal magnitude, provided that the total VCC (VCC+ – VCC–) is between 10 V and 30 V.
10
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
6.4 Thermal Information: TL071x
TL071x
THERMAL METRIC(1)
D (SOIC)
8 PINS
97
P (PDIP)
8 PINS
85
PS (SO)
8 PINS
95
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
—
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: TL072x
TL072x
THERMAL METRIC(1)
D (SOIC)
8 PINS
97
JG (CDIP)
8 PINS
—
P (PDIP)
8 PINS
85
PS (SO)
8 PINS
95
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
—
15.05
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: TL072x (cont.)
TL072x
THERMAL METRIC(1)
PW (TSSOP)
U (CFP)
10 PINS
169.8
62.1
FK (LCCC)
UNIT
8 PINS
150
—
20 PINS
—
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
5.61
—
—
176.2
48.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
—
—
ψJB
—
144.1
5.4
—
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Thermal Information: TL074x
TL074x
THERMAL METRIC(1)
D (SOIC)
14 PINS
86
N (PDIP)
14 PINS
80
NS (SO)
14 PINS
76
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
—
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 1978–2017, Texas Instruments Incorporated
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
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6.8 Thermal Information: TL074x (cont).
TL074x
THERMAL METRIC(1)
J (CDIP)
PW (TSSOP)
W (CFP)
14 PINS
128.8
56.1
UNIT
14 PINS
—
14 PINS
113
—
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
14.5
—
—
127.6
29
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
—
—
ψJB
—
—
106.1
0.5
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.9 Thermal Information: TL074x (cont).
TL074x
THERMAL METRIC(1)
FK (LCCC)
20 PINS
—
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
5.61
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
12
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
6.10 Electrical Characteristics: TL071C, TL072C, TL074C
VCC± = ±15 V (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C
3
10
VO = 0
RS = 50 Ω
VIO
Input offset voltage
mV
13
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
10
pA
nA
pA
nA
IIO
Input offset current
VO = 0
TA = Full range
TA = 25°C
65
200
7
(3)
IIB
Input bias current
VO = 0
TA = Full range
Common-mode input voltage
range
VICR
TA = 25°C
±11 –12 to 15
V
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
TA = 25°C
±12
±12
±10
25
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL≥ 2 kΩ
AVD
V/mV
TA = Full range
15
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
TA = 25°C
3
1012
MHz
Ω
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
TA = 25°C
TA = 25°C
70
70
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply voltage rejection ratio
kSVR
(ΔVCC±/ΔVIO
)
Supply current (each
amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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6.11 Electrical Characteristics: TL071AC, TL072AC, TL074AC
VCC± = ±15 V (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C
3
6
mV
7.5
VO = 0
RS = 50 Ω
VIO
Input offset voltage
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
2
pA
nA
pA
nA
IIO
Input offset current
VO = 0
TA = Full range
TA = 25°C
65
200
7
(3)
IIB
Input bias current
VO = 0
TA = Full range
Common-mode input voltage
range
VICR
TA = 25°C
±11 –12 to 15
V
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
TA = 25°C
±12
±12
±10
50
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL≥ 2 kΩ
AVD
V/mV
TA = Full range
25
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
3
1012
MHz
TA = 25°C
Ω
VIC = VICR(min)
CMRR
Common-mode rejection ratio VO = 0
RS = 50 Ω
TA = 25°C
TA = 25°C
75
80
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
Supply-voltage rejection ratio
(ΔVCC± / ΔVIO
kSVR
)
RS = 50 Ω
Supply current
(each amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
14
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
6.12 Electrical Characteristics: TL071BC, TL072BC, TL074BC
VCC± = ±15 V (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C
2
3
VO = 0
RS = 50 Ω
VIO
Input offset voltage
mV
5
TA = Full range
Temperature coefficient of VO = 0
α
TA = Full range
18
5
µV/°C
input offset voltage
RS = 50 Ω
TA = 25°C
100
2
pA
nA
pA
nA
IIO
Input offset current
VO = 0
TA = Full range
TA = 25°C
65
200
7
(3)
IIB
Input bias current
VO = 0
TA = Full range
Common-mode input
voltage range
VICR
TA = 25°C
±11 –12 to 15
V
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
TA = 25°C
±12
±12
±10
50
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
AVD
V/mV
RL ≥ 2 kΩ
TA = Full range
25
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
TA = 25°C
3
1012
MHz
Ω
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
TA = 25°C
TA = 25°C
75
80
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
kSVR
ratio (ΔVCC±/ΔVIO
)
Supply current (each
amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5 mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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6.13 Electrical Characteristics: TL071I, TL072I, TL074I
VCC± = ±15 V (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C
3
6
VO = 0
RS = 50 Ω
VIO
Input offset voltage
mV
8
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
2
pA
nA
pA
nA
IIO
Input offset current
VO = 0
VO = 0
TA = Full range
TA = 25°C
65
200
7
(3)
IIB
Input bias current
TA = Full range
Common-mode input voltage
range
VICR
TA = 25°C
±11 –12 to 15
V
RL= 10 kΩ
TA = 25°C
±12
±12
±10
50
±13.5
Maximum peak output
voltage swing
VOM
R
L ≥ 10 kΩ
L ≥ 2 kΩ
V
TA = Full range
R
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
L ≥ 2 kΩ
AVD
V/mV
R
TA = Full range
25
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
TA = 25°C
3
1012
MHz
Ω
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
TA = 25°C
TA = 25°C
75
80
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection ratio
kSVR
(ΔVCC±/ΔVIO
)
Supply current (each
amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) TA = –40°C to 85°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
6.14 Electrical Characteristics: TL071M, TL072M
VCC± = ±15 V (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
3
6
9
VO = 0
RS = 50 Ω
VIO
αVIO
IIO
Input offset voltage
mV
TA = Full range
Temperature coefficient VO = 0
TA = Full range
18
5
μV/°C
of input offset voltage
RS = 50 Ω
TA = 25°C
100
20
pA
nA
pA
nA
Input offset current
VO = 0
TA = Full range
TA = 25°C
65
200
50
IIB
Input bias current
VO = 0
TA = Full range
Common-mode input
voltage range
VICR
TA = 25°C
±11 –12 to 15
V
RL = 10 kΩ
RL ≥ 10 kΩ
TA = 25°C
±12
±12
±10
35
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
RL ≥ 2 kΩ
TA = 25°C
200
Large-signal differential VO = ±10 V
AVD
V/mV
voltage amplification
RL ≥ 2 kΩ
TA = Full range
15
B1
ri
Unity-gain bandwidth
Input resistance
3
1012
MHz
Ω
VIC = VICR(min)
VO = 0
RS = 50 Ω
,
Common-mode rejection
ratio
CMRR
kSVR
TA = 25°C
TA = 25°C
80
80
86
86
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO
)
Supply current
(each amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2
Crosstalk attenuation
120
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be
used.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to +125°C.
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6.15 Electrical Characteristics: TL074M
VCC± = ±15 V (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C
3
9
VO = 0
RS = 50 Ω
VIO
αVIO
IIO
Input offset voltage
mV
15
TA = Full range
Temperature coefficient
of input offset voltage
VO = 0, RS = 50 Ω
TA = Full range
18
5
μV/°C
TA = 25°C
100
20
pA
nA
pA
nA
Input offset current
Input bias current
VO = 0
TA = Full range
TA = 25°C
65
200
20
IIB
VO = 0
TA = Full range
Common-mode input
voltage range
VICR
TA = 25°C
±11 –12 to 15
V
RL = 10 kΩ
RL ≥ 10 kΩ
TA = 25°C
±12
±12
±10
35
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
RL ≥ 2 kΩ
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
AVD
V/mV
RL ≥ 2 kΩ
TA = Full range
15
B1
ri
Unity-gain bandwidth
Input resistance
3
1012
MHz
Ω
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
kSVR
TA = 25°C
TA = 25°C
80
80
86
86
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO
)
Supply current
(each amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2
Crosstalk attenuation
120
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be
used .
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to +125°C.
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
6.16 Switching Characteristics: TL07xM
VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
RL = 2 kΩ
MIN
TYP
MAX
UNIT
V/μs
μs
VI = 10 V
CL = 100 pF
SR
tr
Slew rate at unity gain
5
13
See Figure 21
0.1
20%
18
VI = 20 V
CL = 100 pF
RL = 2 kΩ
See Figure 21
Rise-time overshoot factor
f = 1 kHz
nV/√Hz
μV
Equivalent input noise
voltage
Vn
In
RS = 20 Ω
f = 10 Hz to 10 kHz
f = 1 kHz
4
Equivalent input noise current RS = 20 Ω
0.01
pA/√Hz
VIrms = 6 V
AVD = 1
RS ≤ 1 kΩ
THD
Total harmonic distortion
RL ≥ 2 kΩ
0.003%
f = 1 kHz
6.17 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI
VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
RL = 2 kΩ
MIN
TYP
MAX
UNIT
V/μs
μs
VI = 10 V
CL = 100 pF
SR
tr
Slew rate at unity gain
8
13
See Figure 21
0.1
20%
18
VI = 20 V
CL = 100 pF
RL = 2 kΩ
See Figure 21
Rise-time overshoot factor
f = 1 kHz
nV/√Hz
μV
Equivalent input noise
voltage
Vn
In
RS = 20 Ω
f = 10 Hz to 10 kHz
f = 1 kHz
4
Equivalent input noise current RS = 20 Ω
0.01
pA/√Hz
VIrms = 6 V
AVD = 1
RS ≤ 1 kΩ
THD
Total harmonic distortion
RL ≥ 2 kΩ
0.003%
f = 1 kHz
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6.18 Typical Characteristics
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
Table 1. Typical Characteristics: Table of Graphs
FIGURE
IIB
Input bias current
versus free-air temperature
versus frequency
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 9
Figure 10
Figure 10
Figure 11
Figure 20
Figure 13
Figure 12
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
VOM
Maximum peak output voltage
versus free-air temperature
versus load resistance
versus supply voltage
versus free-air temperature
versus load resistance
versus frequency
Large signal differential voltage
amplification
AVD
Phase shift
Normalized unity-gain bandwidth
Normalized phase shift
Common-mode rejection ratio
Input offset voltage change
versus free-air temperature
versus free-air temperature
versus free-air temperature
versus common-mode voltage
versus free-air temperature
versus supply voltage
versus free-air temperature
versus free-air temperature
versus frequency
CMRR
ICC
PD
Supply current
Total power dissipation
Normalized slew rate
Vn
Equivalent input noise voltage
Total harmonic distortion
Large-signal pulse response
Output voltage
THD
versus frequency
versus time
VO
versus elapsed time
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
6.18.1 Typical Characteristics
100
15
V =
CC
15 V
10 V
5 V
R
= 10 kΩ
V
CC
=
15 V
L
T
= 25°C
See Figure 2
A
12.5
10
10
V
CC
=
7.5
5
1
V
CC
=
0.1
2.5
0
0.01
−75 −50 −25
0
25
50
75
100 125
100
1 k
10 k
100 k
1 M
10 M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 1. Input Bias Current vs Free-Air Temperature
Figure 2. Maximum Peak Output Voltage vs Frequency
15
R
= 2 kΩ
= 25°C
L
T
A
V
= 15 V
CC
12.5
10
7.5
5
See Figure 2
V
CC
= 10 V
V
CC
=
5 V
2.5
8
0
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
Figure 4. Maximum Peak Output Voltage vs Frequency
Figure 3. Maximum Peak Output Voltage vs Frequency
15
15
R
= 10 kΩ
= 2 kΩ
L
L
V
=
15 V
CC
T
= 25°C
See Figure 2
A
12.5
10
7.5
5
12.5
10
7.5
5
R
2.5
0
2.5
V
= 15 V
8
CC
8
See Figure 2
−75 −50 −25
− Free-Air Temperature − °C
0
0.1
0
25
50
75 100 125
0.2
0.4 0.7
R − Load Resistance − kΩ
L
1
2
4
7 10
T
A
Figure 5. Maximum Peak Output Voltage vs Free-Air
Temperature
Figure 6. Maximum Peak Output Voltage vs Load
Resistance
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Typical Characteristics (continued)
15
12.5
10
1000
R
T
A
= 10 kΩ
= 25°C
L
400
200
100
40
20
10
7.5
5
4
2
1
V
V
R
=
15 V
10 V
= 2 kΩ
CC
2.5
0
=
O
L
0
2
4
6
8
10
12
14
16
−75 −50 −25
0
25
50
75 100 125
|V
CC
| − Supply Voltage − V
T − Free-Air Temperature − °C
A
Figure 7. Maximum Peak Output Voltage vs Supply
Voltage
Figure 8. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
1.3
1.2
1.1
1
1.03
1.02
Unity-Gain Bandwidth
1.01
1
Phase Shift
0.99
0.98
0.97
0.9
0.8
0.7
V
=
15 V
CC
R = 2 kΩ
f = B for Phase Shift
L
1
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
Figure 10. Normalized Unity-Gain Bandwidth and Phase
Shift vs Free-Air Temperature
Figure 9. Large-Signal Differential Voltage Amplification
and Phase Shift vs Frequency
89
2
V
CC
=
15 V
T
A
= 25°C
1.8
1.6
1.4
1.2
1
R
= 10 kΩ
No Signal
No Load
L
88
87
86
85
84
83
0.8
0.6
0.4
0.2
0
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
|V
CC
| − Supply Voltage − V
Figure 11. Common-Mode Rejection Ratio vs Free-Air
Temperature
Figure 12. Supply Current Per Amplifier vs Supply Voltage
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Typical Characteristics (continued)
2
250
V
CC
= 15 V
V
CC
= 15 V
1.8
1.6
1.4
1.2
1
225
200
175
150
125
100
75
No Signal
No Load
No Signal
No Load
TL074
0.8
0.6
0.4
0.2
0
TL072
TL071
50
25
0
−75 −50 −25
0
25
50
75
100 125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature −°C
Figure 13. Supply Current Per Amplifier vs Free-Air
Temperature
Figure 14. Total Power Dissipation vs Free-Air
Temperature
50
V
CC
=
15 V
A
VD
= 10
Ω
R
T
= 20
= 25°C
S
40
30
20
10
0
A
10
40 100
400 1 k
4 k 10 k 40 k 100 k
f − Frequency − Hz
Figure 16. Equivalent Input Noise Voltage vs Frequency
Figure 15. Normalized Slew Rate vs Free-Air Temperature
1
6
V
CC
= 15 V
V
CC
=
15 V
R
C
T
= 2 kΩ
= 100 pF
= 25°C
A
= 1
L
L
VD
0.4
V
I(RMS)
= 6 V
4
2
T
A
= 25°C
A
Output
0.1
0.04
0
0.01
−2
−4
−6
Input
0.004
0.001
100
400
1 k
4 k 10 k
40 k 100 k
0
0.5
1
1.5
2
2.5
3
3.5
f − Frequency − Hz
t − Time −
µ
s
Figure 17. Total Harmonic Distortion vs Frequency
Figure 18. Voltage-Follower Large-Signal Pulse Response
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Typical Characteristics (continued)
10
8
VCCê = ê15 V
6
4
2
0
-2
-4
-6
-8
-10
-13 -11 -9 -7 -5 -3 -1
1
3
5
7
9
11 13 15 17
D003
VCM (V)
Figure 20. VIO vs VCM
Figure 19. Output Voltage vs Elapsed Time
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6.1 Parameter Measurement Information
−
+
OUT
V
I
C
= 100 pF
R
= 2 kΩ
L
L
Figure 21. Unity-Gain Amplifier
10 kΩ
1 kΩ
−
V
I
OUT
= 100 pF
+
C
R
L
L
Figure 22. Gain-of-10 Inverting Amplifier
Figure 23. Input Offset-Voltage Null Circuit
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
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7 Detailed Description
7.1 Overview
The JFET-input operational amplifiers in the TL07xx series are similar to the TL08x series, with low input bias
and offset currents, and a fast slew rate. The low harmonic distortion and low noise make the TL07xx series
ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high
input impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for
operation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to +125°C.
7.2 Functional Block Diagram
V
CC+
IN+
IN−
64 Ω
128 Ω
64 Ω
OUT
C1
18 pF
1080 Ω
1080 Ω
V
CC−
OFFSET
N1
OFFSET
N2
TL071 Only
All component values shown are nominal.
†
COMPONENT COUNT
COMPONENT
TYPE
TL071
TL072
TL074
Resistors
11
14
2
22
28
4
44
56
6
Transistors
JFET
Diodes
Capacitors
epi-FET
1
2
4
1
2
4
1
2
4
†
Includes bias and trim circuitry
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
7.3 Feature Description
7.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices
have a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when used in
audio signal applications.
7.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. These devices have a 13-V/μs slew rate.
7.4 Device Functional Modes
These devices are powered on when the supply is connected. These devices can be operated as a single-supply
operational amplifier or dual-supply amplifier depending on the application.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on
the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative voltages
positive.
8.2 Typical Application
RF
Vsup+
RI
VOUT
+
VIN
Vsup-
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Inverting Amplifier
8.2.1 Design Requirements
The supply voltage must be selected so the supply voltage is larger than the input voltage range and output
range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient
to accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
VOUT
A
V
=
VIN
1.8
(1)
(2)
A
V
=
= -3.6
-0.5
Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw
too much current. This example uses 10 kΩ for RI which means 36 kΩ is used for RF. This is determined by
Equation 3.
RF
AV = -
RI
(3)
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Typical Application (continued)
8.2.3 Application Curve
2
ëLb
1.5
1
ëhÜÇ
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Çime (ms)
1.5
2
Figure 25. Input and Output Voltages of the Inverting Amplifier
8.3 Unity Gain Buffer
U1 TL072
œ
+
+
VIN
VOUT
10 k
+
12
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Single-Supply Unity Gain Amplifier
8.3.1 Design Requirements
•
•
•
VCC must be within valid range per Recommended Operating Conditions. This example uses a value of 12 V
for VCC
Input voltage must be within the recommended common-mode range, as shown in Recommended Operating
Conditions. The valid common-mode range is 4 V to 12 V ( VCC– + 4 V to VCC+
Output is limited by output range, which is typically 1.5 V to 10.5 V, or VCC– + 1.5 V to VCC+ – 1.5 V.
.
.
8.3.2 Detailed Design Procedure
•
•
Avoid input voltage values below 1 V to prevent phase reversal where output goes high.
Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This
may cause instability in some second-order filter designs.
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Unity Gain Buffer (continued)
8.3.3 Application Curves
12
10
8
1.5
1
0.5
0
6
4
-0.5
-1
2
0
-1.5
0
2
4
6
8
10
12
0
2
4
6
8
10
12
VIN (V)
VIN (V)
D001
D002
Figure 27. Output Voltage vs Input Voltage
Figure 28. Gain vs Input Voltage
8.4 System Examples
Figure 29. 0.5-Hz Square-Wave Oscillator
V
CC+
–
R1
R2
Input
+
Output
V
C3
CC–
R1= R2 = 2R3 = 1.5 MW
R3
C3
C1
C1
C1= C2 =
= 110 pF
= 1kHz
2
1
fo =
2p R1C1
Figure 30. High-Q Notch Filter
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
System Examples (continued)
Figure 31. 100-kHz Quadrature Oscillator
Figure 32. AC Amplifier
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
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9 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a
dual-supply can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
10.2 Layout Example
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
VS+
NC
IN1Þ
IN1+
VCCÞ
NC
VCC+
OUT
NC
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS-
(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 33. Operational Amplifier Board Layout for Noninverting Configuration
RIN
VIN
+
VOUT
RG
RF
Figure 34. Operational Amplifier Schematic for Noninverting Configuration
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
Circuit Board Layout Techniques (SLOA089)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TL071
TL071A
TL071B
TL072
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Click here
TL072A
TL072B
TL072M
TL074
TL074A
TL074B
TL074M
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLOS080N –SEPTEMBER 1978–REVISED JULY 2017
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1978–2017, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
81023052A
8102305HA
8102305PA
ACTIVE
LCCC
CFP
FK
U
20
10
8
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
0 to 70
81023052A
TL072MFKB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
1
Call TI
SNPB
8102305HA
TL072M
CDIP
LCCC
CDIP
CFP
JG
FK
J
1
8102305PA
TL072M
81023062A
20
14
14
8
1
POST-PLATE
SNPB
81023062A
TL074MFKB
8102306CA
8102306DA
JM38510/11905BPA
M38510/11905BPA
TL071ACD
1
8102306CA
TL074MJB
W
JG
JG
D
1
Call TI
8102306DA
TL074MWB
CDIP
CDIP
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
1
SNPB
JM38510
/11905BPA
8
1
SNPB
JM38510
/11905BPA
8
75
75
2500
50
75
2500
50
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
071AC
TL071ACDG4
TL071ACDR
TL071ACP
D
8
Green (RoHS
& no Sb/Br)
0 to 70
071AC
D
8
Green (RoHS
& no Sb/Br)
0 to 70
071AC
P
8
Green (RoHS
& no Sb/Br)
0 to 70
TL071ACP
071BC
TL071BCD
D
8
Green (RoHS
& no Sb/Br)
0 to 70
TL071BCDR
TL071BCP
D
8
Green (RoHS
& no Sb/Br)
0 to 70
071BC
P
8
Green (RoHS
& no Sb/Br)
0 to 70
TL071BCP
TL071C
TL071CD
D
8
Green (RoHS
& no Sb/Br)
0 to 70
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
2500
2500
50
(1)
(2)
(3)
(4/5)
(6)
TL071CDR
TL071CDRE4
TL071CDRG4
TL071CP
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
D
P
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL071C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL071C
TL071C
TL071CP
TL071CP
T071
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL071CPE4
TL071CPSR
TL071ID
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
PS
D
D
D
P
2000
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
Green (RoHS
& no Sb/Br)
TL071I
TL071IDR
2500
2500
50
Green (RoHS
& no Sb/Br)
TL071I
TL071IDRG4
TL071IP
Green (RoHS
& no Sb/Br)
TL071I
Green (RoHS
& no Sb/Br)
TL071IP
072AC
TL072ACD
D
D
D
D
D
P
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TL072ACDE4
TL072ACDR
TL072ACDRE4
TL072ACDRG4
TL072ACP
75
Green (RoHS
& no Sb/Br)
072AC
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
072AC
Green (RoHS
& no Sb/Br)
072AC
Green (RoHS
& no Sb/Br)
072AC
Pb-Free
(RoHS)
TL072ACP
TL072ACP
TL072ACPE4
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL072BCD
TL072BCDE4
TL072BCDG4
TL072BCDR
TL072BCDRG4
TL072BCP
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
072BC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
072BC
D
75
Green (RoHS
& no Sb/Br)
072BC
D
2500
2500
50
Green (RoHS
& no Sb/Br)
072BC
D
Green (RoHS
& no Sb/Br)
072BC
P
Pb-Free
(RoHS)
TL072BCP
TL072BCP
TL072C
TL072C
TL072C
TL072C
TL072C
TL072C
TL072CP
TL072CP
T072
TL072BCPE4
TL072CD
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TL072CDE4
TL072CDG4
TL072CDR
D
75
Green (RoHS
& no Sb/Br)
D
75
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
TL072CDRE4
TL072CDRG4
TL072CP
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Green (RoHS
& no Sb/Br)
TL072CPE4
TL072CPS
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
PS
PS
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TL072CPSR
SO
2000
Green (RoHS
& no Sb/Br)
T072
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2000
2000
2000
2000
2000
75
(1)
(2)
(3)
(4/5)
(6)
TL072CPSRE4
TL072CPSRG4
TL072CPWR
TL072CPWRE4
TL072CPWRG4
TL072ID
ACTIVE
SO
SO
PS
PS
PW
PW
PW
D
8
8
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
T072
T072
T072
T072
T072
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
POST-PLATE
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
8
Green (RoHS
& no Sb/Br)
0 to 70
8
Green (RoHS
& no Sb/Br)
0 to 70
8
Green (RoHS
& no Sb/Br)
0 to 70
8
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
TL072I
TL072I
TL072I
TL072I
TL072I
TL072I
TL072IP
TL072IP
TL072IDE4
D
8
75
Green (RoHS
& no Sb/Br)
TL072IDG4
TL072IDR
D
8
75
Green (RoHS
& no Sb/Br)
D
8
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
TL072IDRE4
TL072IDRG4
TL072IP
D
8
Green (RoHS
& no Sb/Br)
D
8
Green (RoHS
& no Sb/Br)
P
8
Pb-Free
(RoHS)
TL072IPE4
PDIP
P
8
50
Pb-Free
(RoHS)
N / A for Pkg Type
TL072MFKB
LCCC
FK
20
1
TBD
N / A for Pkg Type
81023052A
TL072MFKB
TL072MJG
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL072MJG
TL072MJGB
8102305PA
TL072M
TL072MUB
TL074ACD
ACTIVE
ACTIVE
CFP
U
D
10
14
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
0 to 70
8102305HA
TL072M
SOIC
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
TL074AC
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL074ACDE4
TL074ACDR
TL074ACDRE4
TL074ACDRG4
TL074ACN
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL074AC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL074AC
TL074AC
TL074AC
TL074ACN
TL074ACN
TL074A
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TL074ACNE4
TL074ACNSR
TL074BCD
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
NS
D
2000
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SSOP
SOIC
Green (RoHS
& no Sb/Br)
TL074BC
TL074BC
TL074BC
TL074BC
TL074BC
TL074BCN
TL074BCN
TL074C
TL074BCDE4
TL074BCDR
TL074BCDRE4
TL074BCDRG4
TL074BCN
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TL074BCNE4
TL074CD
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TL074CDBR
TL074CDG4
DB
D
2000
50
Green (RoHS
& no Sb/Br)
T074
Green (RoHS
& no Sb/Br)
TL074C
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
2500
25
(1)
(2)
(3)
(4/5)
(6)
TL074CDR
TL074CDRG4
TL074CN
ACTIVE
SOIC
SOIC
PDIP
PDIP
SO
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
20
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
TL074C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
POST-PLATE
TL074C
TL074CN
TL074CN
TL074
N
Green (RoHS
& no Sb/Br)
0 to 70
TL074CNE4
TL074CNSR
TL074CNSRG4
TL074CPW
TL074CPWR
TL074CPWRE4
TL074CPWRG4
TL074ID
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
NS
NS
PW
PW
PW
PW
D
2000
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
SO
Green (RoHS
& no Sb/Br)
0 to 70
TL074
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
LCCC
Green (RoHS
& no Sb/Br)
0 to 70
T074
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
0 to 70
T074
Green (RoHS
& no Sb/Br)
0 to 70
T074
Green (RoHS
& no Sb/Br)
0 to 70
T074
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
TL074I
TL074I
TL074I
TL074I
TL074I
TL074I
TL074IN
TL074MFK
TL074IDE4
TL074IDG4
TL074IDR
D
50
Green (RoHS
& no Sb/Br)
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
TL074IDRE4
TL074IDRG4
TL074IN
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TL074MFK
FK
1
TBD
N / A for Pkg Type
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL074MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
81023062A
TL074MFKB
TL074MJ
ACTIVE
ACTIVE
CDIP
CDIP
J
J
14
14
1
1
TBD
TBD
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL074MJ
TL074MJB
8102306CA
TL074MJB
TL074MWB
ACTIVE
CFP
W
14
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
8102306DA
TL074MWB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :
Catalog: TL072, TL074
•
Enhanced Product: TL072-EP, TL072-EP, TL074-EP, TL074-EP
•
Military: TL072M, TL074M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL071ACDR
TL071BCDR
TL071CDR
TL071CDR
TL071IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
SOIC
SOIC
SOIC
SO
D
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2500
2500
2500
2000
2500
2500
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
12.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
7.0
6.4
6.4
6.5
8.2
6.5
6.5
6.5
6.9
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
3.6
5.2
5.2
9.0
10.5
9.0
9.0
9.0
5.6
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
1.6
2.1
2.1
2.1
2.5
2.1
2.1
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
8
D
8
D
8
TL072ACDR
TL072BCDR
TL072CDR
TL072CDR
TL072CPWR
TL072IDR
D
8
D
8
D
8
D
8
PW
D
8
8
TL072IDR
D
8
TL074ACDR
TL074ACNSR
TL074BCDR
TL074CDR
TL074CDRG4
TL074CPWR
D
14
14
14
14
14
14
NS
D
SOIC
SOIC
SOIC
TSSOP
D
D
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL074IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL071ACDR
TL071BCDR
TL071CDR
TL071CDR
TL071IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
SOIC
SOIC
SOIC
SO
D
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2500
2500
2500
2000
2500
2500
340.5
340.5
340.5
367.0
340.5
340.5
340.5
340.5
367.0
367.0
367.0
340.5
333.2
367.0
333.2
333.2
338.1
338.1
338.1
367.0
338.1
338.1
338.1
338.1
367.0
367.0
367.0
338.1
345.9
367.0
345.9
345.9
20.6
20.6
20.6
35.0
20.6
20.6
20.6
20.6
35.0
35.0
35.0
20.6
28.6
38.0
28.6
28.6
D
8
D
8
D
8
TL072ACDR
TL072BCDR
TL072CDR
TL072CDR
TL072CPWR
TL072IDR
D
8
D
8
D
8
D
8
PW
D
8
8
TL072IDR
D
8
TL074ACDR
TL074ACNSR
TL074BCDR
TL074CDR
D
14
14
14
14
NS
D
SOIC
SOIC
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL074CDRG4
TL074CPWR
TL074IDR
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
2500
2000
2500
333.2
367.0
333.2
345.9
367.0
345.9
28.6
35.0
28.6
Pack Materials-Page 3
PACKAGE OUTLINE
U0010A
CFP - 2.03 mm max height
S
C
A
L
E
1
.
4
0
0
CERAMIC FLATPACK
.27 MAX
GLASS
.005 MIN
TYP
.010 .002
1
PIN 1 ID
.045 MAX
TYP
10
8X .050 .005
.27 MAX
GLASS
5
6
10X .017 .002
+.019
.241
5X .32 .01
5X .32 .01
-.003
.005 .001
+.013
.067
-.012
.045
.026
4225582/A 01/2020
NOTES:
1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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