TL084HIDYYR [TI]

TL08xx FET-Input Operational Amplifiers;


型号：	TL084HIDYYR
厂家：	TEXAS INSTRUMENTS
描述：	TL08xx FET-Input Operational Amplifiers
文件：	总75页 (文件大小：5276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

TL08xx FET-Input Operational Amplifiers

1 Features

3 Description

•

High slew rate: 20 V/μs (TL08xH, typ)

Low offset voltage: 1 mV (TL08xH, typ)

Low offset voltage drift: 2 μV/°C

Low power consumption: 940 μA/ch (TL08xH, typ)

Wide common-mode and differential

voltage ranges

– Common-mode input voltage range

includes V_CC+

Low input bias and offset currents

Low noise:

The TL08xH (TL081H, TL082H, and TL084H) family

of devices are the next-generation versions of the

industry-standard TL08x (TL081, TL082, and TL084)

devices. These devices provide outstanding value for

cost-sensitive applications, with features including low

offset (1 mV, typical), high slew rate (20 V/μs), and

common-mode input to the positive supply. High ESD

(1.5 kV, HBM), integrated EMI and RF filters, and

operation across the full –40°C to 125°C enable the

TL08xH devices to be used in the most rugged and

demanding applications.

•

V_n= 18 nV/√Hz (typ) at f = 1 kHz

Output short-circuit protection

Low total harmonic distortion: 0.003% (typ)

Wide supply voltage:

•

Device Information

PART NUMBER⁽¹⁾

PACKAGE

BODY SIZE (NOM)

9.59 mm × 6.35 mm

2.00 mm × 1.25 mm

6.20 mm × 5.30 mm

4.90 mm × 3.90 mm

1.60 mm × 1.20 mm

9.59 mm × 6.35 mm

6.20 mm × 5.30 mm

4.90 mm × 3.90 mm

2.90 mm × 1.60 mm

4.40 mm × 3.00 mm

9.59 mm × 6.67 mm

8.89 mm × 8.89 mm

19.30 mm × 6.35 mm

10.30 mm × 5.30 mm

8.65 mm × 3.91 mm

4.20 mm × 2.00 mm

5.00 mm × 4.40 mm

19.56 mm × 6.92 mm

8.89 mm × 8.89 mm

PDIP (8)

±2.25 V to ±20 V, 4.5 V to 40 V

SC70 (5)

SO (8)

2 Applications

TL081x

•

Solar energy: string and central inverter

Motor drives: AC and servo drive control and

power stage modules

Single phase online UPS

Three phase UPS

SOIC (8)

SOT-23 (5)

PDIP (8)

•

SO (8)

TL082x

TL082M

TL084x

TL084M

SOIC (8)

SOT-23 (8)

TSSOP (8)

CDIP (8)

Pro audio mixers

Battery test equipment

LCCC (20)

PDIP (14)

SO (14)

SOIC (14)

SOT-23 (14)

TSSOP (14)

CDIP (14)

LCCC (20)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

TL081

TL082 (EACH AMPLIFIER)

TL084 (EACH AMPLIFIER)

OFFSET N1

−

IN+

IN−

−

IN+

IN−

OUT

OFFSET N2

Logic Symbols

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications................................................................ 10

6.1 Absolute Maximum Ratings: TL08xH .......................10

6.2 Absolute Maximum Ratings: All Other Devices........ 10

6.3 ESD Ratings: TL08xH ..............................................10

6.4 ESD Ratings: All Other Devices................................11

6.5 Recommended Operating Conditions: TL08xH ....... 11

6.6 Recommended Operating Conditions: All Other

Devices........................................................................11

6.7 Thermal Information for Single Channel: TL081H ....11

6.8 Thermal Information for Dual Channel: TL082H ...... 11

6.9 Thermal Information for Quad Channel: TL084H .....12

6.10 Thermal Information: All Other Devices..................12

6.11 Electrical Characteristics: TL08xH ......................... 13

6.12 Electrical Characteristics for TL08xC, TL08xxC,

and TL08xI.................................................................. 15

6.13 Electrical Characteristics for TL08xM and

6.16 Typical Characteristics: TL08xH............................. 18

6.17 Typical Characteristics: All Other Devices.............. 25

7 Parameter Measurement Information..........................28

8 Detailed Description......................................................29

8.1 Overview...................................................................29

8.2 Functional Block Diagram.........................................29

8.3 Feature Description...................................................29

8.4 Device Functional Modes..........................................30

9 Applications and Implementation................................31

9.1 Application Information............................................. 31

9.2 Typical Applications.................................................. 31

9.3 System Examples..................................................... 32

10 Power Supply Recommendations..............................34

11 Layout...........................................................................35

11.1 Layout Guidelines................................................... 35

11.2 Layout Examples.....................................................35

12 Device and Documentation Support..........................36

12.1 Receiving Notification of Documentation Updates..36

12.2 Support Resources................................................. 36

12.3 Trademarks.............................................................36

12.4 Electrostatic Discharge Caution..............................36

12.5 Glossary..................................................................36

13 Mechanical, Packaging, and Orderable

TL084x........................................................................ 16

6.14 Switching Characteristics........................................17

6.15 Dissipation Rating Table......................................... 17

Information.................................................................... 36

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (June 2021) to Revision L (July 2021)

Page

•

Deleted preview note from TL081H SOIC (8), SOT-23 (5), and SC70 (5) packages throughout the data sheet

............................................................................................................................................................................1

Changes from Revision J (November 2020) to Revision K (June 2021)

Page

•

Deleted VSSOP (8) package references throughout data sheet........................................................................1

Deleted preview note from TL082H SOIC (8), SOT-23 (8), and TSSOP (8) packages throughout the data

sheet...................................................................................................................................................................1

Added DBV, DCK, and D packages to TL081H in Pin Configuration and Functions section..............................4

Added ESD information for TL082H................................................................................................................. 10

Added D, DCK, and DBV package thermal information in Thermal Information for Single Channel: TL081H

section...............................................................................................................................................................11

Added D, DDF, and PW package thermal information in Thermal Information for Dual Channel: TL082H

section ..............................................................................................................................................................11

Added I_Band I_OSspecification for single channel DCK and DBV package...................................................... 13

Added I_Qspec for TL081H and TL082H...........................................................................................................13

Removed Related Links section from Device and Documentation Support section.........................................36

•

Changes from Revision I (May 2015) to Revision J (November 2020)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Added TL08xH devices throughout the data sheet.............................................................................................1

Added features for TL08xH to the Features section...........................................................................................1

Added link to applications in the Applications section........................................................................................ 1

Submit Document Feedback

Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

•

Added TL08xH in the Description section...........................................................................................................1

Added TL08xH in the Device Information table.................................................................................................. 1

Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................4

Added TSSOP, VSSOP and DDF packages to TL082x in Pin Configuration and Functions section................. 4

Added DYY package to TL084x in Pin Configuration and Functions section.....................................................4

Added Typical Characteristics:TL08xH section in Specifications section......................................................... 18

Removed Table of Graphs in Typical Characteristics: All Other Devices section............................................. 25

Removed references to obsolete documentation............................................................................................. 35

Changes from Revision H (January 2014) to Revision I (May 2015)

Page

•

Added Applications section, Device Information table, Pin Functions table, Thermal Information table, Feature

Description section, Device Functional Modes section, Application and Implementation section, Power Supply

Recommendations section, ESD information, Layout section, Device and Documentation Support section,

and Mechanical, Packaging, and Orderable Information section....................................................................... 1

Added Applications ............................................................................................................................................1

Moved Typical Characteristics into Specifications section. ..............................................................................25

•

Changes from Revision G (September 2004) to Revision H (January 2014)

Page

•

Deleted Ordering Information table.....................................................................................................................1

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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5 Pin Configuration and Functions

IN–

OUT

Vœ

V+

VCC+

OUT

IN+

INœ

VCC–

Not to scale

NC- no internal connection

Figure 5-1. TL081H DBV and DCK Package

5-Pin SOT-23 and SC70

Top View

Figure 5-2. TL081H D Package

8-Pin SOIC

Top View

Table 5-1. Pin Functions: TL081H

I/O

DESCRIPTION

DBV and

DCK

NAME

IN–

Inverting input

Noninverting input

Do not connect

Output

IN+

—

OUT

VCC–

VCC+

Power supply

Submit Document Feedback

Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

OFFSET N1

INœ

VCC+

OUT

IN+

VCCœ

OFFSET N2

Not to scale

NC- no internal connection

Figure 5-3. TL081x D, P, and PS Package

8-Pin SOIC, PDIP, and SO

Top View

Table 5-2. Pin Functions: TL081x

I/O

DESCRIPTION

NAME

IN–

NO.

Inverting input

IN+

Noninverting input

Do not connect

Input offset adjustment

Output

—

OFFSET N1

OFFSET N2

OUT

VCC–

VCC+

Power supply

Submit Document Feedback

Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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1OUT

1INœ

VCC+

2OUT

2INœ

1IN+

VCCœ

2IN+

Not to scale

Figure 5-4. TL082x D, DDF, DGK, JG, P, PS, and PW Package

8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP

Top View

Table 5-3. Pin Functions: TL082x

I/O

DESCRIPTION

NAME

1IN–

NO.

Inverting input

Noninverting input

Output

1IN+

1OUT

2IN–

Inverting input

Noninverting input

Output

2IN+

2OUT

VCC–

VCC+

—

Power supply

Submit Document Feedback

Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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1INœ

2OUT

1IN+

2INœ

Not to scale

NC- no internal connection

Figure 5-5. TL082 FK Package

20-Pin LCCC

Top View

Table 5-4. Pin Functions: TL082x

I/O

DESCRIPTION

NAME

1IN–

NO.

Inverting input

Noninverting input

Output

1IN+

1OUT

2IN–

Inverting input

Noninverting input

Output

2IN+

2OUT

1, 3, 4, 6, 8,

9, 11, 13, 14,

16, 18, 19

—

Do not connect

VCC–

VCC+

—

Power supply

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

1OUT

1INœ

4OUT

4INœ

1IN+

4IN+

VCC+

2IN+

VCCœ

3IN+

2INœ

3INœ

2OUT

3OUT

Not to scale

Figure 5-6. TL084x D, N, NS, PW, J, and DYY Package

14-Pin SOIC, PDIP, SO, TSSOP, CDIP, and SOT-23 (14)

Top View

Table 5-5. Pin Functions: TL084x

I/O

DESCRIPTION

NAME

1IN–

NO.

Inverting input

Noninverting input

Output

1IN+

1OUT

2IN–

Inverting input

Noninverting input

Output

2IN+

2OUT

3IN–

Inverting input

Noninverting input

Output

3IN+

3OUT

4IN–

Inverting input

Noninverting input

Output

4IN+

4OUT

V_CC–

V_CC+

—

Power supply

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

1IN+

4IN+

VCC+

VCCœ

2IN+

3IN+

Not to scale

NC- no internal connection

Figure 5-7. TL084 FK Package

20-Pin LCCC

Top View

Table 5-6. Pin Functions: TL084x

I/O

DESCRIPTION

NAME

1IN–

NO.

Inverting input

Noninverting input

Output

1IN+

1OUT

2IN–

Inverting input

Noninverting input

Output

2IN+

2OUT

3IN–

Inverting input

Noninverting input

Output

3IN+

3OUT

4IN–

Inverting input

Noninverting input

Output

4IN+

4OUT

1, 5, 7, 11, 15,

—

Do not connect

VCC–

VCC+

—

Power supply

Submit Document Feedback

Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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6 Specifications

6.1 Absolute Maximum Ratings: TL08xH

over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

Supply voltage, V_S= (V_CC+) – (V_CC–

)

Common-mode voltage ⁽³⁾

Differential voltage ⁽³⁾

Current ⁽³⁾

(V_CC–) – 0.5

(V_CC+) + 0.5

V_S+ 0.2

Signal input pins

–10

–55

–65

Output short-circuit ⁽²⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Short-circuit to ground, one amplifier per package.

(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

6.2 Absolute Maximum Ratings: All Other Devices

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_CC+

V_CC-

Supply voltage⁽²⁾

-18

V_ID

V_I

Differential input voltage⁽³⁾

Input voltage^{(2) (4)}

-30

-15

+30

+15

Duration of output short circuit⁽⁵⁾

Continuous total power dissipation

Storage temperature

Unlimited

See Section 6.15

–65 150

T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to the midpoint between V_CC+and V_CC−

(3) Differential voltages are at IN+, with respect to IN−.

(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.

(5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the

dissipation rating is not exceeded.

6.3 ESD Ratings: TL08xH

VALUE

UNIT

TL084H

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1500

±1000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾

TL082H and TL081H

V_(ESD)Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

6.4 ESD Ratings: All Other Devices

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.5 Recommended Operating Conditions: TL08xH

over operating ambient temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

V_S

V_I

Supply voltage, (V_CC+) – (V_CC–

)

(V_CC+) + 0.1

125

Input voltage range

(V_CC–) + 2

–40

T_A

Specified temperature

°C

6.6 Recommended Operating Conditions: All Other Devices

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_CC+

V_CC–

V_CM

Supply voltage

–5

–15

Common-mode voltage

V_CC–+ 4 V_CC+– 4

TL08xM

TL08xQ

TL08xI

–55

–40

125

T_A

Ambient temperature

°C

TL08xC

6.7 Thermal Information for Single Channel: TL081H

TL081H

DCK

(SC70)

DBV

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

(SOT-23)

5 PINS

212.2

111.1

79.4

8 PINS

158.8

98.6

5 PINS

217.5

113.1

63.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

102.3

45.8

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

34.8

51.8

ψ_JB

101.5

N/A

63.5

79.0

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.8 Thermal Information for Dual Channel: TL082H

TL082H

DDF

(SOT-23)

(TSSOP)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

8 PINS

147.8

88.2

8 PINS

181.5

112.5

98.2

8 PINS

200.3

89.4

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

91.4

131.0

22.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

36.8

17.2

ψ_JB

90.6

97.6

129.3

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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6.8 Thermal Information for Dual Channel: TL082H (continued)

TL082H

DDF

(SOT-23)

(TSSOP)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

8 PINS

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.9 Thermal Information for Quad Channel: TL084H

TL084H

DYY ⁽²⁾

(SOT-23)

(TSSOP)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

14 PINS

114.2

70.3

14 PINS

TBD

14 PINS

134.4

62.6

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

TBD

°C/W

70.2

TBD

77.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

28.8

TBD

13.0

ψ_JB

69.8

TBD

77.0

R_θJC(bot)

N/A

TBD

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) This package option is preview for TL084H.

6.10 Thermal Information: All Other Devices

TL08xxx

N (PDIP)

THERMAL METRIC⁽¹⁾

D (SOIC)

J (CDIP)

NS (SO)

PW (TSSOP)

8 PIN 14 PIN

150 113

UNIT

(LCCC)

8 PIN

14 PIN

20 PIN

8 PIN

14 PIN

8 PIN

14 PIN

8 PIN

14 PIN

Junction-to-

ambient thermal

resistance

R_θJA

°C/W

Junction-to-

case (top)

thermal

R_θJC(top)

5.61

15.05

14.5

resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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6.11 Electrical Characteristics: TL08xH

For V_S= (V_CC+) – (V_CC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_{O UT}= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±1

±4

±5

V_OS

Input offset voltage

T_A= –40°C to 125°C

dV_OS/dT

PSRR

Input offset voltage drift

T_A= –40°C to 125°C

±2

±1

µV/℃

μV/V

µV/V

Input offset voltage versus V_S= 5 V to 40 V, V_CM= V_S

power supply

±10

Channel separation

f = 0 Hz

INPUT BIAS CURRENT

±1

±120

±300

±5

I_B

Input bias current

DCK and DBV packages

T_A= –40°C to 125°C ⁽¹⁾

±0.5

±120

±250

±5

I_OS

Input offset current

DCK and DBV packages

T_A= –40°C to 125°C ⁽¹⁾

NOISE

9.2

1.4

μV_PP

E_N

Input voltage noise

f = 0.1 Hz to 10 Hz

µV_RMS

f = 1 kHz

f = 10 kHz

f = 1 kHz

e_N

i_N

Input voltage noise density

Input current noise

nV/√Hz

fA/√Hz

INPUT VOLTAGE RANGE

Common-mode voltage

range

V_CM

(V_CC–) + 1.5

(V_CC+

)

Common-mode rejection

ratio

CMRR

100

105

V_S= 40 V, (V_CC–) + 2.5 V <

V_CM< (V_CC+) – 1.5 V

Common-mode rejection

ratio

T_A= –40°C to 125°C

Common-mode rejection

ratio

V_S= 40 V, (V_CC–) + 2.5 V <

V_CM< (V_CC+

)

Common-mode rejection

ratio

INPUT CAPACITANCE

Z_ID

Differential

100 || 2

6 || 1

MΩ || pF

TΩ || pF

Z_ICM

Common-mode

OPEN-LOOP GAIN

V_S= 40 V, V_CM= V_S/ 2,

A_OLOpen-loop voltage gain

(V_CC–) + 0.3 V < V_O< (V_CC+

– 0.3 V

)

T_A= –40°C to 125°C

118

115

125

120

V_S= 40 V, V_CM= V_S/ 2, R_L

A_OL

Open-loop voltage gain

2 kΩ, (V_CC–) + 1.2 V < V_O

(V_CC+) – 1.2 V

FREQUENCY RESPONSE

GBW

Gain-bandwidth product

5.25

MHz

V/μs

Slew rate

V_S= 40 V, G = +1, C_L= 20 pF

To 0.1%, V_S= 40 V, V_STEP= 10 V , G = +1, CL = 20 pF

To 0.1%, V_S= 40 V, V_STEP= 2 V , G = +1, CL = 20 pF

To 0.01%, V_S= 40 V, V_STEP= 10 V , G = +1, CL = 20 pF

To 0.01%, V_S= 40 V, V_STEP= 2 V , G = +1, CL = 20 pF

G = +1, R_L= 10kΩ, C_L= 20 pF

0.63

0.56

0.91

0.48

t_S

Settling time

μs

Phase margin

Overload recovery time

V_IN× gain > V_S

300

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6.11 Electrical Characteristics: TL08xH (continued)

For V_S= (V_CC+) – (V_CC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_{O UT}= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

V_S= 40 V, V_O= 6 V_RMS, G = +1, f = 1 kHz

f = 1 GHz

MIN

TYP

0.00012

MAX

UNIT

Total harmonic distortion +

noise

THD+N

EMIRR

EMI rejection ratio

OUTPUT

V_S= 40 V, R_L= 10 kΩ

115

520

105

500

±26

300

210

965

Positive rail headroom

Negative rail headroom

V_S= 40 V, R_L= 2 kΩ

V_S= 40 V, R_L= 10 kΩ

V_S= 40 V, R_L= 2 kΩ

Voltage output swing from

rail

215

1030

I_SC

Short-circuit current

Capacitive load drive

C_LOAD

Open-loop output

impedance

Z_O

f = 1 MHz, I_O= 0 A

125

Ω

POWER SUPPLY

I_O= 0 A

937.5

960

1125

1156

1130

1143

1160

I_O= 0 A, (TL081H)

I_O= 0 A

Quiescent current per

amplifier

I_Q

µA

μs

I_O= 0 A, (TL082H)

I_O= 0 A, (TL081H)

T_A= –40°C to 125°C

Turn-On Time

At T_A= 25°C, V_S= 40 V, V_Sramp rate > 0.3 V/µs

(1) Max I_Band I_osdata is specified based on characterization results.

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6.12 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI

V_CC±= ±15 V (unless otherwise noted)

TL081C, TL082C,

TL084C

TL081AC, TL082AC,

TL084AC

TL081BC, TL082BC,

TL084BC

TL081I, TL082I,

TL084I

TEST

CONDITIONS

(1)

PARAMETER

T_A

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP MAX

MIN

TYP

MAX

25°C

Input offset V_O= 0,

V_IO

Full

range

voltage

R_S= 50 Ω

7.5

Temperature

coefficient of

input

offset

V_O= 0,

R_S= 50 Ω

Full

range

α_VIO

μV/°C

voltage

25°C

200

100

Input offset

current⁽²⁾

I_IO

V_O= 0

Full

range

25°C

400

200

Input bias

current⁽²⁾

I_IB

Full

range

Common-

mode

input voltage

range

–12

V_ICR

V_OM

A_VD

25°C

±11

Maximum

peak

output

voltage

swing

R_L= 10 kΩ

R_L≥ 10 kΩ

±12 ±13.5

±12

±12 ±13.5

±12

±12 ±13.5

±12

±12 ±13.5

±12

Full

range

R_L≥ 2 kΩ

±10

±12

200

±10

±12

200

±10

±12

200

±10

±12

200

Large-signal

differential

voltage

25°C

V_O= ±10 V,

R_L≥ 2 kΩ

V/mV

Full

range

amplification

Unity-gain

bandwidth

B₁

r_i

25°C

MHz

Ω

Input

resistance

10¹²

Common-

mode

rejection

ratio

V_IC= V_ICRmin,

V_O= 0,

R_S= 50 Ω

CMRR

25°C

Supply-

voltage

rejection

ratio

V_CC= ±15 V to

±9 V,

V_O= 0,

k_SVR

(ΔV_CC±

ΔV_IO

R_S= 50 Ω

)

Supply

current

(each

V_O= 0,

No load

I_CC

25°C

1.4

2.8

1.4

2.8

1.4

2.8

1.4

2.8

amplifier)

Crosstalk

attenuation

V_O1/V_O2

A_VD= 100

120

(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range

for T_Ais 0°C to 70°C for TL08_C, TL08_AC, TL08_BC and –40°C to 85°C for TL08_I.

(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Figure 6-52. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as

possible.

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6.13 Electrical Characteristics for TL08xM and TL084x

V_CC±= ±15 V (unless otherwise noted)

TL081M, TL082M

MIN TYP MAX

TL084Q, TL084M

MIN TYP MAX

PARAMETER

TEST CONDITIONS⁽¹⁾

T_A

UNIT

25°C

V_IO

Input offset voltage

V_O= 0, R_S= 50 Ω

Full range

Temperature

α_VIO

coefficient of input

offset voltage

V_O= 0, R_S= 50 Ω

Full range

μV/°C

25°C

125°C

25°C

100

I_IO

Input offset current⁽²⁾

Input bias current⁽²⁾

V_O= 0

200

I_IB

125°C

–12

Common-mode

input voltage range

V_ICR

25°C

±11

R_L= 10 kΩ

R_L≥ 10 kΩ

R_L≥ 2 kΩ

25°C

±12

±10

±13.5

±12

±10

±13.5

Maximum peak

output voltage swing

V_OM

Full range

±12

200

±12

200

25°C

Full range

25°C

Large-signal differential

voltage amplification

A_VD

V_O= ±10 V, R_L≥ 2 kΩ

V/mV

B₁

r_i

Unity-gain bandwidth

Input resistance

MHz

Ω

25°C

10¹²

Common-mode

rejection ratio

V_IC= V_ICRmin,

V_O= 0, R_S= 50 Ω

CMRR

k_SVR

I_CC

25°C

Supply-voltage

rejection ratio

V_CC= ±15 V to ±9 V,

V_O= 0, R_S= 50 Ω

(ΔV_CC±/ΔV_IO

)

Supply current

(each amplifier)

V_O= 0, No load

A_VD= 100

25°C

1.4

2.8

1.4

2.8

V_O1/V_O2Crosstalk attenuation

120

(1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified.

(2) Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Figure 6-52. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as

possible.

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6.14 Switching Characteristics

V_CC±= ±15 V, T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V/μs

μs

V_I= 10 V, R_L= 2 kΩ, C_L= 100 pF,

see Figure 7-1

8⁽¹⁾

t_r

Slew rate at unity gain

V_I= 10 V, R_L= 2 kΩ, C_L= 100 pF,

T_A= −55°C to 125°C,

see Figure 7-1

5⁽¹⁾

Rise-time

0.05

20%

V_I= 20 V, R_L= 2 kΩ, C_L= 100 pF,

see Figure 7-1

overshoot factor

f = 1 kHz

nV/√ Hz

μV

Equivalent input noise

voltage

V_n

R_S= 20 Ω

f = 10 Hz to 10 kHz

f = 1 kHz

Equivalent input noise

current

I_n

R_S= 20 Ω

0.01

pA/√ Hz

V_Irms = 6 V, A_VD= 1, R_S≤ 1 kΩ, R_L≥ 2 kΩ,

f = 1 kHz

THD

Total harmonic distortion

0.003%

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.15 Dissipation Rating Table

T_A≤ 25°C

POWER RATING

DERATING

FACTOR

DERATE

ABOVE T_A

T_A= 70°C

T_A= 85°C

T_A= 125°C

PACKAGE

POWER RATING POWER RATING POWER RATING

D (14 pin)

680 mW

7.6 mW/°C

11.0 mW/°C

8.4 mW/°C

60°C

88°C

69°C

604 m/W

680 m/W

672 m/W

490 mW

680 mW

546 mW

186 mW

273 mW

210 mW

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6.16 Typical Characteristics: TL08xH

at T_A= 25°C, V_S= 40 V ( ±20 V), V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 20 pF (unless

otherwise noted)

T_A= 25°C

Figure 6-1. Offset Voltage Production Distribution

Figure 6-2. Offset Voltage Drift Distribution

V_CM= V_S/ 2

T_A= 25°C

Figure 6-3. Offset Voltage vs Temperature

Figure 6-4. Offset Voltage vs Common-Mode

Voltage

T_A= 125°C

T_A= –40°C

Figure 6-5. Offset Voltage vs Common-Mode

Voltage

Figure 6-6. Offset Voltage vs Common-Mode

Voltage

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Figure 6-7. Offset Voltage vs Power Supply

Figure 6-8. Open-Loop Gain and Phase vs

Frequency

Figure 6-9. Closed-Loop Gain vs Frequency

Figure 6-10. Input Bias Current vs Common-Mode

Voltage

Figure 6-11. Input Bias Current vs Temperature

Figure 6-12. Output Voltage Swing vs Output

Current (Sourcing)

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Figure 6-14. CMRR and PSRR vs Frequency

Figure 6-13. Output Voltage Swing vs Output

Current (Sinking)

f = 0 Hz

Figure 6-16. PSRR vs Temperature (dB)

Figure 6-15. CMRR vs Temperature (dB)

Figure 6-17. 0.1-Hz to 10-Hz Noise

Figure 6-18. Input Voltage Noise Spectral Density

vs Frequency

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BW = 80 kHz, V_OUT= 1 V_RMS

BW = 80 kHz, f = 1 kHz

Figure 6-19. THD+N Ratio vs Frequency

Figure 6-20. THD+N vs Output Amplitude

V_CM= V_S/ 2

Figure 6-21. Quiescent Current vs Supply Voltage

Figure 6-22. Quiescent Current vs Temperature

Figure 6-23. Open-Loop Voltage Gain vs

Temperature (dB)

Figure 6-24. Open-Loop Output Impedance vs

Frequency

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G = –1, 25-mV output step

G = 1, 10-mV output step

Figure 6-25. Small-Signal Overshoot vs Capacitive Figure 6-26. Small-Signal Overshoot vs Capacitive

Load

V_S= ±10 V, V_IN= V_OUT

Figure 6-28. No Phase Reversal

Figure 6-27. Phase Margin vs Capacitive Load

G = –10

Figure 6-29. Positive Overload Recovery

Figure 6-30. Negative Overload Recovery

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C_L= 20 pF, G = 1, 10-mV step response

Figure 6-31. Small-Signal Step Response, Rising

Figure 6-32. Small-Signal Step Response, Falling

C_L= 20 pF, G = 1

Figure 6-33. Large-Signal Step Response (Rising) Figure 6-34. Large-Signal Step Response (Falling)

C_L= 20 pF, G = 1

Figure 6-35. Large-Signal Step Response

Figure 6-36. Short-Circuit Current vs Temperature

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Figure 6-38. Channel Separation vs Frequency

Figure 6-37. Maximum Output Voltage vs

Frequency

Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

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6.17 Typical Characteristics: All Other Devices

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various

devices. The Figure numbers referenced in the following graphs are located in Section 7.

12.5

15 V

10 V

5 V

= 10 kΩ

= 2 kΩ

= 25°C

See Figure 2

= 15 V

See Figure 2

= 10 V

7.5

5 V

2.5

100

1 k

10 k

100 k

1 M

10 M

100

1 k

10 k

100 k

1 M

10 M

f − Frequency − Hz

Figure 6-40. Maximum Peak Output Voltage vs Frequency

Figure 6-41. Maximum Peak Output Voltage vs Frequency

= 10 kΩ

= 2 kΩ

15 V

= 2 kΩ

= 25°C

12.5

7.5

12.5

7.5

See Figure 2

= −55°C

= 125°C

2.5

15 V

See Figure 2

−75 −50 −25

75 100 125

10 k

40 k 100 k

400 k 1 M

4 M 10 M

− Free-Air Temperature − °C

f − Frequency − Hz

Figure 6-43. Maximum Peak Output Voltage vs Free-Air

Temperature

Figure 6-42. Maximum Peak Output Voltage vs Frequency

= 10 kΩ

= 25°C

15 V

= 25°C

See Figure 2

12.5

7.5

12.5

7.5

2.5

0.1

0.2

0.4 0.7

7 10

| − Supply Voltage − V

− Load Resistance − kΩ

Figure 6-45. Maximum Peak Output Voltage vs Supply Voltage

Figure 6-44. Maximum Peak Output Voltage vs Load Resistance

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6.17 Typical Characteristics: All Other Devices (continued)

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various

devices. The Figure numbers referenced in the following graphs are located in Section 7.

1000

= 5 V to 15 V

= 2 kΩ

400

200

100

= 25°C

0°

Differential

Voltage

Amplification

45°

90°

Phase Shift

15 V

10 V

= 2 kΩ

135°

180°

−75 −50 −25

75 100 125

100

1 k

10 k 100 k 1 M 10 M

f − Frequency − Hz

− Free-Air Temperature − °C

Figure 6-47. Large-Signal Differential Voltage Amplification and

Phase Shift vs Frequency

Figure 6-46. Large-Signal Differential Voltage Amplification vs

Free-Air Temperature

250

= 15 V

No Signal

= 15 V

C2 = 3 pF

= 25°C

225

200

175

150

125

100

No Load

See Figure 3

TL084, TL085

TL082, TL083

TL081

−75 −50 −25

75 100 125

100

1 k

10 k

100 k

1 M

10 M

− Free-Air Temperature°−C

f − Frequency With Feed-Forward Compensation − Hz

Figure 6-49. Total Power Dissipation vs Free-Air Temperature

Figure 6-48. Differential Voltage Amplification vs Frequency

with Feed-Forward Compensation

= 15 V

= 25°C

1.8

1.6

1.4

1.2

1.8

1.6

1.4

1.2

No Signal

No Load

No Signal

No Load

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

−75 −50 −25

75 100 125

− Free-Air Temperature − °C

| − Supply Voltage − V

Figure 6-50. Supply Current per Amplifier vs Free-Air

Temperature

Figure 6-51. Supply Current per Amplifier vs Supply Voltage

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6.17 Typical Characteristics: All Other Devices (continued)

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various

devices. The Figure numbers referenced in the following graphs are located in Section 7.

100

= 15 V

= 2 kΩ

= 100 pF

= 25°C

Output

−2

−4

−6

Input

0.1

0.01

0.5

1.5

2.5

3.5

− 50 − 25

100

125

t − Time − µs

− Free-Air Temperature − °C

Figure 6-53. Voltage-Follower Large-Signal Pulse Response

Figure 6-52. Input Bias Current vs Free-Air Temperature

= 15 V

= 10 kΩ

= 15 V

= 2 kΩ

= 100 pF

= 25°C

See Figure 1

− 4

0.2

0.4

0.6

0.8

1.0

1.2

− 75 − 50 − 25

100 125

t − Elapsed Time – µs

− Free-Air Temperature −°C

Figure 6-54. Output Voltage vs Elapsed Time

Figure 6-55. Common-Mode Rejection Ratio vs Free-Air

Temperature

= 15 V

15 V

= 10

= 20 Ω

= 25°C

= 1

0.4

I(RMS)

= 6 V

= 25°C

0.1

0.04

0.01

0.004

0.001

100

400

1 k

4 k 10 k

40 k 100 k

40 100

400 1 k

4 k 10 k 40 k 100 k

f − Frequency − Hz

Figure 6-57. Total Harmonic Distortion vs Frequency

Figure 6-56. Equivalent Input Noise Voltage vs Frequency

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7 Parameter Measurement Information

10 kΩ

1 kΩ

−

OUT

= 100 pF

= 2 kΩ

Figure 7-2. Test Figure 2

Figure 7-1. Test Figure 1

100 kΩ

TL081

−

IN−

OUT

IN+

C1 500 pF

100 kΩ

−

IN−

OUT

1.5 kΩ

CC−

Figure 7-4. Test Figure 4

Figure 7-3. Test Figure 3

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TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

8 Detailed Description

8.1 Overview

The TL08xH family (TL081H, TL082H, and TL084H) is the next-generation family of the industry standard TL08x

(TL081, TL082, and TL084) high-voltage general purpose amplifiers. These devices provide outstanding value

for cost-sensitive applications requiring high slew rate with high voltage signals, such as motor drive and inverter

systems.

A robust MUX-friendly input stage enhances flexibility in design, with common-mode voltage range extending to

the positive rail as well as improved settling time in multi-channel applications. Low offset voltage (1 mV, typ) and

low offset voltage drift (2 µV/°C) allows the TL08xH family to be used in rugged applications requiring precision

current and voltage sensing. High voltage operation (up to 40 V) and high slew rate (20 V/µs) make the TL08xH

family a premier choice for high-voltage applications with fast transients.

8.2 Functional Block Diagram

CC+

IN+

64Ω

IN−

OUT

128Ω

64Ω

1080Ω

CC−

OFFSET N1

OFFSET N2

TL081 Only

8.3 Feature Description

8.3.1 Total Harmonic Distortion

Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic

distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These

devices have a very low THD of 0.003% meaning that the TL08x devices will add little harmonic distortion when

used in audio signal applications.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the

input. These devices have a 13-V/μs slew rate.

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TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

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8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single-supply

operational amplifier or dual-supply amplifier depending on the application.

Submit Document Feedback

Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

9 Applications and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TL08x series of operational amplifiers can be used in countless applications. The few applications in this

section show principles used in all applications of these parts.

9.2 Typical Applications

9.2.1 Inverting Amplifier Application

A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage

on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes

negative voltages positive.

Vsup+

VOUT

VIN

Vsup-

Figure 9-1. Schematic for Inverting Amplifier Application

9.2.1.1 Design Requirements

The supply voltage must be chosen such that it is larger than the input voltage range and output range. For

instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to

accommodate this application.

9.2.1.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier:

VOUT

A _V

VIN

(1)

(2)

1.8

A _V

= - 3.6

-0.5

Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable

because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw too much

current. This example will choose 10 kΩ for RI which means 36 kΩ will be used for RF. This was determined by

Equation 3.

A _V= -

(3)

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TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

9.2.1.3 Application Curve

VIN

1.5

VOUT

0.5

-0.5

-1

-1.5

-2

0.5

Time (ms)

1.5

Figure 9-2. Input and Output Voltages of the Inverting Amplifier

9.3 System Examples

9.3.1 General Applications

= 100 kΩ

−

CC+

TL081

15 V

−

Input

Output

3.3 kΩ

Output

CC−

TL081

= 3.3 µF

1 kΩ

R1 = R2 = 2(R3) = 1.5 MΩ

−15 V

C1 = C2 =

= 110 pF

= 1 kHz

3.3 kΩ

9.1 kΩ

2πR1 C1

f =

2πR

Figure 9-4. High-Q Notch Filter

Figure 9-3. 0.5-Hz Square-Wave Oscillator

6 sin ωt

1N4148

CC+

− 15 V

1 MΩ

18 kΩ

−

18 pF

(see Note A)

1 kΩ

18 pF

TL084

Output A

CC+

−

CC+

88.4 kΩ

1/2

TL082

−

1/2

TL082

1 µF

TL084

−

6 cos ωt

88.4 kΩ

CC+

CC−

Input

−

18 pF

1 kΩ

CC−

15 V

TL084

Output B

100 kΩ

100 µF

100 kΩ

1N4148

18 kΩ

88.4 kΩ

(see Note A)

CC+

100 kΩ

A. These resistor values may be adjusted for a symmetrical

output.

CC+

−

TL084

Output C

Figure 9-6. 100-kHz Quadrature Oscillator

Figure 9-5. Audio-Distribution Amplifier

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TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

16 kΩ

220 pF

43 kΩ

30 kΩ

43 kΩ

30 kΩ

CC+

43 kΩ

220 pF

CC+

−

Input

43 kΩ

−

1/4

TL084

1/4

TL084

Output

1/4

TL084

1/4

TL084

1.5 kΩ

CC−

Output A

Output B

2 kHz/div

Second-Order Bandpass Filter

= 100 kHz, Q = 30, GAIN = 4

2 kHz/div

Cascaded Bandpass Filter

f = 100 kHz, Q = 69, GAIN = 16

Figure 9-7. Positive-Feedback Bandpass Filter

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TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

10 Power Supply Recommendations

CAUTION

Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply

can permanently damage the device (see Section 6.2).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high

impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section 11.

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TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance

power sources local to the analog circuitry.

– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current.

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it

is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed

to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance, as shown in Section 11.2.

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

11.2 Layout Examples

Place components close to

device and to each other to

reduce parasitic errors

Run the input traces as far

away from the supply lines

as possible

VS+

IN1Þ

IN1+

VCCÞ

VCC+

OUT

Use low-ESR, ceramic

bypass capacitor

GND

VIN

RIN

GND

Only needed for

dual-supply

operation

GND

VS-

(or GND for single supply)

VOUT

Ground (GND) plane on another layer

Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration

RIN

VIN

VOUT

Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration

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TL084H

TL081, TL081A, TL081B, TL081H

TL082, TL082A, TL082B, TL082H

TL084, TL084A, TL084B, TL084H

SLOS081L – FEBRUARY 1977 – REVISED JULY 2021

www.ti.com

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TL081 TL081A TL081B TL081H TL082 TL082A TL082B TL082H TL084 TL084A TL084B

TL084H

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

5962-9851501Q2A

ACTIVE

LCCC

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

5962-

9851501Q2A

TL082MFKB

5962-9851501QPA

5962-9851503Q2A

ACTIVE

CDIP

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

9851501QPA

TL082M

LCCC

Non-RoHS

& Green

5962-

9851503Q2A

TL084

MFKB

5962-9851503QCA

ACTIVE

CDIP

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

5962-9851503QC

TL084MJB

TL081ACD

TL081ACDR

TL081ACP

TL081BCD

TL081BCDR

TL081BCP

TL081BCPE4

TL081CD

ACTIVE

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

Level-1-260C-UNLIM

0 to 70

-40 to 125

081AC

2500 RoHS & Green

081AC

RoHS & Green

TL081ACP

081BC

2500 RoHS & Green

081BC

RoHS & Green

TL081BCP

TL081C

TL081CP

T081

TL081CDR

TL081CP

2500 RoHS & Green

RoHS & Green

TL081CPE4

TL081CPSR

TL081HIDBVR

DBV

2000 RoHS & Green

3000 RoHS & Green

SOT-23

T81V

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TL081HIDCKR

TL081HIDR

TL081ID

ACTIVE

SC70

SOIC

PDIP

SOIC

PDIP

DCK

3000 RoHS & Green

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 125

-40 to 85

0 to 70

1IP

NIPDAU

TL081D

TL081I

TL081IP

082AC

RoHS & Green

TL081IDR

2500 RoHS & Green

TL081IP

RoHS & Green

TL082ACD

Level-1-260C-UNLIM

N / A for Pkg Type

TL082ACDE4

TL082ACDG4

TL082ACDR

TL082ACDRE4

TL082ACDRG4

TL082ACP

082AC

2500 RoHS & Green

082AC

RoHS & Green

TL082ACP

T082A

TL082ACPSR

TL082BCD

2000 RoHS & Green

Level-1-260C-UNLIM

N / A for Pkg Type

SOIC

PDIP

SOIC

RoHS & Green

082BC

TL082BCDE4

TL082BCDR

TL082BCDRE4

TL082BCDRG4

TL082BCP

082BC

2500 RoHS & Green

082BC

RoHS & Green

TL082BCP

TL082C

TL082BCPE4

TL082CD

N / A for Pkg Type

Level-1-260C-UNLIM

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TL082CDE4

TL082CDR

ACTIVE

SOIC

PDIP

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

0 to 70

TL082C

2500 RoHS & Green

NIPDAU

TL082C

TL082CP

T082

TL082CDRE4

TL082CDRG4

TL082CP

0 to 70

RoHS & Green

0 to 70

TL082CPSR

TL082CPSRG4

TL082CPW

TL082CPWR

TL082CPWRG4

TL082HIDDFR

TL082HIDR

TL082HIPWR

TL082ID

DDF

2000 RoHS & Green

Level-1-260C-UNLIM

N / A for Pkg Type

0 to 70

T082

TSSOP

150

RoHS & Green

0 to 70

T082

2000 RoHS & Green

3000 RoHS & Green

0 to 70

T082

0 to 70

T082

ACTIVE SOT-23-THIN

-40 to 125

-40 to 85

082F

ACTIVE

SOIC

TSSOP

SOIC

PDIP

TL082D

082HPW

TL082I

TL082IP

Z082

RoHS & Green

TL082IDG4

TL082IDR

2500 RoHS & Green

TL082IDRE4

TL082IDRG4

TL082IP

RoHS & Green

TL082IPE4

PDIP

N / A for Pkg Type

TL082IPWR

TSSOP

2000 RoHS & Green

Level-1-260C-UNLIM

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TL082MFKB

ACTIVE

LCCC

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

5962-

9851501Q2A

TL082MFKB

TL082MJG

ACTIVE

CDIP

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

TL082MJG

TL082MJGB

Non-RoHS

& Green

9851501QPA

TL082M

TL084ACD

TL084ACDE4

TL084ACDR

TL084ACDRE4

TL084ACDRG4

TL084ACN

ACTIVE

SOIC

PDIP

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

0 to 70

TL084AC

TL084ACN

TL084A

RoHS & Green

2500 RoHS & Green

2000 RoHS & Green

50 RoHS & Green

RoHS & Green

TL084ACNSR

TL084BCD

Level-1-260C-UNLIM

N / A for Pkg Type

SOIC

PDIP

SOIC

TL084BC

TL084BCN

TL084C

TL084BCDR

TL084BCDRG4

TL084BCN

2500 RoHS & Green

RoHS & Green

TL084BCNE4

TL084CD

N / A for Pkg Type

Level-1-260C-UNLIM

TL084CDE4

TL084CDG4

TL084CDR

TL084C

2500 RoHS & Green

TL084C

TL084CDRE4

TL084C

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TL084CDRG4

TL084CN

ACTIVE

SOIC

PDIP

2500 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

0 to 70

-40 to 125

TL084C

RoHS & Green

NIPDAU

TL084CN

TL084

TL084CNE4

TL084CNSR

TL084CPW

TL084CPWE4

TL084CPWR

TL084HIDR

PDIP

N / A for Pkg Type

2000 RoHS & Green

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

TSSOP

SOIC

RoHS & Green

T084

2000 RoHS & Green

2500 RoHS & Green

T084

TL084HID

TL084HIDYYR

TL084HIPWR

PREVIEW SOT-23-THIN

DYY

3000

TBD

Call TI

-40 to 125

ACTIVE

TSSOP

SOIC

PDIP

2000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

TL084PW

TL084I

TL084ID

TL084IDR

TL084IDRE4

TL084IDRG4

TL084IN

RoHS & Green

NIPDAU

SNPB

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

-55 to 125

2500 RoHS & Green

TL084I

RoHS & Green

TL084IN

TL084MFK

TL084INE4

TL084MFK

PDIP

LCCC

Non-RoHS

& Green

TL084MFKB

ACTIVE

LCCC

CDIP

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

5962-

9851503Q2A

TL084

MFKB

TL084MJ

ACTIVE

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

TL084MJ

Addendum-Page 5

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TL084MJB

ACTIVE

CDIP

Non-RoHS

& Green

SNPB

N / A for Pkg Type

-55 to 125

5962-9851503QC

TL084MJB

TL084QD

TL084QDG4

TL084QDR

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

TL084Q

2500 RoHS & Green

TL084QDRG4

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 6

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL082, TL082M, TL084, TL084M :

Catalog : TL082, TL084

•

Automotive : TL082-Q1, TL082-Q1

•

Military : TL082M, TL084M

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 7

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TL081ACDR

TL081BCDR

TL081CDR

SOIC

2500

2000

3000

2500

2000

2500

2000

3000

330.0

180.0

178.0

330.0

180.0

12.4

16.4

8.4

6.4

8.35

3.2

2.4

6.4

8.35

6.4

8.35

7.0

3.2

5.2

6.6

3.2

2.5

5.2

6.6

5.2

6.6

3.6

3.2

2.1

2.4

1.4

1.2

2.1

2.4

2.1

2.4

1.6

1.4

8.0

12.0

4.0

8.0

12.0

8.0

12.0

8.0

4.0

12.0

16.0

8.0

TL081CPSR

TL081HIDBVR

TL081HIDCKR

TL081HIDR

TL081IDR

DBV

DCK

SOT-23

SC70

SOIC

9.0

8.0

12.4

16.4

12.4

16.4

12.4

8.4

12.0

16.0

12.0

16.0

12.0

8.0

TL082ACDR

TL082ACPSR

TL082BCDR

TL082CDR

SOIC

TL082CDR

TL082CPSR

TL082CPWR

TL082HIDDFR

DDF

TSSOP

SOT-

23-THIN

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Oct-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TL082IDR

SOIC

TSSOP

SOIC

2500

2000

2500

2000

2500

2000

2500

2000

2500

330.0

12.4

16.4

12.4

16.4

12.4

16.4

6.4

7.0

6.5

8.2

6.5

8.2

6.9

6.5

6.9

6.5

5.2

3.6

9.0

10.5

9.0

10.5

5.6

9.0

5.6

9.0

2.1

1.6

2.1

2.5

2.1

2.5

1.6

2.1

1.6

2.1

8.0

12.0

8.0

12.0

8.0

12.0

16.0

12.0

16.0

12.0

16.0

TL082IPWR

TL084ACDR

TL084ACNSR

TL084BCDR

TL084CDR

SOIC

TL084CDR

TL084CDRG4

TL084CNSR

TL084CPWR

TL084HIDR

TL084HIPWR

TL084IDR

TSSOP

SOIC

TSSOP

SOIC

TL084QDR

TL084QDRG4

*All dimensions are nominal

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Oct-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TL081ACDR

TL081BCDR

TL081CDR

SOIC

2500

2000

3000

2500

2000

2500

2000

3000

2500

2000

2500

2000

2500

2000

2500

2000

2500

340.5

853.0

210.0

190.0

853.0

340.5

853.0

340.5

853.0

340.5

853.0

210.0

853.0

340.5

853.0

340.5

853.0

340.5

853.0

340.5

853.0

340.5

350.0

336.1

449.0

185.0

190.0

449.0

336.1

449.0

336.1

449.0

336.1

449.0

185.0

449.0

336.1

449.0

336.1

449.0

336.1

449.0

336.1

449.0

336.1

350.0

25.0

35.0

30.0

35.0

25.0

35.0

25.0

35.0

25.0

35.0

25.0

35.0

32.0

35.0

32.0

35.0

32.0

35.0

32.0

43.0

TL081CPSR

TL081HIDBVR

TL081HIDCKR

TL081HIDR

TL081IDR

DBV

DCK

SOT-23

SC70

SOIC

TL082ACDR

TL082ACPSR

TL082BCDR

TL082CDR

SOIC

TL082CDR

TL082CPSR

TL082CPWR

TL082HIDDFR

TL082IDR

DDF

TSSOP

SOT-23-THIN

SOIC

TSSOP

SOIC

TL082IDR

TL082IPWR

TL084ACDR

TL084ACNSR

TL084BCDR

TL084CDR

SOIC

TL084CDR

TL084CDRG4

TL084CNSR

TL084CPWR

TL084HIDR

TL084HIPWR

TL084IDR

TSSOP

SOIC

TSSOP

SOIC

TL084QDR

TL084QDRG4

Pack Materials-Page 3

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

1.9

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

J0014A

CDIP - 5.08 mm max height

CERAMIC DUAL IN LINE PACKAGE

4X .005 MIN

[0.13]

PIN 1 ID

(OPTIONAL)

.015-.060 TYP

[0.38-1.52]

12X .100

[2.54]

14X .014-.026

[0.36-0.66]

14X .045-.065

[1.15-1.65]

.010 [0.25] C A B

.754-.785

[19.15-19.94]

.245-.283

[6.22-7.19]

.2 MAX TYP

[5.08]

.13 MIN TYP

[3.3]

SEATING PLANE

.308-.314

[7.83-7.97]

AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15

TYP

14X .008-.014

[0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for

reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermitically sealed with a ceramic lid using glass frit.

4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.

5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com

EXAMPLE BOARD LAYOUT

J0014A

CDIP - 5.08 mm max height

CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP

[7.62]

SEE DETAIL B

SEE DETAIL A

12X (.100 )

[2.54]

SYMM

14X ( .039)

[1]

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE: 5X

.002 MAX

[0.05]

ALL AROUND

(.063)

[1.6]

METAL

(

.063)

[1.6]

SOLDER MASK

OPENING

METAL

.002 MAX

[0.05]

ALL AROUND

SOLDER MASK

OPENING

(R.002 ) TYP

[0.05]

DETAIL A

DETAIL B

SCALE: 15X

13X, SCALE: 15X

4214771/A 05/2017

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.280 (7,11)

0.245 (6,22)

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

6X 0.65

3.1

2.9

NOTE 3

1.95

0.30

0.19

4.5

4.3

1.2 MAX

0.1

C A

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

TYP

SYMM

6X (0.65)

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

SYMM

6X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

6X 0.65

2.95

2.85

NOTE 3

1.95

0.4

0.2

0.1

C A

1.65

1.55

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

8X (0.45)

SYMM

6X (0.65)

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8X (0.45)

SYMM

6X (0.65)

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TL084HIDYYR [TI]

相关型号：

TL084HIPWR

TL084I

TL084ID

TL084ID

TL084IDE4

TL084IDG4

TL084IDR

TL084IDR

TL084IDRE4

TL084IDRG4

TL084IDT

TL084IJ