TL16C2550IPFBG4 [TI]
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS; 1.8 V至5 V双UART,具有16字节FIFO型号: | TL16C2550IPFBG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS |
文件: | 总47页 (文件大小:1091K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TL16C2550
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SLWS161D–JUNE 2005–REVISED OCTOBER 2006
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
FEATURES
•
•
•
False-Start Bit Detection
•
•
•
Programmable Auto-RTS and Auto-CTS
Complete Status Reporting Capabilities
In Auto-CTS Mode, CTS Controls Transmitter
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
•
•
Line Break Generation and Detection
Internal Diagnostic Capabilities:
•
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
– Loopback Controls for Communications
Link Fault Isolation
•
•
•
•
•
•
•
Capable of Running With All Existing
TL16C450 Software
– Break, Parity, Overrun, and Framing Error
Simulation
After Reset, All Registers Are Identical to the
TL16C450 Register Set
•
•
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With VCC = 5 V
•
•
Available in 48-Pin TQFP (PFB), 32-Pin QFN
(RHB), or 44-Pin PLCC (FN)(1) Packages
Up to 20-MHz Clock Rate for up to
1.25-Mbaud Operation With VCC = 3.3 V
Pin Compatible with TL16C752B (48-Pin
Package PFB)
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With VCC = 2.5 V
(1) Product Preview
Up to 10-MHz Clock Rate for up to 625-kbaud
Operation With VCC = 1.8 V
APPLICATIONS
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
•
•
•
•
•
•
Point-of-Sale Terminals
Gaming Terminals
Portable Applications
Router Control
Cellular Data
Factory Automation
•
•
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(216 - 1) and Generates an Internal 16 × Clock
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
DESCRIPTION
The TL16C2550 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two TL16C550D UARTs, each UART
having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock
source, otherwise they operate independently.
Another name for the uart function is Asynchronous
Communications Element (ACE), and these terms
will be used interchangeably. The bulk of this
document describes the behavior of each ACE, with
the understanding that two such devices are
incorporated into the TL16C2550.
•
•
•
5-V, 3.3-V, 2.5-V, and 1.8-V Operation
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
•
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbit/s)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
TL16C2550
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SLWS161D–JUNE 2005–REVISED OCTOBER 2006
PFB PACKAGE
(TOP VIEW)
Each ACE is a speed and voltage range upgrade of
the TL16C550C, which in turn is a functional
upgrade of the TL16C450. Functionally equivalent to
the TL16C450 on power up or reset (single character
or TL16C450 mode), each ACE can be placed in an
alternate FIFO mode. This relieves the CPU of
excessive software overhead by buffering received
and to be transmitted characters. Each receiver and
transmitter store up to 16 bytes in their respective
FIFOs, with the receive FIFO including three
additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can
significantly reduce software overload and increase
system efficiency by automatically controlling serial
data flow using handshakes between the RTS#
output and CTS# input, thus eliminating overruns in
the receive FIFO.
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
D5
D6
1
2
D7
3
RXB
RXA
TXRDYB
TXA
4
5
6
TL16C2550PFB
7
8
TXB
9
OPB
CSA
CSB
NC
10
11
12
A1
A2
NC
Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem
and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial
conversions on data sent from its CPU after storing
the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each ACE includes complete modem control
capability and a processor interrupt system that can
be tailored to the application.
13 14 15 16 17 18 19 20 21 22 23 24
NC−No internal connection
FN PACKAGE
(TOP VIEW)
Each ACE includes a programmable baud rate
generator capable of dividing a reference clock with
divisors from 1 to 65535, thus producing a 16×
internal reference clock for the transmitter and
receiver logic. Each ACE accommodates up to a
1.5-Mbaud serial data rate (24-MHz input clock). As
a reference point, that speed would generate a
667-ns bit time and a 6.7-µs character time (for 8,N,1
serial data), with the internal clock running at 24
MHz.
6
5
4
3
2
1 44 43 42 41 40
D5
D6
D7
39
38
37
RESET
DTRB
DTRA
7
8
9
RXB
RXA
10
11
12
13
36
35
RTSA
OPA
TL16C2550FN
TXRDYB
TXA
34
33
32
31
RXRDYA
INTA
TXB
INTB
A0
14
15
Each ACE has a TXRDY# and RXRDY# output that
can be used to interface to a DMA controller.
OPB
CSA
CSB
30
29
A1
A2
16
17
18 19 20 21 22 23 24 25 26 27 28
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RHB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
24
D6
D7
RESET
RTSA
INTA
INTB
A0
23
22
21
20
19
18
17
RXB
RXA
TXA
TXB
CSA
CSB
TL16C2550RHB
A1
A2
NC
NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA, DSRB, RIA, RIB, CDA, CDB inputs, and OPA, OPB,
RXRDYA, RXRDYB, TXRDYA, TXRDYB, DTRA, DTRB outputs.
TL16C2550 Block Diagram
UART Channel A
TXA
A2 − A0
D7 − D0
CSA
Tx
Rx
16 Byte Tx FIFO
UART Regs
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
CSB
IOR
BAUD
Rate
Gen
16 Byte Rx FIFO
RXA
IOW
INTA
INTB
Data Bus
Interface
UART Channel B
16 Byte Tx FIFO
TXRDYA
TXRDYB
RXRDYA
RXRDYB
TXB
Tx
Rx
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
UART Regs
BAUD
Rate
Gen
RESET
16 Byte Rx FIFO
RXB
Crystal
OSC
Buffer
XTAL1
XTAL2
V
CC
GND
3
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SLWS161D–JUNE 2005–REVISED OCTOBER 2006
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
A0
PFB NO.
FN NO.
31
RHB NO.
28
27
26
20
19
18
I
I
I
Address 0 select bit. Internal registers address selection
Address 1 select bit. Internal registers address selection
Address 2 select bit. Internal registers address selection
A1
30
A2
29
Carrier detect (active low). These inputs are associated with individual
UART channels A and B. A low on these pins indicates that a carrier has
been detected by the modem for that channel. The state of these inputs is
reflected in the modem status register (MSR).
CDA, CDB
CSA, CSB
40, 16
10, 11
42, 21
16, 17
–
I
I
Chip select A and B (active low). These pins enable data transfers between
the user CPU and the TL16C2550 for the channel(s) addressed. Individual
UART sections (A, B) are addressed by providing a low on the respective
CSA and CSB pins.
7, 8
Clear to send (active low). These inputs are associated with individual
UART channels A and B. A logic low on the CTS pins indicates the modem
or data set is ready to accept transmit data from the 2550. Status can be
tested by reading MSR bit 4. These pins only affect the transmit and
receive operations when auto CTS function is enabled through the
enhanced feature register (EFR) bit 7, for hardware flow control operation.
CTSA,
CTSB
38, 23
40, 28
25, 16
I
D0-D4
D5-D7
44 - 48
1 - 3
2 - 6
7 - 9
27 - 31
32, 1, 2
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
I/O
I
Data set ready (active low). These inputs are associated with individual
UART channels A and B. A logic low on these pins indicates the modem or
data set is powered on and is ready for data exchange with the UART. The
state of these inputs is reflected in the modem status register (MSR).
DSRA,
DSRB
39, 20
41, 25
–
Data terminal ready (active low). These outputs are associated with
individual UART channels A and B. A logic low on these pins indicates that
theTLl16C2550 is powered on and ready. These pins can be controlled
through the modem control register. Writing a 1 to MCR bit 0 sets the DTR
output to low, enabling the modem. The output of these pins is high after
writing a 0 to MCR bit 0, or after a reset.
DTRA,
DTRB
34, 35
17
37, 38
22
–
O
O
GND
13
Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel
interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to
a logic 1, interrupt sources are enabled in the interrupt enable register
(IER). Interrupt conditions include: receiver errors, available receiver buffer
data, available transmit buffer space or when a modem status flag is
detected. INTA-B are in the high-impedance state after reset.
INTA,
INTB
30, 29
33, 32
22, 21
Read input (active low strobe). A high to low transition on IOR will load the
contents of an internal register defined by address bits A0-A2 onto the
TL16C2550 data bus (D0-D7) for access by an external CPU.
IOR
19
15
24
14
I
I
Write input (active low strobe). A low to high transition on IOW will transfer
the contents of the data bus (D0-D7) from the external CPU to an internal
register that is defined by address bits A0-A2 and CSA and CSB
IOW
NC
20
–
12
12, 24, 25,
37
9, 17
No internal connection
User defined outputs. This function is associated with individual channels A
and B. The state of these pins is defined by the user through the software
settings of the MCR register, bit 3. INTA-B are set to active mode and OP
to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the
3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3,
modem control register (MCR bit 3). The output of these two pins is high
after reset.
OPA, OPB
RESET
32, 9
35, 15
–
O
Reset. RESET will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during reset
time. See TL16C2550 external reset conditions for initialization details.
RESET is an active-high input.
36
39
24
I
4
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
PFB NO.
FN NO.
RHB NO.
Ring indicator (active low). These inputs are associated with individual
UART channels A and B. A logic low on these pins indicates the modem
has received a ringing signal from the telephone line. A low to high
transition on these input pins generates a modem status interrupt, if
enabled. The state of these inputs is reflected in the modem status register
(MSR)
RIA, RIB
41, 21
43, 26
–
I
Request to send (active low). These outputs are associated with individual
UART channels A and B. A low on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a 1 in the modem control
register (MCR bit 1) sets these pins to low, indicating data is available.
After a reset, these pins are set to high. These pins only affects the
transmit and receive operation when auto RTS function is enabled through
the enhanced feature register (EFR) bit 6, for hardware flow control
operation.
RTSA,
RTSB
33, 22
36, 27
11, 10
23, 15
O
Receive data input. These inputs are associated with individual serial
channel data to the 2550. During the local loopback mode, these RX input
pins are disabled and TX data is internally connected to the UART RX input
internally.
RXA, RXB
5, 4
4, 3
I
Receive ready (active low). RXRDY A and B goes low when the trigger
level has been reached or a timeout interrupt occurs. They go high when
the RX FIFO is empty or there is an error in RX FIFO.
RXRDYA,
RXRDYB
31, 18
7, 8
34, 23
13, 14
–
O
O
Transmit data. These outputs are associated with individual serial transmit
channel data from the 2550. During the local loopback mode, the TX input
pin is disabled and TX data is internally connected to the UART RX input.
TXA, TXB
5, 6
Transmit ready (active low). TXRDY A and B go low when there are at least
a trigger level numbers of spaces available. They go high when the TX
buffer is full.
TXRDYA,
TXRDYB
43, 6
42
1, 12
44
–
O
I
VCC
26
Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an
external clock input. A crystal can be connected between XTAL1 and
XTAL2 to form an internal oscillator circuit (see Figure 14). Alternatively, an
external clock can be connected to XTAL1 to provide custom data rates.
XTAL1
13
14
18
19
10
11
I
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is
used as a crystal oscillator output or buffered a clock output.
XTAL2
O
Detailed Description
Autoflow Control (see Figure 1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
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ACE1
ACE2
Parallel
RX
TX
Serial to
Parallel
to Serial
RCV
FIFO
XMT
FIFO
RTS
CTS
Flow
Flow
Control
Control
D7−D0
D7−D0
TX
RX
Parallel
to Serial
Serial to
Parallel
XMT
FIFO
RCV
FIFO
CTS
RTS
Flow
Flow
Control
Control
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-CTS (See Figure 2)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 1). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.
Auto-RTS (See Figure 3 and Figure 4)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 2), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because
it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 3), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.
Enabling Autoflow Control and Auto-CTS
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a
1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem
control register should be cleared (this assumes that a control signal is driving CTS).
Auto-CTS and Auto-RTS Functional Timing
Start Bits 0−7
Start Bits 0−7
Start Bits 0−7
Stop
Stop
Stop
SOUT
CTS
Figure 2. CTS Functional Timing Waveforms
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Start
Byte N
Start Byte N+1
Start
Byte
Stop
Stop
Stop
SIN
RTS
RD
(RD RBR)
1
2
N
N+1
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
Byte 14
Byte 15
Start Byte 16 Stop
Start Byte 18 Stop
SIN
RTS Released After the
First Data Bit of Byte 16
RTS
RD
(RD RBR)
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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S
e
l
Receiver
FIFO
8
Internal
e
8
Data Bus
c
t
Receiver
Shift
Register
3 −1
48−44
5,4
RXA, B
Data
Bus
Receiver
Buffer
D(7−0)
Buffer
Register
13
Crystal
OSC
Buffer
XTAL1
XTAL2
Receiver
Timing and
Control
14
Line
Control
Register
33, 22
RTSA, B
28
A0
A1
A2
27
26
Divisor
Latch (LS)
Baud
Generator
Divisor
Latch (MS)
Autoflow
Control
(AFE)
10
11
CSA
CSB
Transmitter
Timing and
Control
Line
Status
Register
Select
and
Control
Logic
36
19
RESET
IOR
Transmitter
FIFO
S
e
l
e
c
t
Transmitter
Shift
Register
Transmitter
Holding
Register
8
8
7, 8
15
43
TXA, B
IOW
TXRDYA
RXRDYA
TXRDYB
RXRDYB
31
6
Modem
Control
Register
8
38, 23
34, 35
39, 20
40, 16
41, 21
32, 9
CTSA, B
DTRA, B
DSRA, b
CDA,B
18
Modem
Control
Logic
Modem
Status
Register
8
30, 29
RIA, B
INTA, B
OPA, B
Interrupt
Enable
Register
Interrupt
Control
Logic
8
42
17
V
CC
Power
Supply
GND
Interrupt
Identification
Register
8
FIFO
Control
Register
A. Pin numbers shown are for 48-pin TQFP PFB package.
Figure 5. Functional Block Diagram
8
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
(2)
Supply voltage range, VCC (see
)
-0.5 V to 7 V
-0.5 V to 7 V
-0.5 V to 7 V
0°C to 70°C
-40°C to 85°C
-65°C to 150°C
260°C
Input voltage range at any input, VI
Output voltage range, VO
Operating free-air temperature, TA, TL16C2550
Operating free-air temperature, TA, TL16C2550I
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS
.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
1.8 V ±10%
MIN
1.62
0
NOM
MAX
1.98
VCC
1.98
0.4
UNIT
V
VCC
VI
Supply voltage
1.8
Input voltage
V
VIH
VIL
VO
IOH
IOL
High-level input voltage
Low-level input voltage
Output voltage
1.4
-0.3
0
V
V
VCC
0.5
V
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
mA
mA
MHz
1
10
2.5 V ±10%
MIN
2.25
0
NOM
MAX
2.75
VCC
2.75
0.6
VCC
1
UNIT
V
VCC
VI
Supply voltage
2.5
Input voltage
V
VIH
VIL
VO
IOH
IOL
High-level input voltage
Low-level input voltage
Output voltage
1.8
-0.3
0
V
V
V
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
mA
mA
MHz
2
16
3.3 V ±10%
MIN
NOM
MAX
3.6
UNIT
V
VCC
VI
Supply voltage
3
0
3.3
Input voltage
VCC
V
VIH
VIL
VO
IOH
IOL
High-level input voltage
Low-level input voltage
Output voltage
0.7VCC
V
0.3VCC
VCC
1.8
V
0
V
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
mA
mA
MHz
3.2
20
5 V ±10%
VCC
MIN
4.5
0
NOM
MAX
5.5
UNIT
V
Supply voltage
Input voltage
5
VI
VCC
V
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
5 V ±10%
MIN
2
NOM
MAX
UNIT
VIH
High-level input voltage
Low-level input voltage
Output voltage
All except XTAL1, XTAL2
XTAL1, XTAL2
V
0.7VCC
VIL
All except XTAL1, XTAL2
XTAL1, XTAL2
0.8
0.3VCC
VCC
4
V
VO
IOH
IOL
0
V
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
mA
mA
MHz
4
24
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
1.8 V Nominal
PARAMETER
TEST CONDITIONS
IOH = -0.5 mA
MIN
TYP(1)
MAX
UNIT
V
VOH
VOL
II
High-level output voltage(2)
Low-level output voltage(2)
Input current
1.3
IOL = 1 mA
0.5
10
V
VCC = 1.98 V, VSS = 0, VI = 0 to
1.98 V, All other terminals floating
µA
IOZ
High-impedance-state output current VCC = 1.98 V, VSS = 0, VI = 0 to
1.98 V, Chip slected in write mode
±20
1.5
µA
or chip deselcted
ICC
Supply current
VCC = 1.98 V, TA = 0°C, RXA, RXB,
DSRA, DSRB, CDA, CDB, CTSA,
CTSB, RIA, and RIB at 1.4 V, All
other inputs at 0.4 V, XTAL1 at 10
MHz, No load on outputs
mA
Ci(CLK)
CO(CLK)
CI
Clock input impedance
Clock output impedance
Input impedance
15
20
6
20
30
10
20
pF
pF
pF
pF
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals
grounded
CO
Output impedance
10
(1) All typical values are at VCC = 1.8 V and TA = 25°C.
(2) These parameters apply for all outputs except XTAL2.
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.5 V Nominal
PARAMETER
TEST CONDITIONS
IOH = -1 mA
MIN
TYP(1)
MAX
UNIT
V
VOH
VOL
II
High-level output voltage(2)
Low-level output voltage(2)
Input current
1.8
IOL = 2 mA
0.5
10
V
VCC = 2.75 V, VSS = 0, VI = 0 to
2.75 V, All other terminals floating
µA
IOZ
High-impedance-state output current VCC = 2.75 V, VSS = 0, VI = 0 to
2.75 V, Chip slected in write mode
±20
2.5
µA
or chip deselcted
ICC
Supply current
VCC = 2.75 V, TA = 0°C, RXA, RXB,
DSRA, DSRB, CDA, CDB, CTSA,
CTSB, RIA, and RIB at 1.8 V, All
other inputs at 0.6 V, XTAL1 at 16
MHz, No load on outputs
mA
(1) All typical values are at VCC = 2.5 V and TA = 25°C.
(2) These parameters apply for all outputs except XTAL2.
ADDED SPACE
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ELECTRICAL CHARACTERISTICS (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.5 V Nominal
PARAMETER
Clock input impedance
Clock output impedance
Input impedance
TEST CONDITIONS
MIN
TYP(1)
15
MAX
20
UNIT
pF
Ci(CLK)
CO(CLK)
CI
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals
grounded
20
30
pF
6
10
pF
CO
Output impedance
10
20
pF
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
3.3 V Nominal
PARAMETER
TEST CONDITIONS
IOH = -1.8 mA
MIN
TYP(1)
MAX
UNIT
V
VOH
VOL
II
High-level output voltage(2)
Low-level output voltage(2)
Input current
2.4
IOL = 3.2 mA
0.5
10
V
VCC = 3.6 V, VSS = 0, VI = 0 to
3.6 V, All other terminals floating
µA
IOZ
High-impedance-state output current VCC = 3.6 V, VSS = 0, VI = 0 to
3.6 V, Chip slected in write mode or
±20
4
µA
chip deselcted
ICC
Supply current
VCC = 3.6 V, TA = 0°C, RXA, RXB,
DSRA, DSRB, CDA, CDB, CTSA,
CTSB, RIA, and RIB at 2 V, All
other inputs at 0.8 V, XTAL1 at 20
MHz, No load on outputs
mA
Ci(CLK)
CO(CLK)
CI
Clock input impedance
Clock output impedance
Input impedance
15
20
6
20
30
10
20
pF
pF
pF
pF
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals
grounded
CO
Output impedance
10
(1) All typical values are at VCC = 3.3 V and TA = 25°C.
(2) These parameters apply for all outputs except XTAL2.
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
5 V Nomial
PARAMETER
TEST CONDITIONS
IOH = -4 mA
MIN
TYP(1)
MAX
UNIT
V
VOH
VOL
II
High-level output voltage(2)
Low-level output voltage(2)
Input current
4
IOL = 4 mA
0.4
10
V
VCC = 5.5 V, VSS = 0, VI = 0 to
5.5 V, All other terminals floating
µA
IOZ
High-impedance-state output current VCC = 5.5 V, VSS = 0, VI = 0 to
5.5 V, Chip slected in write mode or
±20
7.5
µA
chip deselcted
ICC
Supply current
VCC = 5.5 V, TA = 0°C, RXA, RXB,
DSRA, DSRB, CDA, CDB, CTSA,
CTSB, RIA, and RIB at 2 V, All
other inputs at 0.8 V, XTAL1 at 24
MHz, No load on outputs,
mA
Ci(CLK)
CO(CLK)
CI
Clock input impedance
Clock output impedance
Input impedance
15
20
6
20
30
10
20
pF
pF
pF
pF
VCC = 0, VSS = 0, f = 1 MHz,
TA = 25°C, All other terminals
grounded
CO
Output impedance
10
(1) All typical values are at VCC = 5 V and TA = 25°C.
(2) These parameters apply for all outputs except XTAL2.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LIMITS
ALT.
SYMBOL
TEST
CONDITIONS
PARAMETER
FIGURE
1.8 V
MIN MAX
1
2.5 V
3.3 V
5 V
MIN MAX
1
UNIT
MIN MAX MIN MAX
tw8
tw1
tw2
tcR
tcW
tw6
tw7
tSU3
th3
Pulse duration, RESET
tRESET
tXH
1
1
µs
ns
Pulse duration, clock high
Pulse duration, clock low
Cycle time, read (tw7 + td8 + th7
6
40
25
20
18
tXL
)
RC
WC
tIOW
tIOR
tDS
8
7
7
8
7
7
7
7
8
8
7
7
8
8
8
8
115
115
80
80
25
0
80
80
55
55
20
0
62
62
45
45
15
0
57
57
40
40
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycle time, write (tw6 + td5 + th4
)
Pulse duration,IOW
Pulse duration, IOR
Setup time, data valid before IOW↑
Hold time, CS valid afterIOW↑
tWCS
tWA
th4
Hold time, address valid after IOW↑
Hold time, data valid after IOW↑
Hold time, chip select valid after IOR↑
Hold time, address valid afterIOR↑
Delay time, CS valid before IOW↓
Delay time, address valid before IOW↓
Delay time, CS valid to IOR↓
20
15
0
15
10
0
10
5
10
5
th5
tDH
th6
tRCS
tRA
tCSW
tAW
tCSR
tAR
tRVD
tHZ
0
0
th7
20
0
15
0
10
0
10
0
td4
td5
15
0
10
0
7
7
td7
0
0
td8
Delay time, address valid to IOR↓
Delay time, IOR↓ to data valid
15
55
40
10
7
7
td10
td11
CL = 30 pF
CL = 30 pF
35
30
25
20
20
20
Delay time, IOR↑ to floating data
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RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
(1)
)
LIMITS
ALT.
SYMBOL
TEST
CONDITIONS
PARAMETER
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT
MIN MAX
MIN MAX
MIN MAX MIN MAX
td12
td13
Delay time, RCLK to sample
tSCD
tSINT
9
20
1
15
1
10
1
10
ns
Delay time, stop to set INT or read RBR to LSI
interrupt or stop to RXRDY↓
8, 9, 10,
11, 12
1
RCLK
cycle
td14
td26
td27
td28
td29
Delay time, read RBR/LSR to reset INT
tRINT
8, 9, 10,
11, 12
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
100
90
80
70
2
ns
Delay time, RCV threshold byte to RTS↑
19
19
20
20
baudout
cycles
Delay time, read of last byte in receive FIFO to
RTS↓
2
baudout
cycles
Delay time, first data bit of 16th character to RTS↑
2
baudout
cycles
Delay time, RBRRD low to RTS↓
2
baudout
cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
LIMITS
TEST
CONDITIONS
PARAMETER
ALT. SYMBOL
FIGURE
1.8 V
MIN
2.5 V
3.3 V
5 V
UNIT
MAX
MIN MAX
MIN MAX
MIN MAX
td15
td16
Delay time, initial write to transmit start
Delay time, start to INT
tIRS
tSTI
14
14
8
24
8
24
8
24
8
24 baudout
cycles
8
10
8
10
8
10
8
10 baudout
cycles
td17
td18
Delay time, IOW (WR THR) to reset INT
tHR
tSI
14
14
CL = 30 pF
70
34
60
34
50
34
50
ns
Delay time, initial write to INT (THRE(1)
)
16
30
16
20
16
10
16
10
34 baudout
cycles
td19
td20
td21
Delay time, read IOR↑ to reset INT (THRE(1)
Delay time, write to TXRDY inactive
Delay time, start to TXRDY active
)
tIR
14
CL = 30 pF
CL = 30 pF
CL = 30 pF
70
60
9
50
45
9
35
35
9
35
35
9
ns
ns
tWXI
tSXA
15, 16
15, 16
baudout
cycles
tSU4
td25
Setup time, CTS↑ before midpoint of stop bit
Delay time, CTS low to TX↓
18
18
ns
CL = 30 pF
24
24
24
24 baudout
cycles
(1) THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
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MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
LIMITS
ALT.
SYMBOL
TEST
CONDITIONS
PARAMETER
FIGURE
1.8 V
2.5 V
3.3 V
5 V
UNIT(1)
MIN MAX
MIN MAX
MIN MAX
MIN MAX
td22
td23
td24
Delay time, WR MCR to output
tMDO
tSIM
tRIM
17
17
17
CL = 30 pF
CL = 30 pF
CL = 30 pF
90
60
80
70
50
60
60
40
50
50
35
40
ns
ns
ns
Delay time, modem interrupt to set INT
Delay time, RD MSR to reset INT
(1) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
TYPICAL CHARACTERISTICS
0.5
Divisor = 1
1.1
V
T
= 1.8 V
= 22°C
V
T
= 2.5 V
= 22°C
CC
CC
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
A
A
Divisor = 1
0.4
0.3
0.2
0.1
0.0
Divisor = 2
Divisor = 3
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
Divisor = 10
Divisor = 255
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
14
16
f − Frequency − MHz
f − Frequency − MHz
G001
G002
Figure 6.
Figure 7.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Divisor = 1
Divisor = 1
V
T
= 3.3 V
= 22°C
V
T
= 5 V
= 22°C
CC
CC
A
A
Divisor = 2
Divisor = 3
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
Divisor = 10
Divisor = 255
0
2
4
6
8
10 12 14 16 18 20
0
4
8
12
16
20
24
f − Frequency − MHz
f − Frequency − MHz
G003
G004
Figure 8.
Figure 9.
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t
w2
t
w1
XTALI
Figure 10. Clock Input
A2−A0
50%
Valid
50%
t
d5
t
h4
CSA, CSB
IOW
50%
50%
t
h3
t
d4
50%
50%
t
w6
t
su3
t
h5
Valid Data
D7−D0
Figure 11. Write Cycle Timing Waveforms
A2−A0
50%
Valid
50%
th7
t
d8
CSA, CSB
IOR
50%
50%
t
h6
t
d7
t
w7
50%
50%
t
d10
t
d11
Valid Data
D7−D0
Figure 12. Read Cycle Timing Waveforms
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RCLK
(Internal)
t
d12
8 CLKs
Sample Clock
(Internal)
TL16C450 Mode:
RXA, RXB
Start
Data Bits 5−8
Parity
Stop
Sample Clock
INT
50%
50%
(data ready)
t
d13
t
d14
INT
(RCV error)
50%
50%
IOR
(read RBR)
50%
Active
IOR
(read LSR)
50%
Active
t
d14
Figure 13. Receiver Timing Waveforms
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RXA, RXB
Data Bits 5−8
Stop
Sample Clock
(Internal)
(FIFO at or above
Trigger Level
INT
(FCR6, 7 = 0, 0)
trigger level)
50%
50%
50%
(FIFO below
trigger level)
t
d13
(see Note A)
t
d14
INT
Line Status
50%
Interrupt (LSI)
t
d14
IOR
(RD LSR)
Active
50%
Active
IOR
(RD RBR)
50%
Figure 14. Receive FIFO First Byte (Sets DR Bit) Waveforms
RXA, RXB
Stop
Sample Clock
(Internal)
(FIFO at or above
trigger level)
Time-Out or
Trigger Level
Interrupt
50%
50%
(FIFO below
trigger level)
t
d13
(see Note A)
t
d14
50%
50%
Line Status
Top Byte of FIFO
Interrupt (LSI)
t
t
d14
d13
IOP
(RD LSR)
50%
50%
IOR
(RD RBR)
50%
Active
Active
Previous Byte
Read From FIFO
Figure 15. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
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IOR
(RD RBR)
50%
Active
See Note A
RXA, RXB
(first byte)
Stop
Sample Clock
(Internal)
t
d13
(see Note B)
t
d14
50%
50%
RXRDYA, RXRDYB
Figure 16. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOR
(RD RBR)
Active
50%
See Note A
RXA, RXB
(first byte that reaches
the trigger level)
Sample Clock
(Internal)
t
d13
(see Note B)
t
d14
50%
50%
RXRDYA, RXRDYB
Figure 17. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
Start
50%
Start
50%
Data Bits
50%
Parity
Stop
TXA, TXB
t
d15
t
d16
INT
(THRE)
50%
50%
50%
50%
t
d18
t
d17
t
d17
IOW
(WR THR)
50%
50%
50%
t
d19
IOR
50%
Figure 18. Transmitter Timing Waveforms
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Byte 1
50%
IOW
(WR THR)
Start
TXA, TXB
Data
Parity
Stop
50%
t
d21
t
d20
TXRDYA, TXRDYB
50%
50%
Figure 19. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Byte 16
IOW
50%
(WR THR)
Start
50%
TXA, TXB
Data
Parity
Stop
t
t
d21
d20
TXRDYA, TXRDYB
50%
50%
FIFO Full
Figure 20. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
IOW
(WR MCR)
50%
50%
t
d22
t
d22
RTSA, RTSB, DTRA,
DTRB, OPA, OPB
50%
50%
50%
CTSA, CTSB, DSRA,
DSRB, CDA, CDB
t
d23
INT
(modem)
50%
50%
50%
t
d24
IOR
(RD MSR)
50%
t
d23
RI
50%
Figure 21. Modem Control Timing Waveforms
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t
su4
CTSA, CTSB
50%
50%
t
d25
50%
TXA, TXB
Midpoint of Stop Bit
Figure 22. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
RXA, RXB
t
t
d27
d26
50%
50%
RTSA,
RTSB
50%
IOR
Figure 23. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Midpoint of Data Bit 0
15th Character
16th Character
RXA,
RXB
t
t
d29
d28
50%
50%
RTSA,
RTSB
50%
IOR
Figure 24. Auto-RTS Timing for RCV Threshold of 14 Waveforms
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APPLICATION INFORMATION
TXA, B
D7−D0
D7−D0
RXA, B
MEMR or I/OR
MEMW or I/OW
INTR
RTSA, B
DTRA, B
DSRA, B
CDA, B
CTSA, B
RIA, B
IOR
EIA-232-D
Drivers
and Receivers
IOW
INTA, B
RESET
A0
C
P
U
RESET
A0
A1
A2
A1
A2
B
u
s
TL16C2550
XTAL1
CS
CSA, B
3.072 MHz
33 pF
XTAL2
(Optional)
33 pF
Figure 25. Basic TL16C2550 Configuration
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APPLICATION INFORMATION (continued)
TL16C2550
XTAL1
14
15
33 pF
A0−A23
A0−A2
XTAL2
(Optional)
33 pF
10
11
CSA
CSB
Address
Decoder
CPU
34, 35
33, 22
20
1
DTRA, B
RTSA, B
36
RSI/ABT
D0−D15
RESET
D0−D7
D0−D7
Buffer
(Optional)
41, 21
40, 16
39, 20
38, 23
RIA, B
8
6
5
CDA, B
PHI1 PHI2
DSRA, B
CTSA, B
RSTO
RD
PHI1 PHI2
19
15
IOR
7, 8
5, 4
TCU
TXA, B
RXA, B
2
3
IOW
WR
30, 29
INTA, B
7
1
EIA-232-D
Connector
17
42
GND
(V
)
SS
V
CC
A. Pin numbers shown are for 48-pin TQFP PFB package.
Figure 26. Typical TL16C2550 Connection
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PRINCIPLES OF OPERATION
Table 1. Register Selection
Register Selection
DLAB(1)
A2
L
A1
L
A0
L
REGISTER
0
0
Receiver buffer (read), transmitter holding register (write)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write)
Line control register
L
L
H
L
X
X
X
X
X
X
X
1
L
H
H
H
L
L
L
L
H
L
H
H
H
H
L
Modem control register
L
H
L
Line status register
H
H
L
Modem status register
H
L
Scratch register
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
(1) The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
Interrupt enable register
RESET CONTROL
Master reset
RESET STATE
All bits cleared (0 - 3 forced and 4 - 7 permanent)
Interrupt identification register
Master reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits
4 - 5 are permanently cleared
FIFO control register
Line control register
Modem control register
Line status register
Master reset
Master reset
All bits cleared
All bits cleared
Master reset
All bits cleared (6 - 7 permanent)
Master reset
Bits 5 and 6 are set; all other bits are cleared
Modem status register
TX
Master reset
Bits 0 - 3 are cleared; bits 4 - 7 are input signals
Master reset
High
INT
Master reset, MCR3
Read LSR/MR
Read RBR/MR
Read IIR/write THR/MR
Output buffer tristated
Interrupt condition (receiver error flag)
Interrupt condition (received data available)
Low
Low
Low
Interrupt condition (transmitter holding register
empty)
Interrupt condition (modem status changes)
Read MSR/MR
Master reset
Low
OP
High
RTS
Master reset
High
DTR
Master reset
High
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
Master reset
No effect
No effect
No effect
No effect
All bits cleared
All bits cleared
Master reset
Master reset
Master reset
MR/FCR1 - FCR0/DFCR0
MR/FCR2 - FCR0/DFCR0
XMIT FIFO
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Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow Table 3.
Table 3. Summary of Accessible Registers
BIT
REGISTER ADDRESS
NO.
DLAB = 0
DLAB = 1
0
0
1
2
2
3
4
5
6
7
0
1
Receiver
Buffer
Register
(Read Only)
Transmitter
Holding
Register
(Write
Interrupt
Enable
Register
Interrupt
Ident
.Register
FIFO
Control
Register
Line
Control
Register
Modem
Control
Register
Line Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch (LSB)
Divisor
Latch
(MSB)
(Read Only) (WriteOnly)
Only)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
0
1
Data Bit 0(1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
0 if Interrupt
Pending
FIFO
Enable
Word
Length
Select Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data Ready
(DR)
Delta Clear
to Send
(∆CTS)
Bit 0
Bit 0
Bit 8
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt ID
Bit 1
Receiver
FIFO Reset
Word
Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(∆DSR)
Bit 1
Bit 1
Bit 9
Interrupt
(ETBEI)
2
3
Data Bit 2
Data Bit 3
Data Bit 2
Data Bit 3
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt ID
Bit 2
Transmitter
FIFO Reset
Number of
Stop Bits
(STB)
OUT1
Parity Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 3
Bit 2
Bit 3
Bit 10
Bit 11
Enable
Modem
Status
Interrupt ID
Bit 3(2)
DMA Mode
Select
Parity
Enable
(PEN)
OUT2,
OPcontrol,
INT Enable
Framing
Error (FE)
Delta Data
Carrier
Detect
Interrupt
(EDSSI)
(∆DCD)
4
5
Data Bit 4
Data Bit 5
Data Bit 4
Data Bit 5
0
0
0
Reserved
Reserved
Even Parity
Select
(EPS)
Loop
Break
Clear to
Bit 4
Bit 5
Bit 4
Bit 5
Bit 12
Bit 13
Interrupt (BI) Send (CTS)
0
Stick Parity
Autoflow
Control
Enable
(AFE)
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
6
7
Data Bit 6
Data Bit 7
Data Bit 6
Data Bit 7
0
0
FIFOs
Receiver
Trigger
(LSB)
Break
Control
0
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Bit 6
Bit 7
Bit 6
Bit 7
Bit 14
Bit 15
Enabled(2)
FIFOs
Enabled(2)
Receiver
Trigger
(MSB)
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO(2)
Data Carrier
Detect
(DCD)
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
•
•
•
Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
•
•
•
Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
Bits 4 and 5: These two bits are reserved for future use.
Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).
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Table 4. Receiver FIFO Trigger Level
BIT 7
BIT 6
RECEIVER FIFOTRIGGER LEVEL (BYTES)
0
0
1
1
0
1
0
1
01
04
08
14
FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. FIFO time-out interrupt occurs if the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of 160
ms at a 300-baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to
the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register empty interrupt [IIR (3 - 0) = 2] occurs when the transmit FIFO is empty. It is
cleared [IIR (3 -0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that
the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Because the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
•
•
LSR0 is set as long as one byte is in the receiver FIFO.
LSR1 - LSR 4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
•
•
LSR5 indicates when the THR is empty.
LSR6 indicates that both the THR and TSR are empty.
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•
LSR7 indicates whether any errors are in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the
receiver and transmitter FIFOs are still fully capable of holding characters.
Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of
this register are summarized in Table 3 and are described in the following bullets.
•
•
•
•
•
Bit 0: When set, this bit enables the received data available interrupt.
Bit 1: When set, this bit enables the THRE interrupt.
Bit 2: When set, this bit enables the receiver line status interrupt.
Bit 3: When set, this bit enables the modem status interrupt.
Bits 4 through 7: These bits are not used (always cleared).
Interrupt Identification Register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with the
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
•
•
•
•
Priority 1 - Receiver line status (highest priority)
Priority 2 - Receiver data ready or receiver character time-out
Priority 3 - Transmitter holding register empty
Priority 4 - Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in
its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 5. Detail on each bit is as follows:
•
Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending. If bit 0 is set, no interrupt is pending.
•
•
Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3.
Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
•
•
Bits 4 and 5: These two bits are not used (always cleared).
Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
Table 5. Interrupt Control Functions
INTERRUPT IDENTIFICATION
REGISTER
PRIORITY INTERRUPT TYPE
LEVEL
INTERRUPT SOURCE
NTERRUPT RESET
METHOD
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
1
0
1
1
0
None
1
None
Receiver line status Overrun error, parity
error, framing error, or break
None
None
Read the line status
register
interrupt
0
1
1
1
0
0
0
0
2
2
Received data
available
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode
Read the receiver buffer
register
Character time-out
indication
No characters have been removed Read the receiver buffer
from or input to the receiver FIFO
during the last four character times,
and there is at least one character
in it during this time
register
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Table 5. Interrupt Control Functions (continued)
INTERRUPT IDENTIFICATION
REGISTER
PRIORITY INTERRUPT TYPE
LEVEL
INTERRUPT SOURCE
NTERRUPT RESET
METHOD
BIT 3
BIT 2
BIT 1
BIT 0
0
0
1
0
3
4
Transmitter holding Transmitter holding
Read the interrupt
register empty
register empty
identification register (if
source of interrupt) or
writing into the transmitter
holding register
0
0
0
0
Modem status
Clear to send, data set ready, ring
indicator, or data carrier detect
Read the modem status
register
Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
•
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
BIT 1
BIT 0
WORD LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
•
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit
regardless of the number of stop bits selected. The number of stop bits generated in relation to word length
and bit 2 are shown in Table 7.
Table 7. Number of Stop Bits Generated
BIT 2
Word Length Selectedby Bits 1 and 2
Number of Stop Bits Generated
0
1
1
1
1
Any word length
5 bits
1
1 1/2
2
6 bits
7 bits
2
8 bits
2
•
•
•
•
•
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit
5 is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where TX is
forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effect
on the transmitter logic; it only effects TX.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
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Line Status Register (LSR)
NOTE:
The line status register is intended for read operations only; writing to this register is
not recommended outside of a factory testing environment.
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and described in the following bulleted list.
•
Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
NOTE:
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
•
Bit 1: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the
trigger level, an overrun error occurs only after the FIFO is full, and the next character has been completely
received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.
•
•
Bit 2: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU
reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the
FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the
FIFO.
Bit 3: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character did
not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO
mode, this error is associated with the particular character in the FIFO to which it applies. This error is
revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize
after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The
ACE samples this start bit twice and then accepts the input data.
•
•
Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was
held low for longer than a full-word transmission time. A full-word transmission time is defined as the total
time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of
the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a
break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after RX
goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to
accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE
is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading
of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when
at least one byte is written to the transmit FIFO.
•
•
Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO
mode, TEMT is set when the transmitter FIFO and shift register are both empty.
Bit 7: In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at
least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR
and there are no subsequent errors in the FIFO.
Modem Control Register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
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•
•
•
•
Bit 0: This bit (DTR) controls the DTR output.
Bit 1: This bit (RTS) controls the RTS output.
Bit 2: This bit (OUT1) is reserved for output and can also be used for loopback mode.
Bit 3: This bit (OUT2) controls the high-impedance state output buffer for the INT signal and the OP output.
When low, the INT signal is in a high-impedance state and OP is high. When high, the INT signal is enabled
and OP is low.
•
Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is
set, the following occurs:
– The transmitter TX is set high.
– The receiver RX is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs (CTS, DSR, CD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to the inactive (high) levels.
•
Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the
detailed description is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt's sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
Table 8. ACE Flow Configuration
MCR BIT 5 (AFE)
MCR BIT 1 (RTS)
ACE FLOW CONFIGURATION
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
1
1
0
1
0
X
Auto-RTS and auto-CTS disabled
Modem Status Register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
•
Bit 0: This bit is the change in clear-to-send (∆CTS) indicator. ∆CTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When ∆CTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled (∆CTS is cleared), no interrupt is generated.
•
•
•
Bit 1: This bit is the change in data set ready (∆DSR) indicator. ∆DSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When ∆DSR is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the
chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. ∆DCD indicates that the DCD input to
the chip has changed state since the last time it was read by the CPU. When ∆DCD is set and the modem
status interrupt is enabled, a modem status interrupt is generated.
•
•
Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
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•
•
Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic
test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
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Programmable Baud Generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16
MHz and divides it by a divisor in the range between 1 and (216 -1). The output frequency of the baud generator
is sixteen times (16 y) the baud rate. The formula for the divisor is:
divisor = XIN frequency input P (desired baud rate y 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When
either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072
MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clock
circuits).
Table 9. Baud Rates Using a 1.8432-MHz Crystal
DESIRED BAUD
RATE
DIVISOR USED TO GENERATE
16× CLOCK
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50
75
2304
1536
1047
857
768
384
192
96
110
0.026
0.058
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
64
58
0.69
48
32
24
16
12
6
3
2
2.86
Table 10. Baud Rates Using a 3.072-MHz Crystal
DESIRED BAUD
RATE
DIVISOR USED TO GENERATE
16× CLOCK
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50
75
3840
2560
1745
1428
1280
640
320
160
107
96
110
0.026
0.034
134.5
150
300
600
1200
1800
2000
2400
3600
0.312
0.628
80
53
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Table 10. Baud Rates Using a 3.072-MHz Crystal (continued)
DESIRED BAUD
RATE
DIVISOR USED TO GENERATE
16× CLOCK
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED AND ACTUAL
4800
7200
40
27
20
10
5
1.23
9600
19200
38400
V
CC
V
CC
Driver
XIN
XIN
External
Clock
C1
Crystal
R
P
Optional
Driver
RX2
XOUT
Optional
Clock
Output
Oscillator Clock
to Baud Generator
Logic
Oscillator Clock
to Baud Generator
Logic
XOUT
C2
Figure 27. Typical Clock Circuits
Table 11. Typical Crystal Oscillator Network
Crystal
3.072 MHz
1.8432 MHz
16 MHz
RP
RX2 (Optional)
1.5 kΩ
C1
C2
1 MΩ
1 MΩ
1 MΩ
10 - 30 pF
10 - 30 pF
33 pF
40 - 60 pF
40 - 60 pF
33 pF
1.5 kΩ
0 kΩ
Receiver Buffer Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is derived from the input clock divided by the programmed devisor. Receiver section control is a
function of the ACE line control register.
The ACE RSR receives serial data from RX. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
Scratch Register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.
Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is derived from the input clock divided by the programmed devisor. Transmitter section
control is a function of the ACE line control register.
32
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TL16C2550
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SLWS161D–JUNE 2005–REVISED OCTOBER 2006
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at TX. In the TL16C450 mode, if the THR is empty and the
transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
Table 12. Typical Package Thermal Resistance Data
Package
48-Pin TQFP PFB
32-Pin TQFP RHB
44-Pin PLCC FN
θJA = 50.1°C/W
θJA = xx°C/W
θJC = 21.1°C/W
θJC = xx°C/W
θJC = 22°C/W
θJA = 46.2°C/W
Table 13. Typical Package Weight
Package
Weight in Grams
48-Pin TQFP PFB
32-Pin TQFP RHB
44-Pin PLCC FN
0.2
0.15
0.5
33
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MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2008
PACKAGING INFORMATION
Orderable Device
TL16C2550IPFB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PFB
48
48
48
48
32
32
32
32
48
48
48
48
32
32
32
32
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TL16C2550IPFBG4
TL16C2550IPFBR
TL16C2550IPFBRG4
TL16C2550IRHB
TQFP
TQFP
TQFP
QFN
PFB
PFB
PFB
RHB
RHB
RHB
RHB
PFB
PFB
PFB
PFB
RHB
RHB
RHB
RHB
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TL16C2550IRHBG4
TL16C2550IRHBR
TL16C2550IRHBRG4
TL16C2550PFB
QFN
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TQFP
TQFP
TQFP
TQFP
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TL16C2550PFBG4
TL16C2550PFBR
TL16C2550PFBRG4
TL16C2550RHB
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TL16C2550RHBG4
TL16C2550RHBR
TL16C2550RHBRG4
QFN
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TL16C2550IPFBR
TL16C2550IRHBR
TL16C2550PFBR
TL16C2550RHBR
TQFP
QFN
PFB
RHB
PFB
RHB
48
32
48
32
1000
3000
1000
3000
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
9.6
5.3
9.6
5.3
9.6
5.3
9.6
5.3
1.5
1.5
1.5
1.5
12.0
8.0
16.0
12.0
16.0
12.0
Q2
Q2
Q2
Q2
TQFP
QFN
12.0
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL16C2550IPFBR
TL16C2550IRHBR
TL16C2550PFBR
TL16C2550RHBR
TQFP
QFN
PFB
RHB
PFB
RHB
48
32
48
32
1000
3000
1000
3000
346.0
340.5
346.0
340.5
346.0
333.0
346.0
333.0
33.0
20.6
33.0
20.6
TQFP
QFN
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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