TL16C550BFNR [TI]
Single UART with 16-Byte FIFOs 44-PLCC 0 to 70;
| 型号： | TL16C550BFNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single UART with 16-Byte FIFOs 44-PLCC 0 to 70 通信 |
| 文件： | 总31页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Capable of Running With All Existing
TL16C450 Software
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
After Reset, All Registers Are Identical to
the TL16C450 Register Set
In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
False-Start Bit Detection
Complete Status Reporting Capabilities
In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Line Break Generation and Detection
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 –1) and Generates an Internal 16×
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
16
Clock
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
†
Functionally identical to the TL16C450 on power up (character mode ), the TL16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
16
dividing a reference clock input by divisors from 1 to (2 –1) and producing a 16× clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
†
The TL16C550A can also be reset to the TL16C450 mode under software control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
N PACKAGE
(TOP VIEW)
FN PACKAGE
(TOP VIEW)
D0
D1
V
CC
RI
1
40
39
38
37
36
2
D2
DCD
DSR
CTS
3
6 5
4
3
2 1 44 43 42 41 40
D3
MR
4
D5
D6
7
39
38
37
36
35
34
33
D4
5
OUT1
DTR
8
D5
6
35 MR
9
D7
7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D6
OUT1
DTR
RTS
10
11
12
13
14
15
16
17
RCLK
SIN
8
D7
OUT2
NC
9
RCLK
SIN
RTS
NC
10
11
12
13
14
15
16
17
18
19
20
OUT2
INTRPT
RXRDY
A0
INTRPT
SOUT
CS0
SOUT
CS0
CS1
CS2
BAUDOUT
XIN
32 RXRDY
31
30
29
A0
A1
AS
CS1
CS2
A1
BAUDOUT
18 19 20 21 22 23 24 25 26 27 28
A2
ADS
XOUT
WR1
WR2
TXRDY
DDIS
RD2
NC–No internal connection
V
RD1
SS
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
block diagram
S
e
l
e
c
t
Receiver
FIFO
Internal
Data Bus
Receiver
10
8–1
Buffer
SIN
Line
Control
Register
Receiver
Buffer
Register
D7–D0
Register
Receiver
Timing and
Control
9
Line
Control
Register
RCLK
28
27
26
A0
A1
A2
Divisor
Latch (LS)
Baud
Generator
15
BAUDOUT
Divisor
12
13
14
25
35
21
22
18
19
23
24
16
17
29
Latch (MS)
CS0
CS1
CS2
ADS
MR
Line
Control
Register
Line
Status
Register
Select
and
Control
Logic
S
e
l
e
c
t
Transmitter
FIFO
RD1
RD2
Line
Control
Register
Transmitter
Holding
Register
11
SOUT
WR1
WR2
DDIS
32
Modem
Control
Register
RTS
TXRDY
XIN
36
CTS
33
DTR
XOUT
RXRDY
37
Modem
Control
Logic
Modem
Status
Register
DSR
38
DCD
39
RI
34
OUT1
40
20
31
V
CC
Power
Supply
OUT2
Interrupt
Enable
Register
Interrupt
Control
Logic
V
SS
30
INTRPT
Interrupt
I/O
Register
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the N package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Terminal Functions
TERMINAL
NAME NO.
A0
A1
A2
I/O
DESCRIPTION
†
28 [31]
27 [30]
26 [29]
I
Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description.
25 [28]
15 [17]
I
O
I
ADS
Addressstrobe. WhenADSis active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0,
CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in
the state they were in when the low-to-high transition of ADS occurred.
BAUDOUT
Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established by
the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.
CS0
CS1
CS2
12 [14]
13 [15]
14 [16]
Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description.
36 [40]
I
CTS
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.
D0 – D7
DCD
1 – 8
[2 – 9]
I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the
ACE and the CPU.
38 [42]
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCDchanges
state, an interrupt is generated.
DDIS
DSR
23 [26]
37 [41]
O
I
Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable
an external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.
33 [37]
30 [33]
35 [39]
O
O
DTR
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication.DTRisplacedintheactivestatebysettingtheDTRbitofthemodemcontrolregistertoahighlevel.
DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing
bit 0 (DTR) of the modem control register.
INTRPT
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditionsthatcauseaninterrupttobeissuedare:areceivererror,receiveddataisavailableortimeout(FIFOmode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.
MR
I
Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer
to Table 2.
34 [38]
31 [35]
O
OUT1
OUT2
Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
theirrespective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.
RCLK
9 [10]
I
I
Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
21 [24]
22 [25]
RD1
RD2
Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1 tied high).
†
Terminal numbers shown in brackets are for the FN package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Terminal Functions (continued)
TERMINAL
NAME NO.
RI
I/O
DESCRIPTION
†
39 [43]
I
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the RI input has transitioned from a low to a high
statesincethelastreadfromthemodemstatusregister.Ifthemodemstatusinterruptisenabledwhenthistransition
occurs, an interrupt is generated.
32 [36]
29 [32]
O
O
RTS
Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register.
RXRDY
Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. WhenoperatingintheTL16C450
mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between
CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character
in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there
are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3
= 1), when the trigger level or the timeout has been reached, RXRDY goes active (low); when it has been active
but there are no more characters in the FIFO or holding register, it goes inactive (high).
SIN
10 [11]
11 [13]
I
Serial input. SIN is a serial data input from a connected communications device.
SOUT
O
Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the
marking (high) state as a result of master reset.
24 [27]
O
TXRDY
Transmitter ready output. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles.
Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has
been filled.
V
CC
V
SS
40 [44]
20 [22]
5-V supply voltage
Supply common
18 [20]
19 [21]
I
WR1
WR2
Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU
is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer
data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1 tied high).
XIN
XOUT
16 [18] I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
17 [19]
†
Terminal numbers shown in brackets are for the FN package.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
†
absolute maximum ratings over free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range at any input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Operating free-air temperature range, T
Storage temperature range, T
Case temperature for 10 seconds, T : FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.75
2
5
5.25
CC
High-level input voltage, V
V
CC
0.8
V
IH
Low-level input voltage, V
–0.5
0
V
IL
Operating free-air temperature, T
70
°C
A
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
‡
V
V
High-level output voltage
Low-level output voltage
I
I
= –1 mA
= 1.6 mA
2.4
OH
OH
OL
‡
0.4
V
OL
V
= 5.25 V,
V
= 0,
CC
V = 0 to 5.25 V,
SS
All other terminals floating
I
Input leakage current
±10
µA
lkg
I
V
V
= 5.25 V,
V
= 0
CC
= 0 to 5.25 V,
SS
I
High-impedance output current
±20
µA
OZ
CC
O
Chip selected in write mode or chip deselected
V
CC
= 5.25 V, = 25°C,
T
A
SIN, DSR, DCD, CTS, and RI at 2 V,
I
Supply current
10
mA
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kbit/s
C
C
C
C
Clock input capacitance
Clock output capacitance
Input capacitance
15
20
6
20
30
10
20
pF
pF
pF
pF
XIN
V
= 0,
V
= 0,
SS
CC
All other terminals grounded,
f = 1 MHz,
XOUT
i
T
A
= 25°C
Output capacitance
10
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
These parameters apply for all outputs except XOUT.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT. SYMBOL
FIGURE
MIN
175
175
15
80
80
1
MAX
UNIT
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read (t
+ t + t
)
RC
cR
cW
w5
w6
w7
w8
su1
su2
su3
h1
w7 d8 d9
Cycle time, write (t
+ t + t
w6 d5 d6
)
WC
t
2, 3
2
Pulse duration, ADS low
Pulse duration, write strobe
Pulse duration, read strobe
Pulse duration, master reset
ADS
t
WR
tRD
3
t
MR
Setup time, address valid before ADS↑
Setup time, CS before ADS↑
t
2, 3
2, 3
2
15
15
15
0
AS
CS
DS
AH
CH
t
Setup time, data valid before WR1↓ or WR2↑
Hold time, address low after ADS↑
t
t
2, 3
2, 3
2
Hold time, CS valid after ADS↑
t
0
h2
Hold time, CS valid after WR1↑ or WR2↓
Hold time, address valid after WR1↑ or WR2↓
Hold time, data valid after WR1↑ or WR2↓
t
20
20
15
20
20
15
15
80
15
15
80
h3
WCS
§
t
2
h4
WA
t
2
h5
h6
DH
Hold time, CS valid after RD1↑
RD2↓
t
3
RCS
§
Hold time, address valid after RD1↑ or RD2↓
Delay time, CS valid before WR1↓ or WR2↑
Delay time, address valid before WR1↓ or WR2↑
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓
t
3
h7
RA
§
t
2
d4
CSW
§
t
2
d5
AW
WC
§
t
2
d6
§
Delay time, CS valid to RD1↓
↑
t
3
d7
CSR
§
Delay time, address valid to RD1↓ or RD2↑
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
t
3
d8
AR
tRC
3
d9
§
Applicable only when ADS is tied low.
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
f = 9 MHz maximum
f = 9 MHz maximum
MIN
50
MAX
UNIT
ns
t
t
t
t
t
Pulse duration, clock high
t
1
1
3
3
3
w1
XH
Pulse duration, clock low
t
50
ns
w2
XL
Delay time, RD1↓ or RD2↑ to data valid
Delay time, RD1↑ or RD2↓ to floating data
Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓
t
C
C
C
= 100 pF
= 100 pF
= 100 pF
60
60
60
ns
d10
d11
dis(R)
RVD
L
L
L
t
0
ns
HZ
t
ns
RDD
NOTE 2: Charge and discharge time is determined by V , V
, and external loading.
OL OH
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
f = 9 MHz, CLK ÷ 2,
t
t
Pulse duration, BAUDOUT low
t
1
80
ns
w3
LW
C
= 100 pF
L
f = 9 MHz, CLK ÷ 2,
Pulse duration, BAUDOUT high
t
1
100
ns
w4
HW
C
C
C
= 100 pF
= 100 pF
= 100 pF
L
L
L
t
t
Delay time, XIN↑ to BAUDOUT↑
Delay time, XIN↑↓ to BAUDOUT↓
t
1
1
125
125
ns
ns
d1
BLD
t
d2
BHD
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
t
t
t
Delay time, RCLK to sample clock
t
4
100
ns
d12
d13
d14
SCD
Delay time, stop to set RCV error interrupt or
read RBR to LSI interrupt or stop to
RXRDY↓
RCLK
cycles
t
4,5,6,7,8
1
SINT
Delay time, read RBR/LSR to reset interrupt
t
4,5,6,7,8
C
= 100 pF
150
ns
RINT
L
NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or
line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN MAX
UNIT
baudout
cycles
t
Delay time, INTRPT to transmit start
t
9
8
8
24
d15
IRS
baudout
cycles
t
t
t
Delay time, start to interrupt
t
9
9
9
8
140
32
d16
d17
d18
STI
Delay time, WR THR to reset interrupt
Delay time, initial write to interrupt (THRE)
t
C
= 100 pF
ns
HR
L
baudout
cycles
t
SI
16
t
t
Delay time, read IIR to reset interrupt (THRE)
Delay time, write to TXRDY inactive
t
9
C
C
= 100 pF
= 100 pF
140
195
ns
ns
d19
IR
L
L
t
10,11
d20
WXI
baudout
cycles
t
Delay time, start to TXRDY active
t
10,11
C
= 100 pF
8
d21
SXA
L
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
ALT. SYMBOL
FIGURE
12
TEST CONDITIONS
MIN
MAX
100
170
140
UNIT
ns
t
t
t
Delay time, WR MCR to output
t
C
C
C
= 100 pF
= 100 pF
= 100 pF
d22
d23
d24
MDO
L
L
L
Delay time, modem interrupt to set interrupt
Delay time, RD MSR to reset interrupt
t
12
ns
SIM
t
12
ns
RIM
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w1
2.4 V
0.4 V
2 V
XIN or RCLK
(9 MHz Max)
0.8 V
t
w2
N
XIN
t
d2
t
d1
BAUDOUT
(1/1)
t
d1
t
d2
BAUDOUT
(1/2)
t
w3
t
w4
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N > 3)
2 XIN Cycles
(N-2) XIN Cycles
Figure 1. Baud Generator Timing Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w5
50%
50%
50%
50%
ADS
t
su1
t
h1
†
Valid
A0–A2
50%
Valid
50%
t
su2
Valid
†
t
h2
†
CS0, CS1, CS2
50%
50%
Valid
t
h3
t
w6
t
d4
†
t
h4
†
t
d5
†
t
d6
WR1, WR2
D7–D0
50%
50%
Active
t
su3
t
h5
Valid Data
†
Applicable only when ADS is tied low.
Figure 2. Write Cycle Timing Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w5
50%
50%
50%
ADS
t
su1
t
h1
†
A0–A2
Valid
Valid
50%
su2
50%
50%
t
t
h2
†
50%
50%
Valid
CS0, CS1, CS2
Valid
50%
t
h6
t
w7
†
t
d7
†
t
h7
t †
d8
t
d9
50%
50%
RD1, RD2
DDIS
Active
t
dis(R)
t
dis(R)
50%
50%
t
d10
t
d11
Valid Data
D7–D0
†
Applicable only when ADS is tied low.
Figure 3. Read Cycle Timing Waveforms
11
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RCLK
t
d12
8 Clocks
Sample Clock
TL16C450 Mode:
SIN
Start
Data Bits 5–8
Parity
Stop
Sample Clock
INTRPT
(data ready)
50%
50%
t
d13
t
d14
INTRPT
(RCV error)
50%
50%
RD1, RD2
(read RBR)
50%
Active
RD1, RD2
(read LSR)
50%
Active
t
d14
Figure 4. Receiver Timing Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
SIN
Data Bits 5-8
Stop
Sample Clock
(FIFO at or Above
Trigger Level)
Trigger-Level
Interrupt
(FCR6, 7 = 0, 0)
(FIFO Below
Trigger Level)
t
d13
(see Note A)
t
d14
LSI Interrupt
t
d14
RD1
Active
(RD LSR)
Active
RD1
(RD RBR)
NOTE A: For a timeout interrupt, t
= 8 RCLKs.
d13
Figure 5. Receiver FIFO First Byte (Sets DR Bit) Waveforms
SIN
Stop
Sample Clock
(FIFO at or Above
Trigger Level)
Time Out or
Trigger Level
Interrupt
(FIFO Below
Trigger Level)
t
d13
(see Note A)
t
d14
LSI Interrupt
Top Byte of FIFO
t
t
d13
d14
RD1, RD2
(RDLSR)
RD1, RD2
(RDRBR)
Active
Active
Previous Byte
Read From FIFO
NOTE A: For a timeout interrupt, t
= 8 RCLKs.
d13
Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RD
(RD RBR)
Active
See Note A
SIN
(first byte)
Stop
Sample Clock
t
d13
(see Note B)
t
d14
RXRDY
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, t = 8 RCLKs.
d13
Figure 7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0)
RD
(RD RBR)
Active
See Note A
SIN
(first byte that reaches
the trigger level)
Sample Clock
t
d13
(see Note B)
t
d14
RXRDY
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, t = 8 RCLKs.
d13
Figure 8. Receiver Ready (RXRDY) Waveforms, FCR = 1 or FCR3 = 1 (mode 1)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Start
50%
Start
50%
Data Bits
Parity
Stop
t
SOUT
t
d15
d16
INTRPT
(THRE)
50%
50%
50%
50%
50%
t
d18
t
d17
t
d17
WR THR
50%
50%
50%
t
d19
RD IIR
50%
Figure 9. Transmitter Timing Waveforms
Byte #1
WR
(WR THR)
Start
SOUT
Data
Parity
Stop
t
t
d21
d20
TXRDY
Figure 10. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0)
Byte #16
WR
(WR THR)
Start
SOUT
Data
Parity
Stop
t
t
d21
d20
TXRDY
FIFO Full
Figure 11. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (mode 1)
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
WR
(WR MCR)
50%
50%
50%
t
d22
t
d22
RTS, DTR,
OUT1, OUT2
50%
50%
CTS, DSR, DCD
t
d23
INTRPT
(modem)
50%
50%
50%
t
d24
t
d23
RD2
(RD MSR)
50%
RI
50%
Figure 12. Modem Control Timing Waveforms
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
APPLICATION INFORMATION
SOUT
SIN
D7–D0
D7–D0
MEMR or I/OR
MEMW or I/ON
INTR
RTS
DTR
DSR
DCD
CTS
RI
RD1
EIA
WR1
232-D Drivers
and Receivers
INTRPT
RESET
A0
C
P
U
MR
A0
TL16C550A
(ACE)
A1
A2
A1
A2
B
u
s
ADS
WR2
RD2
XIN
3.072 MHz
L
CS
CS2
CS1
CS0
XOUT
BAUDOUT
RCLK
H
Figure 13. Basic TL16C550A Configuration
Receiver Disable
WR
WR1
TL16C550A
(ACE)
Microcomputer
System
Data Bus
Data Bus
D7–D0
8-Bit
Bus Transceiver
DDIS
Driver Disable
Figure 14. Typical Interface for a High-Capacity Data Bus
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
APPLICATION INFORMATION
†
Alternate
XTAL Control
TL16C550A
16
XIN
A16–A23
A16–A23
17
15
9
XOUT
12
13
14
BAUDOUT
RCLK
CS0
CS1
CS2
Address
Decoder
CPU
33
32
34
31
20
1
DTR
RTS
25
ADS
ADS
OUT1
OUT2
35
RSI/ABT
MR
A0–A2
AD0–AD7
Buffer
D0–D2
39
38
37
36
AD0–AD15
PHI1 PHI2
RI
8
6
5
DCD
DSR
CTS
ADS RSTO
RD
PHI1 PHI2
21
18
RD1
11
TCU
SOUT
2
3
WR
WR1
10
30
24
23
29
SIN
INTRPT
AD0–AD15
TXRDY
DDIS
22
19
RD2
7
1
WR2
RXRDY
EIA-232-D
Connector
20
40
GND
(V
SS)
5 V
(V
CC)
†
Terminal numbers for the TL16C550A are for the N package.
Figure 15. Typical TL16C550A Connection to a CPU
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
Table 1. Register Selection
†
A2
L
A1
L
A0
L
REGISTER
DLAB
0
0
Receiver buffer (read), transmitter holding register (write)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write)
Line control register
L
L
H
L
X
X
X
X
X
X
X
1
L
H
H
H
L
L
L
L
H
L
H
H
H
H
L
Modem control register
L
H
L
Line status register
H
H
L
Modem status register
H
L
Scratch register
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
†
Thedivisorlatchaccessbit(DLAB)isthemostsignificantbitofthelinecontrolregister.TheDLABsignal
is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
RESET
CONTROL
REGISTER/SIGNAL
Interrupt Enable Register
RESET STATE
Master Reset
All bits cleared (0–3 forced and 4–7 permanent)
Bit 0 is set, bits 1–3 are cleared, and bits 4–7 are permanently
cleared
Interrupt Identification Register
Master Reset
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Read LSR/MR
Read RBR/MR
All bits cleared
All bits cleared
All bits cleared (5–7 permanent)
Bits 5 and 6 are set, all other bits are cleared
Modem Status Register
SOUT
Bits 0–3 are cleared, bits 4–7 are input signals
High
Low
Low
INTRPT (receiver error flag)
INTRPT (received data available)
Read IR/Write
THR/MR
INTRPT (transmitter holding register empty)
Low
INTRPT (modem status changes)
Read MSR/MR
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Low
High
OUT2
High
RTS
High
DTR
High
OUT1
Scratch Register
No effect
No effect
No effect
No effect
Divisor Latch (LSB and MSB) Registers
Receiver Buffer Registers
Transmitter Holding Registers
MR/FCR1-FCR0/
RCVR FIFO
XMIT FIFO
All bits low
All bits low
∆FCR0
MR/FCR2-FCR0/
∆FCR0
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0
0 DLAB = 0
1 DLAB = 0
2
2
3
4
5
6
7
0 DLAB = 1
1 DLAB = 1
Receiver
Buffer
Register
(Read
Transmitter
Holding
Register
(Write
Interrupt
Ident.
Register
(Read
FIFO
Control
Register
(Write
Bit
No.
Interrupt
Enable
Register
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Divisor
Latch
(LSB)
Scratch
Register
Latch
(MSB)
Only)
Only)
Only)
Only)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Enable
Received
Data
Available
Interrupt
(ERB)
Word
Length
Select
Bit 0
Delta
Clear
to Send
Data
Terminal
Ready
(DTR)
”0“ If
Interrupt
Pending
Data
Ready
(DR)
FIFO
Enable
†
0
Data Bit 0
Data Bit 0
Bit 0
Bit 0
Bit 8
(∆CTS)
(WLS0)
Enable
Transmitter
Holding
Register
Empty
Delta
Data
Set
Word
Length
Select
Bit 1
Interrupt
ID
Bit 0
Receiver
FIFO
Reset
Request
to Send
(RTS)
Overrun
Error
(OE)
1
2
Data Bit 1
Data Bit 2
Data Bit 1
Data Bit 2
Bit 1
Bit 2
Bit 1
Bit 2
Bit 9
Ready
Interrupt
(ETBEI)
(WLS1)
(∆DSR)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Trailing
Edge Ring
Indicator
(TERI)
Number
of
Stop Bits
(STB)
Interrupt
ID
Bit (1)
Transmitter
FIFO
Reset
Parity
Error
(PE)
Out1
Bit 10
Delta
Data
Carrier
Detect
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit (2)
(Note 4)
DMA
Mode
Select
Parity
Enable
(PEN)
Framing
Error
(FE)
3
4
Data Bit 3
Data Bit 4
Data Bit 3
Data Bit 4
Out2
Loop
Bit 3
Bit 4
Bit 3
Bit 4
Bit 11
Bit 12
(∆DCD)
Even
Parity
Select
(EPS)
Clear
to
Send
(CTS)
Break
Interrupt
(BI)
0
0
0
Reserved
Reserved
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
(DSR)
Stick
Parity
5
6
Data Bit 5
Data Bit 6
Data Bit 5
Data Bit 6
0
0
0
0
Bit 5
Bit 6
Bit 5
Bit 6
Bit 13
Bit 14
FIFOs
Enabled
(Note 4)
Receiver
Trigger
(LSB)
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Set
Break
Divisor
Latch
Access
Bit
Error in
RCVR
FIFO
Data
Carrier
Detect
(DCD)
FIFOs
Enabled
(Note 4)
Receiver
Trigger
(MSB)
7
Data Bit 7
Data Bit 7
0
0
Bit 7
Bit 7
Bit 15
(Note 4)
(DLAB)
†
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
NOTE 4: These bits are always cleared in the TL16C450 mode.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
Bit 0: This bit (FCR0), when set, enables the transmit and receive FIFOs. Bit 0 must be set when other FCR
bits are written to or they are not programmed. Changing this bit clears the FIFOs.
Bit1: Thisbit(FCR1), whenset, clearsallbytesinthereceiverFIFOandclearsitscounter. Theshiftregister
is not cleared. The 1 that is written to this bit position is self clearing.
Bit2: Thisbit(FCR2), whenset, clearsallbytesinthetransmitFIFOandclearsitscounter. Theshiftregister
is not cleared. The 1 that is written to this bit position is self clearing.
Bit 3: When this bit (FCR0) and FCR3 are set, RXRDY and TXRDY change from mode 0 to mode 1.
Bits 4 and 5: These two bits (FCR4 and FCR5) are reserved for future use.
Bits 6 and 7: These two bits (FCR6 and FCR7) set the trigger level for the receiver FIFO interrupt.
Table 4 shows the trigger level for the receiver FIFO interrupt.
Table 4. Receiver FIFO Trigger Level
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
BIT 7
BIT 6
0
0
1
1
0
1
0
1
01
04
08
14
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1) receiver interrupts occur as
follows:
1. The receive data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared as soon as the FIFO drops below its programmed trigger level.
2. TheIIRreceivedataavailableindicationalsooccurswhentheFIFOtriggerlevelisreached, and, likethe
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06), as before, has higher priority than the received data
available (IIR = 04) interrupt.
4. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the
receiver FIFO. It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO timeout interrupts occur as follows:
21
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
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PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1. FIFO timeout interrupt occurs when the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character received was longer than 4 continuous character times ago (when
2 stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO was longer than 4 continuous character times
ago. This causes a maximum character received to interrupt issued delay of 160 ms at 300 baud
with 12-bit characters.
2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay
proportional to the baud rate).
3. When a timeout interrupt has occurred, it is cleared and the timer reset when the microprocessor reads
one character from the receiver FIFO.
4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur
as follows:
1. The THR interrupt (02) occurs when the transmit FIFO is empty. It is cleared as soon as the THR is
written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR
is read.
2. The transmit FIFO empty indications are delayed 1 character time minus the last stop bit time when the
following occurs: THRE = 1 and there have not been at least two bytes at the same time in the transmit
FIFO since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, if it is
enabled.
Character timeout interrupt and receiver FIFO trigger level interrupts have the same priority as the current
received data available interrupt. The transmit FIFO empty interrupt has the same priority as the current THRE
interrupt.
FIFO polled mode operation
When FCR0 is set, clearing IER0, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of
operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled
mode of operation.
In this mode, the user program checks the receiver and transmitter status using the LSR.
LSR0 is set as long as there is one byte in the receiver FIFO.
LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode and the IIR is not affected since IER2 = 0.
LSR5 indicates when the transmit FIFO is empty.
LSR6 indicates that both the transmit FIFO and shift registers are empty.
LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or timeout conditions indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the four types of interrupts (refer to Table 5) and the INTRPT output signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table3 and are described in the following bulleted list.
Bit 0: This bit, when set, enables the received data available interrupt.
Bit 1: This bit, when set, enables the THRE interrupt.
Bit 2: This bit, when set, enables the receiver line status interrupt.
Bit 3: This bit, when set, enables the modem status interrupt.
Bits 4 – 7: These bits in the IER are not used and are always cleared.
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character time out
Priority 3 –Transmitter holding register empty
Priority 4–Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt is defined
by the interrupt’s three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in
Table 3 and described in Table 4. Details of each bit are as follows:
Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 5.
Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a timeout interrupt is pending.
Bits 4 thru 5: These two bits are not used and are always cleared.
Bits 6 and 7: These two bits are always cleared in the TL16C450 mode. They are set when bit 0 of the FCR
is set.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER (IIR)
PRIORITY
LEVEL
INTERRUPT RESET
METHOD
INTERRUPT TYPE
INTERRUPT SOURCE
BIT 3 BIT 2 BIT 1 BIT 0
0
0
0
1
None
1
None
None
–
Overrun error, parity error,
framing error, or break interrupt (LSR)
Reading the line status register
0
1
1
0
Receiver line status
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode.
Reading the receiver buffer
register (RBR)
0
1
1
1
0
0
0
0
2
Received data available
No characters have been
removed from or input to the
receiver FIFO during the last
four character times and there
is at least one character in it
during this time
Character timeout
indication
Reading the receiver buffer
register (RBR)
2
Reading the interrupt
identification register (IIR) (if
source of interrupt) or writing
into the transmitter holding
register (THR)
Transmitter holding
register empty
Transmitter holding register
empty
0
0
0
0
1
0
0
0
3
4
Clear to send, data set ready,
ring indicator, or data carrier
detect
Reading the modem status
register (MSR)
Modem status
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
Bit 1
Bit 0
Word Length
5 Bits
0
0
1
1
0
1
0
1
6 Bits
7 Bits
8 Bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks the first stop bit only,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 7. Number of Stop Bits Generated
Word Length Selected
by Bits 1 and 2
Number of Stop
Bits Generated
Bit 2
0
1
1
1
1
Any word length
5 bits
1
1 1/2
2
6 bits
7 bits
2
8 bits
2
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in the transmitted data
between the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked.
When bit 3 is cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1’s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When
bit 5 is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e., a condition where the serial
output (SOUT) terminal is forced to the spacing (low) state. When bit 6 is cleared, the break condition is
disabled. The break condition has no affect on the transmitter logic; it only affects the serial output.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
†
line status register (LSR)
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are described in the following bulleted list and summarized in Table 3.
Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO and is cleared by reading all of the
data in the RBR or the FIFO.
‡
Bit 1 : This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator
is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been
completely received in the shift register. OE is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten but is not transferred to the FIFO.
†
‡
The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment
Bits 1 through 4 are the error conditions that produce a receiver line status Interrupt.
25
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PRINCIPLES OF OPERATION
†
line status register (LSR) (continued)
‡.
Bit 2 : This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top
of the FIFO.
‡
Bit 3 : This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE then samples this start bit twice and then accepts the input data.
‡
Bit 4 : This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the
total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When
break occurs, only the 0 character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the marking state and receives the next valid start bit.
Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the
transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.
Bit 7: In the TL16C550A, this bit is always cleared. In the TL16C450 mode, this bit is cleared. In the FIFO
mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when
the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its low state. When bit 0 is cleared, DTR goes high.
Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over
the DTR output.
Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR output.
†
‡
The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR output.
Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the
following occurs:
1. The SOUT is set high.
2. The SIN is disconnected.
3. The output of the TSR is looped back into the RSR input.
4. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
5. The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
6. The four modem control output terminals are forced to their inactive states (high).
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational but the modem control interrupt’s sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
Bit 5 – 7: These bits are permanently cleared.
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
Bit 0: This bit is the change in clear to send (∆CTS) indicator. Bit 0 indicates that the CTS input has changed
states since the last time it was read by the CPU . When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.
Bit 1: This bit is the change in data set ready (∆DSR) indicator. Bit 1 indicates that the DSR input has
changed states since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. Bit 3 indicates that the DCD input to
the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.
Bit 4: This bit is the compliment of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set,
bit 4 is equivalent to the MCR bit 1 (RTS).
Bit 5: This bit is the compliment of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
bit 5 is equivalent to the MCR bit 1 (DTR).
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Bit 6: This bit is the compliment of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6
is equivalent to the MCR bit 2 (OUT1).
Bit 7: This bit is the compliment of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
bit 7 is equivalent to the MCR bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz
16
and divides it by a divisor in the range between 1 and (2 –1). The output frequency of the baud generator is
16× the baud rate. The formula for the divisor is:
divisor # = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
beloadedduringinitializationoftheACEinordertoensuredesiredoperationofthebaudgenerator. Wheneither
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 8 and 9, which follow, illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz
and 3.072 MHz, respectively For baud rates of 38.4 kbit/s and below, the error obtained is very small. The
accuracy of the selected baud rate is dependent on the selected crystal frequency.
Refer to Figure 16 for examples of typical clock circuits.
Table 8. Baud Rates Using a 1.8432-MHz Crystal
DIVISOR USED
TO GENERATE
16× CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
2304
1536
1047
857
768
384
192
96
110
0.026
0.058
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
64
58
0.69
48
32
24
16
12
6
3
2
2.86
28
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 9. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED
TO GENERATE
16× CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
3840
2560
1745
1428
1280
640
320
160
107
96
110
0.026
0.034
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
0.312
80
53
0.628
1.23
40
27
20
10
5
V
CC
V
CC
Driver
XIN
XIN
External
Clock
C1
Crystal
R
p
Optional
Driver
RX2
XOUT
Optional
Clock
Output
Oscillator Clock
to Baud
Generator Logic
Oscillator Clock
to Baud
Generator Logic
XOUT
C2
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
R
RX2
C1
C2
P
3.1 MHz
1.8 MHz
1 MΩ
1.5 kΩ
1.5 kΩ
10–30 pF
10–30 pF
40–60 pF
40–60 pF
1 MΩ
Figure 16. Typical Clock Circuits
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACEs RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it
into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data
available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of
the RBR. in the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
scratch register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is suppled by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE line control register.
The ACE THR receives data off the internal data bus and, when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at the serial output (SOUT). In the TL16C450 mode, when the THR
is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
30
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