TL16C550D_技术文档

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

D

Programmable Auto-RTS and Auto-CTS

D

5-V, 3.3-V, and 2.5-V Operation

In Auto-CTS Mode, CTS Controls

Transmitter

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data

Set Interrupts Independently Controlled

In Auto-RTS Mode, RCV FIFO Contents and

Threshold Control RTS

Fully Programmable Serial Interface

Characteristics:

− 5-, 6-, 7-, or 8-Bit Characters

− Even-, Odd-, or No-Parity Bit Generation

and Detection

Serial and Modem Control Outputs Drive a

RJ11 Cable Directly When Equipment Is on

the Same Power Drop

D

Capable of Running With All Existing

TL16C450 Software

− 1-, 1 1/2-, or 2-Stop Bit Generation

− Baud Generation (dc to 1 Mbit/s)

After Reset, All Registers Are Identical to

the TL16C450 Register Set

D

False-Start Bit Detection

Complete Status Reporting Capabilities

Up to 24-MHz Clock Rate for up to

1.5-Mbaud Operation With V = 5 V

3-State Output TTL Drive Capabilities for

Bidirectional Data Bus and Control Bus

CC

Up to 20-MHz Clock Rate for up to

1.25-Mbaud Operation With V = 3.3 V

D

Line Break Generation and Detection

CC

Up to 16-MHz Clock Rate for up to 1-Mbaud

D

Internal Diagnostic Capabilities:

− Loopback Controls for Communications

Link Fault Isolation

− Break, Parity, Overrun, and Framing

Error Simulation

Operation With V = 2.5 V

CC

In the TL16C450 Mode, Hold and Shift

Registers Eliminate the Need for Precise

Synchronization Between the CPU and

Serial Data

D

Fully Prioritized Interrupt System Controls

D

Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1

Modem Control Functions (CTS, RTS, DSR,

DTR, RI, and DCD)

16

to (2 −1) and Generates an Internal 16×

Available in 48-Pin PT, 48-Pin PFB, and

32-Pin RHB Packages

Clock

Standard Asynchronous Communication

Bits (Start, Stop, and Parity) Added to or

Deleted From the Serial Data Stream

description

The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents)

of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the

TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the

TL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relieves

the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and

transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver

FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software

overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS

input signals.

The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheral

device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE

status at any time. The ACE includes complete modem control capability and a processor interrupt system that

can be tailored to minimize software management of the communications link.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of

dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal

transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates

up to a 1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is

6.7 µs (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550D and the TL16C550DI have been changed to

TXRDY and RXRDY, which provide signaling to a DMA controller.

PT/PFB PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

NC

MR

NC

D5

D6

1

2

OUT1

DTR

RTS

OUT2

INTRPT

RXRDY

A0

A1

A2

NC

3

D7

RCLK

NC

SIN

SOUT

CS0

4

5

6

7

8

9

10

11

12

CS1

CS2

BAUDOUT

13 14 15 16 17 18 19 20 21 22 23 24

NC−No internal connection

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

RHB PACKAGE

(TOP VIEW)

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

16

DSR

DCD

RI

NC

15

14

13

12

11

10

9

NC

RD1

V_SS

WR1

XOUT

XIN

V_CC

D0

D1

D2

D3

NC

1

2

3

4

5

6

7

8

NC−No internal connection

The TL16C550D is being made available in a reduced pin count package, the 32-pin RHB package. This is

accomplished by eliminating some signals that are not required for some applications. These include the CS0,

CS1, ADS, RD2, WR2, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, and BAUDOUT

output signals. There is an internal connection between BAUDOUT and RCLK.

All of the functionality of the TL16C550D is maintained in the RHB package.

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

detailed description

autoflow control (see Figure 1)

Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before

the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data

and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless

the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a

TLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds

the receiver FIFO read latency.

ACE1

ACE2

SIN

SOUT

CTS

Serial to

Parallel

to Serial

RCV

FIFO

XMT

FIFO

RTS

Flow

Control

D7−D0

SOUT

CTS

SIN

Parallel

to Serial

Serial to

Parallel

XMT

FIFO

RCV

FIFO

RTS

Flow

Control

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

auto-RTS (see Figure 1)

Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)

and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level

of 1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send

an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)

because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS

is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.

When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is

present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.

auto-CTS (see Figure 1)

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next

byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the

last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host

system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device

automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the

transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to

a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem

control register must be cleared (this assumes that a control signal is driving CTS).

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

auto-CTS and auto-RTS functional timing

Start Bits 0−7

Stop

SOUT

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does

not send the next byte.

C. When CTS goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

Start

Byte N

Start Byte N+1

Start

Byte

Stop

SIN

RTS

RD1

(RD RBR)

1

2

N

N+1

NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes

Byte 14

Byte 15

Start Byte 16 Stop

Start Byte 18 Stop

SIN

RTS Released After the

First Data Bit of Byte 16

RTS

RD1

(RD RBR)

NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the

sixteenth byte.

B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than

one byte of space available.

C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

functional block diagram (for PT and PFB packages)

S

e

l

Receiver

FIFO

8

Internal

Data Bus

e

c

t

8

Receiver

Shift

Register

4−2

47−43

7

SIN

Data

Bus

Receiver

Buffer

D(7−0)

Buffer

Register

5

RCLK

RTS

Receiver

Timing and

Control

Line

Control

Register

32

28

A0

A1

A2

27

26

Divisor

Latch (LS)

Baud

Generator

12

BAUDOUT

Divisor

9

Latch (MS)

CS0

CS1

Autoflow

Control

(AFE)

10

11

Transmitter

Timing and

Control

Line

Status

Register

CS2

24

35

19

ADS

Select

and

Control

Logic

MR

Transmitter

FIFO

S

e

l

RD1

20

16

17

22

RD2

e

c

t

Transmitter

Shift

Register

Transmitter

Holding

Register

8

SOUT

WR1

WR2

DDIS

TXRDY

XIN

Modem

Control

Register

8

23

14

15

29

38

33

39

40

41

34

31

CTS

DTR

XOUT

RXRDY

Modem

Control

Logic

Modem

Status

8

DSR

DCD

RI

Register

OUT1

OUT2

INTRPT

42

18

V

CC

Power

Supply

Interrupt

Enable

Register

Interrupt

Control

Logic

8

V

30

SS

Interrupt

Identification

Register

8

FIFO

Control

Register

6

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

functional block diagram (for RHB package)

S

e

l

e

c

t

Receiver

FIFO

8

Internal

Data Bus

8

Receiver

6

5−3, 1

32−29

Shift

SIN

Data

Bus

Receiver

Buffer

Register

D(7−0)

Buffer

Register

Receiver

Timing and

Control

Line

Control

Register

21

RTS

19

A0

A1

A2

18

17

Divisor

Latch (LS)

Baud

Generator

Divisor

Latch (MS)

Autoflow

Control

(AFE)

8

Transmitter

Timing and

Control

Line

Status

Register

CS2

Select

and

Control

Logic

23

14

MR

Transmitter

FIFO

S

e

l

RD1

e

c

t

Transmitter

Shift

Register

Transmitter

Holding

Register

8

7

12

SOUT

WR1

Modem

Control

Register

8

24

22

25

26

27

10

11

CTS

DTR

DSR

DCD

RI

XIN

XOUT

Modem

Control

Logic

Modem

Status

Register

8

28

13

V

CC

Power

Supply

Interrupt

Enable

Register

Interrupt

Control

Logic

8

V

20

SS

INTRPT

Interrupt

Identification

Register

8

FIFO

Control

Register

7

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

Terminal Functions (for PT and PFB packages)

TERMINAL

NAME NUMBER

A0

A1

A2

I/O

DESCRIPTION

28

27

26

Register select. A0−A2 are used during read and write operations to select the ACE register to read from or

write to. See Table 1 for register addresses, and see the ADS description.

I

Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal select

logic directly; when ADS is high, the register select and chip select signals are held at the logic levels they were

in when the low-to-high transition of ADS occurred.

ADS

24

12

I

O

I

Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established

by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.

BAUDOUT may also be used for the receiver section by tying this output to RCLK.

BAUDOUT

CS0

CS1

CS2

9

10

11

Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any of these

inputs are inactive, the ACE remains inactive (see the ADS description).

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem

status register. Bit 0 (∆CTS) of the modem status register indicates that CTS has changed states since the

last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels

and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to

control the transmitter.

CTS

38

I

D0

D1

D2

D3

D4

D5

D6

D7

43

44

45

46

47

2

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU.

I/O

3

4

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (∆DCD) of the modem status register indicates that DCD has changed states

since the last read from the modem status register. If the modem status interrupt is enabled when DCD

changes levels, an interrupt is generated.

DCD

DDIS

DSR

40

22

39

I

O

I

Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an

external transceiver.

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the

modem status register. Bit 1 (∆DSR) of the modem status register indicates DSR has changed levels since

the last read from the modem status register. If the modem status interrupt is enabled when DSR changes

levels, an interrupt is generated.

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish

communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR

is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the

DTR bit.

DTR

33

O

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed

out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT

is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

INTRPT

30

35

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals

(see Table 2).

MR

NC

I

1, 6, 13,

21, 25, 36,

37, 48

No connection

Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by setting

respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to inactive the

(high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2)

of the MCR.

OUT1

OUT2

34

31

O

I

RCLK

5

Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.

8

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

Terminal Functions (for PT and PFB packages) (continued)

TERMINAL

NAME NUMBER

I/O

DESCRIPTION

Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE is selected, the CPU

is allowed to read status information or data from a selected ACE register. Only one of these inputs is required

for the transfer of data during a read operation; the other input must be tied to its inactive level (i.e., RD2 tied

low or RD1 tied high).

RD1

RD2

19

20

I

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem

status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high

level since the last read from the modem status register. If the modem status interrupt is enabled when this

transition occurs, an interrupt is generated.

RI

41

32

I

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS

is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either

as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the

auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.

RTS

O

Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating

in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control register bit 3

(FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer

DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which

multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0

or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register,

RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or holding

register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the

time-out has been reached, RXRDY goes active (low); when it has been active but there are no more

characters in the FIFO or holding register, it goes inactive (high).

RXRDY

29

O

SIN

7

8

I

Serial data input. SIN is serial data input from a connected communications device

Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set

to the marking (high) level as a result of master reset.

SOUT

O

Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,

one of two types of DMA signalling can be selected using FCR3. When operating in the TL16C450 mode, only

DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus

cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit

FIFO has been filled.

TXRDY

23

O

V

42

18

2.25-V to 5.5-V power supply voltage

Supply common

CC

SS

Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while the ACE is selected, the

CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required

to transfer data during a write operation; the other input must be tied to its inactive level (i.e., WR2 tied low or

WR1 tied high).

WR1

WR2

16

17

I

XIN

XOUT

14

15

I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

9

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

Terminal Functions (for RHB package)

TERMINAL

I/O

DESCRIPTION

NAME

NUMBER

A0

A1

A2

19

18

17

Register select. A0−A2 are used during read and write operations to select the ACE register to read from or

write to. See Table 1 for register addresses, and see the ADS description.

I

CS2

8

Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remains inactive.

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem

status register. Bit 0 (∆CTS) of the modem status register indicates that CTS has changed states since the

last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels

and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to

control the transmitter.

CTS

24

I

D0

D1

D2

D3

D4

D5

D6

D7

29

30

31

32

1

3

4

5

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU.

I/O

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (∆DCD) of the modem status register indicates that DCD has changed states

since the last read from the modem status register. If the modem status interrupt is enabled when DCD

changes levels, an interrupt is generated.

DCD

26

25

22

I

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the

modem status register. Bit 1 (∆DSR) of the modem status register indicates DSR has changed levels since

the last read from the modem status register. If the modem status interrupt is enabled when DSR changes

levels, an interrupt is generated.

DSR

I

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish

communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR

is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the

DTR bit.

DTR

O

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed

out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT

is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

INTRPT

20

23

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals

(see Table 2).

MR

NC

I

−

I

2, 9,

15, 16

No connection

Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to read status information

or data from a selected ACE register.

RD1

14

27

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem

status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high

level since the last read from the modem status register. If the modem status interrupt is enabled when this

transition occurs, an interrupt is generated.

RI

I

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS

is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either

as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the

auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.

RTS

21

O

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

Terminal Functions (for RHB package) (continued)

TERMINAL

NAME NUMBER

SIN

I/O

I

DESCRIPTION

6

7

Serial data input. SIN is serial data input from a connected communications device

Serial data output. SOUT is composite serial data output to a connected communication device. SOUT is set

to the marking (high) level as a result of master reset.

SOUT

O

V

28

13

2.25-V to 5.5-V power supply

Supply common, ground

CC

SS

Write input. When WR1 is active (low) while the ACE is selected, the CPU is allowed to write control words

or data into a selected ACE register.

WR1

12

I

XIN

XOUT

10

11

I

O

External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†

Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range at any input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Output voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Operating free-air temperature range, T , TL16C550D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

TL16C550DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: PT and PFB packages . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

.

SS

11

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

recommended operating conditions

2.5 V + 10%

MIN

2.25

0

NOM

MAX

UNIT

Supply voltage, V

2.5

2.75

V

CC

Input voltage, V

V

CC

I

High-level input voltage, V

1.8

2.75

0.6

V

IH

Low-level input voltage, V

−0.3

V

IL

Output voltage, V

0

V

CC

V

O

High-level output current, I (all outputs)

1

mA

MHz

OH

Low-level output current, I (all outputs)

2

OL

Oscillator/clock speed

16

3.3 V + 10%

MIN

3

NOM

MAX

UNIT

V

Supply voltage, V

3.3

3.6

CC

Input voltage, V

0

V

CC

V

I

High-level input voltage, V

0.7 V

V

IH

CC

Low-level input voltage, V

0.3 V

V

IL

CC

Output voltage, V

0

V

CC

V

O

High-level output current, I (all outputs)

1.8

3.2

20

mA

MHz

OH

Low-level output current, I (all outputs)

OL

Oscillator/clock speed

5 V + 10%

MIN

4.5

0

NOM

MAX

UNIT

V

Supply voltage, V

5

5.5

CC

Input voltage, V

V

CC

V

I

Except XIN

XIN

2

High-level input voltage, V

V

IH

0.7 V

CC

Except XIN

XIN

0.8

0.3 V

Low-level input voltage, V

IL

CC

Output voltage, V

0

V

CC

V

O

High-level output current, I (all outputs)

4

mA

MHz

OH

Low-level output current, I (all outputs)

OL

Oscillator/clock speed

24

12

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

2.5 V nominal

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

‡

V

High-level output voltage

Low-level output voltage

I

= −1 mA

1.8

OH

‡

= 2 mA

0.5

10

V

OL

V

= 3.6 V,

V

SS

= 0,

CC

I

l

Input current

µA

V = 0 to 3.6 V,

All other terminals floating

V = 0,

SS

I

V

= 3.6 V,

CC

= 0 to 3.6 V,

I

High-impedance-state output current

±20

O

OZ

Chip selected in write mode or chip deselect

V

CC

= 3.6 V, = 25°C,

T

A

SIN, DSR, DCD, CTS, and RI at 2 V,

All other inputs at 0.8 V, XTAL1 at 4 MHz,

I

Supply current

8

mA

CC

No load on outputs,

Baud rate = 50 kbit/s

V = 0,

SS

C

Clock input capacitance

Clock output capacitance

Input capacitance

15

20

30

10

20

pF

i(CLK)

V

CC

= 0,

20

6

o(CLK)

f = 1 MHz,

All other terminals grounded

T = 25°C,

A

i

Output capacitance

10

o

†

‡

All typical values are at V = 2.5 V and T = 25°C.

These parameters apply for all outputs except XOUT.

CC

A

3.3 V nominal

†

PARAMETER

TEST CONDITIONS

MIN TYP

2.4

MAX

UNIT

V

‡

V

High-level output voltage

Low-level output voltage

I

= −1.8 mA

OH

‡

= 3.2 mA

0.5

10

V

OL

V

= 3.6 V,

V

SS

= 0,

CC

I

l

Input current

µA

V = 0 to 3.6 V,

All other terminals floating

V = 0,

SS

I

V

= 3.6 V,

CC

= 0 to 3.6 V,

I

High-impedance-state output current

±20

O

OZ

Chip selected in write mode or chip deselect

V

CC

= 3.6 V, = 25°C,

T

A

SIN, DSR, DCD, CTS, and RI at 2 V,

All other inputs at 0.8 V, XTAL1 at 4 MHz,

I

Supply current

8

mA

CC

No load on outputs,

Baud rate = 50 kbit/s

V = 0,

SS

C

Clock input capacitance

Clock output capacitance

Input capacitance

15

20

6

20

30

10

20

pF

i(CLK)

V

CC

= 0,

o(CLK)

f = 1 MHz,

All other terminals grounded

T = 25°C,

A

i

Output capacitance

10

o

†

‡

All typical values are at V = 3.3 V and T = 25°C.

These parameters apply for all outputs except XOUT.

CC

A

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

5 V nominal

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

‡

V

High-level output voltage

Low-level output voltage

I

= −4 mA

4.0

OH

‡

= 4 mA

0.4

10

V

OL

V

= 5.25 V,

V

SS

= 0,

CC

I

l

Input current

µA

V = 0 to 5.25 V,

All other terminals floating

I

V

= 5.25 V,

V

SS

= 0,

CC

= 0 to 5.25 V,

I

High-impedance-state output current

±20

O

OZ

Chip selected in write mode or chip deselect

V

CC

= 5.25 V, = 25°C,

T

A

SIN, DSR, DCD, CTS, and RI at 2 V,

All other inputs at 0.8 V, XTAL1 at 4 MHz,

I

Supply current

10

mA

CC

No load on outputs,

Baud rate = 50 kbit/s

V = 0,

SS

C

Clock input capacitance

Clock output capacitance

Input capacitance

15

20

30

10

20

pF

i(CLK)

V

CC

= 0,

20

6

o(CLK)

f = 1 MHz,

All other terminals grounded

T = 25°C,

A

i

Output capacitance

10

o

†

‡

All typical values are at V = 5 V and T = 25°C.

These parameters apply for all outputs except XOUT.

CC

A

14

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SLLS597C − APRIL 2004 − REVISED JUNE 2005

system timing requirements over recommended ranges of supply voltage and operating free-air

temperature

ALT. SYMBOL FIGURE TEST CONDITIONS

MIN

87

MAX

UNIT

ns

t

Cycle time, read (t + t + t )

d9

RC

cR

cW

w1

w2

w1

w2

w1

w2

w5

w6

w7

w8

su1

su2

su3

su4

h1

w7

d8

Cycle time, write (t + t + t )

d6

WC

87

ns

w6

d5

Pulse duration, clock high

Pulse duration, clock low

Pulse duration, clock high

Pulse duration, clock low

Pulse duration, clock high

Pulse duration, clock low

Pulse duration, ADS low

Pulse duration, WR

t

XH

f = 16 MHz Max,

= 2.5 V

5

25

20

18

ns

V

CC

t

XL

XH

f = 20 MHz Max,

= 3.3 V

V

CC

t

XL

XH

f = 24 MHz Max,

= 5 V

V

CC

t

XL

t

6, 7

6

9

40

1

ns

µs

ADS

t

WR

Pulse duration, RD

t

7

RD

Pulse duration, MR

t

MR

Setup time, address valid before ADS↑

Setup time, CS valid before ADS↑

t

AS

CS

DS

6, 7

8

ns

t

Setup time, data valid before WR1↑ or WR2↓

Setup time, CTS↑ before midpoint of stop bit

Hold time, address low after ADS↑

6

15

10

ns

17

t

AH

6, 7

6

0

ns

Hold time, CS valid after ADS↑

t

h2

CH

Hold time, CS valid after WR1↑ or WR2↓

Hold time, address valid after WR1↑ or WR2↓

Hold time, data valid after WR1↑ or WR2↓

Hold time, CS valid after RD1↑ or RD2↓

Hold time, address valid after RD1↑ or RD2↓

Delay time, CS valid before WR1↓ or WR2↑

Delay time, address valid before WR1↓ or WR2↑

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓

Delay time, CS valid to RD1↓ or RD2↑

Delay time, address valid to RD1↓ or RD2↑

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓

Delay time, RD1↓ or RD2↑ to data valid

Delay time, RD1↑ or RD2↓ to floating data

t

WCS

h3

10

t

h4

WA

t

6

7

5

10

20

ns

h5

DH

t

h6

RCS

t

h7

RA

†

t

d4

CSW

6

7

ns

†

t

d5

AW

WC

†

t

40

d6

†

t

d7

CSR

7

ns

†

t

d8

AR

tRC

7

40

ns

d9

t

C = 75 pF

L

45

20

d10

d11

RVD

t

HZ

C = 75 pF

L

†

Only applies when ADS is low

system switching characteristics over recommended ranges of supply voltage and operating

free-air temperature (see Note 2)

PARAMETER

ALT. SYMBOL

FIGURE TEST CONDITIONS

C = 75 pF

MIN

MAX

UNIT

t

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓

t

7

20

ns

dis(R)

RDD

L

NOTE 2: Charge and discharge times are determined by V , V , and external loading.

OL

OH

15

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ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

baud generator switching characteristics over recommended ranges of supply voltage and

operating free-air temperature, C_L= 75 pF (for PT and PFB packages only)

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

t

w3

t

w4

t

d1

t

d2

Pulse duration, BAUDOUT low

Pulse duration, BAUDOUT high

Delay time, XIN↑ to BAUDOUT↑

Delay time, XIN↑↓ to BAUDOUT↓

t

5

LW

f = 24 MHz, CLK ÷ 2,

CC

35

ns

V

= 5 V

t

HW

t

45

ns

BLD

t

BHD

receiver switching characteristics over recommended ranges of supply voltage and operating

free-air temperature (see Note 3)

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

t

Delay time, RCLK to sample

t

8

10

ns

d12

SCD

Delay time, stop to set INTRPT or read

RBR to LSI interrupt or stop to RXRDY↓

8, 9, 10,

11, 12

RCLK

cycle

t

1

d13

SINT

8, 9, 10,

11, 12

t

Delay time, read RBR/LSR to reset INTRPT

t

C = 75 pF

L

70

ns

d14

RINT

NOTE 3: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification

register or line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating

free-air temperature

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN MAX

UNIT

baudout

cycles

t

Delay time, initial write to transmit start

t

13

8

24

d15

IRS

baudout

cycles

t

Delay time, start to INTRPT

t

13

10

50

34

d16

d17

d18

STI

Delay time, WR1 (WR THR) to reset INTRPT

t

C = 75 pF

L

ns

HR

baudout

cycles

†

Delay time, initial write to INTRPT (THRE )

t

SI

16

†

Delay time, read IIR to reset INTRPT

(THRE )

t

13

C = 75 pF

35

9

ns

d19

d20

d21

IR

L

†

Delay time, write to TXRDY inactive

Delay time, start to TXRDY active

t

14,15

C = 75 pF

L

WXI

baudout

cycles

C = 75 pF

L

SXA

†

THRE = transmitter holding register empty; IIR = interrupt identification register.

16

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ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

modem control switching characteristics over recommended ranges of supply voltage and

operating free-air temperature, C_L= 75 pF

PARAMETER

Delay time, WR2 MCR to output

ALT. SYMBOL

FIGURE

16

MIN

MAX

50

UNIT

ns

t

MDO

d22

d23

d24

Delay time, modem interrupt to set INTRPT

Delay time, RD2 MSR to reset INTRPT

t

16

35

ns

SIM

RIM

t

16

40

ns

baudout

cycles

t

Delay time, CTS low to SOUT↓

17

18

19

24

2

d25

d26

d27

d28

d29

baudout

cycles

Delay time, RCV threshold byte to RTS↑

Delay time, read of last byte in receive FIFO to RTS↓

Delay time, first data bit of 16th character to RTS↑

Delay time, RBRRD low to RTS↓

baudout

cycles

2

baudout

cycles

2

baudout

cycles

2

17

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ꢊ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒꢒ ꢑꢍꢉ ꢄ ꢊꢀꢉ ꢐ ꢍꢋ ꢓꢁ ꢓꢒ ꢓꢍ ꢀ

ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

N

t

w2

w1

XIN

t

d2

t

d1

BAUDOUT

(1/1)

t

d1

t

d2

BAUDOUT

(1/2)

t

w3

t

w4

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N−2) XIN Cycles

Figure 5. Baud Generator Timing Waveforms (for PT and PFB Packages Only)

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋ ꢌꢍꢄꢎꢏ ꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒ ꢒꢑꢍ ꢉꢄꢊꢀ ꢉꢐ ꢍꢋ ꢓ ꢁꢓ ꢒ ꢓꢍ ꢀ

ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

t

w5

‡

50%

ADS

t

su1

t

h1

†

A0−A2

50%

Valid

50%

t

su2

t

h2

‡

†

CS0 , CS1 , CS2

50%

Valid

t

h3

t

w6

t

†

d4

t

h4

t

d5

t

d6

‡

WR1, WR2

50%

Active

t

su3

t

h5

Valid Data

D7−D0

†

Applicable only when ADS is low

The ADS, CS0, CS1 and WR2 signals are applicable only to the PT and PFB packages.

‡

Figure 6. Write Cycle Timing Waveforms

19

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ꢊ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒꢒ ꢑꢍꢉ ꢄ ꢊꢀꢉ ꢐ ꢍꢋ ꢓꢁ ꢓꢒ ꢓꢍ ꢀ

ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

t

w5

50%

‡

50%

ADS

t

su1

t

h1

†

A0−A2

Valid

50%

t

su2

t

h2

‡

†

50%

Valid

CS0 , CS1 , CS2

Valid

50%

t

h6

t

w7

†

t

†

d7

t

h7

†

t

d8

t

d9

‡

50%

RD1, RD2

Active

50%

t

dis(R)

t

dis(R)

‡

DDIS

50%

t

d10

t

d11

D7−D0

Valid Data

†

Applicable only when ADS is low

The ADS, CS0, CS1, DDIS, and RD2 signals are applicable only to the PT and PFB packages.

‡

Figure 7. Read Cycle Timing Waveforms

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋ ꢌꢍꢄꢎꢏ ꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒ ꢒꢑꢍ ꢉꢄꢊꢀ ꢉꢐ ꢍꢋ ꢓ ꢁꢓ ꢒ ꢓꢍ ꢀ

ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

RCLK

t

d12

8 CLKs

Sample Clock

TL16C450 Mode:

SIN

Start

Data Bits 5−8

Parity

Stop

Sample Clock

INTRPT

(data ready)

50%

t

d13

t

d14

INTRPT

(RCV error)

50%

‡

RD1, RD2

50%

Active

(read RBR)

‡

RD1, RD2

50%

Active

(read LSR)

t

d14

‡

The RD2 signal is applicable only to the PT and PFB packages.

Figure 8. Receiver Timing Waveforms

21

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ꢊ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒꢒ ꢑꢍꢉ ꢄ ꢊꢀꢉ ꢐ ꢍꢋ ꢓꢁ ꢓꢒ ꢓꢍ ꢀ

ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

SIN

Data Bits 5−8

Stop

Sample Clock

(FIFO at or above

trigger level)

Trigger Level

INTRPT

(FCR6, 7 = 0, 0)

50%

(FIFO below

trigger level)

t

d13

(see Note A)

t

d14

INTRPT

Line Status

50%

Interrupt (LSI)

t

d14

RD1

(RD LSR)

Active

50%

Active

RD1

(RD RBR)

50%

NOTE A: For a time-out interrupt, t

= 9 RCLKs.

d13

Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms

22

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ꢊꢋ ꢌꢍꢄꢎꢏ ꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒ ꢒꢑꢍ ꢉꢄꢊꢀ ꢉꢐ ꢍꢋ ꢓ ꢁꢓ ꢒ ꢓꢍ ꢀ

ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

SIN

Stop

Sample Clock

(FIFO at or above

trigger level)

Time-Out or

Trigger Level

Interrupt

50%

(FIFO below

trigger level)

t

d13

(see Note A)

t

d14

50%

Line Status

Top Byte of FIFO

Interrupt (LSI)

t

d14

d13

‡

RD1, RD2

50%

(RD LSR)

‡

RD1, RD2

50%

Active

(RD RBR)

Previous Byte

Read From FIFO

‡

The RD2 signal is applicable only to the PT and PFB packages.

NOTE A: For a time-out interrupt, t = 9 RCLKs.

d13

Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

RD1

(RD RBR)

50%

Active

See Note A

SIN

Stop

(first byte)

Sample Clock

t

d13

(see Note B)

t

d14

50%

‡

RXRDY

‡

The RXRDY signal is applicable only to the PT and PFB packages.

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a time-out interrupt, t = 9 RCLKs.

d13

Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

23

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ꢊ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒꢒ ꢑꢍꢉ ꢄ ꢊꢀꢉ ꢐ ꢍꢋ ꢓꢁ ꢓꢒ ꢓꢍ ꢀ

ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

RD1

(RD RBR)

Active

See Note A

50%

SIN

(first byte that reaches

the trigger level)

Sample Clock

t

d13

(see Note B)

t

d14

‡

50%

RXRDY

‡

The RXRDY signal is applicable only to the PT and PFB packages.

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a time-out interrupt, t

= 9 RCLKs.

d13

Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

Start

50%

Start

50%

Data Bits

Parity

Stop

SOUT

t

d15

t

d16

INTRPT

(THRE)

50%

t

d18

t

d17

t

d17

WR1

(WR THR)

50%

t

d19

RD IIR

50%

Figure 13. Transmitter Timing Waveforms

24

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ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

Byte 1

50%

WR1

(WR THR)

Start

50%

SOUT

Data

Parity

Stop

t

d21

d20

‡

TXRDY

50%

‡

The TXRDY signal is applicable only to the PT and PFB packages.

Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

Byte 16

WR1

50%

(WR THR)

Start

50%

SOUT

Data

Parity

Stop

t

d21

d20

‡

TXRDY

50%

FIFO Full

‡

The TXRDY signal is applicable only to the PT and PFB packages.

Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒꢒ ꢑꢍꢉ ꢄ ꢊꢀꢉ ꢐ ꢍꢋ ꢓꢁ ꢓꢒ ꢓꢍ ꢀ

ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

‡

WR2

50%

(WR MCR)

t

d22

t

d22

RTS, DTR,

50%

‡

OUT1 , OUT2

CTS, DSR, DCD

t

d23

INTRPT

(modem)

50%

t

d24

t

d23

‡

RD2

50%

(RD MSR)

RI

50%

‡

The OUT1, OUT2, RD2, and WR2 signals are applicable only to the PT and PFB packages.

Figure 16. Modem Control Timing Waveforms

t

su4

CTS

50%

t

d25

50%

SOUT

Midpoint of Stop Bit

Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms

Midpoint of Stop Bit

SIN

t

d27

d26

50%

RTS

50%

RBRRD

Figure 18. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋ ꢌꢍꢄꢎꢏ ꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒ ꢒꢑꢍ ꢉꢄꢊꢀ ꢉꢐ ꢍꢋ ꢓ ꢁꢓ ꢒ ꢓꢍ ꢀ

ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

Midpoint of Data Bit 0

15th Character

16th Character

SIN

t

d29

d28

50%

RTS

50%

RBRRD

Figure 19. Auto-RTS Timing for RCV Threshold of 14 Waveforms

APPLICATION INFORMATION

SOUT

D7−D0

SIN

RTS

DTR

DSR

DCD

CTS

RI

MEMR or I/OR

MEMW or I/ON

INTR

RD1

EIA-232-D

Drivers

and Receivers

WR1

INTRPT

RESET

A0

C

P

U

MR

A0

TL16C550D

(ACE)

A1

A2

A1

A2

B

u

s

ADS

WR2

RD2

XIN

3.072 MHz

L

CS

CS2

CS1

CS0

XOUT

BAUDOUT

RCLK

H

Figure 20. Basic TL16C550D Configuration (for PT and PFB Packages)

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢐꢑ ꢋ ꢄꢐ ꢒꢒ ꢑꢍꢉ ꢄ ꢊꢀꢉ ꢐ ꢍꢋ ꢓꢁ ꢓꢒ ꢓꢍ ꢀ

ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

APPLICATION INFORMATION

SOUT

D7−D0

SIN

MEMR or I/OR

MEMW or I/ON

INTR

RTS

DTR

DSR

DCD

CTS

RI

RD1

EIA-232-D

Drivers

and Receivers

WR1

INTRPT

RESET

C

MR

A0

P

A0

U

TL16C550D

(ACE)

A1

A2

A1

A2

B

u

s

XIN

3.072 MHz

CS

CS2

XOUT

Figure 21. Basic TL16C550D Configuration (for RHB Package)

Receiver Disable

WR

WR1

TL16C550D

(ACE)

Microcomputer

System

Data Bus

D7−D0

8-Bit

Bus Transceiver

DDIS

Driver Disable

Figure 22. Typical Interface for a High Capacity Data Bus

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢔ ꢉꢀ ꢎ ꢊꢑꢀꢐ ꢕ ꢁꢐ ꢔ ꢄꢐ ꢍ ꢀꢏ ꢐꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

APPLICATION INFORMATION

Alternate

TL16C550D

Crystal Control

14

XIN

A16−A23

15

12

5

XOUT

9

BAUDOUT

RCLK

CS0

CS1

CS2

Address

Decoder

10

11

CPU

33

32

34

31

20

1

DTR

RTS

24

ADS

OUT1

OUT2

35

RSI/ABT

MR

A0−A2

AD0−AD7

Buffer

D0−D7

41

40

39

38

AD0−AD15

RI

8

6

5

DCD

PHI1 PHI2

DSR

CTS

ADS RSTO

RD

PHI1 PHI2

19

16

RD1

8

TCU

SOUT

2

3

WR1

WR

7

SIN

30

23

22

29

INTRPT

AD0−AD15

TXRDY

DDIS

20

17

RD2

7

1

WR2

RXRDY

EIA-232-D

Connector

18

42

GND

(V

SS

)

V

CC

Figure 23. Typical TL16C550D Connection to a CPU (for PT and PFB Packages)

29

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

APPLICATION INFORMATION

Alternate

TL16C550D

Crystal Control

10

11

XIN

A16−A23

XOUT

Address

Decoder

8

CS2

CPU

22

21

20

1

DTR

RTS

ADS

23

RSI/ABT

MR

A0−A2

AD0−AD7

Buffer

D0−D7

27

26

25

24

AD0−AD15

RI

8

6

5

DCD

PHI1 PHI2

DSR

CTS

ADS RSTO

RD

PHI1 PHI2

14

12

RD1

7

TCU

SOUT

2

3

WR1

WR

6

SIN

20

INTRPT

AD0−AD15

7

1

9, 13

2, 28

GND

(V

SS

)

V

CC

EIA-232-D

Connector

Figure 24. Typical TL16C550D Connection to a CPU (for RHB Package)

30

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

Table 1. Register Selection

†

DLAB

A2

L

A1

L

A0

L

REGISTER

0

Receiver buffer (read), transmitter holding register (write)

Interrupt enable register

Interrupt identification register (read only)

FIFO control register (write)

Line control register

L

H

L

X

1

L

H

L

H

L

H

L

Modem control register

L

H

L

Line status register

H

L

Modem status register

H

L

Scratch register

Divisor latch (LSB)

1

L

H

Divisor latch (MSB)

†

The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal

is controlled by writing to this bit location (see Table 4).

Table 2. ACE Reset Functions

REGISTER/SIGNAL

Interrupt enable register

RESET CONTROL

RESET STATE

Master reset

All bits cleared (0−3 forced and 4−7 permanent)

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4−5 are

permanently cleared

Interrupt identification register

Master reset

FIFO control register

Line control register

Modem control register

Line status register

Modem status register

SOUT

Master reset

All bits cleared

Master reset

All bits cleared (6−7 permanent)

Master reset

Bits 5 and 6 are set; all other bits are cleared

Master reset

Bits 0−3 are cleared; bits 4−7 are input signals

Master reset

High

INTRPT (receiver error flag)

INTRPT (received data available)

INTRPT (transmitter holding register empty)

INTRPT (modem status changes)

OUT2

Read LSR/MR

Read RBR/MR

Read IR/write THR/MR

Read MSR/MR

Master reset

Low

High

RTS

Master reset

High

DTR

Master reset

High

OUT1

Master reset

High

Scratch register

Master reset

No effect

Divisor latch (LSB and MSB) registers

Receiver buffer register

Transmitter holding register

RCVR FIFO

Master reset

MR/FCR1−FCR0/∆FCR0 All bits cleared

MR/FCR2−FCR0/∆FCR0 All bits cleared

XMIT FIFO

31

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are

summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions

of these registers follow Table 3.

Table 3. Summary of Accessible Registers

REGISTER ADDRESS

0 DLAB = 0

1 DLAB = 0

2

3

4

5

6

7

0 DLAB = 1

1 DLAB = 1

Receiver

Buffer

Register

(Read

Transmitter

Holding

Register

(Write

Interrupt

Ident.

Register

(Read

FIFO

Control

Register

(Write

BIT

NO.

Interrupt

Enable

Register

Line

Control

Register

Modem

Control

Register

Line

Status

Register

Modem

Status

Register

Divisor

Latch

(LSB)

Scratch

Register

Latch

(MSB)

Only)

RBR

THR

IER

IIR

FCR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

Enable

Received

Data

Available

Interrupt

(ERBI)

Word

Length

Select

Bit 0

Delta

Clear

to Send

Data

Terminal

Ready

(DTR)

0 if

Interrupt

Pending

Data

Ready

(DR)

FIFO

Enable

†

0

1

Data Bit 0

Bit 0

Bit 8

(∆CTS)

(WLS0)

Enable

Transmitter

Holding

Register

Empty

Delta

Data

Set

Word

Length

Select

Bit 1

Interrupt

ID

Bit 1

Receiver

FIFO

Reset

Request

to Send

(RTS)

Overrun

Error

(OE)

Data Bit 1

Bit 1

Bit 9

Ready

Interrupt

(ETBEI)

(WLS1)

(∆DSR)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Number

of

Stop Bits

(STB)

Trailing

Edge Ring

Indicator

(TERI)

Interrupt

ID

Bit 2

Transmitter

FIFO

Reset

Parity

Error

(PE)

2

3

Data Bit 2

Data Bit 3

Data Bit 2

Data Bit 3

OUT1

Bit 2

Bit 3

Bit 2

Bit 3

Bit 10

Bit 11

Delta

Data

Carrier

Detect

Enable

Modem

Status

Interrupt

(EDSSI)

Interrupt

ID

Bit 3

(see

Note 4)

DMA

Mode

Select

Parity

Enable

(PEN)

Framing

Error

(FE)

OUT2

Loop

(∆DCD)

Even

Parity

Select

(EPS)

Clear

to

Send

(CTS)

Break

Interrupt

(BI)

4

5

6

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 4

Data Bit 5

Data Bit 6

0

Reserved

Bit 4

Bit 5

Bit 6

Bit 4

Bit 5

Bit 6

Bit 12

Bit 13

Bit 14

Autoflow

Control

Enable

(AFE)

Transmitter

Holding

Register

(THRE)

Data

Set

Ready

(DSR)

Stick

Parity

FIFOs

Enabled

(see

Receiver

Trigger

(LSB)

Transmitter

Empty

(TEMT)

Ring

Indicator

(RI)

Break

Control

0

Note 4)

Divisor

Latch

Access

Bit

Error in

RCVR

FIFO

(see

Note 4)

FIFOs

Enabled

(see

Data

Receiver

Trigger

(MSB)

Carrier

Detect

(DCD)

7

Data Bit 7

0

Bit 7

Bit 15

Note 4)

(DLAB)

†

Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

NOTE 4: These bits are always 0 in the TL16C450 mode.

32

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables

and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

D

Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR

bits are written to or they are not programmed. Changing this bit clears the FIFOs.

Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not

cleared. The 1 that is written to this bit position is self-clearing.

Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not

cleared. The 1 that is written to this bit position is self-clearing.

D

Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.

Bits 4 and 5: These two bits are reserved for future use.

Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).

Table 4. Receiver FIFO Trigger Level

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

BIT 7

BIT 6

0

1

0

1

0

1

01

04

08

14

FIFO interrupt mode operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt

occurs as follows:

1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its

programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.

2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the

interrupt, it is cleared when the FIFO drops below the trigger level.

3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)

interrupt.

4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.

It is cleared when the FIFO is empty.

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

FIFO interrupt mode operation (continued)

When the receiver FIFO and receiver interrupts are enabled:

1. FIFO time-out interrupt occurs if the following conditions exist:

a. At least one character is in the FIFO.

b. The most recent serial character was received more than four continuous character times ago (if two

stop bits are programmed, the second one is included in this time delay).

c. The most recent microprocessor read of the FIFO has occurred more than four continuous character

times before. This causes a maximum character received command to interrupt an issued delay of

160 ms at a 300-baud rate with a 12-bit character.

2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional

to the baud rate).

3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads

one character from the receiver FIFO.

4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received

or after the microprocessor reads the receiver FIFO.

When the transmitter FIFO and THRE interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur

as follows:

1. The transmitter-holding-register-empty interrupt [IIR (3−0) = 2] occurs when the transmit FIFO is empty. It

is cleared [IIR (3−0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO

while servicing this interrupt) or the IIR is read.

2. The transmitter-holding-register-empty interrupt is delayed one character time minus the last stop bit time

when there have not been at least two bytes in the transmitter FIFO at the same time since the last time

that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.

FIFO-polled mode operation

With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts

the ACE in the FIFO-polled mode of operation. Because the receiver and transmitter are controlled separately,

either one or both can be in the polled mode of operation.

In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:

D

LSR0 is set as long as one byte is in the receiver FIFO.

LSR1 through LSR4 specify which error(s) have occurred. Character error status is handled the same way

as when in the interrupt mode; the IIR is not affected since IER2 = 0.

D

LSR5 indicates when the THR is empty.

LSR6 indicates that both the THR and TSR are empty.

LSR7 indicates whether any errors are in the receiver FIFO.

There is no trigger level reached or time-out condition indicated in the FIFO-polled mode. However, the receiver

and transmitter FIFOs are still fully capable of holding characters.

34

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

interrupt enable register (IER)

The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an

interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents

of this register are summarized in Table 3 and are described in the following bullets.

D

Bit 0: When set, this bit enables the received data available interrupt.

Bit 1: When set, this bit enables the THRE interrupt.

Bit 2: When set, this bit enables the receiver line status interrupt.

Bit 3: When set, this bit enables the modem status interrupt.

Bits 4 through 7: These bits are not used (always cleared).

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with

the most popular microprocessors.

The ACE provides four prioritized levels of interrupts:

D

Priority 1 − Receiver line status (highest priority)

Priority 2 − Receiver data ready or receiver character time-out

Priority 3 − Transmitter holding register empty

Priority 4 − Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt

in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and

described in Table 5. Detail on each bit is as follows:

D

Bit 0: This bit is used either in a hardwire-prioritized or polled-interrupt system. When bit 0 is cleared, an

interrupt is pending. If bit 0 is set, no interrupt is pending.

D

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3

Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a

time-out interrupt is pending.

D

Bits 4 and 5: These two bits are not used (always cleared).

Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control

register is set.

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION REGISTER

PRIORITY

LEVEL

INTERRUPT RESET

METHOD

INTERRUPT TYPE

INTERRUPT SOURCE

BIT 3 BIT 2 BIT 1 BIT 0

0

1

None

1

None

Overrun error, parity error,

framing error, or break interrupt

0

1

0

Receiver line status

Read the line status register

Receiver data available in the

0

1

0

2

Received data available TL16C450 mode or trigger level Read the receiver buffer register

reached in the FIFO mode

No characters have been

removed from or input to the

Character time-out

indication

receiver FIFO during the last four

character times, and there is at

least one character in it during

this time

Read the receiver buffer register

Read the interrupt identification

register (if source of interrupt) or

writing into the transmitter

holding register

Transmitter holding

register empty

Transmitter holding register

empty

0

1

0

3

4

Clear to send, data set ready,

Modem status

ring indicator, or data carrier Read the modem status register

detect

line control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the

LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates

the need for separate storage of the line characteristics in system memory. The contents of this register are

summarized in Table 3 and described in the following bulleted list.

D

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.

These bits are encoded as shown in Table 6.

Table 6. Serial Character Word Length

BIT 1

BIT 0

WORD LENGTH

5 bits

0

1

0

1

0

1

6 bits

7 bits

8 bits

D

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When

bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated

is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit

regardless of the number of stop bits selected. The number of stop bits generated in relation to word length

and bit 2 are shown in Table 7.

36

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

line control register (LCR) (continued)

Table 7. Number of Stop Bits Generated

WORD LENGTH SELECTED

BY BITS 1 AND 2

NUMBER OF STOP

BITS GENERATED

BIT 2

0

1

Any word length

5 bits

1

1 1/2

2

6 bits

7 bits

2

8 bits

2

D

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between

the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is

cleared, no parity is generated or checked.

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity

(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is

cleared, odd parity (an odd number of logic 1s) is selected.

Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked

as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.

If bit 5 is cleared, stick parity is disabled.

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT

is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no

effect on the transmitter logic; it only effects SOUT.

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the

baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver

buffer, the THR, or the IER.

line status register (LSR)^†

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register

are summarized in Table 3 and described in the following bulleted list.

D

Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming

character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the

data in the RBR or the FIFO.

‡

D

Bit 1 : This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in

the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every

time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the

trigger level, an overrun error occurs only after the FIFO is full, and the next character has been completely

received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character

in the shift register is overwritten, but it is not transferred to the FIFO.

†

‡

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

line status register (LSR) (continued)^†

‡

D

Bit 2 : This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received

data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads

the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO

to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.

‡

D

Bit 3 : This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character

did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the

FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error

is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to

resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the

next start bit. The ACE samples this start bit twice and then accepts the input data.

‡

D

Bit 4 : This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input

was held low for longer than a full-word transmission time. A full-word transmission time is defined as the

total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents

of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it

applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a

break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN

goes to the marking state for at least two RCLK samples and then receives the next valid start bit.

Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready

to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated.

THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the

loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared

when at least one byte is written to the transmit FIFO.

D

Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are

both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,

TEMT is set when the transmitter FIFO and shift register are both empty.

Bit 7: In the TL16C550D mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared.

In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is

cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is

emulating a modem. The contents of this register are summarized in Table 3 and are described in the following

bulleted list.

D

Bit 0: This bit (DTR) controls the DTR output.

Bit 1: This bit (RTS) controls the RTS output.

Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal.

Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.

When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,

the associated output is forced high.

†

‡

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

38

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

D

Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP

is set, the following occurs:

−

The transmitter SOUT is set high.

The receiver SIN is disconnected.

The output of the TSR is looped back into the receiver shift register input.

The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.

The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four

modem control inputs.

−

The four modem control outputs are forced to the inactive (high) levels.

D

Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the

detailed description is enabled.

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify

the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.

The modem control interrupts are also operational, but the modem control interrupt’s sources are now the

lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the

IER.

The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.

Table 8. ACE Flow Configuration

MCR BIT 5

(AFE)

MCR BIT 1

(RTS)

ACE FLOW CONFIGURATION

1

0

1

0

Auto-RTS and auto-CTS enabled (autoflow control enabled)

Auto-CTS only enabled

X

Auto-RTS and auto-CTS disabled

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the

modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change

information; when a control input from the modem changes state, the appropriate bit is set. All four bits are

cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are

described in the following bulleted list.

D

Bit 0: This bit is the change in clear-to-send (∆CTS) indicator. ∆CTS indicates that the CTS input has

changed state since the last time it was read by the CPU. When ∆CTS is set (autoflow control is not enabled

and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control

is enabled (∆CTS is cleared), no interrupt is generated.

D

Bit 1: This bit is the change in data set ready (∆DSR) indicator. ∆DSR indicates that the DSR input has

changed state since the last time it was read by the CPU. When ∆DSR is set and the modem status interrupt

is enabled, a modem status interrupt is generated.

Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to

the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled,

a modem status interrupt is generated.

39

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ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

D

Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. ∆DCD indicates that the DCD input to

the chip has changed state since the last time it was read by the CPU. When ∆DCD is set and the modem

status interrupt is enabled, a modem status interrupt is generated.

D

Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test

mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).

Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test

mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).

Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode

(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).

Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic

test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz

16

and divides it by a divisor in the range between 1 and (2 −1). The output frequency of the baud generator is

sixteen times (16×) the baud rate. The formula for the divisor is:

divisor = XIN frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must

be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either

of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Tables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz

respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the selected

baud rate is dependent on the selected crystal frequency (see Figure 25 for examples of typical clock circuits).

40

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

programmable baud generator (continued)

Table 9. Baud Rates Using a 1.8432-MHz Crystal

DIVISOR USED

TO GENERATE

16 × CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

DESIRED

BAUD RATE

50

75

2304

1536

1047

857

768

384

192

96

110

0.026

0.058

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

64

58

0.69

48

32

24

16

12

6

3

2

2.86

Table 10. Baud Rates Using a 3.072-MHz Crystal

DIVISOR USED

TO GENERATE

16 × CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

DESIRED

BAUD RATE

50

75

3840

2560

1745

1428

1280

640

320

160

107

96

110

0.026

0.034

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

0.312

80

53

0.628

1.23

40

27

20

10

5

41

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ꢔꢉ ꢀ ꢎ ꢊ ꢑ ꢀꢐꢕ ꢁ ꢐꢔ ꢄꢐ ꢍꢀ ꢏꢐ ꢁ

ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

PRINCIPLES OF OPERATION

programmable baud generator (continued)

V

CC

V

CC

Driver

XIN

External

Clock

C1

Crystal

R

P

Optional

Driver

RX2

XOUT

Optional

Clock

Output

Oscillator Clock

to Baud Generator

Logic

Oscillator Clock

to Baud Generator

Logic

XOUT

C2

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

3.072 MHz

1.8432 MHz

16 MHz

R

RX2

1.5 kΩ

0 Ω

C1

C2

P

1 MΩ

10−30 pF

33 pF

40−60 pF

33 pF

Figure 25. Typical Clock Circuits

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte

FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE

line control register.

The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR

FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt

is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.

In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

scratch register

The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense

that it temporarily holds the programmer’s data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a

16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line control

register.

The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.

The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the

transmitter-holding-register-empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This

interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated

based on the control setup in the FIFO control register.

42

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ꢖ

SLLS597C − APRIL 2004 − REVISED JUNE 2005

Revision History

DATE

REV

PAGE

3

SECTION

RHB Pinout

DESCRIPTION

Change pin 2 to NC and pin 9 to NC

7

Functional Block Diagram Change VCC 2,28 to VCC 28 and VSS 9,13 to VSS 9

Change VCC description to 2.25-V to 5.5-V power supply voltage

Change NC to 2, 9, 15, 16

9

6/22/05

B

10

11

Terminal Functions Table

Change VCC to pin 28 only and VSS to pin 13 only

Added RHB package

1, 3

7

Added functional block diagram for RHB package

Added Terminal Functions table for RHB package

Added Figure 21, Basic TL16C550D Configuration (for RHB Package)

10, 11

27

6/02/04

A

*

Application Information

Mechanical Information

Added Figure 24, Typical TL16C550D Connection to a CPU (for RHB

Package)

29

45

Added RHB Mechanical Data information

Original version

4/02/04

:

NOTE Page numbers for previous revisions may differ from page numbers in the current version.

43

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PACKAGE OPTION ADDENDUM

www.ti.com

22-Jul-2005

PACKAGING INFORMATION

Orderable Device

TL16C550DIPFB

TL16C550DIPFBR

TL16C550DIPT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TQFP

PFB

48

32

48

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TQFP

LQFP

QFN

PFB

PT

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C550DIPTG4

TL16C550DIPTR

TL16C550DIPTRG4

TL16C550DIRHB

TL16C550DPFB

TL16C550DPFBR

TL16C550DPT

PT

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

PT

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

PT

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

RHB

PFB

PT

73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TQFP

LQFP

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C550DPTG4

TL16C550DPTR

PT

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

PT

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C550DPTRG4

TL16C550DRHB

ACTIVE

LQFP

QFN

PT

48

32

1000

TBD

Call TI

RHB

73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Jul-2005

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

M

0,08

0,50

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

6,80

Gage Plane

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040052/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Logic

interface.ti.com

logic.ti.com

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microcontroller.ti.com

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Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TL16C550D
厂家：	TEXAS INSTRUMENTS
描述：	ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL 带自动流控异步通信部件通信
文件：	总50页 (文件大小：822K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TL16C550D [TI]

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