TL16C554AI [TI]
ASYNCHRONOUS-COMMUNICATIONS ELEMENT; 异步通信元型号: | TL16C554AI |
厂家: | TEXAS INSTRUMENTS |
描述: | ASYNCHRONOUS-COMMUNICATIONS ELEMENT |
文件: | 总40页 (文件大小:599K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
Integrated Asynchronous-Communications
Element
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1-Mbit Per
Second)
Consists of Four Improved TL16C550C
ACEs Plus Steering Logic
In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
False Start Bit Detection
In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
Complete Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
– Break, Parity, Overrun, Framing Error
Simulation
Programmable Baud-Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (2 –1) and
16
Fully Prioritized Interrupt System Controls
Generate an Internal 16 × Clock
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial-Data Stream
3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
Programmable Auto-RTS and Auto-CTS
CTS Controls Transmitter in Auto-CTS
Mode,
5-V and 3.3-V Operation
RCV FIFO Contents and Threshold Control
RTS in Auto-RTS Mode,
description
The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element
(ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete
status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The
information obtained includes the type and condition of the operation performed and any error conditions
encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs
to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and
transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can
significantly reduce software overhead and increase system efficiency by automatically controlling serial-data
flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize
system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE
includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor
16
between 1 and 2 –1.
TheTL16C554Aisavailableina68-pinplastic-leadedchip-carrier(PLCC)FNpackageandinan80-pin(TQFP)
PN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
FN PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60 DSRD
DSRA
CTSA
DTRA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
RTSA
INTA
CSA
TXA
IOW
IOR
TXB
TXC
CSB
CSC
INTC
RTSC
INTB
RTSB
GND
DTRB
CTSB
DSRB
V
CC
DTRC
CTSC
DSRC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PN PACKAGE
(TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
DSRC
CTSC
DTRC
NC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
DSRB
CTSB
DTRB
GND
RTSB
INTB
CSB
TXB
IOW
NC
TXA
CSA
INTA
RTSA
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
RTSC
INTC
CSC
TXC
IOR
NC
TXD
CSD
INTD
RTSD
GND
DTRD
CTSD
DSRD
NC
V
CC
DTRA
CTSA
DSRA
NC
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC – No internal connection
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
functional block diagram (per channel)
Internal
Data
S
e
l
e
c
t
Bus
Data
Bus
Buffer
Receiver
FIFO
5 – 66
8
D(7–0)
8
Receiver
Shift
Register
7
RXA
Receiver
Buffer
Register
Receiver
Timing and
Control
Line
Control
Register
14
RTSA
34
A0
A1
A2
Divisor
Latch (LS)
33
32
Baud
Generator
Divisor
Latch (MS)
Autoflow
Control
(AFE)
16
CSA
CSB
Transmitter
Timing and
Control
20
50
Line
Status
Register
CSC
Select
and
Control
Logic
54
37
52
CSD
Transmitter
FIFO
S
e
l
e
c
t
RESET
IOR
Transmitter
Shift
Register
Transmitter
Holding
Register
8
8
17
TXA
18
39
35
36
IOW
TXRDY
XTAL1
XTAL2
RXRDY
Modem
Control
Register
8
11
12
10
9
38
65
CTSA
DTRA
DSRA
DCDA
RIA
INTN
Modem
Control
Logic
Modem
Status
Register
8
8
13, 30, 47, 64
CC
V
Power
Supply
Interrupt
Enable
Register
Interrupt
Control
Logic
8
6, 23, 40, 57
15
INTA
GND
Interrupt
Identification
Register
8
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the FN package and channel A.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
Terminal Functions
TERMINAL
I/O
DESCRIPTION
FN
NO.
PN
NO.
NAME
A0
A1
A2
34
33
32
48
47
46
I
Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
select the ACE register to read or write.
CSA, CSB,
CSC, CSD
16, 20, 28, 33,
50, 54 68, 73
I
I
Chip select. Each chip select (CSx) enables read and write operations to its respective channel.
CTSA, CTSB,
CTSC, CTSD
11, 25, 23, 38,
45, 59 63, 78
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
of the modem-status register. Bit 0 (∆CTS) of the modem-status register indicates that CTS has
changed state since the last read from the modem-status register. If the modem-status interrupt is
enabledwhen CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated.
CTS is also used in the auto-CTS mode to control the transmitter.
D7–D0
66–68 15–11, I/O Databus. Eightdatalineswith3-stateoutputsprovideabidirectionalpathfordata, control, andstatus
1–5
9, 27, 19,42,
43, 61 59, 2
9–7
information between the TL16C554A and the CPU. D0 is the least-significant bit (LSB).
DCDA, DCDB,
DCDC, DCDD
I
Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
condition of this signal is checked by reading bit 7 of the modem-status register.
DSRA, DSRB,
DSRC, DSRD
10, 26, 22, 39,
44, 60 62, 79
Data set ready. DSRx is a modem-status signal. Its condition can be checked by reading bit 5 (DSR)
of the modem-status register. DSR has no effect on the transmit or receive operation.
I
DTRA, DTRB,
DTRC, DTRD
12, 24, 24, 37,
46, 58 64, 77
O
Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
to establish communications. It is placed in the active state by setting the DTR bit of the modem-
controlregister. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop-mode operation, or when clearing bit 0 (DTR) of the modem-control register.
GND
INTN
6, 23, 16, 36,
40, 57 56, 76
Signal and power ground
65
6
I
Interrupt normal. INTN operates in conjunction with bit 3 of the modem-status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.
INTN
OPERATION OF INTERRUPTS
Brought low or Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
allowed to float bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.
Brought high
Interrupts are always enabled, overriding the OUT2 enables.
INTA, INTB,
INTC, INTD
15, 21, 27, 34,
49, 55 67, 74
O
External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and
inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: receiver error, receiver data available or timeout (FIFO mode only), transmitter
holding register empty, and an enabled modem-status interrupt. The interrupt is disabled when it is
serviced or as the result of a master reset.
IOR
52
70
I
Read strobe. A low level on IOR transfers the contents of the selected register to the external CPU
bus.
IOW
18
37
31
53
I
I
Write strobe. IOW allows the the CPU to write to the register selected by the address.
RESET
Master reset. When active, RESET clears most ACE registers and sets the state of various signals.
The transmitter output and the receiver input are disabled during reset time.
RIA, RIB,
RIC, RID
8, 28, 18, 43,
42, 62 58, 3
I
Ringdetectindicator. A low on RIxindicatesthemodemhasreceivedaringsignalfromthetelephone
line. The condition of this signal can be checked by reading bit 6 of the modem-status register.
RTSA, RTSB,
RTSC, RTSD
14, 22, 26, 35,
48, 56 66, 75
O
Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to the active level by setting the RTS modem-control register bit, and is set to the
inactive(high)leveleitherasaresultofamasterreset, orduringloop-modeoperations, orbyclearing
bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver
threshold-control logic.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
Terminal Functions (Continued)
TERMINAL
I/O
I
DESCRIPTION
FN
NO.
PN
NO.
NAME
RXA, RXB
RXC, RXD
7, 29, 17, 44,
41, 63
Serial input. RXx is a serial-data input from a connected communications device. During loopback
mode, the RXx input is disabled from external connection and connected to the TXx output internally.
57, 4
RXRDY
38
54
O
O
O
Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer
or multitransfer.
TXA, TXB
TXC, TXD
17, 19, 29, 32,
51, 53 69, 72
Transmit outputs. TXx is a composite serial-data output connected to a communications device.
TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.
TXRDY
39
55
Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer
or multitransfer function.
V
CC
13, 30, 5, 25,
47, 64 45, 65
Power supply
XTAL1
XTAL2
35
50
I
Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to utilize the
internal oscillator circuit. An external clock can be connected to drive the internal-clock circuits.
36
51
O
Crystal output 2 or buffered clock output (see XTAL1).
†
absolute maximum ratings over free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range at any input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 3 V
O
CC
Continuous total-power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, T : TL16C554A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TL16C554AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
recommended operating conditions, standard voltage (5 V-nominal)
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
4.75
2
5
5.25
Clock high-level input voltage at XTAL1, V
V
CC
0.8
V
IH(CLK)
Clock low-level input voltage at XTAL1, V
High-level input voltage, V
–0.5
2
V
IL(CLK)
V
CC
0.8
V
IH
Low-level input voltage, V
–0.5
V
IL
Clock frequency, f
clock
16
70
85
MHz
°C
°C
TL16C554A
TL16C554AI
0
Operating free-air temperature, T
A
–40
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage, standard voltage (5-V nominal) (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
‡
V
V
High-level output voltage
Low-level output voltage
I
I
= –1 mA
2.4
OH
OH
‡
= 1.6 mA
0.4
V
OL
OL
V
= 5.25 V,
GND = 0,
All other terminals floating
CC
V = 0 to 5.25 V,
I
Input leakage current
±10
µA
µA
Ikg
I
High-impedance output
current
V
CC
= 5.25 V,
GND = 0,
V
O
= 0 to 5.25 V,
I
±20
OZ
CC
Chip selected in write mode or chip deselected
V
CC
= 5.25 V, = 25°C,
T
A
RX, DSR, DCD, CTS, and RI at 2 V,
I
Supply current
50
mA
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kilobits per second
C
C
C
C
Clock input capacitance
Clock output capacitance
Input capacitance
15
20
6
20
30
10
20
pF
pF
pF
pF
i(XTAL1)
V
= 0,
V
T
= 0, all other terminals grounded,
o(XTAL2)
CC
f = 1 MHz,
SS
= 25°C
A
i
Output capacitance
10
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
These parameters apply for all outputs except XTAL2.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
recommended operating conditions, low voltage (3.3-V nominal)
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
Clock high-level input voltage at XTAL1, V
V
V
V
IH(CLK)
CC
0.8
Clock low-level input voltage at XTAL1, V
High-level input voltage, V
–0.5
2
V
IL(CLK)
V
IH
CC
0.8
Low-level input voltage, V
–0.5
V
IL
Clock frequency, f
clock
16
70
85
MHz
°C
°C
TL16C554A
TL16C554AI
0
Operating free-air temperature, T
A
–40
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage, low voltage (3.3-V nominal) (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
‡
V
V
High-level output voltage
Low-level output voltage
I
I
= –1 mA
2.4
OH
OH
‡
= 1.6 mA
0.4
V
OL
OL
V
= 3.6 V,
GND = 0,
All other terminals floating
CC
V = 0 to 3.6 V,
I
Input leakage current
±10
µA
µA
Ikg
I
High-impedance output
current
V
CC
= 3.6 V,
GND = 0,
V
O
= 0 to 3.6 V,
I
±20
OZ
CC
Chip selected in write mode or chip deselected
V
CC
= 3.6 V, = 25°C,
T
A
RX, DSR, DCD, CTS, and RI at 2 V,
I
Supply current
40
mA
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kilobits per second
C
C
C
C
Clock input capacitance
Clock output capacitance
Input capacitance
15
20
6
20
30
10
20
pF
pF
pF
pF
i(XTAL1)
V
= 0,
V
T
= 0, all other terminals grounded,
o(XTAL2)
CC
f = 1 MHz,
SS
= 25°C
A
i
Output capacitance
10
o
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
These parameters apply for all outputs except XTAL2.
clocktimingrequirementsoverrecommendedrangesofoperatingfree-airtemperatureandsupply
voltage (see Figure 1)
MIN
31
MAX
UNIT
ns
t
t
t
Pulse duration, clock high (external clock)
Pulse duration, clock low (external clock)
Pulse duration, RESET
w1
w2
w3
31
ns
1000
ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN
75
10
15
0
MAX
UNIT
ns
t
t
t
t
t
t
t
Pulse duration, IOR low
w4
su1
su2
h1
Setup time, CSx valid before IOR low (see Note 2)
Setup time, A2–A0 valid before IOR low (see Note 2)
Hold time, A2–A0 valid after IOR high (see Note 2)
Hold time, CSx valid after IOR high (see Note 2)
ns
ns
ns
0
ns
h2
Delay time, t
+ t
+ t (see Note 3)
140
50
ns
d1
su2 w4 d2
Delay time, IOR high to IOR or IOW low
ns
d2
NOTES: 2. The internal address strobe is always active.
3. In the FIFO mode, t = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt-identification register
d1
and line-status register).
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN
50
10
15
10
5
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
Pulse duration, IOW↓
w5
su3
su4
su5
h3
Setup time, CSx valid before IOW↓ (see Note 2)
Setup time, A2–A0 valid before IOW↓ (see Note 2)
Setup time, D7–D0 valid before IOW↑
Hold time, A2–A0 valid after IOW↑ (see Note 2)
Hold time, CSx valid after IOW↑ (see Note 2)
Hold time, D7–D0 valid after IOW↑
ns
ns
ns
ns
5
ns
h4
25
120
55
ns
h5
Delay time, t
+ t
+ t
ns
d3
su4 w5 d4
Delay time, IOW↑ to IOW or IOR↓
ns
d4
NOTE 2: The internal address strobe is always active.
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, C = 100 pF (see Note 4 and Figure 4)
L
PARAMETER
MIN
MAX
30
UNIT
ns
t
t
Enable time, IOR↓ to D7–D0 valid
en
Disable time, IOR↑ to D7–D0 released
0
20
ns
dis
NOTE 4:
V
OL
and V
(and the external loading) determine the charge and discharge time.
OH
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
TEST CONDITIONS
MIN MAX
UNIT
RCLK
cycles
t
d5
t
d6
t
d7
t
d8
Delay time, INTx↓ to TXx↓ at start
See Note 7
8
8
24
8
RCLK
cycles
Delay time, TXx↓ at start to INTx↑
See Note 5
See Note 5
RCLK
cycles
Delay time, IOW high or low (WR THR) to INTx↑
Delay time, TXx↓ at start to TXRDY↓
16
32
8
RCLK
cycles
C
= 100 pF
L
t
t
t
Propagation delay time, IOW (WR THR)↓ to INTx↓
Propagation delay time, IOR (RD IIR)↑ to INTx↓
Propagation delay time, IOW (WR THR)↑ to TXRDY↑
C
C
C
= 100 pF
= 100 pF
= 100 pF
35
30
50
ns
ns
ns
pd1
pd2
pd3
L
L
L
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop-bit time.
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
RCLK
cycle
t
d9
Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt
See Note 6
1
C
= 100 pF,
L
t
t
Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
Propagation delay time, IOR RCLK↓ to RXRDY↑
40
30
ns
ns
pd4
See Note 7
See Note 7
pd5
NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayedthreeRCLK(internalreceivertimingclock)cyclesintheFIFOmode(FCR0=1). Afterthefirstbytehasbeenreceived, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, C = 100 pF (see Figures 14, 15, 16, and 17)
L
PARAMETER
MIN
MAX
50
UNIT
ns
t
t
t
t
Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑
Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑
Propagation delay time, IOR (RD MSR)↑ to interrupt↓
Propagation delay time, RIx↑ to INTx↑
pd6
pd7
pd8
pd9
30
ns
35
ns
30
ns
baudout
cycles
t
t
t
t
t
t
Propagation delay time, CTS low to SOUT↓ (See Note 7)
Setup time CTS high to midpoint of Tx stop bit
24
2
pd10
su6
baudout
cycles
baudout
cycles
Propagation delay time, RCV threshold byte to RTS↑
2
pd11
pd12
pd13
pd14
baudout
cycles
Propagation delay time, IOR (RD RBR) low (read of last byte in receive FIFO) to RTS↓
2
baudout
cycles
th
Propagation delay time, first data bit of 16 character to RTS↑
2
baudout
cycles
Propagation delay time, IOR (RD RBR) low to RTS↓
2
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
t
w1
2 V
0.8 V
2 V
2 V
Clock
(XTAL1)
0.8 V
0.8 V
t
w2
f
= 16 MHz MAX
clock
(a) CLOCK INPUT VOLTAGE WAVEFORM
RESET
t
w3
(b) RESET VOLTAGE WAVEFORM
Figure 1. Clock Input and RESET Voltage Waveforms
2.54 V
Device Under Test
680 Ω
TL16C554
82 pF
(see Note A)
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
Serial
Channel 1
Buffers
9-Pin D Connector
9-Pin D Connector
Data Bus
Address Bus
Control Bus
Serial
Channel 2
TL16C554A
Buffers
Quadruple
ACE
Serial
Channel 3
Buffers
9-Pin D Connector
9-Pin D Connector
Serial
Channel 4
Buffers
Figure 3. Basic Test Configuration
11
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
Valid
A2, A1, A0
50%
50%
t
h1
Valid
50%
50%
CSx
t
t
h2
su1
t
d1
t
su2
Active
Active
IOR
50%
50%
50%
50%
t
d2
or
t
w4
Active
IOW
t
t
dis
en
D7–D0
Valid Data
Figure 4. Read Cycle Timing Waveforms
Valid
A2, A1, A0
50%
50%
t
h3
t
Valid
50%
50%
CSx
t
h4
su3
t
d3
t
su4
IOW
50%
50%
50%
50%
Active
Active
t
t
w5
d4
or
Active
IOR
t
t
h5
su5
D7–D0
Valid Data
Figure 5. Write Cycle Timing Waveforms
12
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
Start
Start
Data (5–8)
50%
Stop (1–2)
50%
t
TXx
Parity
t
d5
d6
50%
50%
50%
50%
INTx
50%
t
pd1
t
t
d7
pd1
IOW
(WR THR)
50%
50%
50%
t
pd2
IOR
(RD IIR)
50%
Figure 6. Transmitter Timing Waveforms
Byte #1
IOW
(WR THR)
50%
Data
Parity
Stop
50% Start
TXx
t
t
d8
pd3
TXRDY
50%
50%
FIFO Empty
Figure 7. Transmitter Ready Mode 0 Timing Waveforms
IOW
(WR THR)
Byte #16
50%
Start
50%
Data
Parity
Stop
Start
TXx
t
t
d8
pd3
TXRDY
FIFO Full
50%
50%
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
TL16C450 Mode:
SIN
Start
Data Bits (5–8)
Parity
Stop
(receiver input data)
Sample Clock
t
d9
INTx
(data ready or
RCVR ERR)
50%
50%
t
pd4
Active
50%
IOR
Figure 9. Receiver Timing Waveforms
Start
Data Bits (5–8)
Parity
Stop
RXx
Sample
Clock
(FIFO at or
above trigger
level)
INTx (trigger
interrupt)
(FCR6, 7 = 0, 0)
50%
50%
(FIFO below
trigger level)
t
t
d9
pd4
50%
IOR
(RD RBR)
Active
LSR
Interrupt
50%
50%
t
pd4
IOR
(RD LSR)
50%
Active
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
14
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SLLS509A – AUGUST 2001 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
RXx
Stop
Sample
Clock
t
(see Note A)
d9
(FIFO at or above
trigger level)
INTx
(time-out or
trigger level)
Interrupt
50%
50%
(FIFO below
trigger level)
t
pd4
INTx
Interrupt
50%
50%
Top Byte of FIFO
t
t
d9
pd4
IOR
(RD LSR)
Active
50%
Active
Active
IOR
(RD RBR)
50%
50%
Previous BYTE
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
50%
RXx
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, then t = 3 RCLK cycles. For a time-out interrupt, t = 8 RCLK cycles.
d9 d9
Figure 12. Receiver Ready Mode 0 Timing Waveforms
15
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
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PARAMETER MEASUREMENT INFORMATION
50%
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, t = 3 RCLK cycles. For a trigger change level interrupt, t = 8 RCLK.
d9 d9
Figure 13. Receiver Ready Mode 1 Timing Waveforms
IOW
(WR MCR)
50%
50%
50%
t
t
pd6
pd6
50%
RTSx, DTRx
CTSx, DSRx,
DCDx
50%
50%
50%
t
t
pd7
pd7
50%
INTx
50%
50%
t
t
pd9
pd8
IOR
(RD MSR)
50%
50%
RIx
Figure 14. Modem Control Timing Waveforms
16
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
t
su6
CTS
TXx
50%
50%
t
pd10
50%
Midpoint of Stop Bit
Figure 15. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
RXx
t
t
PD12
PD11
50%
50%
RTSx
IOR
50%
RD RBR
Figure 16. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Midpoint of Data Bit 0
15th Character
16th Character
RXx
t
t
pd14
pd13
50%
50%
RTSx
IOR
50%
RD RBR
Figure 17. Auto-RTS Timing for RCV Threshold of 14 Waveforms
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each register and whether
it is read only, write only, or read writable.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL
MNEMONIC
LCR
STATUS
MNEMONIC
LSR
DATA
MNEMONIC
RBR
Line-control register
FIFO-control register
Modem-control register
Divisor-latch LSB
Line-status register
Modem-status register
Receiver-buffer register
Transmitter-holding register
FCR
MSR
THR
MCR
DLL
Divisor-latch MSB
DLM
Interrupt enable register
IER
†
Table 2. Register Selection
‡
§
A2
§
A1
§
A0
DLAB
READ MODE
WRITE MODE
0
0
0
0
0
Receiver-buffer register
Transmitter-holding register
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
Interrupt-enable register
X
X
X
X
X
X
1
Interrupt-identification register FIFO-control register
Line-control register
Modem-control register
Line-status register
Modem-status register
Scratchpad register
Scratchpad register
LSB divisor-latch
MSB divisor-latch
1
X = irrelevant, 0 = low level, 1 = high level
†
‡
§
The serial channel is accessed when either CSA or CSD is low.
DLAB is the divisor-latch access bit, located in bit 7 of the LCR.
A2–A0 are device terminals.
Individual bits within the registers with the bit number in parenthesis are referred to by the register mnemonic. For
example, LCR7 refers to line-control register bit 7. The transmitter-buffer register and the receiver-buffer register are
data registers that hold from five to eight bits of data. If less than eight data bits are transmitted, data is right-justified
to the LSB. Bit 0 of a data word is always the first serial-data bit received and transmitted. The ACE data registers
are double buffered (TL16450 mode) or FIFO buffered (FIFO mode) so that read and write operations can be
performed when the ACE is performing the parallel-to-serial or serial-to-parallel conversion.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
ADDRES
S
REGISTER
MNEMONIC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
RBR
(read only)
Data Bit 7
(MSB)
Data Bit 6
Data Bit 5
Data
Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
0
THR
(write only)
Data BIt 7
Data BIt 6
Data BIt 5
Data
BIt 4
Data BIt 3
Data BIt 2
Data BIt 1
Data BIt 0
†
†
0
DLL
DLM
IER
Bit 7
Bit 15
0
Bit 6
Bit 14
0
Bit 5
Bit 13
0
Bit 4
Bit 12
0
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
1
Bit 11
Bit 10
1
(EDSSI)
Enable
modem
status
(ERLSI)
Enable
receiver
line status
interrupt
(ETBEI)
Enable
transmitter
holding
register empty
interrupt
(ERBI)
Enable
received
data
available
interrupt
interrupt
2
FCR
(write only)
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
Reserved
0
DMA
mode
select
Transmit
FIFO reset
Receiver
FIFO reset
FIFO Enable
2
3
IIR
(read only)
FIFOs
Enabled
FIFOs
Enabled
0
Interrupt
ID Bit (3)
Interrupt ID
Bit (2)
Interrupt ID
Bit (1)
0 If interrupt
pending
‡
‡
‡
LCR
(DLAB)
Divisor
latch
Set break
Stick parity
(EPS)
Even-
parity
select
(PEN)
Parity
enable
(STB)
Number of
stop bits
(WLSB1)
Word-length
select bit 1
(WLSB0)
Word-length
select bit 0
access bit
4
5
6
MCR
0
0
Autoflow
control
enable
(AFE)
Loop
OUT2
Enable
external
interrupt
(INT)
Reserved
(RTS)
Request to
send
(DTR) Data
terminal
ready
LSR
Error in
receiver
FIFO
(TEMT)
Transmitter Transmitter
registers
empty
(THRE)
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
(OE)
(DR)
Data ready
Parity error Overrun error
‡
holding
register
empty
MSR
SCR
(DCD)
Data
carrier
detect
(RI)
Ring
indicator
(DSR)
Data set
ready
(CTS)
Clear to Delta data
send
(∆DCD)
(TERI)
Trailing
edge ring
indicator
(∆DSR)
Delta data
set ready
(∆CTS)
Delta
clear to send
carrier
detect
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
†
‡
DLAB = 1
These bits are always 0 when FIFOs are disabled.
19
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PRINCIPLES OF OPERATION
FIFO-control register (FCR)
The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of
the receiver FIFO, and selects the type of DMA signalling.
Bit 0: FCR0 enables the transmit and receive FIFOs. All bytes in both FIFOs can be cleared by clearing
FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450
mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCR0.
Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the
shift register.
Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the
shift register.
Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCR0 is set.
Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt and the auto-RTS flow
control (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
7
0
0
1
1
6
0
1
0
1
01
04
08
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and the receiver interrupts are enabled:
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2. IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt
IIR = 04.
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
20
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ASYNCHRONOUS-COMMUNICATIONS ELEMENT
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PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
The following receiver FIFO character time-out status occurs when receiver FIFO and the receiver interrupts
are enabled.
1. When the following conditions exist, a FIFO character time-out interrupt occurs:
a. Minimum of one character in FIFO
b. No new serial characters have been received for at least four character times. At 300 baud and 12-bit
characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received character
to interrupt generation.
c. The receive FIFO has not been read for at least four character times.
2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled
(FCR0 = 1, IER = 1).
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2. ThetransmitterFIFOemptyindicatorsaredelayedonecharactertimeminusthelaststop-bittimewhenever
the following occurs:
THRE = 1, and there have not been at least two bytes in transmit FIFO since the last THRE = 1. The first
transmitter interrupt comes immediately after changing FCR0, assuming the interrupt is enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
FIFO polled mode operation
When the FIFOs are enabled and all interrupts are disabled, the device is in the FIFO polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receive
and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.
21
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PRINCIPLES OF OPERATION
interrupt-enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IER0 – IER3 of the IER. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list:
Bit 0: When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts in
the FIFO mode.
Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.
Bit 2: When IER2 is set, the receiver line status interrupt is enabled.
Bit 3: When IER3 is set, the modem-status interrupt is enabled.
Bits 4 – 7: IER4 – IER7. These four bits of the IER are cleared.
interrupt-identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels as follows:
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character timeout
Priority 3 –Transmitter holding register empty
Priority 4–Modem status (lowest priority)
The IIR stores information indicating that a prioritized interrupt is pending and the type of interrupt. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL
INTERRUPT
RESET CONTROL
BIT 3 BIT 2 BIT 1 BIT 0
INTERRUPT TYPE
INTERRUPT SOURCE
0
0
0
0
1
1
0
1
0
1
0
0
—
None
None
—
First
Receiver line status
OE, PE, FE, or BI
LSR read
Second
Received data available Receiver data available or
trigger level reached
RBR read until FIFO
drops below the trigger
level
1
1
0
0
Second
Character time-out
indicator
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time.
RBR read
0
0
0
0
1
0
0
0
Third
THRE
THRE
IIR read (if THRE is the
interrupt source), or
THR write
Fourth
Modem status
CTS, DSR, RI, or DCD
MSR read
22
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PRINCIPLES OF OPERATION
interrupt-identification register (IIR) (continued)
Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.
Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.
Bit 3: IIR3 is always cleared in the TL16C450 mode. This bit, along with bit 2, is set when in the FIFO mode
and a character time-out interrupt is pending.
Bits 4 and 5: IIR4 and IIR5 are always cleared.
Bits 6 and 7: IIR6 and IIR7 are set when FCR0 = 1.
line-control register (LCR)
The format of the data character is controlled by LCR. LCR may be read. Its contents are described in the
following bulleted list and shown in Figure 18.
Bits 0 and 1: LCR0 and LCR1 are word-length select bits. These bits program the number of bits in each
serial character and are shown in Figure 18.
Bit 2: LCR2 is the stop-bit select bit. This bit specifies the number of stop bits in each transmitted character.
The receiver always checks for one stop bit.
Bit 3: LCR3 is the parity-enable bit. When LCR3 is set, a parity bit between the last data word bit and the
stop bit is generated and checked.
Bit 4: LCR4 is the even-parity select bit. When this bit is set and parity is enabled (LCR3 is set), even parity
is selected. When this bit is cleared and parity is enabled, odd parity is selected.
Bit 5: LCR5 is the stick-parity bit. When parity is enabled (LCR3 is set) and this bit is set, the transmission
and reception of a parity bit is placed in the opposite state from the value of LCR4. This forces parity to a
known state and allows the receiver to check the parity bit in a known state.
Bit 6: LCR6 is a break-control bit. When this bit is set, the serial outputs TXx are forced to the spacing state
(low). The break-control bit acts only on the serial output and does not affect the transmitter logic. If the
following sequence is used, no invalid characters are transmitted because of the break.
Step 1.
Step 2.
Step 3.
Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.
Set the break in response to the next THRE status indicator.
Wait for the transmitter to be idle when transmitter empty status signal is set (TEMT = 1); then
clear the break when the normal transmission has to be restored.
Bit 7: LCR7 is the divisor-latch access bit (DLAB) bit. This bit must be set to access the divisor latches DLL
and DLM of the baud-rate generator during a read or write operation. LCR7 must be cleared to access the
receiver-buffer register, the transmitter-holding register, or the interrupt-enable register.
23
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PRINCIPLES OF OPERATION
line-control register (LCR) (continued)
LINE CONTROL REGISTER
LCR LCR LCR LCR LCR LCR LCR LCR
7
6
5
4
3
2
1
0
0
0
1
1
0 = 5 Data Bits
1 = 6 Data Bits
0 = 7 Data Bits
1 = 8 Data bits
Word-Length
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Stop-Bit
Select
0 = Parity Disabled
1 = Parity Enabled
Parity Enable
Even-Parity
Select
0 = Odd Parity
1 = Even Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Stick Parity
0 = Break Disabled
1 = Break Enabled
Break Control
Divisor-Latch 0 = Access Receiver Buffer
Access BIt 1 = Access Divisor Latches
Figure 18. Line-Control Register Contents
line-status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the
following bulleted list:
Bit 0: LSR0 is the data ready (DR) bit. Data ready is set when an incoming character is received and
transferred to the receiver-buffer register or to the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver-buffer register or in the FIFO.
Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver-buffer register
is not read by the CPU before the next character is transferred to the receiver-buffer register, therefore
overwriting the previous character. The OE indicator is cleared whenever the CPU reads the contents of
the LSR. An overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely
received. The overrun error is detected by the CPU on the first LSR read after it occurs. The character in
the shift register is not transferred to the FIFO, but it is overwritten.
Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not
have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error
and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated
with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.
24
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PRINCIPLES OF OPERATION
line-status register (LSR) (continued)
Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the
spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).
TheBIindicatorisclearedwhentheCPUreadsthecontentsoftheLSR. IntheFIFOmode, thisisassociated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.
LSR1 – LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt-identification register) when any of the conditions are detected. This interrupt is enabled by setting
IER2 in the interrupt-enable register.
Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to
accept a new character for transmission. The THRE bit is set when a character is transferred from the
transmitter holding register (THR) to the transmitter shift register (TSR). LSR5 is cleared when the CPU
loads THR. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode, this bit is set when the transmit
FIFO is empty, and it is cleared when one byte is written to the transmit FIFO. When the THRE interrupt
is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source indicated
by IIR, INTRPT is cleared by a read of the IIR.
Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when both THR and TSR are empty.
LSR6 is cleared when a character is loaded into THR, and remains low until the character is transferred out
of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, this bit is set when both the
transmitter FIFO and shift register are empty.
Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).
In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing
error, or break interrupt indicator. It is cleared when the CPU reads the LSR, unless there are subsequent
errors in the FIFO.
NOTE
The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.
Table 6. Line-Status Register BIts
LSR BITS
1
Ready
Error
0
LSR0 data ready (DR)
Not ready
No error
LSR1 overrun error (OE)
LSR2 parity error (PE)
Error
No error
LSR3 framing error (FE)
Error
No error
LSR4 break interrupt (BI)
Break
No break
Not empty
Not empty
No error in FIFO
LSR5 transmitter holding register empty (THRE)
LSR6 transmitter register empty (TEMT)
LSR7 receiver FIFO error
Empty
Empty
Error in FIFO
25
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PRINCIPLES OF OPERATION
modem-control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 19. The MCR can be written
and read. Outputs RTS and DTR are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
Bit 2: MCR2 has no effect on operation.
Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.
Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped
back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The
four modem control output bits (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem
control input bits (DSR, CTS, RI, and DCD), respectively. The modem control output terminals are forced
to their inactive (high) state. In the diagnostic mode, data transmitted is received by its own receiver. This
allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt
control is fully operational; however, modem-status interrupts are generated by controlling the lower four
MCR bits internally. Interrupts are not generated by activity on the external terminals represented by those
four bits.
Bit 5: This bit is the autoflow control enable (AFE). When set, the autoflow control is enabled, as described
in the detailed description.
The ACE flow control can be configured by programming bits 1 and 5 of the MCR, as shown in Table 7.
Table 7. ACE Flow Configuration
MSR BIT 5
(AFE)
MSR BIT 1
(RTS)
ACE FLOW CONFIGURATION
1
1
0
1
0
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
X
Auto-RTS and auto-CTS disabled
26
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modem-control register (MCR) (continued)
Bit 6 – Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
MODEM CONTROL REGISTER
MCR MCR MCR MCR MCR MCR MCR MCR
7
6
5
4
3
2
1
0
0 = DTR Output Inactive (high)
1 = DTR Output Active (low)
Data Terminal
Ready
0 = RTS Output Inactive (high)
1 = RTS Output Active (low)
Request
to Send
Out1 (internal)
Out2 (internal)
No effect on external operation
0 = External Interrupt Disabled
1 = External Interrupt Enabled
0 = Loop Disabled
1 = Loop Enabled
Loop
AFE
0 = AFE Disabled
1 = AFE Enabled
Bits Are Set to Logic 0
Figure 19. Modem-Control Register Contents
modem-status register (MSR)
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR
allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE.
It also reads the current status of four bits of the MSR that indicate whether the modem inputs have changed
since the last reading of the MSR. The delta status bits are set when a control input from the modem changes
states, and are cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 – MSR7 are status indicators of these lines. A status
bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem-status
interrupt in the IER is enabled (IIR3 is set), an interrupt is generated whenever any one of MSR0 – MSR3 is set,
except as noted below in the delta CTS description. The MSR is a priority 4 interrupt. The contents of the MSR
are described in Table 8.
Bit 0: MSR0 is the delta clear-to-send (∆CTS) bit. ∆CTS indicates that the CTS input to the serial channel
has changed state since it was last read by the CPU. No interrupt will be generated if auto-CTS mode is
enabled.
Bit 1: MSR1 is the delta data set ready (∆DSR) bit. ∆DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.
Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
Bit 3: MSR3 is the delta data carrier detect (∆DCD) bit. ∆DCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.
Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in
the MCR.
27
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PRINCIPLES OF OPERATION
modem-status register (MSR) (continued)
Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.
Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2
in the MCR.
Reading the MSR clears the delta modem status indicators but has no effect on the other status bits. For LSR
and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read IOR operation, the status bit is not set until the trailing edge of the read. When a status
bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing
edge of the read instead of being set again. In the loopback mode, CTS, DSR, RI, and DCD inputs are ignored
when modem-status interrupts are enabled; however, a modem-status interrupt can still be generated by writing
to MCR3–MCR0. Applications software should not write to the MSR.
Table 8. Modem-Status Register BIts
MSR BIT
MSR0
MSR1
MSR2
MSR3
MSR4
MSR5
MSR6
MSR7
MNEMONIC
∆CTS
∆DSR
TERI
DESCRIPTION
Delta clear to send
Delta data set ready
Trailing edge of ring indicator
Delta data carrier detect
Clear to send
∆DCD
CTS
DSR
Data set ready
RI
Ring indicator
DCD
Data carrier detect
programming
The serial channel of the ACE is programmed by control registers LCR, IER, DLL, DLM, MCR, and FCR. These
control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
programmable baud-rate generator
The ACE serial channel contains a programmable baud-rate generator (BRG) that divides the clock (dc to
16
8 MHz) by any divisor from 1 to 2 –1. Two 8-bit divisor-latch registers store the divisor in a 16-bit binary format.
These divisor-latch registers must be loaded during initialization. A 16-bit baud counter is immediately loaded
upon loading of either of the divisor latches. This prevents long counts on initial load. The BRG can use any of
three different popular frequencies to provide standard baud rates. These frequencies are 1.8432 MHz,
3.072 MHz, 8 MHz, and 16 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are
available. Tables 9, 10, 11, and 12 illustrate the divisors needed to obtain standard rates using these three
frequencies. The output frequency of the baud-rate generator is 16 times the data rate [divisor # = clock + (baud
rate × 16)]. RCLK runs at this frequency.
28
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PRINCIPLES OF OPERATION
programmable baud-rate generator (continued)
Table 9. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE
DIVISOR (N) USED TO
PERCENT ERROR DIFFERENCE
DESIRED
GENERATE 16× CLOCK
BETWEEN DESIRED AND ACTUAL
50
2304
1536
1047
857
768
384
192
96
—
—
75
110
0.026
0.058
—
134.5
150
300
—
600
—
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
—
64
—
58
0.690
—
48
32
—
24
—
16
—
12
—
6
—
3
—
2
2.860
Table 10. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DIVISOR (N) USED TO
PERCENT ERROR DIFFERENCE
DESIRED
GENERATE 16× CLOCK
BETWEEN DESIRED AND ACTUAL
50
3840
2560
1745
1428
1280
640
320
160
107
96
—
—
75
110
0.026
0.034
—
134.5
150
300
—
600
—
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
—
0.312
—
80
—
53
0.628
—
40
27
1.230
—
20
10
—
5
—
29
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PRINCIPLES OF OPERATION
programmable baud-rate generator (continued)
Table 11. Baud Rates Using an 8-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16× CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
10000
6667
4545
3717
333
1667
883
417
277
250
208
139
104
69
—
0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080
—
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400
52
26
13
9
4
2
1
30
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Table 12. Baud Rates Using an 16-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16× CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
20000
13334
9090
7434
6666
3334
1666
834
554
500
416
278
208
138
104
52
0
0.00
0.01
0.01
0.01
–0.02
0.04
–0.08
0.28
0.00
0.16
–0.08
0.16
0.64
0.16
0.16
0.16
–0.79
–2.34
–2.34
–2.34
0.00
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
1000000
26
18
8
4
2
1
receiver
Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-low
transition. When the transition is detected, a circuit is enabled to sample incoming data bits at the optimum point,
which is the center of each bit. The start bit is valid when RXx is still low at the sample point. Verifying the start
bits prevents the receiver from assembling a false data character due to a low-going noise spike on the RXx
input.
The numberofdatabitsinacharacteriscontrolledbyLCR0andLCR1. Paritychecking, generation, andpolarity
are controlled by LCR3 and LCR4. Receiver status is provided in the LSR. When a full character is received,
including parity and stop bits, the data received indicator in LSR0 is set. In non-FIFO mode, the CPU reads the
RBR, which clears LSR0. If the character is not read prior to a new character transfer from RSR to RBR, an
overrun occurs and the overrun error status indicator is set in LSR1. If there is a parity error, the parity error is
set in LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.
In the FIFO mode, the data character and the associated error bits are stored in the receiver FIFO. If the data
in RXx is a symmetrical square wave, the center of the data cells occurs within ±3.125% of the actual center,
providing an error margin of 46.875%. The start bit can begin as much as one 16× clock cycles prior to being
detected.
31
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PRINCIPLES OF OPERATION
autoflow control (see Figure 20)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can send data. With auto-RTS, RTS becomes active when the receiver can handle more
data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur
unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from
a TL16C554A with the autoflow control enabled. Otherwise, overrun errors may occur when the transmit-data
rate exceeds the receiver FIFO read latency.
ACE1
ACE2
SIN
SOUT
CTS
Serial to
Parallel
Parallel
to Serial
RCV
FIFO
XMT
FIFO
RTS
Flow
Flow
Control
Control
D7–D0
D7–D0
SOUT
CTS
SIN
Parallel
to Serial
Serial to
Parallel
XMT
FIFO
RCV
FIFO
RTS
Flow
Flow
Control
Control
Figure 20. Autoflow Control (Auto-RTS and Auto-CTS) Example
auto-RTS (see Figure 20)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
andislinkedtotheprogrammedreceiverFIFOtriggerlevel. WhenthereceiverFIFOlevelreachesatriggerlevel
of 1, 4, or 8 (see Figure 22) RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the RCV FIFO is emptied by reading the receiver-buffer register.
When the trigger level is 14 (see Figure 23), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
auto-CTS (see Figure 20)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the
last stop bit currently being sent (see Figure 21). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.
enabling autoflow control and auto-CTS
Autoflow control is enabled by setting modem-control register bits 5 (autoflow enable or AFE) and 1 (RTS) to
a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem-
control register should be cleared (this assumes that an external control signal is driving CTS).
32
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PRINCIPLES OF OPERATION
auto-CTS and auto-RTS functional timing
Start Bits 0–7
Start Bits 0–7
Start Bits 0–7
Stop
Stop
Stop
SOUT
CTS
NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does
not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 21. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
Start
Byte N
Start Byte N+1
Start
Byte
Stop
Stop
Stop
SIN
RTS
RD
(RD RBR)
1
2
N
N+1
NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.
Figure 22. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
Byte 14
Byte 15
Start Byte 16 Stop
Start Byte 18 Stop
SIN
RTS Released After the
First Data Bit of Byte 16
RTS
RD
(RD RBR)
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than
one byte of space available.
C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
Figure 23. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
33
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PRINCIPLES OF OPERATION
reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1. Initializes the transmitter and receiver internal clock counters.
2. Clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and
transmitter-buffer register are not affected.
RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).
In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, many received characters are read by the DMA device, reducing the number of times it
is interrupted.
RXRDY and TXRDY outputs from each of the four internal ACEs of the TL16C554A are ANDed together
internally. This combined signal is brought out externally to RXRDY and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 13.
Table 13. RESET Effects on Registers and Signals
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt-enable register
Reset
All bits cleared (0–3 forced and 4–7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4–5 are permanently cleared
Interrupt-identification register
Reset
Line-control register
Modem-control register
FIFO-control register
Line-status register
Modem-status register
TXx
Reset
Reset
All bits cleared
All bits cleared (5–7 permanent)
Reset
All bits cleared
Reset
All bits cleared, except bits 5 and 6 are set
Reset
Bits 0–3 cleared, bits 4–7 input signals
Reset
High
Low
Low
Low
Low
High
High
Interrupt (RCVR ERRS)
Interrupt (receiver data ready)
Interrupt (THRE)
Read LSR/reset
Read RBR/reset
Read IIR/write THR/reset
Read MSR/reset
Reset
Interrupt (modem status changes)
RTS
Reset
DTR
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
PRINCIPLES OF OPERATION
scratchpad register
The scratchpad register is an 8-bit read/write register that has no effect on any ACE channel. It is intended to
be used by the programmer to hold data temporarily.
TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).
In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY is asserted (low).
V
CC
V
CC
Driver
XTAL1
XTAL1
External
Clock
C1
Crystal
R
P
Optional
Driver
RX2
XTAL2
Optional
Clock
Output
Oscillator Clock
to Baud
Generator Logic
Oscillator Clock
to Baud
Generator Logic
XTAL2
C2
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
3.1 MHz
1.8 MHz
R
RX2
C1
C2
P
1 MΩ
1 MΩ
1.5 kΩ
1.5 kΩ
10–30 pF
10–30 pF
40–60 pF
40–60 pF
Figure 24. Typical Clock Circuits
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A – AUGUST 2001 – REVISED JULY 2003
MECHANICAL DATA
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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