TL16C554FNR_技术文档

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SLLS165G − JANUARY 1994 − REVISED MARCH 2006

D

Integrated Asynchronous Communications

Element

D

Fully Programmable Serial Interface

Characteristics:

− 5-, 6-, 7-, or 8-Bit Characters

− Even-, Odd-, or No-Parity Bit

− 1-, 1 1/2-, or 2-Stop Bit Generation

− Baud Generation (DC to 1-Mbit Per

Second)

Consists of Four Improved TL16C550 ACEs

Plus Steering Logic

In FIFO Mode, Each ACE Transmitter and

Receiver Is Buffered With 16-Byte FIFO to

Reduce the Number of Interrupts to CPU

D

False Start Bit Detection

D

In TL16C450 Mode, Hold and Shift

Registers Eliminate Need for Precise

Synchronization Between the CPU and

Serial Data

Complete Status Reporting Capabilities

Line Break Generation and Detection

Internal Diagnostic Capabilities:

− Loopback Controls for Communications

Link Fault Isolation

− Break, Parity, Overrun, Framing Error

Simulation

D

Up to 16-MHz Clock Rate for up to 1-Mbaud

Operation

Programmable Baud Rate Generators

Which Allow Division of Any Input

16

Reference Clock by 1 to (2 ꢀ −ꢀ 1) and

D

Fully Prioritized Interrupt System Controls

Generate an Internal 16 × Clock

Modem Control Functions (CTS, RTS, DSR,

DTR, RI, and DCD)

D

Adds or Deletes Standard Asynchronous

Communication Bits (Start, Stop, and

Parity) to or From the Serial Data Stream

3-State Outputs Provide TTL Drive

Capabilities for Bidirectional Data Bus and

Control Bus

Independently Controlled Transmit,

Receive, Line Status, and Data Set

Interrupts

description

The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous

communications element (ACE). Each channel performs serial-to-parallel conversion on data characters

received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted

by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional

operation by the CPU. The information obtained includes the type and condition of the operation performed and

any error conditions encountered.

The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates

the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in

both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on

the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes

a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and

16

(2 −1).

The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and

in an 80-pin (TQFP) PN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  1994 − 2006, Texas Instruments Incorporated

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1

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SLLS165G − JANUARY 1994 − REVISED MARCH 2006

FN PACKAGE

(TOP VIEW)

9

8

7

6

5

4

3

2

1 68 67 66 65 64 63 62 61

60 DSRD

DSRA

CTSA

DTRA

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

59

CTSD

DTRD

GND

RTSD

INTD

CSD

TXD

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

V

CC

RTSA

INTA

CSA

TXA

IOW

IOR

TXB

TXC

CSB

CSC

INTC

RTSC

INTB

RTSB

GND

DTRB

CTSB

DSRB

V

CC

DTRC

CTSC

DSRC

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC − No internal connection

2

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PN PACKAGE

(TOP VIEW)

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

40

NC

DSRC

CTSC

DTRC

NC

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

DSRB

CTSB

DTRB

GND

RTSB

INTB

CSB

TXB

IOW

NC

TXA

CSA

INTA

RTSA

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

V

CC

RTSC

INTC

CSC

TXC

IOR

NC

TXD

CSD

INTD

RTSD

GND

DTRD

CTSD

DSRD

NC

V

CC

DTRA

CTSA

DSRA

NC

1

2

3

4

5

6

7 8 9 10 11 12 13 14 15 16 17 18 19 20

NC − No internal connection

3

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

†

functional block diagram

8

Data

Bus

D7−D0

TL16C550B

Circuitry

Receive

Control

Logic

RXx

TXx

TL16C550B

Circuitry

A2−A0

CSx

IOR, IOW

RESET

Control

Logic

Transmit

Control

Logic

TL16C550B

Circuitry

Interrupt

Logic

INTx

TXRDY, RXRDY

CTSx

RTSx

DSRx

DTRx

RIx

Modem

Control

Logic

TL16C550B

Circuitry

XTAL1

XTAL2

Clock

Circuit

DCDx

†

For TL16C550 circuitry, refer to the TL16C550B data sheet.

Terminal Functions

TERMINAL

I/O

DESCRIPTION

FN

NO.

PN

NO.

NAME

A0

A1

A2

34

33

32

48

47

46

I

Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to

select the ACE register to read or write.

CSA, CSB,

CSC, CSD

16, 20, 28, 33,

50, 54 68, 73

I

Chip select. Each chip select (CSx) enables read and write operations to its respective channel.

CTSA, CTSB,

CTSC, CTSD

11, 25, 23, 38,

45, 59 63, 78

Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS)

of the modem status register. CTS has no affect on the transmit or receive operation.

D7−D0

66−68 15−11, I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

1−5

9, 27, 19,42,

43, 61 59, 2

9−7

information between the TL16C554 and the CPU. D0 is the least significant bit (LSB).

DCDA, DCDB,

DCDC, DCDD

I

Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The

condition of this signal is checked by reading bit 7 of the modem status register.

DSRA, DSRB,

DSRC, DSRD

10, 26, 22, 39,

44, 60 62, 79

Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR)

of the modem status register. DSR has no affect on the transmit or receive operation.

I

DTRA, DTRB,

DTRC, DTRD

12, 24, 24, 37,

46, 58 64, 77

O

Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready

to establish communications. It is placed in the active state by setting the DTR bit of the modem

control register. DTRx is placed in the inactive state (high) either as a result of the master reset during

loop mode operation or clearing bit 0 (DTR) of the modem control register.

GND

INTN

6, 23, 16, 36,

40, 57 56, 76

Signal and power ground

65

6

I

Interrupt normal. INTN operates in conjunction with bit 3 of the modem status register and affects

operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous

receiver/transceivers (UARTs) per the following table.

INTN

OPERATION OF INTERRUPTS

Brought low or Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR

allowed to float bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance

state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.

Brought high

Interrupts are always enabled, overriding the OUT2 enables.

4

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SLLS165G − JANUARY 1994 − REVISED MARCH 2006

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

FN

NO.

PN

NO.

NAME

INTA, INTB,

INTC, INTD

15, 21, 27, 34,

49, 55 67, 74

O

External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and

inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt

to be issued are: a receiver error, receiver data available or timeout (FIFO mode only), transmitter

holding register empty, and an enabled modem status interrupt. The interrupt is disabled when it is

serviced or as the result of a master reset.

IOR

52

70

I

Read strobe. A low level on IOR transfers the contents of the TL16C554 data bus to the external CPU

bus.

IOW

18

37

31

53

I

Write strobe. IOW allows the CPU to write into the selected address by the address register.

RESET

Master reset. When active, RESET clears most ACE registers and sets the state of various signals.

The transmitter output and the receiver input is disabled during reset time.

RIA, RIB,

RIC, RID

8, 28, 18, 43,

42, 62 58, 3

I

Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone

line. The condition of this signal can be checked by reading bit 6 of the modem status register.

RTSA, RTSB,

RTSC, RTSD

14, 22, 26, 35,

48, 56 66, 75

O

Request to send. When active, RTSx informs the modem or data set that the ACE is ready to receive

data. Writing a 1 in the modem control register sets this bit to a low state. After reset, this terminal

is set high. These terminals have no affect on the transmit or receive operation.

RXA, RXB

RXC, RXD

7, 29, 17, 44,

I

Serial input. RXx is a serial data input from a connected communications device. During loopback

mode, the RXx input is disabled from external connection and connected to the TXx output internally.

41, 63

57, 4

RXRDY

38

54

O

Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer

or multitransfer.

TXA, TXB

TXC, TXD

17, 19, 29, 32,

51, 53 69, 72

Transmit outputs. TXx is a composite serial data output that is connected to a communications

device. TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.

TXRDY

39

55

Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer

or multitransfer function.

VCC

13, 30, 5, 25,

47, 64 45, 65

Power supply

XTAL1

XTAL2

35

50

I

Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to utilize the

internal oscillator circuit. An external clock can be connected to drive the internal clock circuits.

36

51

O

Crystal output 2 or buffered clock output (see XTAL1).

†

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range at any input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Output voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 3 V

O

CC

Continuous total power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW

Operating free-air temperature range, T : TL16C554 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0°C to 70°C

A

TL16C554I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to GND.

5

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

CC

4.75

2

5

5.25

V

Clock high-level input voltage at XTAL1, V

V

CC

0.8

IH(CLK)

Clock low-level input voltage at XTAL1, V

High-level input voltage, V

−0.5

2

V

IL(CLK)

V

CC

0.8

V

IH

Low-level input voltage, V

IL

−0.5

V

Clock frequency, f

clock

16

70

85

MHz

°C

TL16C554

TL16C554I

0

Operating free-air temperature, T

A

−40

electrical characteristics over recommended ranges of operating free-air temperature and supply

voltage (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

‡

V

High-level output voltage

Low-level output voltage

I

= −1 mA

= 1.6 mA

2.4

OH

‡

0.4

10

V

OL

V

= 5.25 V,

GND = 0,

All other terminals floating

CC

V = 0 to 5.25 V,

I

Input leakage current

µA

Ikg

I

High-impedance output

current

V

= 5.25 V,

GND = 0,

V

O

= 0 to 5.25 V,

CC

I

20

50

OZ

CC

Chip selected in write mode or chip deselected

V

= 5.25 V, = 25°C,

T

CC

A

RX, DSR, DCD, CTS, and RI at 2 V,

I

Supply current

mA

All other inputs at 0.8 V, XTAL1 at 4 MHz,

No load on outputs,

Baud rate = 50 kilobits per second

V = 0,

SS

C

Clock input capacitance

Clock output capacitance

Input capacitance

15

20

6

20

30

10

20

pF

i(XTAL1)

V

= 0,

CC

All other terminals grounded,

= 25°C

o(XTAL2)

f = 1 MHz,

i

T

A

Output capacitance

10

o

†

‡

All typical values are at V

CC

= 5 V, T = 25°C.

A

These parameters apply for all outputs except XTAL2.

clock timing requirements over recommended ranges of operating free-air temperature and supply

voltage (see Figure 1)

MIN

31

MAX

UNIT

ns

t

Pulse duration, clock high (external clock)

Pulse duration, clock low (external clock)

Pulse duration, RESET

w1

w2

w3

31

ns

1000

ns

6

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

read cycle timing requirements over recommended ranges of operating free-air temperature and

supply voltage (see Figure 4)

MIN

75

10

15

0

MAX

UNIT

ns

t

Pulse duration, IOR low

w4

su1

su2

h1

Setup time, CSx valid before IOR low (see Note 2)

Setup time, A2−A0 valid before IOR low (see Note 2)

Hold time, A2−A0 valid after IOR high (see Note 2)

Hold time, CSx valid after IOR high (see Note 2)

ns

0

ns

h2

Delay time, t

+ t

+ t (see Note 3)

140

50

ns

d1

su2 w4 d2

Delay time, IOR high to IOR or IOW low

ns

d2

NOTES: 2. The internal address strobe is always active.

3. In the FIFO mode, t = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification register

d1

and line status register).

write cycle timing requirements over recommended ranges of operating free-air temperature and

supply voltage (see Figure 5)

MIN

50

10

15

10

5

MAX

UNIT

ns

t

Pulse duration, IOW↓

w5

su3

su4

su5

h3

Setup time, CSx valid before IOW↓ (see Note 2)

Setup time, A2−A0 valid before IOW↓ (see Note 2)

Setup time, D7−D0 valid before IOW↑

Hold time, A2−A0 valid after IOW↑ (see Note 2)

Hold time, CSx valid after IOW↑ (see Note 2)

Hold time, D7−D0 valid after IOW↑

ns

5

ns

h4

25

120

55

ns

h5

Delay time, t

+ t

ns

d3

su4 w5 d4

Delay time, IOW↑ to IOW or IOR↓

ns

d4

NOTE 2: The internal address strobe is always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature

and supply voltage, C = 100 pF (see Note 4 and Figure 4)

L

PARAMETER

MIN

MAX

30

UNIT

ns

t

Enable time, IOR↓ to D7−D0 valid

en

Disable time, IOR↑ to D7−D0 released

0

20

ns

dis

NOTE 4:

V

OL

and V

OH

(and the external loading) determine the charge and discharge time.

7

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

transmitter switching characteristics over recommended ranges of operating free-air temperature

and supply voltage (see Figures 6, 7, and 8)

PARAMETER

TEST CONDITIONS

MIN MAX

UNIT

RCLK

cycles

t

d5

t

d6

t

d7

t

d8

Delay time, INTx↓ to TXx↓ at start

8

24

8

RCLK

cycles

Delay time, TXx↓ at start to INTx↑

See Note 5

RCLK

cycles

Delay time, IOW high or low (WR THR) to INTx↑

Delay time, TXx↓ at start to TXRDY↓

16

32

8

RCLK

cycles

C

= 100 pF

L

t

Propagation delay time, IOW (WR THR)↓ to INTx↓

Propagation delay time, IOR (RD IIR)↑ to INTx↓

Propagation delay time, IOW (WR THR)↑ to TXRDY↑

C

= 100 pF

35

30

50

ns

pd1

pd2

pd3

L

NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.

receiver switching characteristics over recommended ranges of operating free-air temperature

and supply voltage (see Figures 9 through 13)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

RCLK

cycle

t

d9

Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt

See Note 6

1

C

= 100 pF,

L

t

Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓

Propagation delay time, IOR RCLK↓ to RXRDY↑

40

30

ns

pd4

See Note 7

pd5

NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are

delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status

indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after

IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.

7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.

modem control switching characteristics over recommended ranges of operating free-air

temperature and supply voltage, C = 100 pF (see Figure 14)

L

PARAMETER

MIN

MAX

50

UNIT

ns

t

Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑

Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑

Propagation delay time, IOR (RD MSR)↑ to interrupt↓

Propagation delay time, RIx↑ to INTx↑

pd6

pd7

pd8

pd9

30

ns

35

ns

30

ns

8

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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢆꢈ

ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PARAMETER MEASUREMENT INFORMATION

t

w1

2 V

0.8 V

2 V

Clock

(XTAL1)

0.8 V

t

w2

f

= 16 MHz MAX

clock

(a) CLOCK INPUT VOLTAGE WAVEFORM

RESET

t

w3

(b) RESET VOLTAGE WAVEFORM

Figure 1. Clock Input and RESET Voltage Waveforms

2.54 V

Device Under Test

680 Ω

TL16C554

82 pF

(see Note A)

NOTE A: This includes scope and jig capacitance.

Figure 2. Output Load Circuit

Serial

Channel 1

Buffers

9-Pin D Connector

Data Bus

Address Bus

Control Bus

Serial

Channel 2

TL16C554

Buffers

Quadruple

ACE

Serial

Channel 3

Buffers

9-Pin D Connector

Serial

Channel 4

Buffers

Figure 3. Basic Test Configuration

9

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ꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑꢑ ꢐꢌꢈ ꢄ ꢉꢀꢈ ꢏ ꢌꢊ ꢒꢁ ꢒꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PARAMETER MEASUREMENT INFORMATION

Valid

A2, A1, A0

50%

t

h1

Valid

50%

CSx

t

h2

su1

t

d1

t

su2

Active

IOR

50%

t

d2

or

t

w4

Active

IOW

t

dis

en

D7−D0

Valid Data

Figure 4. Read Cycle Timing Waveforms

Valid

A2, A1, A0

50%

t

h3

t

Valid

50%

CSx

t

h4

su3

t

d3

t

su4

IOW

50%

Active

t

w5

d4

or

Active

IOR

t

h5

su5

D7−D0

Valid Data

Figure 5. Write Cycle Timing Waveforms

10

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ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PARAMETER MEASUREMENT INFORMATION

Start

Data (5−8)

50%

Stop (1−2)

50%

t

TXx

Parity

t

d5

d6

50%

INTx

50%

t

pd1

t

d7

pd1

IOW

(WR THR)

50%

t

pd2

IOR

(RD IIR)

50%

Figure 6. Transmitter Timing Waveforms

Byte #1

IOW

(WR THR)

50%

Data

Parity

Stop

50% Start

TXx

t

d8

pd3

TXRDY

50%

FIFO Empty

Figure 7. Transmitter Ready Mode 0 Timing Waveforms

IOW

(WR THR)

Byte #16

50%

Start

50%

Data

Parity

Stop

Start

TXx

t

d8

pd3

TXRDY

FIFO Full

50%

Figure 8. Transmitter Ready Mode 1 Timing Waveforms

11

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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢅ ꢆ ꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢅ ꢆ ꢈ

ꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑꢑ ꢐꢌꢈ ꢄ ꢉꢀꢈ ꢏ ꢌꢊ ꢒꢁ ꢒꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PARAMETER MEASUREMENT INFORMATION

TL16C450 Mode:

SIN

Start

Data Bits (5−8)

Parity

Stop

(receiver input data)

Sample Clock

t

d9

INTx

(data ready or

RCVR ERR)

50%

t

pd4

Active

50%

IOR

Figure 9. Receiver Timing Waveforms

Start

Data Bits (5−8)

Parity

Stop

RXx

Sample

Clock

(FIFO at or

above trigger

level)

INTx (trigger

interrupt)

(FCR6, 7 = 0, 0)

50%

(FIFO below

trigger level)

t

d9

pd4

50%

IOR

(RD RBR)

Active

LSR

Interrupt

50%

t

pd4

IOR

(RD LSR)

50%

Active

Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms

12

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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢆꢈ

ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PARAMETER MEASUREMENT INFORMATION

RXx

Stop

Sample

Clock

t

(see Note A)

d9

(FIFO at or above

trigger level)

INTx

(time-out or

trigger level)

Interrupt

50%

(FIFO below

trigger level)

t

pd4

INTx

Interrupt

50%

Top Byte of FIFO

t

d9

pd4

IOR

(RD LSR)

Active

50%

Active

IOR

(RD RBR)

50%

Previous BYTE

Read From FIFO

NOTE A: This is the reading of the last byte in the FIFO.

Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms

ꢒ

ꢓ

ꢔ

50%

ꢁ ꢂꢃ ꢄꢅꢆ

ꢇꢔꢕ ꢔ ꢐꢔ ꢋ

ꢇꢈ ꢆꢆ ꢉ ꢊꢃ ꢆ ꢁ ꢋ

RXx

ꢌꢃ ꢊꢍ

ꢌꢖ ꢗꢍ ꢘꢆ

ꢙꢘꢊ ꢂꢚ

ꢃ

ꢎ ꢏ

ꢇ

ꢈ

ꢆ

ꢉ

ꢊ

ꢃ

ꢆ

ꢐ

ꢋ

50%

ꢔ ꢛꢔ ꢕꢜ

ꢃ

ꢍ ꢎ ꢑ

NOTES: A. This is the reading of the last byte in the FIFO.

B. If FCR0 = 1, then t = 3 RCLK cycles. For a time-out interrupt, t = 8 RCLK cycles.

d9 d9

Figure 12. Receiver Ready Mode 0 Timing Waveforms

13

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ꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑꢑ ꢐꢌꢈ ꢄ ꢉꢀꢈ ꢏ ꢌꢊ ꢒꢁ ꢒꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PARAMETER MEASUREMENT INFORMATION

ꢒꢓ ꢔ

50%

ꢁ ꢂꢃ ꢄꢅꢆ

ꢇ ꢔꢕ ꢔ ꢐꢔ ꢋ

ꢇꢈ ꢆꢆ ꢉ ꢊꢃ ꢆ ꢁ ꢋ

ꢌꢒ ꢉ

ꢇꢝ ꢄꢞ ꢈꢃ ꢟꢠꢃ ꢆ ꢃꢡ ꢖ ꢃ ꢞ ꢆꢖ ꢂꢡ ꢆꢈ

ꢃꢡ ꢆ ꢃꢞꢄ ꢢꢢ ꢆꢞ ꢘꢆꢅ ꢆꢘꢋ

ꢌꢃ ꢊꢍ

ꢌꢖ ꢗꢍ ꢘꢆ

ꢙꢘꢊ ꢂꢚ

ꢃ

ꢎ ꢏ

ꢇ ꢈꢆꢆ ꢉꢊꢃ ꢆ ꢐ ꢋ

50%

ꢔ ꢛꢔꢕꢜ

ꢃ

ꢍ ꢎ ꢑ

NOTES: A. This is the reading of the last byte in the FIFO.

B. If FCR0 = 1, t = 3 RCLK cycles. For a trigger change level interrupt, t = 8 RCLK.

d9 d9

Figure 13. Receiver Ready Mode 1 Timing Waveforms

IOW

(WR MCR)

50%

t

pd6

50%

RTSx, DTRx

CTSx, DSRx,

DCDx

50%

t

pd7

50%

INTx

50%

t

pd9

pd8

IOR

(RD MSR)

50%

RIx

Figure 14. Modem Control Timing Waveforms

14

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ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic

abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each register and whether

it is read only, write only, or read writable.

Table 1. Internal Register Mnemonic Abbreviations

CONTROL

MNEMONIC

LCR

STATUS

MNEMONIC

LSR

DATA

MNEMONIC

RBR

Line control register

FIFO control register

Modem control register

Divisor latch LSB

Line status register

Modem status register

Receiver buffer register

Transmitter holding register

FCR

MSR

THR

MCR

DLL

Divisor latch MSB

DLM

Interrupt enable register

IER

†

Table 2. Register Selection

‡

§

A2

§

A1

§

A0

DLAB

READ MODE

WRITE MODE

0

Receiver buffer register

Transmitter holding register

Interrupt enable register

0

1

X

1

0

1

0

Interrupt identification register FIFO control register

Line control register

0

1

0

Modem control register

1

0

1

Line status register

1

0

Modem status register

1

Scratchpad register

LSB divisor latch

MSB divisor latch

0

1

0

1

X = irrelevant, 0 = low level, 1 = high level

†

‡

§

The serial channel is accessed when either CSA or CSD is low.

DLAB is the divisor latch access bit and bit 7 in the LCR.

A2−A0 are device terminals.

Individual bits within the registers with the bit number in parenthesis are referred to by the register mnemonic. For

example, LCR7 refers to line control register bit 7. The transmitter buffer register and receiver buffer register are data

registers that hold from five to eight bits of data. If less than eight data bits are transmitted, data is right justified to

the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted. The ACE data registers are

double buffered (TL16450 mode) or FIFO buffered (FIFO mode) so that read and write operations can be performed

when the ACE is performing the parallel-to-serial or serial-to-parallel conversion.

15

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ꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑꢑ ꢐꢌꢈ ꢄ ꢉꢀꢈ ꢏ ꢌꢊ ꢒꢁ ꢒꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are

summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions

of these registers follow Table 3.

Table 3. Summary of Accessible Registers

REGISTER ADDRESS

REGISTER

MNEMONIC

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

RBR

(read only)

Data Bit 7

(MSB)

Data Bit 6

Data Bit 5

Data

Bit 4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0

(LSB)

0

THR

(write only)

Data BIt 7

Data BIt 6

Data BIt 5

Data

BIt 4

Data BIt 3

Data BIt 2

Data BIt 1

Data BIt 0

†

0

DLL

DLM

IER

Bit 7

Bit 15

0

Bit 6

Bit 14

0

Bit 5

Bit 13

0

Bit 4

Bit 12

0

Bit 3

Bit 2

Bit 1

Bit 9

Bit 0

Bit 8

1

Bit 11

Bit 10

1

(EDSSI)

Enable

modem

status

(ERLSI)

Enable

receiver

line status

interrupt

(ETBEI)

Enable

transmitter

holding

register

empty

(ERBI)

Enable

received

data

available

interrupt

2

FCR

(write only)

Receiver

Trigger

(MSB)

Receiver

Trigger

(LSB)

Reserved

0

DMA

mode

select

Transmit

FIFO reset

Receiver

FIFO reset

FIFO Enable

2

3

IIR

(read only)

FIFOs

Enabled

FIFOs

Enabled

0

Interrupt

ID Bit (3)

Interrupt ID Interrupt ID

Bit (2)

0 If interrupt

pending

‡

Bit (1)

LCR

(DLAB)

Divisor

latch

Set break

Stick parity

(EPS)

Even

parity

select

(PEN)

Parity

enable

(STB)

(WLSB1)

(WLSB0)

Number of Word length Word length

stop bits

select bit 1

select bit 0

access bit

4

5

6

MCR

0

Loop

OUT2

Enable

external

interrupt

(INT)

Reserved

(RTS)

Request to

send

(DTR) Data

terminal

ready

LSR

Error in

receiver

FIFO

(TEMT)

Transmitter

registers

empty

(THRE)

Transmitter

holding

register

empty

(BI)

Break

interrupt

(FE)

Framing

error

(PE)

Parity error

(OE)

Overrun

error

(DR)

Data ready

‡

MSR

SCR

(DCD)

Data

carrier

detect

(RI)

Ring

indicator

(DSR)

Data set

ready

(CTS)

Clear to Delta data

send

(∆DCD)

(TERI)

Trailing

edge ring

indicator

(∆DSR)

Delta data

set ready

(∆CTS)

Delta

clear to send

carrier

detect

7

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

†

‡

DLAB = 1

These bits are always 0 when FIFOs are disabled.

16

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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢆꢈ

ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of

the receiver FIFO, and selects the type of DMA signalling.

D

Bit 0: FCR0 enables the transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing

FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450

mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCR0.

D

Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the

shift register.

Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the

shift register.

D

Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCR0 is set.

Bits 4 and 5: FCR4 and FCR5 are reserved for future use.

Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).

Table 4. Receiver FIFO Trigger Level

BIT

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

7

0

1

6

0

1

0

1

01

04

08

14

FIFO interrupt mode operation

The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.

1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is

empty, it is reset.

2. IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt

IIR = 04.

3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the

FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.

4. IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared

when the FIFO drops below the programmed trigger level.

The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are

enabled.

17

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ꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑꢑ ꢐꢌꢈ ꢄ ꢉꢀꢈ ꢏ ꢌꢊ ꢒꢁ ꢒꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

FIFO interrupt mode operation (continued)

1. When the following conditions exist, a FIFO character time-out interrupt occurs:

a. Minimum of one character in FIFO

b. Last received serial character is longer than four continuous previous character times ago. (If two stop

bits are programmed, the second one is included in the time delay.)

c. The last CPU of the FIFO read is more than four continuous character times earlier. At 300 baud and

12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received

character to interrupt issued.

2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional

to the baud rate.

3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This

occurs when there has been no time-out interrupt.

4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.

Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled

(FCR0 =1, IER1 = 1).

1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt

is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can

be written to the transmit FIFO when servicing this interrupt.

2. The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time whenever

the following occurs:

THRE = 1, and there has not been a minimum of two bytes at the same time in transmit FIFO since the last

THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is

enabled.

Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data

available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO

empty interrupt.

FIFO polled mode operation

Clearing IER0, IER1, IER2, IER3, or all to zero with FCR0 = 1 puts the ACE into the FIFO polled mode. receiver

and transmitter are controlled separately. Either or both can be in the polled mode.

In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the Receiver

and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE

status.

interrupt enable register (IER)

The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,

D) output. All interrupts are disabled by clearing IER0 − IER3 of the IER. Interrupts are enabled by setting the

appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.

All other system functions operate in their normal manner, including the setting of the LSR and MSR. The

contents of the IER are shown in Table 3 and described in the following bulleted list:

18

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ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

interrupt enable register (IER) (continued)

D

Bit 0: When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts in

the FIFO mode.

D

Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.

Bit 2: When IER2 is set, the receiver line status interrupt is enabled.

Bit 3: When IER3 is set, the modem status interrupt is enabled.

Bits 4 − 7: IER4 − IER7. These four bits of the IER are cleared.

interrupt identification register (IIR)

In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts

into four levels. The four levels of interrupt conditions are as follows:

D

Priority 1 − Receiver line status (highest priority)

Priority 2 − Receiver data ready or receiver character timeout

Priority 3 −Transmitter holding register empty

Priority 4−Modem status (lowest priority)

Information indicating that a prioritized interrupt is pending and the type of interrupt that is stored in the IIR. The

IIR indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION

REGISTER

INTERRUPT SET AND RESET FUNCTIONS

PRIORITY

LEVEL

INTERRUPT

RESET CONTROL

BIT 3

BIT 2 BIT 1 BIT 0

INTERRUPT TYPE

INTERRUPT SOURCE

0

1

0

1

0

1

0

—

None

—

First

Receiver line status

OE, PE, FE, or BI

LSR read

Second

Received data available Receiver data available or

trigger level reached

RBR read until FIFO

drops below the trigger

level

1

0

Second

Character time-out

indicator

No characters have been

removed from or input to the

receiver FIFO during the last

four character times, and there

is at least one character in it

during this time.

RBR read

0

1

0

Third

THRE

IIR read if THRE is the

interrupt source or THR

write

Fourth

Modem status

CTS, DSR, RI, or DCD

19

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SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

D

Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.

Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.

Bit 3: IIR3 is always cleared when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO

mode and a trigger change level interrupt is pending.

D

Bits 4 and 5: IIR4 and IIR5 are always cleared.

Bits 6 and 7: IIR6 and IIR7 are set when FCR0 = 1.

D

line control register (LCR)

The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described

in the following bulleted list and shown in Figure 15.

D

Bits 0 and 1: LCR0 and LCR1 are word length select bits. These bits program the number of bits in each

serial character and are shown in Figure 15.

Bit 2: LCR2 is the stop bit select bit. This bit specifies the number of stop bits in each transmitted character.

The receiver always checks for one stop bit.

Bit 3: LCR3 is the parity enable bit. When LCR3 is set, a parity bit between the last data word bit and stop

bit is generated and checked.

Bit 4: LCR4 is the even parity select bit. When this bit is set and parity is enabled (LCR3 is set), even parity

is selected. When this bit is cleared and parity is enabled, odd parity is selected.

Bit 5: LCR5 is the stick parity bit. When parity is enabled (LCR3 is set) and this bit is set, the transmission

and reception of a parity bit is placed in the opposite state from the value of LCR4. This forces parity to a

known state and allows the receiver to check the parity bit in a known state.

D

Bit 6: LCR6 is a break control bit. When this bit is set, the serial outputs TXx are forced to the spacing state

(low). The break control bit acts only on the serial output and does not affect the transmitter logic. If the

following sequence is used, no invalid characters are transmitted because of the break.

Step 1.

Step 2.

Step 3.

Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.

Set the break in response to the next THRE status indicator.

Wait for the transmitter to be idle when transmitter empty status signal is set (TEMT = 1); then

clear the break when the normal transmission has to be restored.

D

Bit 7: LCR7 is the divisor latch access bit (DLAB) bit. This bit must be set to access the divisor latches DLL

and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the

receiver buffer register, the transmitter holding register, or the interrupt enable register.

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

line control register (LCR) (continued)

LINE CONTROL REGISTER

LCR LCR LCR LCR LCR LCR LCR LCR

7

6

5

4

3

2

1

0

1

0 = 5 Data Bits

1 = 6 Data Bits

0 = 7 Data Bits

1 = 8 Data bits

Word Length

Select

0 = 1 Stop Bit

1 = 1.5 Stop Bits if 5 Data Bits Selected

2 Stop Bits if 6, 7, 8 Data Bits Selected

Stop Bit

Select

0 = Parity Disabled

1 = Parity Enabled

Parity Enable

Even Parity

Select

0 = Odd Parity

1 = Even Parity

0 = Stick Parity Disabled

1 = Stick Parity Enabled

Stick Parity

0 = Break Disabled

1 = Break Enabled

Break Control

Divisor Latch 0 = Access Receiver Buffer

Access BIt 1 = Access Divisor Latches

Figure 15. Line Control Register Contents

line status register (LSR)

The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the

following bulleted list:

D

Bit 0: LSR0 is the data ready (DR) bit. Data ready is set when an incoming character is received and

transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the

receiver buffer register or the FIFO.

D

Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver buffer register

is not read by the CPU before the next character is transferred into the receiver buffer register overwriting

the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An

overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely received.

The overrun error is detected by the CPU on the first LSR read after it happens. The character in the shift

register is not transferred to the FIFO, but it is overwritten.

D

Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not

have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error

and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated

with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.

Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have

a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero

bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO

mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when

the character is at the top of the FIFO.

21

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SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

line status register (LSR) (continued)

D

Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the

spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).

The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated

with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the

FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the

first LSR read. Only one zero character is loaded into the FIFO when BI occurs.

LSR1 − LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the

interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting IER2

in the interrupt enable register.

D

Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to

accept a new character for transmission. The THRE bit is set when a character is transferred from the

transmitter holding register (THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading

of the THR by the CPU. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode, when the transmit

FIFO is empty, this bit is set. It is cleared when one byte is written to the transmit FIFO. When the THRE

interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source

indicated in IIR, INTRPT is cleared by a read of the IIR.

D

Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when the THR and the TSR are both

empty. LSR6 is cleared when a character is loaded into THR and remains low until the character is

transferred out of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the

transmitter FIFO and shift register are empty, this bit is set.

Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).

In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing

error, or break interrupt indicator. It is cleared when the CPU reads the LSR if there are no subsequent errors

in the FIFO.

NOTE

The LSR may be written. However, this function is intended only for factory test. It should be considered as read

only by applications software.

Table 6. Line Status Register BIts

LSR BITS

1

Ready

Error

0

LSR0 data ready (DR)

Not ready

No error

LSR1 overrun error (OE)

LSR2 parity error (PE)

Error

No error

LSR3 framing error (FE)

Error

No error

LSR4 break interrupt (BI)

Break

No break

Not empty

No error in FIFO

LSR5 transmitter holding register empty (THRE)

LSR6 transmitter register empty (TEMT)

LSR7 receiver FIFO error

Empty

Error in FIFO

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

modem control register (MCR)

The MCR controls the interface with the modem or data set as described in Figure 16. MCR can be written and

read. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts

a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:

D

Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced

high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the

proper polarity input at the modem or data set.

D

Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced

high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper

polarity input at the modem or data set.

D

Bit 2: MCR2 has no affect on operation.

Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.

Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,

serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped

back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The

modem control outputs (DTR and RTS) are internally connected to the four modem control inputs. The

modem control output terminals are forced to their inactive (high) state on the TL16C554. In the diagnostic

mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive

data paths of the selected serial channel. Interrupt control is fully operational; however, interrupts are

generated by controlling the lower four MCR bits internally. Interrupts are not generated by activity on the

external terminals represented by those four bits.

D

Bit 5 − Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.

MODEM CONTROL REGISTER

MCR MCR MCR MCR MCR MCR MCR MCR

7

6

5

4

3

2

1

0

0 = DTR Output Inactive (high)

1 = DTR Output Active (low)

Data Terminal

Ready

0 = RTS Output Inactive (high)

1 = RTS Output Active (low)

Request

to Send

Out1 (internal)

Out2 (internal)

No affect on external operation

0 = External Interrupt Disabled

1 = External Interrupt Enabled

0 = Loop Disabled

1 = Loop Enabled

Loop

Bits Are Set to Logic 0

Figure 16. Modem Control Register Contents

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

modem status register (MSR)

The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR

allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE.

It also reads the current status of four bits of the MSR that indicate whether the modem inputs have changed

since the last reading of the MSR. The delta status bits are set when a control input from the modem changes

states and are cleared when the CPU reads the MSR.

The modem input lines are CTS, DSR, and DCD. MSR4 − MSR7 are status indicators of these lines. A status

bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem status interrupt

in the IER is enabled (IIR3 is set), an interrupt is generated whenever MSR0 − MSR3 is set. The MSR is a priority

4 interrupt. The contents of the MSR are described in Table 7.

D

Bit 0: MSR0 is the delta clear-to-send (∆CTS) bit. DCTS indicates that the CTS input to the serial channel

has changed state since it was last read by the CPU.

Bit 1: MSR1 is the delta data set ready (∆DSR) bit. ∆DSR indicates that the DSR input to the serial channel

has changed states since the last time it was read by the CPU.

Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RIx input to the serial

channel has changed states from low to high since the last time it was read by the CPU. High-to-low

transitions on RI do not activate TERI.

D

Bit 3: MSR3 is the delta data carrier detect (∆DCD) bit. ∆DCD indicates that the DCD input to the serial

channel has changed states since the last time it was read by the CPU.

Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem

indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel

is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.

D

Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to

the serial channel that indicates that the modem is ready to provide received data from the serial channel

receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in

the MCR.

D

Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the

loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.

Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier

detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2

in the MCR.

Reading the MSR clears the delta modem status indicators but has no affect on the other status bits. For LSR

and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is

generated during a read IOR operation, the status bit is not set until the trailing edge of the read. When a status

bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing

edge of the read instead of being set again. In the loopback mode when modem status interrupts are enabled,

CTS, DSR, RI, and DCD inputs are ignored; however, a modem status interrupt can still be generated by writing

to MCR3−MCR0. Applications software should not write to the MSR.

24

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

Table 7. Modem Status Register BIts

MSR BIT

MSR0

MSR1

MSR2

MSR3

MSR4

MSR5

MSR6

MSR7

MNEMONIC

∆CTS

∆DSR

TERI

DESCRIPTION

Delta clear to send

Delta data set ready

Trailing edge of ring indicator

Delta data carrier detect

Clear to send

∆DCD

CTS

DSR

Data set ready

RI

Ring indicator

DCD

Data carrier detect

programming

The serial channel of the ACE is programmed by the control registers LCR, IER, DLL, DLM, MCR, and FCR.

These control words define the character length, number of stop bits, parity, baud rate, and modem interface.

While the control registers can be written in any order, the IER should be written last because it controls the

interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any

time the ACE serial channel is not transmitting or receiving data.

programmable baud rate generator

The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (dc to

16

8 MHz) by any divisor from 1 to (2 −1). Two 8-bit divisor latch registers store the divisor in a 16-bit binary

format. These divisor latch registers must be loaded during initialization. Upon loading either of the divisor

latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The BRG can

use any of three different popular frequencies to provide standard baud rates. These frequencies are 1.8432

MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are available.

Tables 8, 9, 10, and 11 illustrate the divisors needed to obtain standard rates using these three frequencies. The

output frequency of the baud rate generator is 16× the data rate [divisor # = clock + (baud rate × 16)] referred

to in this document as RCLK.

25

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

programmable baud rate generator (continued)

Table 8. Baud Rates Using an 1.8432-MHz Crystal

BAUD RATE

DESIRED

DIVISOR (N) USED TO

GENERATE 16× CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

50

75

2304

1536

1047

857

768

384

192

96

—

110

0.026

0.058

—

134.5

150

300

—

600

—

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

—

64

—

58

0.690

—

48

32

—

24

—

16

—

12

—

6

—

3

—

2

2.860

Table 9. Baud Rates Using an 3.072-MHz Crystal

BAUD RATE

DIVISOR (N) USED TO

PERCENT ERROR DIFFERENCE

DESIRED

GENERATE 16× CLOCK

BETWEEN DESIRED AND ACTUAL

50

3840

2560

1745

1428

1280

640

320

160

107

96

—

75

110

0.026

0.034

—

134.5

150

300

—

600

—

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

—

0.312

—

80

—

53

0.628

—

40

27

1.230

—

20

10

—

5

—

26

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

programmable baud rate generator (continued)

Table 10. Baud Rates Using an 8-MHz Clock

BAUD RATE

DESIRED

DIVISOR (N) USED TO

GENERATE 16× CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

50

75

10000

6667

4545

3717

333

1667

883

417

277

250

208

139

104

69

—

0.005

0.010

0.013

0.010

0.020

0.040

0.080

—

110

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

128000

256000

512000

0.160

0.080

0.160

0.644

0.160

0.790

2.344

2.400

52

26

13

9

4

2

1

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ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

programmable baud rate generator (continued)

Table 11. Baud Rates Using an 16-MHz Clock

BAUD RATE

DESIRED

DIVISOR (N) USED TO

GENERATE 16× CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

50

75

20000

13334

9090

7434

6666

3334

1666

834

554

500

416

278

208

138

104

52

0

0.00

110

0.01

134.5

150

0.01

300

−0.02

0.04

600

1200

−0.08

0.28

1800

2000

0.00

2400

0.16

3600

−0.08

0.16

4800

7200

0.64

9600

0.16

19200

38400

56000

128000

256000

512000

1000000

0.16

26

0.16

18

−0.79

−2.34

0.00

8

4

2

1

receiver

Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-low

transition from the idle state. When the transition is detected, a counter is reset and counts the 16× clock to

7 1/2, which is the center of the start bit. The start bit is valid when the RXx is still low. Verifying the start bits

prevents the receiver from assembling a false data character due to a low going noise spike on the RXx input.

The LCR determines the number of data bits in a character (LCR0, LCR1). When parity is enabled, LCR3 and

the polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is

received including parity and stop bits, the data received indicator in LSR0 is set. The CPU reads the RBR, which

clears LSR0. If the character is not read prior to a new character transfer from the RSR to the RBR, the overrun

error status indicator is set in LSR1. If there is a parity error, the parity error is set in LSR2. If a stop bit is not

detected, a framing error indicator is set in LSR3.

In the FIFO mode operation, the data character and the associated error bits are stored in the receiver FIFO.

If the data into RXx is a symmetrical square wave, the center of the data cells occurs within 3.125% of the actual

center, providing an error margin of 46.875%. The start bit can begin as much as one 16× clock cycle prior to

being detected.

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢆꢈ

ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

reset

After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an

idle mode until initialization. A high on RESET causes the following:

1. It initializes the transmitter and receiver internal clock counters.

2. It clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),

which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic

associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and

transmitter buffer register are not affected.

RXRDY operation

In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO

is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).

In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out

has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is

empty. In this mode, multiple received characters are read by the DMA device, reducing the number of times

it is interrupted.

RXRDY and TXRDY outputs from each of the four internal ACEs of the TL16C554 are ANDed together

internally. This combined signal is brought out externally to RXRDY and TXRDY.

Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.

A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently

enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 12.

Table 12. RESET Affects on Registers and Signals

REGISTER/SIGNAL

RESET CONTROL

RESET STATE

Interrupt enable register

Reset

All bits cleared (0−3 forced and 4−7 permanent)

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,

Bits 4−5 are permanently cleared

Interrupt identification register

Reset

Line control register

Modem control register

FIFO control register

Line status register

Modem status register

TXx

Reset

All bits cleared

All bits cleared (5−7 permanent)

Reset

All bits cleared

Reset

All bits cleared, except bits 5 and 6 are set

Reset

Bits 0−3 cleared, bits 4−7 input signals

Reset

High

Low

Interrupt (RCVR ERRS)

Interrupt (receiver data ready)

Interrupt (THRE)

Read LSR/Reset

Read RBR/Reset

Read IIR/Write THR/Reset Low

Interrupt (modem status changes)

RTS

Read MSR/Reset

Reset

Low

High

Reset

DTR

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢅ ꢆ ꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢅ ꢆ ꢈ

ꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢏꢐ ꢊ ꢄꢏ ꢑꢑ ꢐꢌꢈ ꢄ ꢉꢀꢈ ꢏ ꢌꢊ ꢒꢁ ꢒꢑ ꢒꢌ ꢀ

ꢓ

SLLS165G − JANUARY 1994 − REVISED MARCH 2006

PRINCIPLES OF OPERATION

scratchpad register

The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended

to be used by the programmer to hold data temporarily.

TXRDY operation

In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO

contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).

In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written

with another byte when TXRDY is asserted (low).

V

CC

V

CC

Driver

XTAL1

External

Clock

C1

Crystal

R

P

Optional

Driver

RX2

XTAL2

Optional

Clock

Output

Oscillator Clock

to Baud

Generator Logic

Oscillator Clock

to Baud

Generator Logic

XTAL2

C2

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

3.1 MHz

1.8 MHz

R

RX2

C1

C2

P

1 MΩ

1.5 kΩ

10ā−ā30 pF

10−30 pF

40ā−ā60 pF

40−60 pF

Figure 17. Typical Clock Circuits

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

29-Jul-2009

PACKAGING INFORMATION

Orderable Device

TL16C554FN

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

PLCC

FN

68

80

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C554FNG4

TL16C554FNR

TL16C554FNRG4

TL16C554IFN

PLCC

LQFP

FN

PN

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C554IFNG4

TL16C554IFNR

TL16C554IFNRG4

TL16C554IPN

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C554IPNG4

TL16C554PN

119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C554PNG4

TL16C554PNR

TL16C554PNRG4

119 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

29-Jul-2009

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TL16C554PNR

LQFP

PN

80

1000

330.0

24.4

14.6

1.9

20.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

LQFP PN 80

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 41.0

TL16C554PNR

1000

Pack Materials-Page 2

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TL16C554FNR
厂家：	TEXAS INSTRUMENTS
描述：	ASYNCHRONOUS COMMUNICATIONS ELEMENT 异步通信部件微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
文件：	总35页 (文件大小：589K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TL16C554FNR [TI]

相关型号：

TL16C554FNRG4

TL16C554I

TL16C554IFN

TL16C554IFNG4

TL16C554IFNR

TL16C554IFNRG4

TL16C554IPN

TL16C554IPNG4

TL16C554IPNRG4

TL16C554PN

TL16C554PNG4

TL16C554PNR