TL16C750E [TI]

具有 128 字节 FIFO 及自动流控制的单路 UART;


型号：	TL16C750E
厂家：	TEXAS INSTRUMENTS
描述：	具有 128 字节 FIFO 及自动流控制的单路 UART 先进先出芯片
文件：	总61页 (文件大小：1852K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TL16C750E

ZHCSKJ6 –DECEMBER 2019

具有 128 字节 FIFO 的 TL16C750E UART

1 特性

3 说明

•

支持 1.62V 至 5.5V 的宽电源电压范围

TL16C750E 是一款单路通用异步接收器发送器

(UART)，具有 128 字节 FIFO、分数波特率支持、自

动硬件和软件流控制功能以及高达 6Mbps 的数据速

率。该器件具备增强功能，如分数波特率和传输字符

控制寄存器 (TCR)，该寄存器存储接收到的 FIFO 阈值

水平，以便在硬件和软件流控制期间自动启动或停止传

输，而无需 CPU 干预。

–

5V 和 3.3V 时为 6Mbps

（48MHz 振荡器输入时钟）

5V 和 3.3V 时为 3Mbps

（48MHz 振荡器输入时钟）

3.3V 时为 2Mbps

（32MHz 振荡器输入时钟）

2.5V 时为 1.5Mbps

（24MHz 振荡器输入时钟）

利用 FIFO RDY 寄存器，软件可以获取 TXRDY 或

RXRDY 的状态，而无需额外使用 GPIO。片上状态寄

存器可为用户提供错误指示、运行状态以及调制解调器

接口控制。可根据用户要求定制系统中断。内部环回功

能支持板上诊断。TL16C750E 整合了 UART 的功

能，UART 具有其自己的寄存器组和 FIFO。

1.8V 时为 1Mbps

（16MHz 振荡器输入时钟）

•

额定运行温度范围为 –40°C 至 105°C

128 字节发送或接收 FIFO

6 位分数波特率分频器

可通过软件选择的波特率发生器

该版本包含替代功能寄存器 (AFR)，用于启用

用于 DMA、中断生成以及软件或硬件流控制的可

编程且可选的发送和接收 FIFO 触发电平

TL16C750 版本以外的某些其他功能。一项附加功能是

IrDA 模式，它支持标准 IrDA (SIR) 模式，其波特率为

2400 至 115.2kbps。第三项附加功能是通过在每个通

道上提供一个输出引脚 (DTRx) 来支持 RS-485 总线驱

动器或收发器，对该引脚进行了定时，只要有传输数据

待处理，就使 RS-485 驱动器保持启用状态。

•

软件/硬件流控制

–

可编程的 Xon 和 Xoff 字符，可选“Xon 任意”

(Xon Any) 字符

–

可编程的自动 RTS 和自动 CTS 调制解调器控

制功能（CTS、RTS、DSR、DTR、RI 和

CD）

器件信息⁽¹⁾

•

用于接收和传输的数据的 DMA 信号功能

RS-485 模式支持

器件型号

封装

封装尺寸（标称值）

TL16C750E

TQFP (48)

7.00mm × 7.00mm

红外数据协会 (IrDA) 功能

可编程睡眠模式

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

可编程串行接口特性

方框图

–

5、6、7 或 8 位字符，可生成 1、1.5 或 2 个停

止位

A2 to A0

D7 to D0

UART

CTS

–

偶校验、奇校验或无奇偶校验位生成与检测

OP, DTR

DSR, RI, CD

RTS

128-Byte TX FIFO TX

UART Registers

Baud

Rate

Generator

•

错误启动位和线路中断检测

内部测试和环回功能

IOR

Data Bus

Interface

IOW

128-Byte RX FIFO RX

INT

TXRDY

RXRDY

RESET

2 应用

•

工业计算

Crystal

Oscillator

Buffer

XTAL1

XTAL2

通信设备

白色家电

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSF10

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.3 Feature Description................................................. 20

9.4 Device Functional Modes........................................ 32

9.5 Register Maps......................................................... 34

10 Application and Implementation........................ 50

10.1 Application Information.......................................... 50

10.2 Typical Application ................................................ 50

11 Power Supply Recommendations ..................... 53

12 Layout................................................................... 53

12.1 Layout Guidelines ................................................. 53

12.2 Layout Examples................................................... 54

13 器件和文档支持 ..................................................... 55

13.1 文档支持................................................................ 55

13.2 接收文档更新通知 ................................................. 55

13.3 支持资源................................................................ 55

13.4 商标....................................................................... 55

13.5 静电放电警告......................................................... 55

13.6 Glossary................................................................ 55

14 机械、封装和可订购信息....................................... 55

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 7

7.7 Typical Characteristics............................................ 10

Parameter Measurement Information ................ 10

Detailed Description ............................................ 19

9.1 Overview ................................................................. 19

9.2 Functional Block Diagrams ..................................... 19

4 修订历史记录

日期

修订版本

说明

2019 年 12 月

初始发行版

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

5 说明（续）

UART 功能也称作异步通信元件 (ACE)，这两个术语可互换使用。本文档主要介绍每个 ACE 的行为并让读者了解

TL16C750E 器件中整合了两个此类器件。

6 Pin Configuration and Functions

PFB Package

48-Pin TQFP

Top View

RESET

DTR

RTS

INT

RXRDY

MODE

Not to scale

N.C. – No internal connection

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Address bit 0 select. Internal registers address selection. Refer to 图 30 for register address map.

Address bit 1 select. Internal registers address selection. Refer to 图 30 for register address map.

Address bit 2 select. Internal registers address selection. Refer to 图 30 for register address map.

Carrier detect (active low). A low on these pins indicates that a carrier has been detected by the modem.

Chip select. When CS is low, this input enables the ACE. When this input is high, the ACE remains inactive. When

MODE is pulled low for "IOR Unused" mode, this will be pulled low and the state of IOW is read to determine if the

transaction is a read or a write

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem

status register. Bit 0 (ΔCTS) of the modem status register indicates that CTS has changed states since the last read

from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto-

CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the

transmitter.

CTS

D0, D1, D2

D3, D4, D5, D6,

43, 44, 45

46, 47, 2,

3, 4

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the

controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.

I/O

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem

status register. Bit 1 (ΔDSR) of the modem status register indicates DSR has changed levels since the last read

from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is

generated.

DSR

DTR

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish

communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is

placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit.

These pins can also be used in the RS-485 mode to control an external RS-485 driver or transceiver.

Interface mode select pin. This pin must be tied to VCC or to GND. If MODE is pulled to VCC, IOR is used in

communication. If MODE is pulled to GND, IOR is NOT used for communication. Only the state of IOW is sampled

when CS is toggled low to determine if the transaction is a read or a write. In this mode, IOR must be connected to

VCC

MODE

V_SS

GND Power Reference

Interrupt. When active, INT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that

cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only),

an empty transmitter holding register, or an enabled modem status interrupt. INT is reset (deactivated) either when

the interrupt is serviced or as a result of a master reset.

INT

Read inputs. When IOR is active (low) while the ACE is selected, the CPU is allowed to read status information or

data from ACE register.

IOR

Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0 through D7) from

the external CPU to an internal register that is defined by address bits A0 through A2.

IOW

1, 5, 6, 9,

12, 13, 17,

20, 21, 22,

24, 25, 34,

36, 37, 48

No internal connection

The state of this pin is defined by the user through the software settings of the MCR register, bit 3. INT is set to

active mode and OP to logic 0 when the MCR-3 is set to logic 1. INT is set to the 3-state mode and OP to a logic 1

when MCR-3 is set to a logic 0

Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input

are disabled during reset time.

RESET

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status

the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs,

an interrupt is generated.

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is

set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a

result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS

mode, RTS is set to the inactive level by the receiver threshold control logic

RTS

Receive data input. During the local loopback mode, this RX input pin is disabled and TX data is internally

connected to the UART RX input internally. During normal mode, RX should be held high when no data is being

received. This input also can be used in IrDA mode. For more information, see IrDA Overview.

Receive ready (active low). RXRDY goes low when the trigger level has been reached or a timeout interrupt occurs.

It go high when the RX FIFO is empty or there is an error in RX FIFO.

RXRDY

Transmit data. This output is associated with serial transmit data from the TL16C750E device. During the local

loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.

Transmit ready (active low). TXRDY goes low when there are a trigger level number of spaces available. They go

high when the TX buffer is full.

TXRDY

V_CC

PWR Power supply inputs

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Pin Functions (continued)

I/O

DESCRIPTION

NAME

XTAL1

NO.

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be

connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see 图 27). Alternatively, an external

clock can be connected to XTAL1 to provide custom data rates.

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or

buffered clock output.

XTAL2

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–40

MAX

UNIT

V_CC

V_I

Supply voltage

Input voltage

V_CC+ 0.5

105

V_O

T_A

Output voltage

Operating free-air temperature

Storage temperature

°C

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC= 1.8 V ±10%

V_CC

V_I

Supply voltage

1.62

–0.3

1.4

1.8

1.98

Input voltage

0.9 × V_CC

V_IH

V_IL

V_O

I_OH

I_OL

High-level input voltage

Low-level input voltage

Output voltage

0.4

V_CC

–0.5

High-level output current

Low-level output current

Oscillator/clock speed

Operating free-air temperature

All outputs

MHz

℃

T_A

-40

105

V_CC= 2.5 V ±10%

V_CC

V_I

Supply voltage

2.25

–0.3

1.8

2.5

2.75

Input voltage

0.9 × V_CC

V_IH

V_IL

V_O

I_OH

I_OL

High-level input voltage

Low-level input voltage

Output voltage

0.6

V_CC

–1

High-level output current

Low-level output current

Oscillator/clock speed

Operating free-air temperature

All outputs

MHz

℃

T_A

-40

105

V_CC= 3.3 V ±10%

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC

V_I

Supply voltage

3.3

3.6

Input voltage

–0.3

V_CC

V_IH

V_IL

V_O

I_OH

I_OL

High-level input voltage

Low-level input voltage

Output voltage

0.7 × V_CC

0.8

V_CC

–1.8

3.2

High-level output current

Low-level output current

Oscillator or clock speed

Operating free-air temperature

All outputs

MHz

℃

T_A

-40

105

V_CC= 5 V ±10%

V_CC

V_I

Supply voltage

4.5

–0.3

5.5

Input voltage

V_CC

Except XTAL1

XTAL1

V_IH

V_IL

High-level input voltage

0.7 × V_CC

Except XTAL1

XTAL1

0.8

Low-level input voltage

0.3 × V_CC

V_O

I_OH

I_OL

Output voltage

V_CC

–4

MHz

℃

High-level output current

Low-level output current

Oscillator or clock speed

Operating free-air temperature

All outputs

T_A

-40

105

7.4 Thermal Information

PFB (TQFP)

48 PINS

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

°C/W

R_θJC(top)

R_θJC(bot)

17.3

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_CC= 1.8 V

V_OH

High-level output voltage

Low-level output voltage

I_OH= –0.5 mA

I_OL= 1 mA

1.3

V_OL

0.5

V_CC= 1.98 V,

V_I= 0 to 1.98 V

V_SS= 0,

All other terminals floating

I_I

Input current

μA

High-impedance state

output current

V_CC= 1.98 V,

V_O= 0 to 1.98 V

Chip selected in write mode or chip

deselect

I_OZ

±20

All other inputs at 0.4 V,

V_CC= 1.98 V, DSR, CTS, and RI at 2 No load on outputs, XTAL1 at 16

I_CC

Supply current

MHz,

Baud rate = 1 Mb/s

C_I(CLK)

C_O(CLK)

C_I

Clock input capacitance

Clock output capacitance

Input capacitance

V_CC= 0,

f = 1 MHz,

All other terminals grounded

V_SS= 0,

T_A= 25°C,

C_O

Output capacitance

V_CC= 2.5 V

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OH

V_OL

High-level output voltage

Low-level output voltage

I_OH= –1 mA

I_OL= 2 mA

1.8

0.5

V_CC= 2.75 V,

V_I= 0 to 2.75 V

V_SS= 0,

All other terminals floating

I_I

Input current

μA

V_CC= 2.75 V,

V_O= 0 to 2.75 V

High-impedance state

output current

Chip selected in write mode or chip

deselect

I_OZ

±20

All other inputs at 0.6 V,

V_CC= 2.75 V, DCD, CTS, and RI at 2 No load on outputs, XTAL1 at 24

I_CC

Supply current

MHz,

Baud rate = 1.5 Mb/s

C_I(CLK)

C_O(CLK)

C_I

Clock input capacitance

Clock output capacitance

Input capacitance

V_CC= 0,

f = 1 MHz,

All other terminals grounded

V_SS= 0,

T_A= 25°C,

C_O

Output capacitance

V_CC= 3.3 V

V_OH

High-level output voltage

Low-level output voltage

I_OH= –1.8 mA

I_OL= 3.2 mA

2.4

V_OL

0.5

V_CC= 3.6 V,

V_I= 0 to 3.6 V

V_SS= 0,

All other terminals floating

I_I

Input current

μA

High-impedance state

output current

V_CC= 3.6 V,

V_O= 0 to 3.6 V

Chip selected in write mode or chip

deselect

I_OZ

±20

All other inputs at 0.8 V,

No load on outputs, XTAL1 at 32

MHz,

I_CC

Supply current

V_CC= 3.6 V, DSR, CTS, and RI at 2 V

Baud rate = 2 Mb/s

C_I(CLK)

C_O(CLK)

C_I

Clock input capacitance

Clock output capacitance

Input capacitance

V_CC= 0,

f = 1 MHz,

All other terminals grounded

V_SS= 0,

T_A= 25°C,

C_O

Output capacitance

V_CC= 5 V

V_OH

High-level output voltage

Low-level output voltage

I_OH= –4 mA

I_OL= 4 mA

V_OL

0.5

V_CC= 5.5 V,

V_I= 0 to 5.5 V

V_SS= 0,

All other terminals floating

I_I

Input current

μA

High-impedance state

output current

V_CC= 5.5 V,

V_O= 0 to 5.5 V

Chip selected in write mode or chip

deselect

I_OZ

±20

All other inputs at 0.8 V,

No load on outputs, XTAL1 at 48

MHz,

I_CC

Supply current

V_CC= 5.5 V, DSR, CTS, and RI at 2 V

Baud rate = 3 Mb/s

C_I(CLK)

C_O(CLK)

C_I

Clock input capacitance

Clock output capacitance

Input capacitance

V_CC= 0,

f = 1 MHz,

All other terminals grounded

V_SS= 0,

T_A= 25°C,

C_O

Output capacitance

7.6 Timing Requirements

T_A= -40°C to 105°C, V_CC= 1.8 V to 5 V ±10% (unless otherwise noted)

LIMITS

1.8 V

2.5 V

3.3 V

5 V

UNIT

MIN MAX

IOR Used (MODE = VCC)

t_RESET

C_P

Reset pulse width

CP clock period

200

t_3w

Oscillator or clock speed

MHz

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Timing Requirements (continued)

T_A= -40°C to 105°C, V_CC= 1.8 V to 5 V ±10% (unless otherwise noted)

LIMITS

1.8 V

2.5 V

3.3 V

5 V

UNIT

MIN MAX

t_6s

Address setup time

Address hold time

IOR strobe width

Read cycle delay

Delay from IOR to data

Data disable time

IOW strobe width

Write cycle delay

Data setup time

t_6h

See 图 2 and 图 4

See 图 4

t_7w

t_9w

t_12d

t_12h

t_13w

t_15w

t_16s

t_16h

t_17d

See 图 4

See 图 2

Data hold time

See 图 2

Delay from IOW to output

50-pF load, see 图 6

Delay to set interrupt from MODEM

input

t_18d

50-pF load, see 图 6

120

t_19d

t_20d

t_21d

t_22d

Delay to reset interrupt from IOR

Delay from stop to set interrupt

Delay from IOR to reset interrupt

Delay from stop to interrupt

50-pF load

100

See 图 8

baudrate

50-pF load, see 图 8

See 图 14

100

baudrate

Delay from initial IOW reset to

transmit start

t_23d

See 图 14

baudrate

t_24d

t_25d

t_26d

t_27d

t_28d

Delay from IOW to reset interrupt

Delay from stop to set RXRDY

Delay from IOR to reset RXRDY

Delay from IOW to set TXRDY

Delay from start to reset TXRDY

See 图 14

baudrate

See 图 10 and 图 12

See 图 16 and

100

See 图 16 and

baudrate

No IOR (MODE = GND)

t_RESET

C_P

Reset pulse width

CP clock period

200

t_3w

Oscillator or clock speed

Address setup time

Address hold time

Read cycle delay

Delay from CS to data

Data disable time

IOW strobe width

Write cycle delay

Data setup time

MHz

t_6s

t_6h

See 图 3 and 图 5

See 图 5

t_9w

t_12d

t_12h

t_13w

t_15w

t_16s

t_16h

t_17d

See 图 5

See 图 3

Data hold time

See 图 3

Delay from CS to output

50-pF load, see 图 6

Delay to set interrupt from MODEM

input

t_18d

50-pF load, see 图 6

120

t_19d

t_20d

t_21d

t_22d

Delay to reset interrupt from CS

Delay from stop to set interrupt

Delay from IOR to reset interrupt

Delay from stop to interrupt

50-pF load

See 图 8

baudrate

50-pF load, see 图 8

See 图 14

baudrate

Delay from initial CS reset to transmit

start

t_23d

See 图 14

baudrate

t_24d

t_25d

t_26d

Delay from IOW to reset interrupt

Delay from stop to set RXRDY

Delay from CS to reset RXRDY

See 图 14

baudrate

See 图 10 and 图 12

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Timing Requirements (continued)

T_A= -40°C to 105°C, V_CC= 1.8 V to 5 V ±10% (unless otherwise noted)

LIMITS

1.8 V

2.5 V

3.3 V

5 V

UNIT

MIN MAX

t_27d

t_28d

t_29h

t_29s

Delay from CS to set TXRDY

Delay from start to reset TXRDY

IOW hold time to CS

See 图 16 and

baudrate

See 图 16 and

See 图 3 and 图 5

IOW setup time to CS

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

7.7 Typical Characteristics

Tested as per electrical characteristics table

1.98 V

2.75 V

3.6 V

5.5 V

-40 -25 -10

Temperature (°C)

95 105

图 1. I_CCvs Temperature

8 Parameter Measurement Information

A[2:0]

Valid Address

t_6s

t_6h

t_6s

t_6h

t_13w

t_15d

t_13w

IOW

[7:0]

t_16s

t_16h

t_16s

Valid Data

图 2. General Write Timing (IOR and IOW Mode, MODE = VCC)

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Parameter Measurement Information (接下页)

A[2:0]

Valid Address

t_6s

t_6h

t_6s

t_6h

t_13w

t_29s

t_29h

IOW

[7:0]

t_16s

t_16h

t_16s

t_16h

Valid Data

图 3. General Write Timing (IOW Only Mode, MODE = GND)

A[2:0]

Valid Address

t_6s

t_6h

t_6s

t_6h

t_7w

t_9w

t_7w

IOR

t_12h

t_12d

[7:0]

Valid Data

图 4. General Read Timing (IOR and IOW Mode, MODE = VCC)

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Parameter Measurement Information (接下页)

A[2:0]

Valid Address

t_6s

t_6h

t_6s

t_6h

t_7w

t_29s

t_29h

IOW

[7:0]

t_12d

t_12h

t_12d

t_12h

Valid Data

图 5. General Read Timing (IOW Only Mode, MODE = GND)

IOW

Active

17d

RTS

DTR

Change of State

CTS

DSR

Change of State

t_18d

Active

INT

Active

t_19d

Active

IOR

t_18d

Change of State

图 6. Modem or Output Timing (IOR and IOW Mode, MODE = VCC)

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Parameter Measurement Information (接下页)

图 7. Modem or Output Timing (IOW Only Mode, MODE = GND)

Stop

Bit

Start

Bit

Data Bits (5œ8)

Parity

Bit

Next Data

Start Bit

5 Data Bits

6 Data Bits

7 Data Bits

t_20d

INT

Active

t_21d

Active

IOR

16-Baud Rate Clock

图 8. Receive Timing (IOR and IOW Mode, MODE = VCC)

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Parameter Measurement Information (接下页)

图 9. Receive Timing (IOW Only Mode, MODE = GND)

Start

Stop

Bit

Data Bits (5œ8)

Parity

Bit

Next Data

Start Bit

t_25d

Active Data

Ready

RXRDY

t_26d

Active

IOR

图 10. Receive Ready Timing in Non-FIFO Mode (IOR and IOW Mode, MODE = VCC)

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Parameter Measurement Information (接下页)

图 11. Receive Ready Timing in Non-FIFO Mode (IOW Only Mode, MODE = GND)

RXRDY

IOR

图 12. Receive Timing in FIFO Mode (IOR and IOW Mode, MODE = VCC)

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Parameter Measurement Information (接下页)

图 13. Receive Timing in FIFO Mode (IOW Only Mode, MODE = GND)

Stop

Bit

Start

Bit

Data Bits (5œ8)

Next Data

Start Bit

Parity

Bit

5 Data Bits

6 Data Bits

7 Data Bits

t_22d

Active

Tx Ready

INT

t_24d

t_23d

Active

IOW

16-Baud Rate Clock

图 14. Transmit Timing (IOR and IOW Mode, MODE = VCC)

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Parameter Measurement Information (接下页)

图 15. Transmit Timing (IOW Only Mode, MODE = GND)

Start

Bit

Stop

Bit

Data Bits (5œ8)

Next Data

Start Bit

Parity

Bit

Active

Byte 1

IOW

t_28d

D0œD7

t_27d

Active

Transmitter Ready

Transmitter

Not Ready

TXRDY

图 16. Transmit Ready Timing in Non-FIFO Mode (IOR and IOW Mode, MODE = VCC)

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Parameter Measurement Information (接下页)

t_27d

图 17. Transmit Ready Timing in Non-FIFO Mode (IOW Only Mode, MODE = GND)

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9 Detailed Description

9.1 Overview

The TL16C750E UART is pin-compatible with the TL16C550D UART in the PFB package. It provides more

enhanced features. All additional features are provided through a special enhanced features register.

The TL16C750E UART performs serial-to-parallel conversion on data characters received from peripheral

devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The

complete status of the TL16C750E UART can be read at any time during functional operation by the processor.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the

RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 128-byte receive FIFO and

transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own

desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity

and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.

The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control

operations, software flow control and hardware flow control capabilities.

9.2 Functional Block Diagrams

A2 to A0

D7 to D0

UART

CTS

OP, DTR

DSR, RI, CD

RTS

128-Byte TX FIFO TX

UART Registers

Baud

Rate

Generator

IOR

Data Bus

Interface

IOW

128-Byte RX FIFO RX

INT

TXRDY

RXRDY

RESET

Crystal

Oscillator

Buffer

XTAL1

XTAL2

图 18. TL16C750E Functional Block Diagram

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Functional Block Diagrams (接下页)

Modem Control Signals

Control Signals

Status Signals

Bus

Interface

Control

and

Status Block

Divisor

Control Signals

Fractional

Baud-Rate

Generator

Status Signals

UART_CLK

Int_Rx

IrDA

Receiver Block

Logic

Vote

Logic

128-Byte

Receiver FIFO

Int_Tx

Transmitter Block

Logic

128-Byte

Transmitter FIFO

IrDA

NOTE: The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a

majority vote to determine the logic level received. The vote logic operates on all bits received.

图 19. TL16C750E Functional Block Diagram – Control Blocks

9.3 Feature Description

9.3.1 UART Modes

The TL16C750E UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive

software overhead by buffering received and transmitted characters.

The TL16C750E UART has selectable hardware flow control and software flow control. Both schemes

significantly reduce software overhead and increase system efficiency by automatically controlling serial data

flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses

programmable Xon and Xoff characters.

9.3.2 Trigger Levels

The TL16C750E UART provides independent selectable and programmable trigger levels for both receiver and

transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in

effect, the trigger level is the default value of one byte. The selectable trigger levels are available through the

FCR. The programmable trigger levels are available through the TLR.

Both the receiver and transmitter FIFOs can store up to 128 bytes (including three additional bits of error status

per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and

TXRDY allow signaling of DMA transfers.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Feature Description (接下页)

注

When writing data into the transmit FIFO, the transmission starts immediately, which shifts

the first element out of the FIFO. Depending on the speed of the processor, it may be

possible to get a pulse on the TXRDY pin, since the level falls below the trigger threshold.

9.3.3 Hardware Flow Control

Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled or

disabled independently by programming EFR[7:6].

With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output

when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is

sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is

activated or deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated

during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive

FIFO servicing latency.

9.3.4 Auto-RTS

Auto-RTS data flow control originates in the receiver block (see 图 18). 图 20 shows RTS functional timing. The

receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below

the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached, RTS is deasserted.

The sending device (for example, another UART) may send an additional byte after the trigger level is reached

(assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTS

until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches

the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume

transmission.

Byte N

Byte N+1

Stop

Start

RTS

IOR

N+1

A. N = receiver FIFO trigger level B.

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.

图 20. RTS Functional Timing

9.3.5 Auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter

sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the

middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host

system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the

device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the

transmit FIFO and a receiver overrun error can result. 图 21 shows CTS functional timing, and 图 22 shows an

example of autoflow control.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

Feature Description (接下页)

Byte 0–7

Stop

Byte 0–7 Stop

Start

CTS

A. When CTS is low, the transmitter keeps sending serial data out.

B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the

current byte, but it does not send the next byte.

C. When CTS goes from high to low, the transmitter begins sending data again.

图 21. CTS Functional Timing

UART 1

UART 2

Serial to

Parallel

Parallel to

Serial

FIFO

Flow

RTS CTS

Flow

Control

D7 – D0

Parallel to

Serial

Serial to

Parallel

FIFO

Flow

CTS RTS

Flow

Control

图 22. Autoflow Control (Auto-RTS and Auto-CTS) Example

9.3.6 Software Flow Control

Software flow control is enabled through the enhanced feature register and the modem control register. Different

combinations of software flow control can be enabled by setting different combinations of EFR[3−0]. 表 1 shows

software flow control options.

Two other enhanced features relate to software flow control:

•

Xon Any Function [MCR(5): Operation resumes after receiving any character after recognizing the Xoff

character.

•

Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character sets the

Xoff interrupt [IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The

special character is transferred to the RX FIFO.

注

It is possible for an Xon1 character to be recognized as an Xon Any character, which

could cause an Xon2 character to be written to the RX FIFO.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

表 1. Software Flow Control Options EFR[3:0]

BIT 3

BIT 2

BIT 1

BIT 0

TX, RX SOFTWARE FLOW CONTROLS

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1, Xon2: Xoff1, Xoff2

No receive flow control

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1, Xon2: Xoff1, Xoff2

Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

No transmit flow control

Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

When software flow control operation is enabled, the TL16C750E device compares incoming data with Xoff1 and

(1)

Xoff2 programmed characters (in certain cases Xoff1 and Xoff2 must be received sequentially). When an Xoff

character is received, transmission is halted after completing transmission of the current character. Xoff character

detection also sets IIR[4] and causes INT to go high (if enabled via IER[5]).

To resume transmission an Xon1 and Xon2 character must be received (in certain cases Xon1 and Xon2 must

be received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt

disappears.

注

If a parity, framing, or break error occurs while receiving a software flow control character,

this character is treated as normal data and is written to the RCV FIFO.

Xoff1 and Xoff2 characters are transmitted when the RX FIFO has passed the programmed trigger level

TCR[3:0].

Xon1 and Xon2 characters are transmitted when the RX FIFO reaches the trigger level programmed via

TCR[7:4].

注

If, after an Xoff character has been sent, software flow control is disabled, the UART

transmits Xon characters automatically to enable normal transmission to proceed. A

feature of the TL16C750E UART design is that if the software flow combination (EFR[3:0])

changes after an Xoff has been sent, the originally programmed Xon is automatically sent.

If the RX FIFO is still above the trigger level, the newly programmed Xoff1 or Xoff2 is

transmitted.

The transmission of Xoff and Xon follows the exact same protocol as transmission of an ordinary byte from the

FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least

significant bits of Xoff1, Xoff2 and Xon1, Xon2 are transmitted. The transmission of 5, 6, or 7 bits of a character

is seldom done, but this functionality is included to maintain compatibility with earlier designs.

It is assumed that software flow control and hardware flow control are never enabled simultaneously. 图 23

shows a software flow control example.

(1) When pairs of Xon and Xoff characters are programmed to occur sequentially, received Xon1 and Xoff1 characters is written to the RX

FIFO if the subsequent character is not Xon2 and Xoff2.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

UART 1

UART 2

Transmit

FIFO

Receive

FIFO

Data

Parallel to Serial

Serial to Parallel

Xon-1 Word

Serial to Parallel

Parallel to Serial

Xon-1 Word

Xoff − Xon − Xoff

Xon-2 Word

Xoff-1 Word

Compare

Programmed

Xon −Xoff

Xoff-2 Word

Characters

图 23. Software Flow Control Example

9.3.7 Software Flow Control Example

Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with

single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0] = 7) set to 56 and Xon

threshold (TCR[7:4] = 4) set to 32. Both have the interrupt receive threshold (TLR[7:4] = 6) set to 48.

UART1 begins transmission and sends 48 characters, at which point UART2 generates an interrupt to its

processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 continues sending

characters until a total of 56 characters have been sent. At this time UART2 transmits a 0F to UART1, informing

UART1 to halt transmission. UART1 likely sends the 57^thcharacter while UART2 is sending the Xoff character.

Now, UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level drops to 32.

UART2 now sends a 0D to UART1, informing UART1 to resume transmission.

注

It is possible that there could be a glitch on the RXRDY pin when the Xoff2 character is

received with a parity error. A read to the LSR register shows that bit 7 is set, due to an

error in the RX FIFO.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9.3.8 Reset

表 2 summarizes the state of outputs after reset.

表 2. Register Reset Functions⁽¹⁾

RESET

CONTROL

NAME

RESET STATE

IER

IIR

Interrupt enable register

RESET

0x00

0x01

Interrupt identification

RESET

FCR

LCR

MCR

LSR

FIFO control register

Line control register

Modem control register

Line status register

RESET

0x00

0x1D

0x00

0x60

Bits 0 to 3 cleared. Bits 4 to 7 input

signals.

MSR

Modem status register

RESET

EFR

RHR

Enhanced feature register

Receiver holding register

RESET

0x00

Pointer logic cleared

Transmitter holding

THR

TCR

RESET

Pointer logic cleared

0x00

Transmission control

TLR

AFR

Trigger level register

RESET

0x00

0x10

Alternate function register

(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, and Xoff2 are not reset by the top-level reset signal

RESET, that is, they hold their initialization values during reset.

表 3 summarizes the state of outputs after reset.

表 3. Signal Reset Functions

SIGNAL

RESET CONTROL

RESET

RESET STATE

High

Low

RTS

DTR

RESET

RXRDY

TXRDY

RESET

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.3.9 Interrupts

The TL16C750E UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability.

The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to

an interrupt generation. The IER also can disable the interrupt system by clearing bits 0 to 3, 5 to 7. When an

interrupt is generated, the interrupt identification register (IIR) indicates that an interrupt is pending and provides

the type of interrupt through IIR[5−0]. 表 4 summarizes the interrupt control functions.

表 4. Interrupt Control Functions

PRIORITY

LEVEL

INTERRUPT

TYPE

IIR[5–0]

INTERRUPT SOURCE

INTERRUPT RESET METHOD

000001

000110

None

Receiver line

status

OE, FE, PE, or BI errors occur in

characters in the RX FIFO

FE < PE < BI: All erroneous characters are

read from the RX FIFO. OE: Read LSR

001100

000100

RX timeout

Stale data in RX FIFO

Read RHR

RHR interrupt

DRDY (data ready)

(FIFO disable)

RX FIFO above trigger level (FIFO enable)

000010

THR interrupt

TFE (THR empty)

Read IIR or a write to the THR

(FIFO disable)

TX FIFO passes above trigger level (FIFO

enable)

001000

010000

Modem status

Xoff interrupt

MSR[3:0] != 0

Read MSR

Receive Xoff character or

characters/special character

Receive Xon character or characters/Read of

IIR

100000

CTS, RTS

RTS pin or CTS pin change state from

active (low) to inactive (high)

Read IIR

It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.

LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors

remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the RX

FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the

FIFO. If the RX FIFO is empty, then LSR[4–2] is all 0.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon

flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of

the ISR.

9.3.10 Interrupt Mode Operation

In interrupt mode (if any bit of IER[3:0] is 1), the processor is informed of the status of the receiver and

transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register

(LSR) to see if any interrupt needs to be serviced. 图 24 shows interrupt mode operation.

IER

IOW IOR

INT

Processor

IIR

THR

RHR

图 24. Interrupt Mode Operation

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9.3.11 Polled Mode Operation

In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the

line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the

receiver and transmitter is automatically known by means of interrupts sent to the CPU. 图 25 shows polled

mode operation.

LSR

IOW IOR

Processor

IER

THR

RHR

图 25. FIFO Polled Mode Operation

9.3.12 Break and Timeout Conditions

An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×

programmed word length) + 12 bits and there is at least one byte stored in the RX FIFO.

When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.3.13 Programmable Baud Rate Generator with Fractional Divisor

The TL16C750E UART contains a programmable baud generator that divides reference clock by a divisor in the

range between 1 and (2¹⁶− 1) and a decimal resolution of 1/64. The output frequency of the baud rate generator

is 8× or 16× the baud rate, depending on the value of DLF[7]. An additional divide-by-4 prescaler is also

available and can be selected by MCR[7] as shown in the following. The formula for the divisor is:

Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate × baud divider)

Where 'baud divider' is either 8 or 16, depending on the value of DLF[7]. By default, DLF[7] = 0, which

corresponds

baud

divider

and

1 when MCR[7] is set to 0 after reset

4 when MCR[7] is set to 1 after reset

Prescaler =

图 26 shows the internal prescaler and baud rate generator circuitry.

DLL, DLH,

DLF

MCR[7] = 0

Prescaler Logic

(Divide By 1)

Internal Baud

Rate Clock For

Transmitter and

Receiver

XTAL 1

XTAL 2

Baud Rate

Generator

Logic

Input Clock

Reference

Clock

Prescaler Logic

(Divide By 4)

MCR[7] = 1

图 26. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and

most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled,

because no baud clock is generated. The programmable baud rate generator is provided to select both the

transmit and receive clock rates. 表 5 and 表 6 show the baud rate and divisor correlation for the crystal with

frequency 1.8432 and 3.072 MHz, respectively.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

表 5. Baud Rates Using a 1.8432-MHz Crystal

DIVISOR USED TO

GENERATE 16×

CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

DESIRED

BAUD RATE

2304

1536

1047

857

768

384

192

110

0.026

134.5

150

0.058

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

0.69

2.86

表 6. Baud Rates Using a 3.072-MHz Crystal

DIVISOR USED TO

GENERATE 16×

CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

DESIRED

BAUD RATE

3840

2560

1745

1428

1280

640

320

160

107

110

0.026

134.5

150

0.034

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

0.312

0.628

1.23

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

图 27 shows the crystal clock circuit reference.

V_CC

Driver

XTAL1

External

Clock

Crystal

R_p

Optional

Driver

RX2

XTAL2

Optional

Clock

Output

Oscillator Clock

to Baud Generator

Logic

Oscillator Clock

to Baud Generator

Logic

XTAL2

A. For crystal with fundamental frequency from 1 to 24 MHz

B. For input clock frequency higher than 24 MHz, the crystal is not allowed and the oscillator must be used, because the

TL16C750E internal oscillator cell can only support the crystal frequency up to 24 MHz.

图 27. Typical Crystal Clock Circuits

9.3.14 Fractional Divisor

The TL16C750E supports fractional divisors with a fractional resolution of 64 steps. This makes it possible to

achieve many baud rates with a single crystal selection.

The following register settings must be configured to use the fractional divider:

•

LCR[7] = 1

LCR ≠ 0xBF

EFR[4] = 1

MCR ≠ 0bx1x0x1xx

注

A 'x' denotes a do not care value of the bit.

To calculate the values necessary to put into the registers, the following functions are needed:

•

TRUNC(X): Truncate X, return just the integer portion of a real number. EX: TRUNC(3.14) = 3

ROUND(X): Round X to the nearest integer. EX: ROUND(3.1) = 3 and ROUND(3.6) = 4

>>: Bit shift towards the right operation. EX: 0x1000 >> 8 = 0x0010. Or 0b0001 0000 0000 0000 >> 8 =

0b0000 0000 0001 0000

•

&: Bitwise AND function, used to mask bits. EX: 0x1234 & 0x00FF = 0x0034 and 0x8765 & 0xFF00 = 0x8700

Calculating

the

required

divisor

Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate × baud divider)

calculated

Where 'baud divider' is either 8 or 16, depending on the value of DLF[7]. By default, DLF[7] = 0, which

corresponds to a baud divider of 16.

Once the required divisor is found, then the register values can be calculated from

DLH = TRUNC(Divisor) >> 8

DLL = TRUNC(Divisor) & 0x00FF

DLF = ROUND( (Divisor-TRUNC(Divisor) ) x 128)

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

表 7. Baud Rates Using a 24-MHz Crystal and a 16× Baud Divider

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

(%)

DIVISOR USED TO

GENERATE 16×

CLOCK

CLOSEST

DIVISOR

OBTAINABLE

DLH

VALUE

(HEX)

DLL

VALUE

(HEX)

DLF

VALUE

(HEX)

DESIRED BAUD

RATE

400

2400

3750

625

3750

625

0x0E

0x02

0x01

0x00

0xA6

0x71

0x38

0x9C

0x96

0x4E

0x3C

0x34

0x27

0x1E

0x1A

0x14

0x0F

0x0D

0x09

0x07

0x06

0x05

0x03

0x02

0x01

0x00

0x20

0x10

0x00

0x08

0x00

0x05

0x04

0x00

0x03

0x00

0x01

0x31

0x20

0x2B

0x21

0x00

0x30

0x10

0x00

0x28

0x20

4800

312.5

156.25

150

312 32/64

156 16/64

150

9600

10000

19200

25000

28800

38400

50000

57600

75000

100000

115200

153600

200000

225000

230400

250000

300000

400000

460800

500000

750000

921600

1000000

78.125

78 8/64

52.0833

39.0625

52 5/64

39 4/64

0.01

26.0417

26 3/64

0.02

13.0208

9.7656

7.5

13 1/64

9 49/64

7 32/64

6 43/64

6 33/64

0.04

6.6667

6.5104

0.08

3.75

3 48/64

3 16/64

3.2552

0.16

1.6276

1.5

1 40/64

1 32/64

0.16

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.4 Device Functional Modes

9.4.1 Device Interface Mode

There are 2 options for the interface between the processor and this device. The MODE pin selects the behavior

of the interface by being connected to VCC or to GND.

9.4.1.1 IOR Used (MODE = V_CC

)

When this mode is selected, both IOW and IOR are used to determine if a read or a write is occurring to the

selected address. When CS is pulled low, the device is in an active state and ready for communication. IOW or

IOR may then go low to start the transaction to/from the processor. If IOR is pulled low, a read is performed. If

IOW is pulled low, a write is performed.

9.4.1.2 IOR Unused (MODE = GND)

When this mode is selected, only the state of IOW is used to determine if a read or a write is occurring to the

selected address. When CS is pulled low, the IOW pin is sampled. If IOW is low, then a write occurs. If IOW is

high, then a read occurs.

9.4.2 DMA Signaling

There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].

In DMA mode 0 or FIFO disable (FCR[0] = 0), DMA occurs in single character transfers. In DMA mode 1,

multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.

9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)

Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has

been loaded into it.

Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the

receiver is empty.

图 28 shows TXRDY and RXRDY in DMA mode 0 or FIFO disable.

RXRDY

TXRDY

wrptr

rdptr

At Least One

Location Filled

At Least One

Location Filled

RXRDY

TXRDY

FIFO Empty

wrptr

rdptr

图 28. TXRDY and RXRDY in DMA Mode 0 or FIFO Disable

9.4.2.2 Block DMA Transfers (DMA Mode 1)

Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when the

FIFO is full.

Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It

goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Device Functional Modes (接下页)

图 29 shows TXRDY and RXRDY in DMA mode 1.

wrptr

Trigger

Level

TXRDY

RXRDY

rdptr

At Least One

Location Filled

Trigger

Level

TXRDY

RXRDY

wrptr

FIFO Empty

rdptr

图 29. TXRDY and RXRDY in DMA Mode 1

9.4.3 Sleep Mode

Sleep mode is an enhanced feature of the TL16C750E UART. It is enabled when EFR[4], the enhanced

functions bit, is set and when IER[4] is set. Sleep mode is entered when:

•

The serial data input line, RX, is idle (see Break and Timeout Conditions).

The TX FIFO and TX shift register are empty.

There are no interrupts pending except THR and timeout interrupts.

Sleep mode is not entered if there is data in the RX FIFO.

In sleep mode, the UART clock and baud rate clock are stopped. Because most registers are clocked using

these clocks, the power consumption is greatly reduced. The UART wakes up when any change is detected on

the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO.

注

Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done

during sleep mode. Therefore, TI recommends to disable sleep mode using IER[4] before

writing to DLL or DLH.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.5 Register Maps

9.5.1 Registers Operations

Each register is selected using address lines A[0], A[1], A[2], and in some cases, bits from other registers. The

programming combinations for register selection are shown in 图 30.

ADDRESS

READ MODE

WRITE MODE

[A2:A0]

000

001

010

011

100

101

110

111

RHR

DLL

THR

DLL

Receive Holding Divisor Latch LSB

Transmit Holding Divisor Latch LSB

IER

DLH

IER

DLH

Interrupt Enable Divisor Latch MSB

IIR

Interrupt

Identification

AFR

EFR

FCR

AFR

EFR

Alternate Function Enhanced Feature

FIFO Control

Alternate Function Enhanced Feature

LCR

Line Control

MCR

Xon1

MCR

Xon1

Modem Control

Xon 1 word

Modem Control

Xon 1 word

LSR

Xon2

Line Status

Xon 2 word

MSR

Xoff1

TCR

Transmission

Control

Xoff1

TCR

Transmission

Control

Modem Status

Xoff 1 word

SPR

Xoff2

TLR

DLF

FIFO RDY

SPR

Xoff2

TLR

DLF

Scratch Register

Xoff 2 word

Trigger Level

Fractional Divisor

FIFO Ready

Scratch Register

Xoff 2 word

Trigger Level

Fractional Divisor

Accessible only when LCR[7] = 1

Accessible only when LCR[7:5] = 0b100

Accessible only when LCR = 0b1011 1111 (0xBF)

Accessible only when EFR[4] = 1 and MCR[6] = 1

Accessible only when LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1, MCR ≠ 0bx1x0x1xx

Accessible only when any CS A-B = 0, MCR[2] = 1 and MCR[4] = 0

NOTE: MCR[7:5], FCR[5:4], and IER[7:4] can only be modified when EFR[4] is set.

图 30. Register Map – Read and Write Properties

表 8 lists and describes the TL16C750E internal registers.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

表 8. TL16C750E Internal Registers^{(1) (2)}

ADDRESS

[A2:A0]

R/W

ACCESS

CONSIDERATION

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(3)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RHR

LCR[7] = 0

0 0 0

0 0 1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

THR

DLL⁽⁴⁾

LCR[7] = 1

LCR[7] = 0

LCR[7] = 1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CTS#

Interrupt

enable⁽¹⁾

RTS# Interrupt Xoff Interrupt

Sleep

mode⁽¹⁾

Modem status

RX line status

THR empty

interrupt

RX data available

IER

enable⁽¹⁾

interrupt

DLH⁽⁴⁾

IIR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Interrupt

priority bit 2

Interrupt

priority bit 1

Interrupt

priority bit 0

FCR(0)

CTS# / RTS#

Xoff

Interrupt status

LCR[7] = 0

RX trigger

level

TX trigger

level⁽¹⁾

TX trigger

level⁽¹⁾

DMA mode

select

Resets TX

FIFO

Resets RX

RX trigger level

Enable FIFOs

FCR

FIFO

0 1 0

DLY2

DLY1

DLY0

RCVEN

485LG

485EN

IREN

RES

AFR⁽⁵⁾

LCR[7:5] = 100

Special

character

detect

Enable

enhanced

functions

S/W flow

control bit 3

S/W flow

control bit 2

S/W flow

control bit 1

S/W flow control

LCR[7:0] =

10111111

Auto CTS#

Auto RTS#

EFR⁽⁶⁾

LCR

bit 0

DLAB & EFR Break control

Parity type

select

Sets parity

Parity enable No. of stop bits

Word length

0 1 1

1 0 0

None

enable

bit

1x / 4x

clock⁽¹⁾

TCR & TLR

enable⁽¹⁾

Enable

loopback

FIFORDY

enable

LCR[7:0] ≠

10111111

Xon any⁽¹⁾

INT enable

RTS#

DTR#

MCR

Xon1⁽⁶⁾

LSR

LCR[7:0] =

10111111

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Error in RX

THR & TSR

Break

interrupt

LCR[7:0] ≠

10111111

THR empty

Framing error

Parity error

Overrun error

Data in receiver

FIFO

empty

1 0 1

LCR[7:0] =

10111111

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xon2⁽⁶⁾

(1) Bits represented by the blue shaded cells can only be modified if EFR[4] is enabled, that is, if enhanced functions are enabled.

(2) For more register access information, see 图 30.

(3) Read = R; Write = W

(4) This register is only accessible when LCR[7] = 1

(5) This register is only accessible LCR[7:5] = 100

(6) This register is only accessible when LCR = 1011 1111 (0xBF)

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

表 8. TL16C750E Internal Registers^{(1) (2)}(接下页)

ADDRESS

[A2:A0]

R/W

ACCESS

CONSIDERATION

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(3)

LCR[7:0] ≠

10111111 & none

of the below

CD#

RI#

DSR#

CTS#

CD#

RI#

DSR#

CTS#

MSR

conditions are true

1 1 0

LCR[7:0] =

10111111

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xoff1⁽⁶⁾

EFR[4] = 1 &

MCR[6] = 1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TCR⁽⁷⁾

LCR[7:0] ≠

10111111 & none

of the below

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SPR

conditions are true

LCR[7:0] =

10111111

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xoff2⁽⁶⁾

EFR[4] = 1 &

MCR[6] = 1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TLR⁽⁷⁾

1 1 1

LCR[7] = 1, LCR ≠

0xBF, EFR[4] = 1,

MCR ≠ 0bx1x0

bit 6

0 (Reserved,

RO)

bit 7

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DLF⁽⁸⁾

(9)

x1xx

RX FIFO A

status

FIFORdy⁽¹⁰

MCR[4] = 0 &

MCR[2] = 1

TX FIFO A status

)

(7) This register is only accessible when EFR[4] = 1 and MCR[6] = 1

(8) This register is accessible when LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1, MCR ≠ 0bx1x0 x1xx⁽⁹⁾

(9) A 'x' denotes a do not care for a bit value

(10) This register is accessible when any CS A-B = 0, MCR[2] = 1, and loopback MCR[4] = 0 is disabled.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9.5.2 Receiver Holding Register (RHR)

The receiver section consists of the RHR and the receiver shift register (RSR). The RHR is actually a 128-byte

FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel data and moved to the

RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location 0 of the FIFO

is used to store the characters. If overflow occurs, characters are lost. The RHR also stores the error status bits

associated with each character.

9.5.3 Transmit Holding Register (THR)

The transmitter section consists of the THR and the transmitter shift register (TSR). The transmit holding register

is actually a 128-byte FIFO. The THR receives data and shifts it into the TSR where it is converted to serial data

and moved out on the TX terminal. If the FIFO is disabled, location 0 of the FIFO is used to store the byte.

Characters are lost if overflow occurs.

9.5.4 FIFO Control Register (FCR)

This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and

receiver trigger levels, and selecting the type of DMA signaling. 表 9 shows FIFO control register bit settings.

表 9. FCR Bit Settings

BIT

BIT SETTINGS

0 = Disable the transmit and receive FIFOs

1 = Enable the transmit and receive FIFOs

0 = No change

1 = Clears the receive FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.

0 = No change

1 = Clears the transmit FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.

0 = DMA mode 0

1 = DMA mode 1

Sets the trigger level for the TX FIFO:

00 – 16 spaces

01 – 32 spaces

5:4⁽¹⁾

10 – 64 spaces

11 – 120 spaces

Sets the trigger level for the RX FIFO:

00 – 1 characters

7:6

01 – 4 characters

10 – 120 characters

11 – 124 characters

(1) FCR[5−4] can be modified and enabled only when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced

function.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.5.5 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop bits, and parity type are

selected by writing the appropriate bits to the LCR. 表 10 shows line control register bit settings.

表 10. LCR Bit Settings

BIT

BIT SETTINGS

Specifies the word length to be transmitted or received

00 – 5 bits

01 – 6 bits

10 − 7 bits

11 – 8 bits

1:0

Specifies the number of stop bits:

0 – 1 stop bits (Word length = 5, 6, 7, 8)

1 – 1.5 stop bits (Word length = 5)

1 – 2 stop bits (Word length = 6, 7, 8) 3

0 = No parity

1 = A parity bit is generated during transmission and the receiver checks for received parity.

0 = Odd parity is generated (if LCR[3] = 1)

1 = Even parity is generated (if LCR[3] = 1)

Selects the forced parity format (if LCR(3) = 1)

If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data.

If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received data.

Break control bit

0 = Normal operating condition

1 = Forces the transmitter output to go low to alert the communication terminal.

0 = Normal operating condition

1 = Divisor latch enable

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9.5.6 Line Status Register (LSR)

表 11 shows line status register bit settings.

表 11. LSR Bit Settings

BIT

BIT SETTINGS

0 = No data in the receive FIFO

1 = At least one character in the RX FIFO

0 = No overrun error

1 = Overrun error has occurred.

0 = No parity error in data being read from RX FIFO

1 = Parity error in data being read from RX FIFO

0 = No framing error in data being read from RX FIFO

1 = Framing error occurred in data being read from RX FIFO (that is, received data did not have a valid stop bit)

0 = No break condition

1 = A break condition occurred and associated byte is 00 (that is, RX was low for at least one character time frame)

0 = Transmit hold register is not empty

1 = Transmit hold register is empty. The processor can now load up to 128 bytes of data into the THR if the TX FIFO

is enabled.

0 = Transmitter hold and shift registers are not empty.

1 = Transmitter hold and shift registers are empty.

0 = Normal operation

1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. Bit 7 is cleared when no

errors are present in the FIFO.

When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO

(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is

output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are

identified by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors

remaining in the FIFO.

注

Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO

read pointer is incremented by reading the RHR.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.5.7 Modem Control Register (MCR)

The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. 表

12 shows modem control register bit settings.

表 12. MCR Bit Settings⁽¹⁾

BIT

BIT SETTINGS

0 = Force DTR output to inactive (high)

1 = Force DTR output to active (low). In loopback controls MSR[5]

0 = Force RTS output to inactive (high)

1 = Force RTS output to active (low)

In loopback controls MSR[4]

If Auto-RTS is enabled the RTS output is controlled by hardware flow control

0 Disables the FIFORdy register

1 Enable the FIFORdy register

In loopback controls MSR[6]

0 = Forces the INT output to high-impedance state

1 = Forces the INT output to the active state

In loopback controls MSR[7]

0 = Normal operating mode

1 = Enable local loopback mode (internal)

In this mode, the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input

internally

0 = Disable Xon Any function

1 = Enable Xon Any function

0 = No action

1 = Enable access to the TCR and TLR registers

0 = Divide by one clock input

1 = Divide by four clock input

(1) MCR[7:5] can be modified only when EFR[4] is set, that is, EFR[4] is a write enable.

9.5.8 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the modem, data set, or

peripheral device to the processor. It also indicates when a control input from the modem changes state. 表 13

shows modem status register bit settings.

表 13. MSR Bit Settings⁽¹⁾

BIT

BIT SETTINGS

Indicates that CTS input (or MCR[1] in loopback) has changed state. Cleared on a read.

Indicates that DSR input (or MCR[0] in loopback) has changed state. Cleared on a read.

Indicates that RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read.

Indicates that CD input (or MCR[3] in loopback) has changed state. Cleared on a read.

This bit is equivalent to MCR[1] during local loop-back mode. It is the complement to the CTS input.

This bit is equivalent to MCR[0] during local loop-back mode. It is the complement to the DSR input.

This bit is equivalent to MCR[2] during local loop-back mode. It is the complement to the RI input.

This bit is equivalent to MCR[3] during local loop-back mode. It is the complement to the CD input.

(1) The primary inputs RI, CD, CTS, and DSR are all active low, but their registered equivalents in the MSR and MCR (in loopback)

registers are active high.

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9.5.9 Interrupt Enable Register (IER)

The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR

interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in

response to interrupt generation. 表 14 shows interrupt enable register bit settings.

表 14. Interrupt Enable Register (IER) Bit Settings⁽¹⁾

BIT

BIT SETTINGS

0 = Disable the RHR interrupt

1 = Enable the RHR interrupt

0 = Disable the THR interrupt

1 = Enable the THR interrupt

0 = Disable the receiver line status interrupt

1 = Enable the receiver line status interrupt

0 = Disable the modem status register interrupt

1 = Enable the modem status register interrupt

0 = Disable sleep mode

1 = Enable sleep mode

0 = Disable the Xoff interrupt

1 = Enable the Xoff interrupt

0 = Disable the RTS interrupt

1 = Enable the RTS interrupt

0 = Disable the CTS interrupt

1 = Enable the CTS interrupt

(1) IER[7:4] can be modified only if EFR[4] is set, that is, EFR[4] is a write enable.

Re-enabling IER[1] causes a new interrupt, if the THR is below the threshold.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.5.10 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register, which provides the source of the interrupt in a prioritized manner. 表 15

shows interrupt identification register bit settings.

表 15. IIR Bit Settings

BIT

BIT SETTINGS

0 = An interrupt is pending

1 = No interrupt is pending

3:1

3-Bit encoded interrupt. See 表 14

1 = Xoff or special character has been detected

CTS/RTS low to high change of state

Mirror the contents of FCR[0]

7:6

The interrupt priority list is illustrated in 表 16.

表 16. Interrupt Priority List

PRIORITY

LEVEL

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

INTERRUPT SOURCE

Receiver line status error

Receiver timeout interrupt

RHR interrupt

THR interrupt

Modem interrupt

Received Xoff signal or special character

CTS, RTS change of state from active (low) to inactive (high)

9.5.11 Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. 表 17 shows the enhanced feature

表 17. EFR Bit Settings

BIT

BIT SETTINGS

3:0

Combinations of software flow control can be selected by programming bit 3 to bit 0. See 表 1.

Enhanced functions enable bit.

0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]

1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a

write enable

0 = Normal operation

1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is

transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.

RTS flow control enable bit

0 = Normal operation

1 = RTS flow control is enabled, that is, RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is

reached, and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.

CTS flow control enable bit

0 = Normal operation

1 = CTS flow control is enabled, that is, transmission is halted when a high signal is detected on the CTS pin

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

9.5.12 Divisor Latches (DLL, DLH, DLF)

Two 8-bit registers store the 16-bit divisor and a 6-bit fractional divisor for generation of the baud clock in the

baud rate generator. DLH, stores the most significant part of the divisor. DLL stores the least significant part of

the division. DLF stores the fractional value of the divisor as x / 64 where x is the value in DLF.

表 18. DLF Bit Values

BIT

BIT SETTINGS

Baud divider bit

0 (default) = Enable divide-by-16 baud divider

1 = Enable divide-by-8 baud divider

Reserved

5:0

6 bit fractional divider value (x / 64)

For more information on how to calculate the fractional values, see Fractional Divisor.

DLL, DLH and DLF can only be written to before sleep mode is enabled (that is, before IER[4] is set).

9.5.13 Transmission Control Register (TCR)

This 8-bit register is used to store the receive FIFO threshold levels to start or stop transmission during hardware

or software flow control. 表 19 shows transmission control register bit settings.

表 19. TCR Bit Settings

BIT

3:0

7:4

BIT SETTINGS

RCV FIFO trigger level to HALT transmission (0 to 60)

RCV FIFO trigger level to RESTORE transmission (0 to 60)

TCR trigger levels are available from 0 to 120 bytes with a granularity of 8.

TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that

TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must

be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious

operation of the device.

9.5.14 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt

generation. Trigger levels from 8 to 120 can be programmed with a granularity of 8. 表 20 shows trigger level

表 20. TLR Bit Settings

BIT

3:0

7:4

BIT SETTINGS

Transmit FIFO trigger levels (8 to 120), number of spaces available

RCV FIFO trigger levels (8 to 120), number of characters available

TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, then the selectable

trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels.

Trigger levels from 8 to 120 bytes are available with a granularity of 8. The TLR should be programmed for N / 8,

where N is the desired trigger level.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

9.5.15 FIFO Ready Register

The FIFO ready register provides realtime status of the transmit and receive FIFOs. 表 21 shows the FIFO ready

0), or TLR (when it has a nonzero value).

表 21. FIFO Ready Register

BIT

BIT SETTINGS

0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO.

1 = There are at least a TX trigger level number of spaces available in the TX FIFO.

3:1

Unused, always 0.

0 = There are fewer than a RX trigger level number of characters in the RX FIFO.

1 = The RX FIFO has more than a RX trigger level number of characters available for reading or a timeout condition has

occurred.

7:5

Unused, always 0

The FIFORdy register is a read only register and can be accessed when the UART is selected. CS = 0, MCR[2]

(FIFORdy Enable) is a logic 1, and loopback is disabled. Its address is 111.

9.5.16 Alternate Function Register (AFR)

The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C750. The first

addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to 115.2 kbps.

The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTR), which is

timed to keep the RS-485 driver enabled as long as transmit data is pending.

The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.

表 22. AFR Bit Settings

BIT

BIT SETTINGS

Reserved bit. Does not do anything

IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps; TI does not recommend the use of this

mode at higher speeds.

485EN enables the half duplex RS-485 mode and causes the DTR output to be set high whenever there is any data in

the THR or TSR and to be held high until the delay set by DLY2:0 has expired, at which time it is set low. The DTR

output is intended to drive the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts are held

off until the TSR is empty, unless 485LG is set.

485LG is set when the 485EN is set. This bit indicates that a relatively large data block is being set, requiring more than

a single load of the xmt fifo. In this case, the transmitter interrupts occur as in the standard RS-232 mode, either when

the xmt fifo contents drop below the xmt threshold or when the xmt fifo is empty.

RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in or snoop on the RS-485 traffic

or IrDA traffic. RS-485 mode is generally considered half duplex, and usually a node is either driving or receiving, but

there can be cases when it is advantageous to verify what you are sending. This can be used to detect collisions or as

part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the receiver stores any data

presented on RX, if any. Note that implies that the external RS-485 receiver is enabled. Whenever 485EN is cleared, the

serial receiver is enabled for normal full duplex RS-232 traffic. If RCVEN is cleared while 485EN is set, the receiver is

disabled while transmitting. SIR is also considered half duplex. Often the light energy from the transmitting LED is

coupled back into the receiving PIN diode, which creates an input data stream that is not of interest to the host. Disabling

the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading the data. On the other hand,

for diagnostic or other purposes, it may be useful to observe this data stream. For example, a mirror could be used to

intentionally couple the output LED to the input PIN. For these cases, RCVEN could be set to enable the receiver.

NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available, even in RS-232 mode. This

can be useful when checking code for valid threshold interrupts, as the timeout interrupt does not override the threshold

interrupt.

DLY2 to DLY0 sets a delay after the last stop bit of the last data byte being set before the DTR is set low, to allow for

long cable runs. The delay is in number of bit times and is enabled by 485EN. The delay starts only when both the xmt

serial shift register (TSR) is empty and the xmt fifo (THR) is empty, and if started, is cleared by any data being written to

the THR.

7:5

TL16C750E

www.ti.com.cn

LOOP MODE

ZHCSKJ6 –DECEMBER 2019

表 23. LOOP and RCVEN Functionality

RCVEN

AFR

MODE

DESCRIPTION

Receive threshold, timeout, and error detection interrupts available

Data stored in receive FIFO

AFR = 10

AFR = 14

AFR = 12

AFR = 00

RS-232

Receive threshold, timeout, and error detection interrupts available

Data stored in receive FIFO

RCVEN = 1

RS-485

IrDA

LOOP mode off,

MCR4 = 0,

RX, TX active

Receive threshold, timeout, and error detection interrupts available

Data stored in receive FIFO

Receive threshold and error detection interrupts available

Data stored in receive FIFO

RS-232

RCVEN = 0

RCVEN = 1

AFR = 04

AFR = 02

RS-485

IrDA

No data stored in receive FIFO, hence no interrupts available

Receive threshold, timeout, and error detection interrupts available

Data stored in receive FIFO

AFR = 10

AFR = 14

AFR = 12

AFR = 00

AFR = 04

AFR = 02

RS-232

RS-485

IrDA

Receive threshold, timeout, and error detection interrupts available

Data stored in receive FIFO

Receive threshold, timeout, and error detection interrupts available

Data stored in receive FIFO

LOOP mode on,

MCR4 = 1,

RX, TX inactive

Receive threshold and error detection interrupts available

Data stored in receive FIFO

RS-232

RS-485

IrDA

Receive threshold and error detection interrupts available

Data stored in receive FIFO

RCVEN = 0

Receive threshold and error detection interrupts available

Data stored in receive FIFO

9.5.17 RS-485 Mode

The RS-485 mode is intended to simplify the interface between the UART and an RS-485 driver or transceiver.

When enabled by setting 485EN, the DTR output goes high one bit time before the first stop bit of the first data

byte being sent, and remains high as long as there is pending data in the TSR or THR (xmt fifo). After both are

empty (after the last stop bit of the last data byte), the DTR output stays high for a programmable delay of 0 to

15 bit times, as set by DLY[2:0]. This helps preserve data integrity over long signal lines. This is illustrated in the

following.

Often RS-485 packets are relatively short and the entire packet can fit within the 128 byte xmt fifo. In this case, it

goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to

reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be

reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block), which causes

the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the

threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is

being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being

loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going

empty.

WR THR

1 Baud Time

Controlled by DLY[2:0]

DTRx

A. Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform

varies with baud rate but is typically in the microsecond range.

图 31. DTRx and Transmit Data Relationship

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

RS-485 XCVR

TSR

Loopback

RSR

RS-485 BUS

DEN

REN

DTR

48SEN

RCVEN

UART

图 32. RS-485 Application Example 1

RS-485 XCVR

TSR

RS-485 BUS

DTR

DEN

REN

Loopback

RSR

48SEN

RCVEN

UART

图 33. RS-485 Application Example 2

9.5.18 IrDA Overview

To Optoelectronic

Transmit Shift Register

Int_TX

Int_RX

LED

From

Optoelectronic

Pin Diode

Receive Shift Register

IREN

IrDA Converter

RCVEN

Baud Clock

Reset

图 34. IrDA Mode

The IrDA defines several protocols for sending and receiving serial infrared data, including rates of 115.2 kbps,

0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified first and the others must

maintain downward compatibility with it. At the 115.2 kbps rate, the protocol implemented in the hardware is fairly

simple. It primarily defines a serial infrared data word to be surrounded by a start bit equal to 0 and a stop bit

equal to 1. Individual bits are encoded or decoded the same whether they are start, data, or stop bits. The IrDA

engine in the TL16C750E device only evaluates single bits and follows the 115.2-kbps protocol. The 115.2-kbps

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

rate is a maximum rate. When both ends of the transfer are setup to a lower but matching speed, the protocol

still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843-MHz maximum. To

code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one pulse is sent or

received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6-μs wide and 3 clock cycles

long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3 clock cycles. The

transmitter output, TX, is intended to drive a LED circuit to generate an infrared pulse. The LED circuits work on

positive pulses. A terminal circuit is expected to create the receiver input, RX. Most, but not all, PIN circuits have

inversion and generate negative pulses from the detected infrared light. Their output is normally high. The

TL16C750E device can decode either negative or positive pulses on RX.

9.5.19 IrDA Encoder Function

Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this

block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously

cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7^th16XCLK. On the falling edge of the 10^th

16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the

seventh to tenth clocks of each 16-clock bit cycle.

16 Cycles

Int_TX

16XCLK

Int_TX

图 35. IrDA-SIR Encoding Scheme – Detailed

图 36. Encoding Scheme – Macro View

Timing Diagram

After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls

on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then

returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX,

Int_RX remains high.

16 Cycles

Int_TX

16XCLK

Int_RX

图 37. IrDA-SIR Decoding Scheme – Detailed

图 38. IrDA-SIR Decoding Scheme – Macro View

Timing Diagram

It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one

16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for

the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C750E

UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed

by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe

occurs on the 8^th16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop

bit occurs.

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

16XCLK

Int_RX

图 39. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones

16 Cycles

16XCLK

Int_RX

External Strobe

7 Cycles

16 Cycles

图 40. Recommended Strobing for Decoded Data

The TL16C750E device can decode positive pulses on RX. The timing is different, but the variation is invisible to

the UART. The decoder, which works from the falling edge, now recognizes a 0 on the trailing edge of the pulse

rather than on the leading edge. As long as the pulse duration is fairly constant, as defined by the specification,

the trailing edges should also be 16 clock cycles apart and data can readily be decoded. The 0 appears on

Int_RX after the pulse rather than at the start of it.

16XCLK

Int_RX

图 41. Positive RX Pulse Decode – Detailed View

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

Cycles

16XCLK

Int_RX

图 42. Positive RX Pulse Decode – Macro View

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The typical implementation is to use the TL16C750E as a RS-232 interface, which is intended to operate with a

5-V microprocessor.

10.2 Typical Application

The typical application is to communicate over UART, either through a RS-232 transceiver, or directly. The

general initialization sequence is recommended as following:

1. Set the desired baud rate with DLL and DLH (or with fractional baud rate if required)

2. Set the desired word length and other settings in the LCR register.

3. Reset the FIFOs with the FCR registers

D0-D7

A0-A2

D0-D7

A0-A2

Control

Signals

IOR

RS-232/RS-485

Transceiver

IOR

Processor

TL16C750E

IOW

RESET

TXRDY

RXRDY

RESET

TXRDY

RXRDY

图 43. Typical Application

10.2.1 Design Requirements

For this example, we'll assume a basic 9600 baud UART communication. This is one of the most common and

basic UART configurations.

表 24. Example design considerations

Constraint

Crystal oscillator speed

Desired baud rate

Parity

Value

24 MHz

9600 baud

None

Data bits

8 bits

Stop bits

1 bit

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

10.2.2 Detailed Design Procedure

The procedure to setup the part for transmission involves only a few register writes. Each step of the process is

outlined

10.2.2.1 Set the desired baud rate

As per 表 24, the desired baud rate is 9600 with an input clock of 24 MHz. The math required to calculate the

Since the device by default uses a 16x over sample setting, the math is 24E9 / (16 * 9600) = 156.25. This shows

that the fractional baud rate feature is required to achieve 9600 baud. Since the fractional baud rate gives x/64

resolution, 0.25 * 64 = 16. The below values are the divisor values to be used in the registers.

表 25. 9600 baud divisor values

DLH

Description

MSB of the divisor

LSB of the divisor

Fractional (1/64) divisor

Value

0x00

0x9C

0x10

DLL

DLF

Since these registers have access considerations in order to write to them (see 表 8), a few extra writes are

required to enable the writes to the desired registers.

表 26. Register writes to configure baud rate

Step

Description

Value

0xBF

0x10

0x93

Type

Enable access to EFR (enhanced function)

LCR (0b011) [W]

Enable the enhanced functionality (fractional

baud rate)

EFR (0b010) [W]

LCR (0b011) [W]

Enable extra feature registers and 8 bits/no

parity/1 stop bit

Write the MSB of the divisor

Write to the LSB of the divisor

Write to the fractional divisor

Change LCR back to normal mode

DLH (0b001) [W]

DLL (0b000) [W]

DLF (0b111) [W]

LCR (0b011) [W]

0x00

0x9C

0x10

0x13

10.2.2.2 Reset the fifos

Since the baud rate and UART settings are configured in the previous section, configuration is complete and the

FIFOs are ready to be reset for use.

表 27. Register writes to reset FIFOs

Step

Description

Value

Type

Reset FIFOs

FCR (0b010) [W]

0x06

0x01

Enable the FIFOs

10.2.2.3 Sending data on the bus

Once configuration is complete, the part is ready for data transmission. For the example the data 0xAA is written

to the bus. This is quite simple to do. Writing to THR (0b000) automatically shifts the written data into an internal

FIFO (since FIFOs are enabled) and then begins being shifted out onto the UART bus.

表 28. Register writes to writing data onto the bus

Step

Description

Value

Type

Write data onto bus

THR (0b000) [W]

0xAA

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

10.2.3 Application Curves

图 44. Waveform showing 0xAA waveform

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

11 Power Supply Recommendations

The power supply must provide a constant voltage with a 10% maximum variation of the nominal value and has

to be able to provide at least the maximum current consumption of the device for the selected nominal voltage

only for the UART device:

•

V_CC= 1.8 V

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5 V

The VCC pin must have a 1-µF bypass capacitor placed as close as possible to this pin. Also, TI recommends to

include two extra capacitors in parallel, which should also be placed as close as possible to the VCC pin. The

suggested values for these extra capacitors are 0.1 µF and 0.01 µF, respectively.

VCC_UART

C14

C15

C16

1 µF

0.1 µF

0.01 µF

Place as close as possible to the VCC pin of the UART.

图 45. Recommended Bypass Capacitors Array

12 Layout

12.1 Layout Guidelines

Traces, Vias, and Other PCB Components: A right angle in a trace can cause more radiation. The capacitance

increases in the region of the corner, and the characteristic impedance changes. This impedance change causes

reflections.

•

Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any

impedance change, the best routing would be a round bend (see 图 28).

Separate high-speed signals (for example, clock signals) from low-speed signals and digital from analog

signals; again, placement is important.

To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route

them with 90° to each other

图 46. Layout Do's and Don'ts

TL16C750E

ZHCSKJ6 –DECEMBER 2019

www.ti.com.cn

12.2 Layout Examples

To MCU

To TRX

1 : NC

2 : D5

NC : 36

RESET: 35

NC : 34

To MCU

3 : D6

4 : D7

DTR : 33

RTS : 32

OP : 31

5 : NC

6 : NC

7 : RX

8 : TX

TL16C750E

INT : 30

RXRDY : 29

A0 : 28

To TRX

To MCU

9 : NC

10 : MODE

Pulled to GND,

no IOR used

To MCU

A1 : 27

11 : CS

12 : NC

A2 : 26

NC : 25

To MCU

Legend

Top Layer

Bottom

Layer

Via to GND

Via to VCC

Via

Pull to

VCC

0603

CAP

because

MODE is

GND

Crystal

GND Plane

图 47. Typical UART Layout Example

TL16C750E

www.ti.com.cn

ZHCSKJ6 –DECEMBER 2019

13 器件和文档支持

13.1 文档支持

13.1.1 相关文档

请参阅如下相关文档：:

•

13.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TL16C750EPFBR

ACTIVE

TQFP

PFB

1000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

TL16C750E

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TL16C750EPFBR

TQFP

PFB

1000

330.0

16.4

9.6

1.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TQFP PFB 48

SPQ

Length (mm) Width (mm) Height (mm)

336.6 336.6 31.8

TL16C750EPFBR

1000

Pack Materials-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

0,13 NOM

5,50 TYP

7,20

Gage Plane

6,80

9,20

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TL16C750E [TI]

相关型号：

TL16C750EPFBR

TL16C750FN

TL16C750FNR

TL16C750FNRG4

TL16C750IPM

TL16C750PM

TL16C750PMG4

TL16C750PT

TL16C750Y

TL16C752

TL16C752B

TL16C752B-EP