TL16C752D [TI]
具有 64 字节 FIFO 的双路 UART;型号: | TL16C752D |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 64 字节 FIFO 的双路 UART 先进先出芯片 |
文件: | 总55页 (文件大小:1793K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
TL16C752D 具有 64 字节 FIFO 的双路 UART
1 特性
2 应用
1
•
与 TL16C2550 引脚兼容,可通过 改进的先入先出
(FIFO) 寄存器 提供增强功能
•
•
•
•
•
车用信息娱乐
移动设备
通信设备
白色家电
工业计算
•
支持 1.62V 至 5.5V 的宽电源电压范围
–
–
5V 时为 3Mbps(48MHz 振荡器输入时钟)
3.3V 时为 3Mbps(48MHz 振荡器输入时钟)
3 说明
–
–
2.5V 时为 1.5Mbps(24MHz 振荡器输入时钟)
1.8V 时为 1Mbps(16MHz 振荡器输入时钟)
TL16C752D 是一款双路通用异步收发器 (UART),具
有 64 字节 FIFO 以及自动硬件和软件流控制功能,数
据传输速率最高可达 3Mbps。该器件具备增强 功能的
磁场感测解决方案。该器件具有一个传输字符控制寄存
器 (TCR),可存储接收到的 FIFO 阈值电平,从而在硬
件和软件流控制过程中启动或停止传输。
•
•
•
•
运行温度范围为 –40°C 至 85°C
64 字节发送/接收 FIFO
可通过软件选择的波特率发生器
用于直接存储器存取 (DMA)、中断生成以及软件或
硬件流控制的可编程且可选的发送和接收 FIFO 触
发电平
凭借 FIFO RDY 寄存器,软件只需执行单次访问即可
获得两个端口的 TXRDY 或 RXRDY 状态。片上状态
寄存器可为用户提供错误指示、运行状态以及调制解调
器接口控制。可根据用户要求定制系统中断。内部环回
功能支持板上诊断。TL16C752D 整合了两个 UART
的功能,每个 UART 都有自己的寄存器集和 FIFO。
•
软件/硬件流控制
–
可编程的 Xon 和 Xoff 字符,可选“Xon 任意”
(Xon Any) 字符
–
可编程的自动请求发送 (RTS) 和自动清除发送
(CTS) 调制解调器控制功能(CTS、RTS、数据
准备就绪 (DSR)、数据终端就绪 (DTR)、振铃
指示器 (RI) 和载波检测 (CD))
器件信息(1)
•
DMA 信号传输功能,用于 PN 封装中的数据发送
与接收
器件型号
封装
封装尺寸(标称值)
TL16C752D
TQFP (48)
7.00mm x 7.00mm
•
•
•
•
RS-485 模式支持
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
红外数据协会 (IrDA) 功能
可编程休眠模式
框图
可编程串行接口特性
UART Channel A
–
5、6、7 或 8 位字符,可生成 1、1.5 或 2 个停
止位
TXA
A2 to A0
D7 to D0
CSA
TX
RX
64-Byte TX FIFO
UART Regs
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
CSB
–
偶校验、奇校验或无奇偶校验位生成与检测
Baud
Rate
Generator
IOR
64-Byte RX FIFO
RXA
IOW
INTA
•
•
•
错误启动位和线路中断检测
Data Bus
Interface
INTB
内部测试和环回功能
TXRDYA
TXRDYB
RXRDYA
RXRDYB
UART Channel B
64-Byte TX FIFO
TXB
SC16C752B 和 XR16M752 引脚兼容其他增强功能
TX
RX
CTSB
OPB, DTRB
DSRB, RIB, CDB
UART Regs
RESET
Baud
Rate
Generator
RTSB
RXB
64-Byte RX FIFO
Crystal
Oscillator
Buffer
XTAL1
XTAL2
VCC
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEN8
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 26
8.5 Register Maps......................................................... 28
Application and Implementation ........................ 44
9.1 Application Information............................................ 44
9.2 Typical Application .................................................. 44
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configurations and Function......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements................................................ 9
7.7 Typical Characteristics............................................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 15
9
10 Power Supply Recommendations ..................... 47
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Examples................................................... 48
12 器件和文档支持 ..................................................... 49
12.1 社区资源................................................................ 49
12.2 商标....................................................................... 49
12.3 静电放电警告......................................................... 49
12.4 Glossary................................................................ 49
13 机械、封装和可订购信息....................................... 49
8
4 修订历史记录
Changes from Revision B (March 2016) to Revision C
Page
•
•
•
•
将特性 中的“3.3V 时为 2Mbps(32MHz 振荡器输入时钟)”更改为“3.3V 时为 3Mbps(48MHz 振荡器输入时钟)” ............ 1
将特性 中的“运行温度范围为 0°C 至 70°C”更改为“运行温度范围为 –40°C 至 85°C”............................................................. 1
Removed pin 35 from NC in the Pin Functions table ............................................................................................................. 4
Changed Operating free-air temperature From: MIN = 0, MAX = 70 To: MIN = –40, MAX = 85 in the Absolute
Maximum Ratings................................................................................................................................................................... 5
•
•
Changed Oscillator or clock speed MAX value From: 32 MHz To: 48 MHz in the Recommended Operating Conditions.... 6
Changed CP clock period (3.3 V) values From: MIN = 32, MAX = 32 To: MIN = 20, MAX = 48 ns in the Timing
Requirements ......................................................................................................................................................................... 9
Changes from Revision A (October 2015) to Revision B
Page
•
将器件信息表中的“封装尺寸”列从 3.67mm x 3.67mm 更改为 7.00mm x 7.00mm ................................................................. 1
Changes from Original (September 2015) to Revision A
Page
•
Changed VOL MAX value in the VCC = 5 V section of Electrical Characteristics From: 0.4 V To: 0.5 V ................................ 8
2
版权 © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
5 说明 (续)
两个 UART 只共享数据总线接口和时钟源,除此之外都是独立运行的。UART 功能也称作异步通信元件 (ACE),这
两个术语可互换使用。本文档主要介绍每个 ACE 的行为,并让读者了解到 TL16C752D 器件中整合了这两个
ACE。
6 Pin Configurations and Function
PFB Package
48-Pin TQFP
Top View
48 47 46 45 44 43 42 41 40 39 38 37
D5
D6
RESET
35 DTRB
1
2
3
4
36
D7
34
33
DTRA
RTSA
OPA
RXB
5
32
31
30
29
RXA
TXRDYB
TXA
6
RXRDYA
INTA
7
8
TXB
INTB
OPB
9
28 A0
27 A1
10
11
CSA
CSB
26
25
A2
NC
NC 12
13 14 15 16 17 18 19 20 21 22 23 24
N.C. – No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
TQFP
28
A0
A1
A2
I
I
I
Address bit 0 select. Internal registers address selection. Refer to Figure 26 for register address map.
Address bit 1 select. Internal registers address selection. Refer to Figure 26 for register address map.
Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map.
27
26
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A
low on these pins indicates that a carrier has been detected by the modem for that channel.
CDA, CDB
40, 16
I
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
TL16C752D for the channel or channels addressed. Individual UART sections (A and B) are
addressed by providing a low on the respective CSA and CSB pin.
CSA, CSB
10, 11
I
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
TL16C752D device. Status can be checked by reading MSR[4]. These pins only affect the transmit
and receive operations when auto CTS function is enabled through the enhanced feature register
(EFR[7]), for hardware flow control operation.
CTSA, CTSB
38, 23
I
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or
from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
serial data stream.
D0–D4,
D5–D7
44 to 48,
1 to 3
I/O
I
Data set ready (active low). These inputs are associated with individual UART channels A through B.
A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.
DSRA, DSRB
39, 20
Copyright © 2015–2017, Texas Instruments Incorporated
3
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
DTRA, DTRB
GND
TQFP
34, 35
17
Data terminal ready (active low). These outputs are associated with individual UART channels A
through B. A low on these pins indicates that the TL16C752D is powered on and ready. These pins
can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR output to
low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0], or after a reset.
These pins can also be used in the RS-485 mode to control an external RS-485 driver or transceiver.
O
Pwr Power signal and power ground
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-B. INTA-B are
enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable register (IER) and
INTA, INTB
30, 29
O
when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver
buffer data, transmit buffer empty, or when a modem status flag is detected. INTA-B are in the high-
impedance state after reset.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal register
defined by address bits A0 through A2 onto the TL16C752D device data bus (D0 through D7) for
access by an external CPU.
IOR
19
15
I
I
Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0
through D7) from the external CPU to an internal register that is defined by address bits A0 through
A2.
IOW
NC
12, 24,
37
No internal connection
User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
OPA, OPB
32, 9
O
Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the
receiver input are disabled during reset time. For initialization details, see TL16C752D device
external reset conditions. RESET is an active high input.
RESET
36
I
I
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
low-to-high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR).
RIA, RIB,
41, 21
Request to send (active low). These outputs are associated with individual UART channels A and B.
A low on the RTS pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the
modem control register (MCR[1]) sets these pins to low, indicating data is available. After a reset,
these pins are set to 1. These pins only affect the transmit and receive operation when auto-RTS
function is enabled through the enhanced feature register (EFR[6]), for hardware flow control
operation.
RTSA, RTSB
RXA, RXB
33, 22
O
Receive data input. These inputs are associated with individual serial channel data to the
TL16C752D device. During the local loopback mode, these RX input pins are disabled and TX data is
internally connected to the UART RX input internally. During normal mode, RXn should be held high
when no data is being received. These inputs also can be used in IrDA mode. For more information,
see IrDA Overview.
5, 4
I
Receive ready (active low). RXRDYA and RXRDYB go low when the trigger level has been reached
or a timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX
FIFO.
RXRDYA,
RXRDYB
31, 18
7, 8
O
Transmit data. These outputs are associated with individual serial transmit channel data from the
TL16C752D device. During the local loopback mode, the TX input pin is disabled and TX data is
internally connected to the UART RX input.
TXA, TXB,
O
O
TXRDYA,
TXRDYB
Transmit ready (active low). TXRDYA and TXRDYB go low when there are a trigger level number of
spares available. They go high when the TX buffer is full.
43, 6
42
VCC
PWR Power supply inputs
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A
XTAL1
13
14
I
crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 23). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.
XTAL2
O
4
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–40
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
VCC + 0.5
VCC + 0.5
85
V
VO
TA
Output voltage
V
Operating free-air temperature
Storage temperature
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015–2017, Texas Instruments Incorporated
5
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC = 1.8 V ±10%
VCC
VI
Supply voltage
1.62
–0.3
1.4
1.8
1.98
V
V
Input voltage
0.9 × VCC
VIH
VIL
VO
IOH
IOL
High-level input voltage
Low-level input voltage
Output voltage
V
0.4
VCC
–0.5
1
V
0
V
High-level output current
Low-level output current
Oscillator/clock speed
All outputs
All outputs
mA
mA
MHz
16
VCC = 2.5 V ±10%
VCC
VI
Supply voltage
2.25
–0.3
1.8
2.5
3.3
5
2.75
V
V
Input voltage
0.9 × VCC
VIH
VIL
VO
IOH
IOL
High-level input voltage
Low-level input voltage
Output voltage
V
0.6
VCC
–1
V
0
V
High-level output current
Low-level output current
Oscillator/clock speed
All outputs
All outputs
mA
mA
MHz
2
24
VCC = 3.3 V ±10%
VCC
VI
Supply voltage
3
–0.3
3.6
V
V
Input voltage
VCC
VIH
VIL
VO
IOH
IOL
High-level input voltage
Low-level input voltage
Output voltage
0.7 × VCC
V
0.8
VCC
–1.8
3.2
V
0
V
High-level output current
Low-level output current
Oscillator or clock speed
All outputs
All outputs
mA
mA
MHz
48
VCC = 5 V ±10%
VCC
VI
Supply voltage
4.5
–0.3
5.5
V
V
Input voltage
VCC
Except XTAL1
XTAL1
2
VIH
VIL
High-level input voltage
V
V
0.7 × VCC
Except XTAL1
XTAL1
0.8
Low-level input voltage
0.3 × VCC
VO
IOH
IOL
Output voltage
0
VCC
–4
4
V
High-level output current
Low-level output current
Oscillator or clock speed
All outputs
All outputs
mA
mA
MHz
48
6
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
7.4 Thermal Information
TL16C752D
THERMAL METRIC(1)
PFB (TQFP)
48 PINS
61
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJC(bot)
17.3
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC = 1.8 V
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
VOL
High-level output voltage IOH = –0.5 mA
Low-level output voltage IOL = 1 mA
1.3
V
0.5
VCC = 1.98 V,
Input current
VSS = 0,
All other terminals floating
II
10
μA
μA
VI = 0 to 1.98 V,
VCC = 1.98 V,
VSS = 0,
High-impedance state
VO = 0 to 1.98 V,
IOZ
±20
output current
Chip selected in write mode or chip deselect
VCC = 1.98 V,
TA = 70°C,
DSR, CTS, and RI at 2 V,
ICC
Supply current
4.5
mA
pF
All other inputs at 0.4 V,
No load on outputs,
XTAL1 at 16 MHz,
Baud rate = 1 Mb/s
CI(CLK)
Clock input capacitance
5
5
7
7
VCC = 0,
f = 1 MHz,
All other terminals grounded
CO(CLK) Clock output capacitance
VSS = 0,
TA = 25°C,
CI
Input capacitance
Output capacitance
6
10
15
CO
10
VCC = 2.5 V
VOH
VOL
High-level output voltage IOH = –1 mA
Low-level output voltage IOL = 2 mA
1.8
V
0.5
10
VCC = 2.75 V,
VSS = 0,
All other terminals floating
II
Input current
μA
VI = 0 to 2.75 V,
VCC = 2.75 V,
VO = 0 to 2.75 V,
VSS = 0,
High-impedance state
output current
IOZ
±20
9
μA
Chip selected in write mode or chip deselect
VCC = 2.75 V,
TA = 70°C,
DCD, CTS, and RI at 2 V,
ICC
Supply current
mA
All other inputs at 0.6 V,
No load on outputs,
XTAL1 at 24 MHz,
Baud rate = 1.5 Mb/s
CI(CLK)
Clock input capacitance
5
5
7
7
VCC = 0,
f = 1 MHz,
All other terminals grounded
CO(CLK) Clock output capacitance
VSS = 0,
TA = 25°C,
pF
CI
Input capacitance
Output capacitance
6
10
15
CO
10
Copyright © 2015–2017, Texas Instruments Incorporated
7
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC = 3.3 V
TEST CONDITIONS
MIN
TYP
VOH
VOL
High-level output voltage IOH = –1.8 mA
Low-level output voltage IOL = 3.2 mA
2.4
V
0.5
VCC = 3.6 V,
Input current
VSS = 0,
All other terminals floating
II
10
μA
μA
VI = 0 to 3.6 V,
VCC = 3.6 V,
VSS = 0,
High-impedance state
VO = 0 to 3.6 V,
IOZ
±20
output current
Chip selected in write mode or chip deselect
VCC = 3.6 V,
TA = 70°C,
DSR, CTS, and RI at 2 V,
ICC
Supply current
16
mA
pF
All other inputs at 0.8 V,
No load on outputs,
XTAL1 at 32 MHz,
Baud rate = 2 Mb/s
CI(CLK)
Clock input capacitance
5
5
7
7
VCC = 0,
f = 1 MHz,
All other terminals grounded
CO(CLK) Clock output capacitance
VSS = 0,
TA = 25°C,
CI
Input capacitance
Output capacitance
6
10
15
CO
10
VCC = 5 V
VOH
High-level output voltage IOH = –4 mA
Low-level output voltage IOL = 4 mA
4
V
VOL
0.5
10
VCC = 5.5 V,
Input current
VSS = 0,
All other terminals floating
II
μA
VI = 0 to 5.5 V,
VCC = 5.5 V,
VSS = 0,
High-impedance state
VO = 0 to 5.5 V,
IOZ
±20
40
μA
output current
Chip selected in write mode or chip deselect
VCC = 5.5 V,
DSR, CTS, and RI at 2 V,
TA = 70°C,
ICC
Supply current
mA
All other inputs at 0.8 V,
No load on outputs,
XTAL1 at 48 MHz,
Baud rate = 3 Mb/s
CI(CLK)
Clock input capacitance
5
5
7
7
VCC = 0,
f = 1 MHz,
All other terminals grounded
CO(CLK) Clock output capacitance
VSS = 0,
TA = 25°C,
pF
CI
Input capacitance
Output capacitance
6
10
15
CO
10
8
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
7.6 Timing Requirements
TA = 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted)
LIMITS
1.8 V
2.5 V
3.3 V
5 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tRESET Reset pulse width
200
200
42
200
20
200
20
ns
ns
CP
CP clock period
63
t3w
Oscillator or clock speed
Address setup time
Address hold time
IOR strobe width
16
24
48
48
MHz
ns
t6s
20
15
85
85
15
10
70
70
10
7
5
5
t6h
See Figure 1 and Figure 2
See Figure 1 and Figure 2
See Figure 2
ns
t7w
50
60
40
50
ns
t9d
Read cycle delay
Delay from IOR to data
Data disable time
IOW strobe width
Write cycle delay
Data setup time
ns
t12d
t12h
t13w
t15d
t16s
t16h
t17d
See Figure 2
65
35
50
25
35
20
25
15
ns
ns
See Figure 1
85
85
40
35
70
70
30
25
50
60
20
15
40
50
15
10
ns
See Figure 1
ns
See Figure 1
ns
Data hold time
See Figure 1
ns
Delay from IOW to output
50-pF load, see Figure 3
60
70
40
55
30
45
20
35
ns
Delay to set interrupt from
MODEM input
t18d
50-pF load, see Figure 3
ns
t19d
t20d
t21d
t22d
Delay to reset interrupt from IOR 50-pF load
Delay from stop to set interrupt See Figure 4
Delay from IOR to reset interrupt 50-pF load, see Figure 4
80
1
55
1
40
1
30
1
ns
baudrate
ns
55
1
45
1
35
1
25
1
Delay from stop to interrupt
See Figure 7
baudrate
Delay from initial IOW reset to
transmit start
t23d
t24d
See Figure 7
8
24
75
8
24
45
8
24
35
8
24 baudrate
Delay from IOW to reset
interrupt
See Figure 7
25
ns
t25d
t26d
t27d
t28d
Delay from stop to set RXRDY
See Figure 5 and Figure 6
1
1
1
1
1
1
1
1
baudrate
Delay from IOR to reset RXRDY See Figure 5 and Figure 6
Delay from IOW to set TXRDY See Figure 8 and Figure 9
Delay from start to reset TXRDY See Figure 8 and Figure 9
μs
70
16
60
16
50
16
40
ns
16 baudrate
A[2:0]
Valid Address
Valid Address
t6s
t6s
t6h
t6h
t13w
CS
t15d
t13w
IOW
t16s
t16s
t16h
t16h
D[7:0]
Valid Data
Valid Data
Figure 1. General Write Timing
Copyright © 2015–2017, Texas Instruments Incorporated
9
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
A[2:0]
Valid Address
Valid Address
t6s
t6s
t6h
t6h
t7w
CS
t9d
t7w
IOR
t12d
t12d
t12h
t12h
Valid Data
Valid Data
D[7:0]
Figure 2. General Read Timing
Active
IOW
t17d
RTS (A–B)
DTR (A–B)
Change of State
Change of State
CD (A–B)
CTS (A–B)
DSR (A–B)
Change of State
t18d
t18d
INT (A–B)
Active
Active
Active
t19d
Active
Active
Active
IOR
t18d
Change of State
RI (A–B)
Figure 3. Modem or Output Timing
10
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
RX (A–B)
Parity
Bit
Next
Data
Start
Bit
5 Data Bits
6 Data Bits
7 Data Bits
t20d
INT (A–B)
Active
t21d
Active
IOR
16-Baud Rate Clock
Figure 4. Receive Timing
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
RX (A–B)
Parity
Bit
Next
Data
Start
Bit
t25d
Active
Data
Ready
RXRDY (A–B)
RXRDY
t26d
Active
IOR
Figure 5. Receive Ready Timing in Non-FIFO Mode
Start
Stop
Bit
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
RX (A–B)
First Byte
That Reaches
The Trigger
Level
Parity
Bit
t25d
Active
Data
Ready
RXRDY (A–B)
RXRDY
t26d
Active
IOR
Figure 6. Receive Timing in FIFO Mode
Copyright © 2015–2017, Texas Instruments Incorporated
11
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
TX (A–B)
Parity
Bit
Next
Data
Start
Bit
5 Data Bits
6 Data Bits
7 Data Bits
t22d
INT (A–B)
Active
Tx Ready
t24d
t23d
Active
Active
IOW
16-Baud Rate Clock
Figure 7. Transmit Timing
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
TX (A–B)
Next
Parity
Bit
Data
Start
Bit
Active
IOW
Byte 1
D0–D7
t
28d
T27d
Active
Transmitter Ready
TXRDY (A–B)
TXRDY
Transmitter
Not Ready
Figure 8. Transmit Ready Timing in Non-FIFO Mode
12
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Start
Bit
Stop
Bit
Data Bits (5–8)
D0
D1
D2
D3
D4
D5
D6
D7
TX (A–B)
Parity
Bit
5 Data Bits
6 Data Bits
7 Data Bits
Active
IOW
Trigger
Level
t28d
D0–D7
t27d
TXRDY (A–B)
TXRDY
Trigger
Level
Figure 9. Transmit Timing in FIFO Mode
Copyright © 2015–2017, Texas Instruments Incorporated
13
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
7.7 Typical Characteristics
all channels active, TA = 25°C, unless otherwise noted
2
1.5
1
4.5
3.75
3
2.25
1.5
0.75
0
0.5
VCC = 1.62 V
VCC = 1.8 V
VCC = 1.98 V
VCC = 2.25 V
VCC = 2.5 V
VCC = 2.75 V
0
0
4
8
12
16
0
4
8
12
16
20
24
Frequency, Ö (MHz)
Frequency, Ö (MHz)
D001
D002
Figure 10. Supply Current vs Frequency (VCC = 1.62, 1.8,
and 1.98 V)
Figure 11. Supply Current vs Frequency (VCC = 2.25, 2.5,
and 2.75 V)
30
8
6
4
2
V
T
= 5 V,
CC
= 25°C
A
Div = 1
25
20
15
10
5
Div = 10
VCC = 3 V
VCC = 3.3 V
VCC = 3.5 V
0
0
8
16
24 32
Frequency, Ö (MHz)
D003
0
0
8
12
16
20
24
4
Frequency, f (MHz)
Figure 12. Supply Current vs Frequency (VCC = 3, 3.3, and
3.5 V)
Figure 13. Supply Current vs Frequency (VCC = 5 V)
14
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8 Detailed Description
8.1 Overview
The TL16C752D UART is pin-compatible with the ST16C2550 UART in the PFB package. It provides more
enhanced features. All additional features are provided through a special enhanced feature register.
The TL16C752D UART will perform serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The
complete status of each channel of the TL16C752D UART can be read at any time during functional operation by
the processor.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and
transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.
8.2 Functional Block Diagrams
UART Channel A
TXA
A2 to A0
D7 to D0
CSA
TX
RX
64-Byte TX FIFO
UART Regs
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
CSB
Baud
Rate
Generator
IOR
64-Byte RX FIFO
RXA
IOW
INTA
Data Bus
Interface
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
UART Channel B
64-Byte TX FIFO
TXB
TX
RX
CTSB
OPB, DTRB
DSRB, RIB, CDB
UART Regs
RESET
Baud
Rate
Generator
RTSB
RXB
64-Byte RX FIFO
Crystal
Oscillator
Buffer
XTAL1
XTAL2
VCC
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 14. TL16C752D Functional Block Diagram
Copyright © 2015–2017, Texas Instruments Incorporated
15
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Functional Block Diagrams (continued)
Modem Control Signals
Control Signals
Status Signals
Bus
Interface
Control
and
Divisor
Status Block
Control Signals
Baud-Rate
Generator
Status Signals
UART_CLK
RX
Int_Rx
IrDA
Receiver Block
Logic
Vote
Logic
64-Byte
Receiver FIFO
RX
TX
Int_Tx
Transmitter Block
Logic
64-Byte
Transmitter FIFO
IrDA
TX
Copyright © 2016, Texas Instruments Incorporated
NOTE: The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The vote logic operates on all bits received.
Figure 15. TL16C752D Functional Block Diagram – Control Blocks
8.3 Feature Description
8.3.1 Functional Description
The TL16C752D UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive
software overhead by buffering received and transmitted characters. Both the receiver and transmitter FIFOs can
store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have
selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signaling of DMA
transfers.
The TL16C752D UART has selectable hardware flow control and software flow control. Both schemes
significantly reduce software overhead and increase system efficiency by automatically controlling serial data
flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses
programmable Xon and Xoff characters.
The TL16C752D device includes a programmable baud rate generator that can divide the timing reference clock
by a divisor between 1 and 65535. A bit (MCR7) can be used to invoke a prescaler (divide by 4) off the reference
clock, prior to the baud rate generator input. The divide by 4 prescaler is selected when MCR7 is set to 1.
8.3.1.1 Trigger Levels
The TL16C752D UART provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in
effect, the trigger level is the default value of one byte. The selectable trigger levels are available through the
FCR. The programmable trigger levels are available through the TLR.
16
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Feature Description (continued)
8.3.1.2 Hardware Flow Control
Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled or
disabled independently by programming EFR[7:6].
With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output
when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is
sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is
activated or deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated
during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive
FIFO servicing latency.
8.3.1.3 Auto-RTS
Auto-RTS data flow control originates in the receiver block (see Figure 14). Figure 16 shows RTS functional
timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO
level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached, RTS is
deasserted. The sending device (for example, another UART) may send an additional byte after the trigger level
is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion
of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO
reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending device to
resume transmission.
RX
Byte N
Byte N+1
Stop
Stop
Start
Start
Start
RTS
IOR
1
2
N
N+1
A. N = receiver FIFO trigger level B.
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.
Figure 16. RTS Functional Timing
8.3.1.4 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS state changes and need not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error can result. Figure 17 shows CTS functional timing, and Figure 18
shows an example of autoflow control.
Copyright © 2015–2017, Texas Instruments Incorporated
17
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Feature Description (continued)
Byte 0–7
Stop
Byte 0–7 Stop
Start
Start
TX
CTS
A. When CTS is low, the transmitter keeps sending serial data out.
B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the
current byte, but it does not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 17. CTS Functional Timing
UART 1
UART 2
Serial to
Parallel
Parallel to
Serial
RX
TX
RX
TX
FIFO
FIFO
Flow
RTS CTS
Flow
Control
Control
D7 – D0
D7 – D0
Parallel to
Serial
Serial to
Parallel
TX
RX
TX
RX
FIFO
FIFO
Flow
CTS RTS
Flow
Control
Control
Figure 18. Autoflow Control (Auto-RTS and Auto-CTS) Example
8.3.1.5 Software Flow Control
Software flow control is enabled through the enhanced feature register and the modem control register. Different
combinations of software flow control can be enabled by setting different combinations of EFR[3−0]. Table 1
shows software flow control options.
Two other enhanced features relate to software flow control:
•
Xon Any Function [MCR(5): Operation resumes after receiving any character after recognizing the Xoff
character.
•
Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character sets the
Xoff interrupt [IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The
special character is transferred to the RX FIFO.
NOTE
It is possible for an Xon1 character to be recognized as an Xon Any character, which
could cause an Xon2 character to be written to the RX FIFO.
18
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Table 1. Software Flow Control Options EFR[3:0]
BIT 3
BIT 2
BIT 1
BIT 0
TX, RX SOFTWARE FLOW CONTROLS
No transmit flow control
0
1
0
1
X
X
X
0
0
1
1
X
X
X
X
X
X
X
0
X
X
X
X
0
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1, Xon2: Xoff1, Xoff2
No receive flow control
1
0
Receiver compares Xon1, Xoff1 X X 0 1
Receiver compares Xon2, Xoff2
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1, Xon2: Xoff1, Xoff2
Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
No transmit flow control
Receiver compares Xon1 and Xon2: Xoff1 and Xoff2
When software flow control operation is enabled, the TL16C752D device compares incoming data with Xoff1 and
(1)
Xoff2 programmed characters (in certain cases Xoff1 and Xoff2 must be received sequentially). When an Xoff
character is received, transmission is halted after completing transmission of the current character. Xoff character
detection also sets IIR[4] and causes INT to go high (if enabled via IER[5]).
To resume transmission an Xon1 and Xon2 character must be received (in certain cases Xon1 and Xon2 must
be received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt
disappears.
NOTE
If a parity, framing, or break error occurs while receiving a software flow control character,
this character is treated as normal data and is written to the RCV FIFO.
Xoff1 and Xoff2 characters are transmitted when the RX FIFO has passed the programmed trigger level
TCR[3:0].
Xon1 and Xon2 characters are transmitted when the RX FIFO reaches the trigger level programmed via
TCR[7:4].
NOTE
If, after an Xoff character has been sent, software flow control is disabled, the UART
transmits Xon characters automatically to enable normal transmission to proceed. A
feature of the TL16C752D UART design is that if the software flow combination (EFR[3:0])
changes after an Xoff has been sent, the originally programmed Xon is automatically sent.
If the RX FIFO is still above the trigger level, the newly programmed Xoff1 or Xoff2 is
transmitted.
The transmission of Xoff and Xon follows the exact same protocol as transmission of an ordinary byte from the
FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least
significant bits of Xoff1, Xoff2 and Xon1, Xon2 are transmitted. The transmission of 5, 6, or 7 bits of a character
is seldom done, but this functionality is included to maintain compatibility with earlier designs.
It is assumed that software flow control and hardware flow control are never enabled simultaneously. Figure 19
shows a software flow control example.
(1) When pairs of Xon and Xoff characters are programmed to occur sequentially, received Xon1 and Xoff1 characters will be written to the
RX FIFO if the subsequent character is not Xon2 and Xoff2.
Copyright © 2015–2017, Texas Instruments Incorporated
19
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
UART 1
UART 2
Transmit
FIFO
Receive
FIFO
Data
Parallel to Serial
Serial to Parallel
Xon-1 Word
Serial to Parallel
Parallel to Serial
Xon-1 Word
Xoff − Xon − Xoff
Xon-2 Word
Xon-2 Word
Xoff-1 Word
Xoff-1 Word
Compare
Programmed
Xon −Xoff
Xoff-2 Word
Xoff-2 Word
Characters
Figure 19. Software Flow Control Example
8.3.1.6 Software Flow Control Example
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with
single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0] = F) set to 60 and Xon
threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.
UART1 begins transmission and sends 52 characters, at which point UART2 generates an interrupt to its
processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 continues sending
characters until a total of 60 characters have been sent. At this time UART2 transmits a 0F to UART1, informing
UART1 to halt transmission. UART1 likely sends the 61st character while UART2 is sending the Xoff character.
Now, UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level drops to 32.
UART2 now sends a 0D to UART1, informing UART1 to resume transmission.
20
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.3.1.7 Reset
Table 2 summarizes the state of outputs after reset.
Table 2. Register Reset Functions(1)
REGISTER
Interrupt enable register
Interrupt identification register
FIFO control register
RESET CONTROL
RESET STATE
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
All bits cleared
Bit 0 is set. All other bits cleared.
All bits cleared
Line control register
Reset to 00011101 (1D hex)
All bits cleared
Modem control register
Line status register
Bits 5 and 6 set. All other bits cleared.
Bits 0 to 3 cleared. Bits 4 to 7 input signals.
All bits cleared
Modem status register
Enhanced feature register
Receiver holding register
Transmitter holding register
Transmission control register
Trigger level register
Pointer logic cleared
Pointer logic cleared
All bits cleared
All bits cleared
Alternate function register
All bits (except AFR4) cleared; AFR4 set
(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, and Xoff2 are not reset by the top-level reset signal
RESET, that is, they hold their initialization values during reset.
Table 3 summarizes the state of outputs after reset.
Table 3. Signal Reset Functions
SIGNAL
RESET CONTROL
RESET
RESET STATE
TX
High
High
High
High
Low
RTS
DTR
RESET
RESET
RXRDYA–B
TXRDYA–B
RESET
RESET
Copyright © 2015–2017, Texas Instruments Incorporated
21
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.3.1.8 Interrupts
The TL16C752D UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability.
The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to
an interrupt generation. The IER also can disable the interrupt system by clearing bits 0 to 3, 5 to 7. When an
interrupt is generated, the interrupt identification register (IIR) indicates that an interrupt is pending and provides
the type of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.
Table 4. Interrupt Control Functions
PRIORITY
LEVEL
INTERRUPT
TYPE
IIR[5–0]
INTERRUPT SOURCE
INTERRUPT RESET METHOD
000001
000110
None
1
None
None
None
Receiver line
status
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE < PE < BI: All erroneous characters are
read from the RX FIFO. OE: Read LSR
001100
000100
2
2
RX timeout
Stale data in RX FIFO
Read RHR
Read RHR
RHR interrupt
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
000010
3
THR interrupt
TFE (THR empty)
Read IIR or a write to the THR
(FIFO disable)
TX FIFO passes above trigger level (FIFO
enable)
000000
010000
4
5
Modem status
Xoff interrupt
MSR[3:0] = 0
Read MSR
Receive Xoff character or
characters/special character
Receive Xon character or characters/Read of
IIR
100000
6
CTS, RTS
RTS pin or CTS pin change state from
active (low) to inactive (high)
Read IIR
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the RX
FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the RX FIFO is empty, then LSR[4–2] is all 0.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the ISR.
8.3.1.9 Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is 1), the processor is informed of the status of the receiver and
transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register
(LSR) to see if any interrupt needs to be serviced. Figure 20 shows interrupt mode operation.
IER
IOW IOR
/
0
0
0
0
INT
Processor
IIR
THR
RHR
Figure 20. Interrupt Mode Operation
22
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.3.1.10 Polled Mode Operation
In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 21 shows polled
mode operation.
LSR
IOW IOR
/
Processor
IER
0
0
0
0
THR
RHR
Figure 21. FIFO Polled Mode Operation
8.3.1.11 Break and Timeout Conditions
An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×
programmed word length) + 12 bits and there is at least one byte stored in the RX FIFO.
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
Copyright © 2015–2017, Texas Instruments Incorporated
23
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.3.1.12 Programmable Baud Rate Generator
The TL16C752D UART contains a programmable baud generator that divides reference clock by a divisor in the
range between 1 and (216 − 1). The output frequency of the baud rate generator is 16× the baud rate. An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in the following. The
formula for the divisor is:
Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate X 16)
Where
1 when CLKSEL = high during reset, or MCR[7] is set to 0 after reset
prescaler =
4 when CLKSEL = high during reset, or MCR[7] is set to 1 after reset
Figure 22 shows the internal prescaler and baud rate generator circuitry.
MCR[7] = 0
Prescaler Logic
(Divide By 1)
Internal
Internal
Oscillator
Logic
Band Rate
Generator
Logic
XTAL1
XTAL2
Band Bate Clock
For Transmitter
and Receiver
Input Clock
Reference
Clock
Prescaler Logic
(Divide By 4)
MCR[7] = 1
Figure 22. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled,
because no baud clock is generated. The programmable baud rate generator is provided to select both the
transmit and receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal
with frequency 1.8432 and 3.072 MHz, respectively.
24
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Table 5. Baud Rates Using a 1.8432-MHz Crystal
DIVISOR USED TO
GENERATE 16×
CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
2304
1536
1047
857
768
384
192
96
75
110
0.026
0.058
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
64
58
0.69
48
32
24
16
12
6
3
2
2.86
Table 6. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED TO
GENERATE 16×
CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
3840
2560
1745
1428
1280
640
320
160
107
96
110
0.026
0.034
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
0.312
80
53
0.628
1.23
40
27
20
10
5
Copyright © 2015–2017, Texas Instruments Incorporated
25
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Figure 23 shows the crystal clock circuit reference.
VCC
VCC
Driver
XTAL1
XTAL1
External
Clock
C1
Crystal
Rp
Optional
Driver
RX2
XTAL2
Optional
Clock
Output
Oscillator Clock
to Baud Generator
Logic
Oscillator Clock
to Baud Generator
Logic
XTAL2
C2
Copyright © 2016, Texas Instruments Incorporated
A. For crystal with fundamental frequency from 1 to 24 MHz
B. For input clock frequency higher than 24 MHz, the crystal is not allowed and the oscillator must be used, because the
TL16C752D internal oscillator cell can only support the crystal frequency up to 24 MHz.
Figure 23. Typical Crystal Clock Circuits
8.4 Device Functional Modes
8.4.1 DMA Signaling
There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0] = 0), DMA occurs in single character transfers. In DMA mode 1,
multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY goes inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 24 shows TXRDY and RXRDY in DMA mode 0 or FIFO disable.
TX
RX
RXRDY
TXRDY
wrptr
rdptr
At Least One
Location Filled
At Least One
Location Filled
RXRDY
TXRDY
FIFO Empty
FIFO Empty
wrptr
rdptr
Figure 24. TXRDY and RXRDY in DMA Mode 0 or FIFO Disable
26
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Device Functional Modes (continued)
8.4.1.2 Block DMA Transfers (DMA Mode 1)
Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when the
FIFO is full.
Receiver: RXRDY becomes active when the trigger level has been reached or when a timeout interrupt occurs. It
goes inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).
Figure 25 shows TXRDY and RXRDY in DMA mode 1.
TX
RX
wrptr
Trigger
Level
TXRDY
RXRDY
rdptr
At Least One
Location Filled
Trigger
Level
TXRDY
RXRDY
wrptr
FIFO Empty
rdptr
Figure 25. TXRDY and RXRDY in DMA Mode 1
8.4.2 Sleep Mode
Sleep mode is an enhanced feature of the TL16C752D UART. It is enabled when EFR[4], the enhanced
functions bit, is set and when IER[4] is set. Sleep mode is entered when:
•
•
•
The serial data input line, RX, is idle (see Break and Timeout Conditions).
The TX FIFO and TX shift register are empty.
There are no interrupts pending except THR and timeout interrupts.
Sleep mode is not entered if there is data in the RX FIFO.
In sleep mode, the UART clock and baud rate clock are stopped. Because most registers are clocked using
these clocks, the power consumption is greatly reduced. The UART wakes up when any change is detected on
the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO.
NOTE
Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done
during sleep mode. Therefore, TI recommends to disable sleep mode using IER[4] before
writing to DLL or DLH.
Copyright © 2015–2017, Texas Instruments Incorporated
27
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.5 Register Maps
8.5.1 Principals of Operation
Each register is selected using address lines A[0], A[1], A[2], and in some cases, bits from other registers. The
programming combinations for register selection are shown in Figure 26.
Accessible only when LCR[7] = 1
Accessible only when LCR[7:5] = 100
Accessible only when LCR = 1011 1111 (0xBF)
Accessible only when EFR[4] = 1 and MCR[6] = 1
Accessible when any CS A-B = 0, MCR[2] = 1 and loopback MCR[4] = 0 is disabled
NOTE: MCR[7:5], FCR[5:4], and IER[7:4] can only be modified when EFR[4] is set.
Figure 26. Register Map – Read and Write Properties
Table 7 lists and describes the TL16C752D internal registers.
28
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Table 7. TL16C752D Internal Registers(1) (2)
R/W
ACCESS
CONSIDERATION
ADDRESS REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(3)
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
RHR
R
LCR[7] = 0
0 0 0
THR
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
W
DLL(4)
RW
LCR[7] = 1
LCR[7] = 0
LCR[7] = 1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CTS#
Interrupt
enable(1)
0
RTS# Interrupt Xoff Interrupt
Sleep
mode(1)
0
Modem status
RX line status
THR empty
interrupt
0
RX data available
IER
RW
enable(1)
0
enable(1)
0
interrupt
0
interrupt
0
interrupt
0
0 0 1
DLH(4)
IIR
RW
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Interrupt
priority bit 2
0
Interrupt
priority bit 1
0
Interrupt
priority bit 0
0
FCR(0)
0
FCR(0)
0
CTS# / RTS#
0
Xoff
0
Interrupt status
1
LCR[7] = 0
RX trigger
level
0
TX trigger
level(1)
0
TX trigger
level(1)
0
DMA mode
select
0
Resets TX
FIFO
0
Resets RX
RX trigger level
0
Enable FIFOs
0
FCR
W
FIFO
0
0 1 0
DLY2
0
DLY1
0
DLY0
0
RCVEN
1
485LG
0
485RN
0
IREN
0
CONC
0
AFR(5)
RW
LCR[7:5] = 100
Special
character
detect
0
Enable
enhanced
functions
0
S/W flow
control bit 3
0
S/W flow
control bit 2
0
S/W flow
control bit 1
0
S/W flow control
LCR[7:0] =
10111111
Auto CTS#
0
Auto RTS#
0
EFR(6)
RW
RW
bit 0
0
DLAB & EFR Break control
Parity type
select
1
Sets parity
0
Parity enable No. of stop bits
Word length
0
Word length
1
0 1 1
1 0 0
LCR
None
enable
0
bit
0
1
1
1x / 4x
clock(1)
0
TCR & TLR
enable(1)
0
Enable
loopback
0
FIFORdy
enable
0
LCR[7:0] ≠
10111111
Xon any(1)
0
IRQ enable
0
RTS#
0
DTR#
0
MCR
Xon1(6)
LSR
RW
RW
R
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
Error in RX
THR & TSR
Break
interrupt
0
LCR[7:0] ≠
10111111
THR empty
1
Framing error
0
Parity error
0
Overrun error
0
Data in receiver
0
FIFO
0
empty
1
1 0 1
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
0
bit 3
1
bit 2
1
bit 1
1
bit 0
1
Xon2(6)
RW
(1) Bits represented by the blue shaded cells can only be modified if EFR[4] is enabled, that is, if enhanced functions are enabled.
(2) For more register access information, see Figure 26.
(3) Read = R; Write = W
(4) This register is only accessible when LCR[7] = 1
(5) This register is only accessible LCR[7:5] = 100
(6) This register is only accessible when LCR = 1011 1111 (0xBF)
Copyright © 2015–2017, Texas Instruments Incorporated
29
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Table 7. TL16C752D Internal Registers() () (continued)
R/W
ACCESS
CONSIDERATION
ADDRESS REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(3)
LCR[7:0] ≠
10111111
CD#
1
RI#
1
DSR#
1
CTS#
0
∆CD#
0
∆RI#
0
∆DSR#
∆CTS#
MSR
R
0
0
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
1 1 0
Xoff1(6)
TCR(7)
SPR
RW
RW
RW
RW
RW
EFR[4] = 1 &
MCR[6] = 1
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
LCR[7:0] ≠
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
LCR[7:0] =
10111111
bit 7
1
bit 6
1
bit 5
1
bit 4
1
bit 3
1
bit 2
1
bit 1
1
bit 0
1
Xoff2(6)
TLR(7)
1 1 1
EFR[4] = 1 &
MCR[6] = 1
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
RX FIFO D
status
0
RX FIFO C
status
0
RX FIFO B
status
0
RX FIFO A
status
0
TX FIFO D
status
0
TX FIFO C
status
0
TX FIFO B
status
0
MCR[4] = 0 &
MCR[2] = 1
TX FIFO A status
0
FIFORdy(8)
R
(7) This register is only accessible when EFR[4] = 1 and MCR[6] = 1
(8) This register is accessible when any CS A-B = 0, MCR[2] = 1, and loopback MCR[4] = 0 is disabled
30
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.5.2 Receiver Holding Register (RHR)
The receiver section consists of the RHR and the receiver shift register (RSR). The RHR is actually a 64-byte
FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel data and moved to the
RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location 0 of the FIFO
is used to store the characters. If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
8.5.3 Transmit Holding Register (THR)
The transmitter section consists of the THR and the transmitter shift register (TSR). The transmit holding register
is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR where it is converted to serial data
and moved out on the TX terminal. If the FIFO is disabled, location 0 of the FIFO is used to store the byte.
Characters are lost if overflow occurs.
8.5.4 FIFO Control Register (FCR)
This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and
receiver trigger levels, and selecting the type of DMA signaling. Table 8 shows FIFO control register bit settings.
Table 8. FCR Bit Settings
BIT
BIT SETTINGS
0 = Disable the transmit and receive FIFOs
1 = Enable the transmit and receive FIFOs
0
0 = No change
1
2
3
1 = Clears the receive FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
0 = No change
1 = Clears the transmit FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO.
0 = DMA mode 0
1 = DMA mode 1
Sets the trigger level for the TX FIFO:
00 – 8 spaces
01 – 16 spaces
5:4(1)
10 – 32 spaces
11 – 56 spaces
Sets the trigger level for the RX FIFO:
00 – 1 characters
7:6
01 – 4 characters
10 – 56 characters
11 – 60 characters
(1) FCR[5−4] can be modified and enabled only when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced
function.
Copyright © 2015–2017, Texas Instruments Incorporated
31
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.5.5 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are
selected by writing the appropriate bits to the LCR. Table 9 shows line control register bit settings.
Table 9. LCR Bit Settings
BIT
BIT SETTINGS
Specifies the word length to be transmitted or received
00 – 5 bits
01 – 6 bits
10 − 7 bits
11 – 8 bits
1:0
Specifies the number of stop bits:
0 – 1 stop bits (Word length = 5, 6, 7, 8)
1 – 1.5 stop bits (Word length = 5)
1 – 2 stop bits (Word length = 6, 7, 8) 3
2
0 = No parity
3
4
1 = A parity bit is generated during transmission and the receiver checks for received parity.
0 = Odd parity is generated (if LCR[3] = 1)
1 = Even parity is generated (if LCR[3] = 1)
Selects the forced parity format (if LCR(3) = 1)
5
If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data.
If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received data.
Break control bit
6
7
0 = Normal operating condition
1 = Forces the transmitter output to go low to alert the communication terminal.
0 = Normal operating condition
1 = Divisor latch enable
32
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.5.6 Line Status Register (LSR)
Table 10 shows line status register bit settings.
Table 10. LSR Bit Settings
BIT
BIT SETTINGS
0 = No data in the receive FIFO
1 = At least one character in the RX FIFO
0
0 = No overrun error
1 = Overrun error has occurred.
1
2
3
4
0 = No parity error in data being read from RX FIFO
1 = Parity error in data being read from RX FIFO
0 = No framing error in data being read from RX FIFO
1 = Framing error occurred in data being read from RX FIFO (that is, received data did not have a valid stop bit)
0 = No break condition
1 = A break condition occurred and associated byte is 00 (that is, RX was low for at least one character time frame)
0 = Transmit hold register is not empty
5
6
7
1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is
enabled.
0 = Transmitter hold and shift registers are not empty.
1 = Transmitter hold and shift registers are empty.
0 = Normal operation
1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. Bit 7 is cleared when no
errors are present in the FIFO.
When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO
(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is
output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
Copyright © 2015–2017, Texas Instruments Incorporated
33
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.5.7 Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem.
Table 11 shows modem control register bit settings.
Table 11. MCR Bit Settings(1)
BIT
BIT SETTINGS
0 = Force DTR output to inactive (high)
1 = Force DTR output to active (low). In loopback controls MSR[5]
0
0 = Force RTS output to inactive (high)
1 = Force RTS output to active (low)
In loopback controls MSR[4]
1
If Auto-RTS is enabled the RTS output is controlled by hardware flow control
0 Disables the FIFORdy register
1 Enable the FIFORdy register
In loopback controls MSR[6]
2
3
0 = Forces the IRQ(A-B) outputs to high-impedance state
1 = Forces the IRQ(A-B) outputs to the active state
In loopback controls MSR[7]
0 = Normal operating mode
1 = Enable local loopback mode (internal)
In this mode, the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input
internally
4
0 = Disable Xon Any function
1 = Enable Xon Any function
5
6
0 = No action
1 = Enable access to the TCR and TLR registers
0 = Divide by one clock input
7
1 = Divide by four clock input
This bit reflects the inverse of the CLKSEL pin value at the trailing edge of the RESET pulse
(1) MCR[7:5] can be modified only when EFR[4] is set, that is, EFR[4] is a write enable.
8.5.8 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the modem, data set, or
peripheral device to the processor. It also indicates when a control input from the modem changes state.
Table 12 shows modem status register bit settings.
Table 12. MSR Bit Settings(1)
BIT
0
BIT SETTINGS
Indicates that CTS input (or MCR[1] in loopback) has changed state. Cleared on a read.
Indicates that DSR input (or MCR[0] in loopback) has changed state. Cleared on a read.
Indicates that RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read.
Indicates that CD input (or MCR[3] in loopback) has changed state. Cleared on a read.
This bit is equivalent to MCR[1] during local loop-back mode. It is the complement to the CTS input.
This bit is equivalent to MCR[0] during local loop-back mode. It is the complement to the DSR input.
This bit is equivalent to MCR[2] during local loop-back mode. It is the complement to the RI input.
This bit is equivalent to MCR[3] during local loop-back mode. It is the complement to the CD input.
1
2
3
4
5
6
7
(1) The primary inputs RI, CD, CTS, and DSR are all active low, but their registered equivalents in the MSR and MCR (in loopback)
registers are active high.
34
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.5.9 Interrupt Enable Register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR
interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in
response to interrupt generation. Table 13 shows interrupt enable register bit settings.
Table 13. Interrupt Enable Register (IER) Bit Settings(1)
BIT
BIT SETTINGS
0 = Disable the RHR interrupt
1 = Enable the RHR interrupt
0
0 = Disable the THR interrupt
1 = Enable the THR interrupt
1
2
3
4
5
6
7
0 = Disable the receiver line status interrupt
1 = Enable the receiver line status interrupt
0 = Disable the modem status register interrupt
1 = Enable the modem status register interrupt
0 = Disable sleep mode
1 = Enable sleep mode
0 = Disable the Xoff interrupt
1 = Enable the Xoff interrupt
0 = Disable the RTS interrupt
1 = Enable the RTS interrupt
0 = Disable the CTS interrupt
1 = Enable the CTS interrupt
(1) IER[7:4] can be modified only if EFR[4] is set, that is, EFR[4] is a write enable.
Re-enabling IER[1] causes a new interrupt, if the THR is below the threshold.
Copyright © 2015–2017, Texas Instruments Incorporated
35
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.5.10 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register, which provides the source of the interrupt in a prioritized manner. Table 14
shows interrupt identification register bit settings.
Table 14. IIR Bit Settings
BIT
BIT SETTINGS
0 = An interrupt is pending
1 = No interrupt is pending
0
3:1
4
3-Bit encoded interrupt. See Table 13
1 = Xoff or special character has been detected
CTS/RTS low to high change of state
Mirror the contents of FCR[0]
5
7:6
The interrupt priority list is illustrated in Table 15.
Table 15. Interrupt Priority List
PRIORITY
LEVEL
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INTERRUPT SOURCE
1
2
2
3
4
5
6
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Receiver line status error
Receiver timeout interrupt
RHR interrupt
THR interrupt
Modem interrupt
Received Xoff signal or special character
CTS, RTS change of state from active (low) to inactive (high)
8.5.11 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 16 shows the enhanced feature
register bit settings.
Table 16. EFR Bit Settings
BIT
BIT SETTINGS
3:0
Combinations of software flow control can be selected by programming bit 3 to bit 0. See Table 1.
Enhanced functions enable bit.
0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]
1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a
write enable
4
5
6
7
0 = Normal operation
1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.
RTS flow control enable bit
0 = Normal operation
1 = RTS flow control is enabled, that is, RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is
reached, and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.
CTS flow control enable bit
0 = Normal operation
1 = CTS flow control is enabled, that is, transmission is halted when a high signal is detected on the CTS pin
36
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.5.12 Divisor Latches (DLL, DLH)
Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH,
stores the most significant part of the divisor. DLL stores the least significant part of the division.
DLL and DLH can only be written to before sleep mode is enabled (that is, before IER[4] is set).
8.5.13 Transmission Control Register (TCR)
This 8-bit register is used to store the receive FIFO threshold levels to start or stop transmission during hardware
or software flow control. Table 17 shows transmission control register bit settings.
Table 17. TCR Bit Settings
BIT
3:0
7:4
BIT SETTINGS
RCV FIFO trigger level to HALT transmission (0 to 60)
RCV FIFO trigger level to RESTORE transmission (0 to 60)
TCR trigger levels are available from 0 to 60 bytes with a granularity of four.
TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that
TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must
be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious
operation of the device.
8.5.14 Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 18 shows trigger level
register bit settings.
Table 18. TLR Bit Settings
BIT
3:0
7:4
BIT SETTINGS
Transmit FIFO trigger levels (4 to 60), number of spaces available
RCV FIFO trigger levels (4 to 60), number of characters available
TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, then the selectable
trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels.
Trigger levels from 4 to 60 bytes are available with a granularity of 4. The TLR should be programmed for N / 4,
where N is the desired trigger level.
Copyright © 2015–2017, Texas Instruments Incorporated
37
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
8.5.15 FIFO Ready Register
The FIFO ready register provides realtime status of the transmit and receive FIFOs of both channels. Table 19
shows the FIFO ready register bit settings. The trigger level mentioned in Table 19 refers to the setting in either
FCR (when TLR value is 0), or TLR (when it has a nonzero value).
Table 19. FIFO Ready Register
BIT
BIT SETTINGS
0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO of channel A.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel A.
0
0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO of channel B.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel B.
1
3:2
Unused, always 0
0 = There are fewer than a RX trigger level number of characters in the RX FIFO of channel A.
1 = The RX FIFO of channel A has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
4
0 = There are fewer than a RX trigger level number of characters in the RX FIFO of channel B.
1 = The RX FIFO of channel B has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
5
7:6
Unused, always 0
The FIFORdy register is a read only register and can be accessed when any of the two UARTs are selected.
CSA or CSB = 0, MCR[2] (FIFORdy Enable) is a logic 1, and loopback is disabled. Its address is 111.
8.5.16 Alternate Function Register (AFR)
The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C752B. The first
of these is a concurrent write mode, which can be useful in more expediently setting up all four UART channels.
The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to
115.2 bps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTRx)
per channel, which is timed to keep the RS-485 driver enabled as long as transmit data is pending.
The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.
Table 20. AFR Bit Settings
BIT
BIT SETTINGS
CONC enables the concurrent write of all four (754) or two (752) channels simultaneously, which helps speed up
initialization. Ensure that any indirect addressing modes have been enabled before using.
0
IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps; TI does not recommend the use of this
mode at higher speeds.
1
2
485EN enables the half duplex RS-485 mode and causes the DTRx output to be set high whenever there is any data in
the THR or TSR and to be held high until the delay set by DLY2:0 has expired, at which time it is set low. The DTRx
output is intended to drive the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts are held
off until the TSR is empty, unless 485LG is set.
485LG is set when the 485EN is set. This bit indicates that a relatively large data block is being set, requiring more than
a single load of the xmt fifo. In this case, the transmitter interrupts occur as in the standard RS-232 mode, either when
the xmt fifo contents drop below the xmt threshold or when the xmt fifo is empty.
3
RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in or snoop on the RS485 traffic
or IrDA traffic. RS485 mode is generally considered half duplex, and usually a node is either driving or receiving, but
there can be cases when it is advantageous to verify what you are sending. This can be used to detect collisions or as
part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the receiver stores any data
presented on RX, if any. Note that implies that the external RS485 receiver is enabled. Whenever 485EN is cleared, the
serial receiver is enabled for normal full duplex RS232 traffic. If RCVEN is cleared while 485EN is set, the receiver is
disabled while that channel is transmitting. SIR is also considered half duplex. Often the light energy from the transmitting
LED is coupled back into the receiving PIN diode, which creates an input data stream that is not of interest to the host.
Disabling the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading the data. On the
other hand, for diagnostic or other purposes, it may be useful to observe this data stream. For example, a mirror could be
used to intentionally couple the output LED to the input PIN. For these cases, RCVEN could be set to enable the
receiver.
4
NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available, even in RSA-232 mode. This
can be useful when checking code for valid threshold interrupts, as the timeout interrupt will not override the threshold
interrupt.
38
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Table 20. AFR Bit Settings (continued)
BIT
BIT SETTINGS
DLY2 to DLY0 sets a delay after the last stop bit of the last data byte being set before the DTRx is set low, to allow for
long cable runs. The delay is in number of bit times and is enabled by 485EN. The delay starts only when both the xmt
serial shift register (TSR) is empty and the xmt fifo (THR) is empty, and if started, will be cleared by any data being
written to the THR.
7:5
Table 21. LOOP and RCVEN Functionality
LOOP MODE
RCVEN
AFR
MODE
DESCRIPTION
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 10
RS-232
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
RCVEN = 1
AFR = 14
AFR = 12
AFR = 00
RS-485
IrDA
LOOP mode off,
MCR4 = 0,
RX, TX active
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
Receive threshold and error detection interrupts available
Data stored in receive FIFO
RS-232
RCVEN = 0
RCVEN = 1
AFR = 04
AFR = 02
RS-485
IrDA
No data stored in receive FIFO, hence no interrupts available
No data stored in receive FIFO, hence no interrupts available
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
AFR = 10
AFR = 14
AFR = 12
AFR = 00
AFR = 04
AFR = 02
RS-232
RS-485
IrDA
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
Receive threshold, timeout, and error detection interrupts available
Data stored in receive FIFO
LOOP mode on,
MCR4 = 1,
RX, TX inactive
Receive threshold and error detection interrupts available
Data stored in receive FIFO
RS-232
RS-485
IrDA
Receive threshold and error detection interrupts available
Data stored in receive FIFO
RCVEN = 0
Receive threshold and error detection interrupts available
Data stored in receive FIFO
8.5.17 RS-485 Mode
The RS-485 mode is intended to simplify the interface between the UART channel and an RS-485 driver or
transceiver. When enabled by setting 485EN, the DTRx output goes high one bit time before the first stop bit of
the first data byte being sent, and remains high as long as there is pending data in the TSR or THR (xmt fifo).
After both are empty (after the last stop bit of the last data byte), the DTRx output stays high for a programmable
delay of 0 to 15 bit times, as set by DLY[2:0]. This helps preserve data integrity over long signal lines. This is
illustrated in the following.
Often RS-485 packets are relatively short and the entire packet can fit within the 64 byte xmt fifo. In this case, it
goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to
reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be
reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block), which causes
the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the
threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is
being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being
loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going
empty.
Copyright © 2015–2017, Texas Instruments Incorporated
39
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
WR THR
TX
1 Baud Time
Controlled by DLY[2:0]
DTRx
A. Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform
varies with baud rate but is typically in the microsecond range.
Figure 27. DTRx and Transmit Data Relationship
RS-485 XCVR
TX
TSR
Loopback
RSR
RS-485 BUS
DEN
REN
DTR
RX
48SEN
RCVEN
UART
Copyright © 2016, Texas Instruments Incorporated
Figure 28. RS-485 Application Example 1
RS-485 XCVR
TX
TSR
RS-485 BUS
DTR
DEN
REN
Loopback
RSR
RX
48SEN
RCVEN
UART
Copyright © 2016, Texas Instruments Incorporated
Figure 29. RS-485 Application Example 2
40
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
8.5.18 IrDA Overview
To Optoelectronic
Transmit Shift Register
Int_TX
TX
RX
LED
From
Int_RX
Optoelectronic
Pin Diode
Receive Shift Register
IREN
IrDA Converter
RCVEN
Baud Clock
Reset
Copyright © 2016, Texas Instruments Incorporated
Figure 30. IrDA Mode
The IrDA defines several protocols for sending and receiving serial infrared data, including rates of 115.2 kbps,
0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified first and the others must
maintain downward compatibility with it. At the 115.2 kbps rate, the protocol implemented in the hardware is fairly
simple. It primarily defines a serial infrared data word to be surrounded by a start bit equal to 0 and a stop bit
equal to 1. Individual bits are encoded or decoded the same whether they are start, data, or stop bits. The IrDA
engine in the TL16C752D device only evaluates single bits and follows the 115.2-kbps protocol. The 115.2-kbps
rate is a maximum rate. When both ends of the transfer are setup to a lower but matching speed, the protocol
still works. The clock used to code or sample the data is 16 times the baud rate, or 1.843-MHz maximum. To
code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To code a 0, one pulse is sent or
received within a 1-bit time period, or 16 clock cycles. The pulse must be at least 1.6-μs wide and 3 clock cycles
long at 1.843 MHz. At lower baud rates the pulse can be 1.6 μs wide or as long as 3 clock cycles. The
transmitter output, TX, is intended to drive a LED circuit to generate an infrared pulse. The LED circuits work on
positive pulses. A terminal circuit is expected to create the receiver input, RX. Most, but not all, PIN circuits have
inversion and generate negative pulses from the detected infrared light. Their output is normally high. The
TL16C752D device can decode either negative or positive pulses on RX.
8.5.19 IrDA Encoder Function
Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this
block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously
cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7th 16XCLK. On the falling edge of the 10th
16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the
seventh to tenth clocks of each 16-clock bit cycle.
16 Cycles
16 Cycles
16 Cycles
16 Cycles
Int_TX
16XCLK
16XCLK
Int_TX
TX
1
2
3
4
5
6
7
8
10
12
14
16
TX
Figure 31. IrDA-SIR Encoding Scheme – Detailed
Timing Diagram
Figure 32. Encoding Scheme – Macro View
Copyright © 2015–2017, Texas Instruments Incorporated
41
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls
on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then
returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX,
Int_RX remains high.
16 Cycles
16 Cycles
16 Cycles
16 Cycles
Int_TX
16XCLK
RX
16XCLK
1
2
3
4
5
6
7
8
10
12
14
16
Int_RX
TX
Figure 33. IrDA-SIR Decoding Scheme – Detailed
Timing Diagram
Figure 34. IrDA-SIR Decoding Scheme – Macro
View
It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one
16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for
the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C550C
UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed
by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe
occurs on the 8th 16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop
bit occurs.
RX
16XCLK
1
2
3
4
5
6
7
8
10
12
14
16
1
2
3
4
5
6
7
8
10
12
14
16
Int_RX
Figure 35. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones
16 Cycles
16 Cycles
16XCLK
RX
Int_RX
External Strobe
7 Cycles
16 Cycles
Figure 36. Recommended Strobing for Decoded Data
42
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
The TL16C752D device can decode positive pulses on RX. The timing is different, but the variation is invisible to
the UART. The decoder, which works from the falling edge, now recognizes a 0 on the trailing edge of the pulse
rather than on the leading edge. As long as the pulse duration is fairly constant, as defined by the specification,
the trailing edges should also be 16 clock cycles apart and data can readily be decoded. The 0 appears on
Int_RX after the pulse rather than at the start of it.
RX
16XCLK
1
2
3
4
5
6
7
8
10
12
14
16
Int_RX
Figure 37. Positive RX Pulse Decode – Detailed View
16
Cycles
16
Cycles
16
Cycles
16
Cycles
16XCLK
RX
Int_RX
Figure 38. Positive RX Pulse Decode – Macro View
Copyright © 2015–2017, Texas Instruments Incorporated
43
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The typical implementation is to use the TL16C752D as a dual RS-232 interface, which is intended to operate
with a 5-V microprocessor.
9.2 Typical Application
Voltage
Regulator
Data
MAX232
MAX232
UART Ch 1
UART Ch 2
Address
IOW, IOR, Reset
Microcontroller
TL16C752D
Chip select
Int and RDY
Xtal2 (optional)
Xtal1
Crystal/
Oscillator
1.8432 MHz
Copyright © 2016, Texas Instruments Incorporated
Figure 39. Typical Application Dual RS-232 Interface
9.2.1 Design Requirements
Include the recommended operating conditions for 3.3 V provided by the controller board, but with the input clock
equal to 1.8432 MHz, and include the operating free-air temperature conditions. The controller must have two 8-
bit ports, one for the control signals and another for the I/O data. A third port is optional in order to monitor the
interruptions and TX/RX ready signals (if it is needed).
44
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Implement the schematic as is shown in Figure 39
2. Implement on the controller the READ and WRITE routines in order to meet the timing requirements of the
Timing Requirements, use Figure 1 and Figure 2 as a guideline.
3. Initialize all the configuration registers. TI recommends not to obviate the default settings and initialize all of
the set of configuration registers. The base set of registers that are used during high-speed data transfer
have a straightforward access method. The extended function registers require special access bits to be
decoded along with the address lines. The following guide helps with programming these registers. Note that
the descriptions are for individual register access. Some streamlining through interleaving can be obtained
when programming all the registers.
(a) Set baud rate to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to 80 Set DLL (00) to
VALUE1 Set DLM (01) to VALUE2 Set LCR (03) to temp
(b) Set Xoff1, Xon1 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff1 (06) to
VALUE1 Set Xon1 (04) to VALUE2 Set LCR (03) to temp
(c) Set Xoff2, Xon2 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff2 (07) to
VALUE1 Set Xon2 (05) to VALUE2 Set LCR (03) to temp
(d) Set software flow control mode to VALUE Read LCR (03), save in temp Set LCR (03) to BF Set EFR
(02) to VALUE Set LCR (03) to temp
(e) Set flow control threshold to VALUE Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02),
save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR
(04) to 40 + temp3 Set TCR (06) to VALUE Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to
temp1 Set MCR (04) to temp3
(f) Set xmt and rcv FIFO thresholds to VALUE Read LCR (03), save in temp1 Set LCR (03) to BF Read
EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3
Set MCR (04) to 40 + temp3 Set TLR (07) to VALUE Set LCR (03) to BF Set EFR (02) to temp2 Set
LCR (03) to temp1 Set MCR (04) to temp3
(g) Read FIFORdy register Read MCR (04), save in temp1 Set temp2 = temp1 × EF Set MCR (04), save in
temp2 Read FRR (07), save in temp2 Pass temp2 back to host Set MCR (04) to temp1
The designer can use Figure 39 as a guideline to configure each channel of the UART.
Copyright © 2015–2017, Texas Instruments Incorporated
45
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
Typical Application (continued)
9.2.3 Application Curves
Figure 40. Typical Two Bytes Transmission With 6 Bits of
Data (0x15 and 0X21), Odd Parity and One Stop Bit
Figure 41. Typical Fall Time
Figure 42. Typical Rise Time
46
Copyright © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
10 Power Supply Recommendations
The power supply must provide a constant voltage with a 10% maximum variation of the nominal value and has
to be able to provide at least the maximum current consumption of the device for the selected nominal voltage
only for the UART device:
•
•
•
•
4.5 mA for VCC = 1.8 V
9 mA for VCC = 2.5 V
16 mA for VCC = 3.3 V
40 mA for VCC = 5 V
The VCC pin must have a 1-µF bypass capacitor placed as close as possible to this pin. Also, TI recommends to
include two extra capacitors in parallel, which should also be placed as close as possible to the VCC pin. The
suggested values for these extra capacitors are 0.1 µF and 0.01 µF, respectively.
VCC_UART
C14
C15
C16
1 µF
0.1 µF
0.01 µF
Copyright © 2016, Texas Instruments Incorporated
Place as close as possible to the VCC pin of the UART.
Figure 43. Recommended Bypass Capacitors Array
11 Layout
11.1 Layout Guidelines
Traces, Vias, and Other PCB Components: A right angle in a trace can cause more radiation. The capacitance
increases in the region of the corner, and the characteristic impedance changes. This impedance change causes
reflections.
•
•
•
Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any
impedance change, the best routing would be a round bend (see Figure 24).
Separate high-speed signals (for example, clock signals) from low-speed signals and digital from analog
signals; again, placement is important.
To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route
them with 90° to each other
Figure 44. Layout Do's and Don'ts
Copyright © 2015–2017, Texas Instruments Incorporated
47
TL16C752D
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
www.ti.com.cn
11.2 Layout Examples
Figure 45. RS232 Channel Layout Example
Figure 46. Footprint Example
48
版权 © 2015–2017, Texas Instruments Incorporated
TL16C752D
www.ti.com.cn
ZHCSE91C –SEPTEMBER 2015–REVISED JUNE 2017
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时,我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。
版权 © 2015–2017, Texas Instruments Incorporated
49
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL16C752DPFBR
ACTIVE
TQFP
PFB
48
1000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
T16C752DQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL16C752DPFBR
TQFP
PFB
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PFB 48
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
TL16C752DPFBR
1000
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2020 德州仪器半导体技术(上海)有限公司
相关型号:
©2020 ICPDF网 联系我们和版权申明