TL5001AIPE4 [TI]
PULSE-WIDTH-MODULATION CONTROL CIRCUITS; 脉宽调制控制电路型号: | TL5001AIPE4 |
厂家: | TEXAS INSTRUMENTS |
描述: | PULSE-WIDTH-MODULATION CONTROL CIRCUITS |
文件: | 总32页 (文件大小:705K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
D, JG OR P PACKAGE
(TOP VIEW)
Complete PWM Power Control
3.6-V to 40-V Operation
Internal Undervoltage-Lockout Circuit
Internal Short-Circuit Protection
Oscillator Frequency . . . 20 kHz to 500 kHz
OUT
GND
RT
DTC
SCP
1
2
3
4
8
7
6
5
V
CC
COMP
FB
Variable Dead Time Provides Control Over
Total Range
FK PACKAGE
(TOP VIEW)
±3% Tolerance on Reference Voltage
(TL5001A)
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
3
4
2
1
20 19
NC
NC
RT
18
17
16
15
14
V
5
6
7
CC
NC
NC
DTC
NC
description
COMP
NC
The TL5001 and TL5001A incorporate on a single
monolithic chip all the functions required for a
pulse-width-modulation (PWM) control circuit. De-
signed primarily for power-supply control, the
TL5001/A contains an error amplifier, a regulator, an
oscillator, a PWM comparator with a dead-time-con-
8
9
10 11 12 13
trol
input,
undervoltage
lockout
(UVLO), short-circuit protection (SCP), and an open-collector output transistor. The TL5001A has a typical
reference voltage tolerance of ±3% compared to ±5% for the TL5001.
The error-amplifier common-mode voltage ranges from 0 V to 1.5 V. The noninverting input of the error amplifier
is connected to a 1-V reference. Dead-time control (DTC) can be set to provide 0% to 100% dead time by connecting
an external resistor between DTC and GND. The oscillator frequency is set by terminating RT with an external
resistor to GND. During low V
operating range.
conditions, the UVLO circuit turns the output off until V
recovers to its normal
CC
CC
The TL5001C and TL5001AC are characterized for operation from –20°C to 85°C. The TL5001I and TL5001AI are
characterized for operation from –40°C to 85°C. The TL5001Q and TL5001AQ are characterized for operation from
–40°C to 125°C. The TL5001M and TL5001AM are characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
CERAMIC DIP
(JG)
CHIP CARRIER
(FK)
TL5001CD
TL5001ACD
TL5001ID
TL5001AID
TL5001QD
TL5001AQD
—
TL5001CP
—
—
–20°C to 85°C
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
TL5001ACP
—
—
TL5001IP
—
—
TL5001AIP
—
—
—
—
—
—
—
—
—
—
TL5001MJG
TL5001AMJG
TL5001MFK
TL5001AMFK
—
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL5001CDR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
schematic for typical application
V
I
+
TPS1101
V
O
+
2
V
CC
1
3
5
SCP
V
O
COMP
TL5001/A
DTC
6
7
4
FB
RT
GND
8
functional block diagram
V
DTC
6
RT
7
OUT
1
CC
2
UVLO
I
DT
2.5 V
1 V
1 V
1.5 V
Reference
Voltage
OSC
PWM/DTC
Comparator
Error
Amplifier
SCP
Comparator 1
+
–
4
3
FB
COMP
SCP
Comparator 2
5
SCP
8
GND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
detailed description
voltage reference
A 2.5-V regulator operating from V
is used to power the internal circuitry of the TL5001 and TL5001A and as a
CC
reference for the error amplifier and SCP circuits. A resistive divider provides a 1-V reference for the error amplifier
noninverting input which typically is within 2% of nominal over the operating temperature range.
error amplifier
The error amplifier compares a sample of the dc-to-dc converter output voltage to the 1-V reference and generates
an error signal for the PWM comparator. The dc-to-dc converter output voltage is set by selecting the error-amplifier
gain (see Figure 1), using the following expression:
V
= (1 + R1/R2) (1 V)
O
TL5001/A
3
4
COMP
FB
Compensation
Network
R1
V
I(FB)
–
To PWM
Comparator
R2
+
V
ref
= 1 V
8
GND
Figure 1. Error-Amplifier Gain Setting
The error-amplifier output is brought out as COMP for use in compensating the dc-to-dc converter control loop for
stability. Because the amplifier can only source 45 µA, the total dc load resistance should be 100 kΩ or more.
oscillator/PWM
The oscillator frequency (f ) can be set between 20 kHz and 500 kHz by connecting a resistor between RT and
osc
GND. Acceptable resistor values range from 15 kΩ to 250 kΩ. The oscillator frequency can be determined by using
the graph shown in Figure 5.
The oscillator output is a triangular wave with a minimum value of approximately 0.7 V and a maximum value of
approximately 1.3 V. The PWM comparator compares the error-amplifier output voltage and the DTC input voltage
to the triangular wave and turns the output transistor off whenever the triangular wave is greater than the lesser of
the two inputs.
dead-time control (DTC)
DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, which is critical for boost
and flyback converters. A current source generates a reference current (I ) at DTC that is nominally equal to the
DT
current at the oscillator timing terminal, RT. Connecting a resistor between DTC and GND generates a dead-time
reference voltage (V ), which the PWM/DTC comparator compares to the oscillator triangle wave as described
DT
in the previous section. Nominally, the maximum duty cycle is 0% when V is 0.7 V or less and 100% when V
DT
DT
is 1.3 V or greater. Because the triangle wave amplitude is a function of frequency and the source impedance of
RT is relatively high (1250 Ω), choosing R for a specific maximum duty cycle, D, is accomplished using the
DT
following equation and the voltage limits for the frequency in question as found in Figure 11 (V max and V min
osc
osc
are the maximum and minimum oscillator levels):
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
dead-time control (DTC) (continued)
R
R
1250 D V
max – V
osc
min
osc
V
min
osc
t
DT
Where
R
and R are in ohms, D in decimal
t
DT
Soft start can be implemented by paralleling the DTC resistor with a capacitor (C ) as shown in Figure 2. During
DT
soft start, the voltage at DTC is derived by the following equation:
–t R
C
DT DT
–e
1
V
I
R
DT
DT DT
6
DTC
TL5001/A
C
R
DT
DT
Figure 2. Soft-Start Circuit
If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, R
C
, should
DT DT
be t /3 to t /5. The TL5001/A remains off until V ≈ 0.7 V, the minimum ramp value. C is discharged every time
0
0
DT
DT
UVLO or SCP becomes active.
undervoltage-lockout (UVLO) protection
Theundervoltage-lockoutcircuitturnstheoutputtransistoroffandresetstheSCPlatchwheneverthesupplyvoltage
drops too low (approximately 3 V at 25°C) for proper operation. A hysteresis voltage of 200 mV eliminates false
triggering on noise and chattering.
short-circuit protection (SCP)
The TL5001/A includes short-circuit protection (see Figure 3), which turns the power switch off to prevent damage
when the converter output is shorted. When activated, the SCP prevents the switch from being turned on until the
internal latching circuit is reset. The circuit is reset by reducing the input voltage until UVLO becomes active or until
the SCP terminal is pulled to ground externally.
When a short circuit occurs, the error-amplifier output at COMP rises to increase the power-switch duty cycle in an
attempt to maintain the output voltage. SCP comparator 1 starts an RC timing circuit when COMP exceeds 1.5 V.
If the short is removed and the error-amplifier output drops below 1.5 V before time out, normal converter operation
continues. If the fault is still present at the end of the time-out period, the timer sets the latching circuit and turns
off the TL5001/A output transistor.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
short-circuit protection (SCP) (continued)
2.5 V
R
185 kΩ
12 kΩ
SCP
SCP
Comparator 2
C
SCP
5
SCP
To Output
Drive Logic
From Error
Amp
Q1
V
ref
= 1 V
SCP
1.5 V
Comparator 1
Q2
Figure 3. SCP Circuit
The timer operates by charging an external capacitor (C ), connected between the SCP terminal and ground,
SCP
towards 2.5 V through a 185-kΩ resistor (R
). The circuit begins charging from an initial voltage of approximately
SCP
185 mV and times out when the capacitor voltage reaches 1 V. The output of SCP comparator 2 then goes high,
turnsonQ2, andlatchesthetimercircuit. TheexpressionforsettingtheSCPtimeperiodisderivedfromthefollowing
equation:
–t
(
)
V
2.5 0.185 1
e
0.185
SCP
Where
τ = R
C
SCP SCP
The end of the time-out period, t
, occurs when V
= 1 V. Solving for C
yields:
SCP
SCP
SCP
C
12.46
t
SCP
SCP
Where
t is in seconds, C in µF.
must be much longer (generally 10 to 15 times) than the converter start-up period or the converter will not start.
t
SCP
output transistor
The output of the TL5001/A is an open-collector transistor with a maximum collector current rating of 21 mA and
a voltage rating of 51 V. The output is turned on under the following conditions: the oscillator triangle wave is lower
than both the DTC voltage and the error-amplifier output voltage, the UVLO circuit is inactive, and the short-circuit
protection circuit is inactive.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Amplifier input voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
I(FB)
Output voltage, V , OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 V
O
Output current, I , OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 mA
O
Output peak current, I
, OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
O(peak)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating ambient temperature range, T : TL5001C, TL5001AC . . . . . . . . . . . . . . . . . . . . . . –20°C to 85°C
A
TL5001I, TL5001AI . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TL5001Q, TL5001AQ . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
TL5001M, TL5001AM . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING FACTOR = 70°C
T
≤ 25°C
T
A
T
A
= 85°C
T = 125°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING
A
D
FK
JG
P
725 mW
5.8 mW/°C
11.0 mW/°C
8.4 mW/°C
8.0 mW/°C
464 mW
880 mW
672 mW
640 mW
377 mW
715 mW
546 mW
520 mW
145 mW
275 mW
210 mW
200 mW
1375 mW
1050 mW
1000 mW
recommended operating conditions
MIN
3.6
0
MAX
40
UNIT
V
Supply voltage, V
CC
Amplifier input voltage, V
I(FB)
1.5
50
V
Output voltage, V , OUT
V
O
Output current, I , OUT
O
20
mA
µA
kΩ
kΩ
kHz
COMP source current
45
COMP dc load resistance
Oscillator timing resistor, R
100
15
250
500
85
t
Oscillator frequency, f
osc
20
TL5001C, TL5001AC
TL5001I, TL5001AI
TL5001Q, TL5001AQ
TL5001M, TL5001AM
–20
–40
–40
–55
85
Operating ambient temperature, T
°C
A
125
125
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range, V
osc
= 6 V,
CC
f
= 100 kHz (unless otherwise noted)
reference
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
1.05
12.5
10
MIN TYP
MAX
1.03
12.5
10
Output voltage
Input regulation
COMP connected to FB
0.95
1
2
0.97
1
2
V
V
= 3.6 V to 40 V
mV
CC
T
A
= –20°C to 25°C (C suffix)
= –40°C to 25°C (I suffix)
= 25°C to 85°C
–10
–10
–10
–1
–1
–2
–10
–10
–10
–1
–1
–2
Output voltage change with temperature
T
A
10
10 mV/V
10
T
A
10
†
All typical values are at T = 25°C.
A
undervoltage lockout
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
Upper threshold voltage
Lower threshold voltage
Hysteresis
T
= 25°C
= 25°C
= 25°C
= 25°C
3
3
V
V
A
T
A
2.8
200
2.8
200
T
A
100
2.1
100
2.1
mV
V
Reset threshold voltage
T
A
2.55
2.55
†
All typical values are at T = 25°C.
A
short-circuit protection
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
= 25°C
UNIT
†
†
MIN TYP
MAX
1.05
230
120
–20
MIN TYP
MAX
1.03
230
120
–20
SCP threshold voltage
T
A
0.95
140
1.00
185
60
0.97
140
1.00
185
60
V
SCP voltage, latched
No pullup
No pullup
mV
mV
µA
V
SCP voltage, UVLO standby
Input source current
T
A
= 25°C
–10
–15
1.5
–10
–15
1.5
SCP comparator 1 threshold voltage
†
All typical values are at T = 25°C.
A
oscillator
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
R = 100 kΩ
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
Frequency
100
15
100
15
kHz
kHz
kHz
kHz
kHz
kHz
V
t
Standard deviation of frequency
Frequency change with voltage
V
CC
= 3.6 V to 40 V
1
1
T
= –40°C to 25°C
= –20°C to 25°C
= 25°C to 85°C
–4
–4
–4
–0.4
–0.4
–0.2
1
4
4
4
–4
–4
–4
–0.4
–0.4
–0.2
1
4
4
4
A
Frequency change with temperature
T
A
T
A
Voltage at RT
†
All typical values are at T = 25°C.
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range, V
osc
= 6 V,
CC
f
= 100 kHz (unless otherwise noted) (continued)
dead-time control
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
UNIT
µA
†
TYP
†
TYP
MIN
MAX
MIN
MAX
‡
‡
‡
‡
TL5001C
TL5001I
V
V
= 1.5 V
= 1.5 V
0.9 × I
1.1 × I
1.2 × I
0.9 × I
1.1 × I
1.2 × I
(DT)
RT
RT
RT
RT
RT
RT
RT
RT
Output (source) current
Input threshold voltage
0.9 × I
0.9 × I
(DT)
Duty cycle = 0%
0.5
0.7
1.3
0.5
0.7
1.3
V
Duty cycle = 100%
1.5
1.5
†
‡
All typical values are at T = 25°C.
Output source current at RT
A
error amplifier
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
1.5
MIN TYP
MAX
Input voltage
V
CC
= 3.6 V to 40 V
0
0
1.5
V
nA
V
Input bias current
–160 –500
–160 –500
Positive
1.5
2.3
1.5
2.3
Output voltage swing
Negative
0.3
80
0.4
0.3
80
0.4
V
Open-loop voltage amplification
Unity-gain bandwidth
dB
MHz
µA
µA
1.5
1.5
Output (sink) current
V
V
= 1.2 V, COMP = 1 V
= 0.8 V, COMP = 1 V
100
600
–70
100
600
–70
I(FB)
Output (source) current
–45
–45
I(FB)
†
All typical values are at T = 25°C.
A
output
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
= 10 mA
UNIT
V
†
†
MIN TYP
MAX
2
MIN TYP
MAX
2
Output saturation voltage
Off-state current
I
1.5
1.5
O
V
V
V
= 50 V,
V
CC
= 0
10
10
O
µA
= 50 V
= 6 V
10
10
O
O
Short-circuit output current
40
40
mA
†
All typical values are at T = 25°C.
A
total device
TL5001C, TL5001I
TL5001AC, TL5001AI
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
1.5
MIN TYP
MAX
1.5
Standby supply current
Average supply current
Off state
1
1
mA
mA
R = 100 kΩ
1.4
2.1
1.4
2.1
t
†
All typical values are at T = 25°C.
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range, V
osc
= 6 V,
CC
f
= 100 kHz (unless otherwise noted)
reference
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
1.05
1.07
12.5
MIN TYP
MAX
1.03
1.06
12.5
T
= 25°C
0.95
0.93
1.00
0.98
2
0.97
0.94
1.00
0.98
2
A
Output voltage
Input regulation
COMP connected to FB
= 3.6 V to 40 V
V
T
A
= MIN to MAX
= MIN to MAX
T
A
V
mV
%
CC
Output voltage change with temper-
ature
T
A
= MIN to MAX
*–6
2
*6
*–6
2
*6
†
All typical values are at T = 25°C.
A
*Not production tested.
undervoltage lockout
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
T
= MIN, 25°C
= MAX
3.00
2.55
2.8
3.00
2.55
2.8
A
Upper threshold voltage
V
T
A
T
A
= MIN, 25°C
= MAX
Lower threshold voltage
Hysteresis
V
mV
V
T
A
2.0
2.0
T
A
= MIN to MAX
100
200
100
200
T
A
= MIN, 25°C
2.10
0.35
2.55
0.63
2.10
0.35
2.55
0.63
Reset threshold voltage
T
A
= MAX
†
All typical values are at T = 25°C.
A
short-circuit protection
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
1.05
1.07
230
MIN TYP
MAX
1.03
1.06
230
T
= MIN, 25°C
0.95
0.93
140
1.00
0.98
185
60
0.97
0.94
140
1.00
0.98
185
60
A
SCP threshold voltage
V
T
A
= MAX
SCP voltage, latched
T
= MIN to MAX No pullup
= MIN to MAX No pullup
= MIN to MAX
mV
mV
kΩ
V
A
SCP voltage, UVLO standby
Equivalent timing resistance
SCP comparator 1 threshold voltage
T
A
120
120
T
A
185
1.5
185
1.5
T
A
= MIN to MAX
†
All typical values are at T = 25°C.
A
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range, V
osc
= 6 V,
CC
f
= 100 kHz (unless otherwise noted) (continued)
oscillator
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
Frequency
T
= MIN to MAX R = 100 kΩ
100
2
100
2
kHz
kHz
kHz
A
t
Standard deviation of frequency
Frequency change with voltage
T
A
= MIN to MAX
T
A
= MIN to MAX
= MIN to MAX
= MIN to MAX
V
= 3.6 V to 40 V
1
1
CC
Q suffix
M suffix
*–6
*–9
3
*6
*9
*–6
*–9
3
*6
*9
Frequency change with
temperature
T
A
kHz
V
5
5
Voltage at RT
T
A
1
1
†
All typical values are at T = 25°C.
A
*Not production tested.
dead-time control
TL5001Q, TL5001M
TL5001AQ, TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
1.1 × I
MIN
MAX
1.1 × I
Output (source)
current
‡
‡
T
A
= MIN to MAX
V
(DT)
= 1.5 V
0.9 × I
0.9 × I
µA
RT
RT
RT
RT
Duty cycle = 0%
Duty cycle = 100%
Duty cycle = 0%
Duty cycle = 100%
0.5
0.7
1.3
0.7
1.3
0.5
0.7
1.3
0.7
1.3
T
= 25°C
A
1.5
1.5
Input threshold
voltage
V
0.4
0.4
T
A
= MIN to MAX
1.7
1.7
†
‡
All typical values are at T = 25°C.
Output source current at RT
A
error amplifier
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
Input bias current
T
= MIN to MAX
–160 –500
–160 –500
nA
V
A
Positive
1.5
2.3
1.5
2.3
Output
swing
voltage
T
A
= MIN to MAX
= MIN to MAX
Negative
0.3
80
0.4
0.3
80
0.4
V
Open-loop voltage
amplification
T
A
dB
Unity-gain bandwidth
Output (sink) current
T
= MIN to MAX
= MIN to MAX
= MIN, 25°C
= MAX
1.5
600
–70
–45
1.5
600
–70
–45
MHz
A
T
A
V
V
= 1.2 V, COMP = 1 V
= 0.8 V, COMP = 1 V
100
–45
–30
100
–45
–30
µA
I(FB)
T
A
Output (source) current
µA
I(FB)
T
A
†
All typical values are at T = 25°C.
A
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range, V
osc
= 6 V,
CC
f
= 100 kHz (unless otherwise noted) (continued)
output
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
2
MIN TYP
MAX
2
Output saturation voltage
Off-state current
T
= MIN to MAX
= MIN to MAX
T = MIN to MAX
A
I
= 10 mA
1.5
1.5
V
A
O
V
V
V
= 50 V,
= 50 V
= 6 V
V
CC
= 0
10
10
O
O
O
T
A
µA
mA
10
10
Short-circuit output current
40
40
†
All typical values are at T = 25°C.
A
total device
TL5001Q,
TL5001M
TL5001AQ,
TL5001AM
PARAMETER
TEST CONDITIONS
= MIN to MAX
UNIT
†
†
MIN TYP
MAX
1.5
MIN TYP
MAX
1.5
Standby supply current
Average supply current
Off state
T
1
1
mA
mA
A
T
A
= MIN to MAX R = 100 kΩ
1.4
2.1
1.4
2.1
t
†
All typical values are at T = 25°C.
A
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
2.3 V
COMP
1.5 V
DTC
OSC
PWM/DTC
Comparator
OUT
SCP
Comparator 1
1 V
SCP
SCP Timing Period
0 V
SCP
Comparator 2
3 V
V
CC
NOTE A: The waveforms show timing characteristics for an intermittent short circuit and a longer short circuit that is sufficient to activate SCP.
Figure 4. PWM Timing Diagram
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
OSCILLATION FREQUENCY
vs
OSCILLATOR FREQUENCY
vs
AMBIENT TEMPERATURE
TIMING RESISTANCE
100
98
96
94
92
90
88
1 M
V
= 6 V
V
= 6 V
CC
DT Resistance = R
CC
t
R = 100 kΩ
DT Resistance = 100 kΩ
t
T
A
= 25°C
100 k
10 k
10 k
100 k
1 M
– 50
– 25
0
25
50
75
100
R – Timing Resistance – Ω
t
T
A
– Ambient Temperature – °C
Figure 5
Figure 6
REFERENCE OUTPUT VOLTAGE
vs
REFERENCE OUTPUT VOLTAGE FLUCTUATION
vs
POWER-SUPPLY VOLTAGE
AMBIENT TEMPERATURE
2
1.8
1.6
1.4
1.2
1
0.6
T
= 25°C
A
V
= 6 V
CC
FB and COMP
Connected Together
FB and COMP
Connected Together
0.4
0.2
0
– 0.2
0.8
0.6
– 0.4
– 0.6
0.4
0.2
0
– 0.8
0
1
2
3
4
5
6
7
8
9
10
– 50
– 25
0
25
50
75
100
V
CC
– Power-Supply Voltage – V
T
A
– Ambient Temperature – °C
Figure 7
Figure 8
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
POWER-SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT
vs
AMBIENT TEMPERATURE
2
1.5
1
1.3
1.2
1.1
1
R = 100 kΩ
t
V
= 6 V
CC
t
T
= 25 °C
A
R = 100 kΩ
DT Resistance = 100 kΩ
0.9
0.8
0
0.5
0
0
10
20
30
40
– 50
– 25
0
25
50
75
100
V
CC
– Power-Supply Voltage – V
T
A
– Ambient Temperature – °C
Figure 9
Figure 10
ERROR AMPLIFIER OUTPUT VOLTAGE
PWM TRIANGLE WAVE AMPLITUDE VOLTAGE
vs
vs
OUTPUT (SINK) CURRENT
OSCILLATOR FREQUENCY
3
2.5
2
1.8
1.5
1.2
V
V
= 6 V
= 1.2 V
CC
I(FB)
V
T
A
= 6 V
= 25 °C
CC
T
A = 25 °C
V max (100% duty cycle)
osc
1.5
1
0.9
0.6
V min (zero duty cycle)
osc
0.5
0
0.3
0
0
0.2
0.4
0.6
10 k
100 k
1 M
10 M
f
– Oscillator Frequency – Hz
I
O
– Output (Sink) Current – mA
osc
Figure 11
Figure 12
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER OUTPUT VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
vs
AMBIENT TEMPERATURE
OUTPUT (SOURCE) CURRENT
2.46
2.45
2.44
2.43
2.42
2.41
2.40
3
2.5
2
V
= 6 V
= 0.8 V
V
= 6 V
CC
CC
V
V
T
= 0.8 V
I(FB)
No Load
I(FB)
= 25 °C
A
1.5
1
0.5
0
– 50
– 25
0
25
50
75
100
0
20
40
60
80
100
120
T
A
– Ambient Temperature – °C
I
O
– Output (Source) Current – µA
Figure 13
Figure 14
ERROR AMPLIFIER OPEN-LOOP GAIN AND
ERROR AMPLIFIER OUTPUT VOLTAGE
PHASE SHIFT
vs
vs
AMBIENT TEMPERATURE
FREQUENCY
40
30
20
240
–180°
–210°
V
V
= 6 V
= 1.2 V
V
= 6 V
CC
I(FB)
CC
T = 25 °C
A
No Load
220
200
180
160
–240°
–270°
–300°
–330°
–360°
A
V
10
0
φ
140
120
– 10
– 20
10 k
100 k
1 M
10 M
– 50
– 25
0
25
50
75
100
T
A
– Ambient Temperature – °C
f – Frequency – Hz
Figure 15
Figure 16
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
OUTPUT DUTY CYCLE
vs
SCP TIME-OUT PERIOD
vs
DTC VOLTAGE
SCP CAPACITANCE
120
100
80
60
40
20
0
12
10
8
V
= 6 V
V
= 6 V
CC
R = 100 kΩ
CC
t
R = 100 kΩ
DT Resistance = 200 kΩ
T
A
t
T
A
= 25 °C
= 25 °C
6
4
2
0
0
0.5
1
1.5
2
0
20
40
60
80
100
120
DTC Voltage – V
C
– SCP Capacitance – nF
SCP
Figure 17
Figure 18
OUTPUT SATURATION VOLTAGE
vs
DTC OUTPUT CURRENT
vs
RT OUTPUT CURRENT
OUTPUT (SINK) CURRENT
2
1.5
1
– 60
– 50
– 40
– 30
– 20
– 10
0
V
T
= 6 V
= 25 °C
DT Voltage = 1.3 V
CC
A
T
= 25 °C
A
0.5
0
0
– 10
– 20
– 30
– 40
– 50
– 60
0
5
10
15
20
I
O
– Output (Sink) Current – mA
I
O
– RT Output Current – µA
Figure 19
Figure 20
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
APPLICATION INFORMATION
V
5 V
I
R1
470 Ω
+
C1
100 µF
10 V
Q1
TPS1101
GND
L1
20 µH
3.3 V
GND
C3
0.1 µF
CR1
MBRS140T3
+
C2
2
100 µF
V
C4
1 µF
CC
10 V
1
5
SCP
V
O
+
C5
0.1 µF
3
4
COMP
U1
TL5001/A
R7
2.0 kΩ
R5
7.50 kΩ
1%
C6
0.012 µF
R2
56 kΩ
6
7
C7
0.0047 µF
DTC
R4
5.1 kΩ
R3
43 kΩ
FB
RT
R6
3.24 kΩ
1%
GND
8
Partial Bill of Materials:
U1
Q1
LI
TL5001/A
TPS1101
CTX20-1 or
Texas Instruments
Texas Instruments
Coiltronics
23 turns of #28 wire on
Micrometals No. T50-26B core
TPSD107M010R0100
TPSD107M010R0100
MBRS140T3
C1
C2
CR1
AVX
AVX
Motorola
NOTES: A. Frequency = 200 kHz
B. Duty cycle = 90% max
C. Soft-start time constant (TC) = 5.6 ms
D. SCP TC = 70 msA
Figure 21. Step-Down Converter
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: B. All linear dimensions are in inches (millimeters).
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
E. Falls within JEDEC MS-012
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL5001, TL5001A
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINALS SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.740
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Falls within JEDEC MS-004
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
MECHANICAL DATA
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
LCCC
CDIP
SOIC
Drawing
5962-9958301Q2A
5962-9958301QPA
5962-9958302Q2A
5962-9958302QPA
TL5001ACD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
20
8
1
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
JG
FK
20
8
JG
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001ACDG4
TL5001ACDR
TL5001ACDRG4
TL5001ACP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
D
D
D
D
P
P
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL5001ACPE4
TL5001AID
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001AIDG4
TL5001AIDR
TL5001AIDRG4
TL5001AIP
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TL5001AIPE4
50
Pb-Free
(RoHS)
TL5001AMFKB
TL5001AMJG
TL5001AMJGB
TL5001AQD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
SOIC
SOIC
FK
JG
JG
D
20
8
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
8
1
8
75
CU NIPDAU Level-1-220C-UNLIM
TL5001AQDG4
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001AQDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
TL5001AQDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001CD
TL5001CDG4
TL5001CDR
TL5001CDRG4
TL5001CP
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
D
P
P
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TL5001CP-P
OBSOLETE
Pb-Free
CU NIPDAU N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2008
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
(RoHS)
TL5001CPE4
TL5001CPS
ACTIVE
ACTIVE
ACTIVE
PDIP
SO
P
8
8
8
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
PS
PS
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001CPSG4
SO
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001CPSLE
TL5001CPSR
OBSOLETE
ACTIVE
SO
SO
PS
PS
8
8
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001CPSRG4
TL5001ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
PS
D
D
D
D
P
8
8
8
8
8
8
8
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001IDG4
TL5001IDR
TL5001IDRG4
TL5001IP
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TL5001IPE4
P
50
Pb-Free
(RoHS)
TL5001MFKB
TL5001MJG
TL5001MJGB
TL5001QD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
SOIC
SOIC
FK
JG
JG
D
20
8
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
8
1
8
75
CU NIPDAU Level-1-220C-UNLIM
TL5001QDG4
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL5001QDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
TL5001QDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TL5001ACDR
TL5001AIDR
TL5001CDR
TL5001CPSR
TL5001IDR
SOIC
SOIC
SOIC
SO
D
D
8
8
8
8
8
2500
2500
2500
2000
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
16.4
12.4
6.4
6.4
6.4
8.2
6.4
5.2
5.2
5.2
6.6
5.2
2.1
2.1
2.1
2.5
2.1
8.0
8.0
12.0
12.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
D
8.0
PS
D
12.0
8.0
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL5001ACDR
TL5001AIDR
TL5001CDR
TL5001CPSR
TL5001IDR
SOIC
SOIC
SOIC
SO
D
D
8
8
8
8
8
2500
2500
2500
2000
2500
340.5
340.5
340.5
346.0
340.5
338.1
338.1
338.1
346.0
338.1
20.6
20.6
20.6
33.0
20.6
D
PS
D
SOIC
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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