TLC071CP
更新时间：2024-10-29 02:16:38
品牌：TI
描述：FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS
概述
规格参数
数据手册
替代型号TLC071CP 概述
FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS 家庭宽带宽高输出驱动单电源运算放大器 放大器、缓冲器 运算放大器
TLC071CP 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | DIP |
| 包装说明： | DIP-8 | 针数： | 8 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.33.00.01 | 风险等级： | 1.94 |
| 放大器类型： | OPERATIONAL AMPLIFIER | 架构： | VOLTAGE-FEEDBACK |
| 最大平均偏置电流 (IIB)： | 0.0001 µA | 25C 时的最大偏置电流 (IIB)： | 0.00005 µA |
| 最小共模抑制比： | 80 dB | 标称共模抑制比： | 95 dB |
| 频率补偿： | YES | 最大输入失调电流 (IIO)： | 0.00005 µA |
| 最大输入失调电压： | 1900 µV | JESD-30 代码： | R-PDIP-T8 |
| JESD-609代码： | e4 | 长度： | 9.81 mm |
| 低-偏置： | YES | 低-失调： | NO |
| 微功率： | NO | 功能数量： | 1 |
| 端子数量： | 8 | 最高工作温度： | 70 °C |
| 最低工作温度： | 封装主体材料： | PLASTIC/EPOXY | |
| 封装代码： | DIP | 封装等效代码： | DIP8,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 包装方法： | TUBE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 功率： | NO | 电源： | +-2.25/+-8/4.5/16 V |
| 可编程功率： | NO | 认证状态： | Not Qualified |
| 座面最大高度： | 5.08 mm | 最小摆率： | 9.5 V/us |
| 标称压摆率： | 16 V/us | 子类别： | Operational Amplifier |
| 最大压摆率： | 2.5 mA | 供电电压上限： | 17 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | BIMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 标称均一增益带宽： | 10000 kHz |
| 最小电压增益： | 100000 | 宽带： | NO |
| 宽度： | 7.62 mm | Base Number Matches： | 1 |
TLC071CP 数据手册
通过下载TLC071CP数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
D
D
Wide Bandwidth . . . 10 MHz
High Output Drive
Operational Amplifier
− I
− I
. . . 57 mA at V
. . . 55 mA at 0.5 V
− 1.5 V
OH
OL
DD
−
+
D
High Slew Rate
− SR+ . . . 16 V/µs
− SR− . . . 19 V/µs
D
D
D
Wide Supply Range . . . 4.5 V to 16 V
Supply Current . . . 1.9 mA/Channel
Ultralow Power Shutdown Mode
I
. . . 125 µA/Channel
DD
D
D
D
Low Input Noise Voltage . . . 7 nV√Hz
Input Offset Voltage . . . 60 µV
Ultra-Small Packages
− 8 or 10 Pin MSOP (TLC070/1/2/3)
description
The first members of TI’s new BiMOS general-purpose operational amplifier family are the TLC07x. The BiMOS
family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to
single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16
V across commercial (0°C to 70°C) and an extended industrial temperature range (−40°C to 125°C), BiMOS
suits a wide range of audio, automotive, industrial and instrumentation applications. Familiar features like offset
nulling pins, and new features like MSOP PowerPAD packages and shutdown modes, enable higher levels
of performance in a variety of applications.
Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input
impedance low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum
performance features of both. AC performance improvements over the TL07x BiFET predecessors include a
bandwidth of 10 MHz (an increase of 300%) and voltage noise of 7 nV/√Hz (an improvement of 60%). DC
improvements include a factor of 4 reduction in input offset voltage down to 1.5 mV (maximum) in the standard
grade, and a power supply rejection improvement of greater than 40 dB to 130 dB. Added to this list of impressive
features is the ability to drive 50-mA loads comfortably from an ultrasmall-footprint MSOP PowerPAD package,
which positions the TLC07x as the ideal high-performance general-purpose operational amplifier family.
FAMILY PACKAGE TABLE
PACKAGE TYPES
NO. OF
CHANNELS
UNIVERSAL
EVM BOARD
DEVICE
SHUTDOWN
MSOP
PDIP
8
SOIC
8
TSSOP
—
TLC070
TLC071
TLC072
TLC073
TLC074
TLC075
1
1
2
2
4
4
8
8
Yes
8
8
—
Refer to the EVM
Selection Guide
(Lit# SLOU060)
8
8
8
—
—
Yes
—
10
—
—
14
14
16
14
14
16
—
20
20
Yes
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
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Copyright 2000−2004, Texas Instruments Incorporated
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1
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ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TLC070 and TLC071 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL OUTLINE
SMALL OUTLINE
PLASTIC DIP
(P)
SYMBOL
†
†
(D)
(DGN)
TLC070CD
TLC071CD
TLC070CDGN
TLC071CDGN
xxTIACS
xxTIACU
TLC070CP
TLC071CP
0°C to 70°C
TLC070ID
TLC071ID
TLC070IDGN
TLC071IDGN
xxTIACT
xxTIACV
TLC070IP
TLC071IP
−40°C to 125°C
TLC070AID
TLC071AID
—
—
—
—
TLC070AIP
TLC071AIP
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC070CDR).
TLC072 and TLC073 AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
PLASTIC
DIP
PLASTIC
DIP
MSOP
‡
T
A
OUTLINE
†
†
‡
SYMBOL
†
(DGN)
SYMBOL
(DGQ)
(D)
(N)
(P)
TLC072CD
TLC073CD
TLC072CDGN
—
xxTIADV
—
—
—
xxTIADX
—
TLC072CP
—
0°C to 70°C
TLC073CDGQ
TLC073CN
TLC072ID
TLC073ID
TLC072IDGN
—
xxTIADW
—
—
—
xxTIADY
—
TLC072IP
—
TLC073IDGQ
TLC073IN
−40°C to 125°C
TLC072AID
TLC073AID
—
—
—
—
—
—
—
—
—
TLC072AIP
—
TLC073AIN
†
‡
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC072CDR).
xx represents the device date code.
TLC074 and TLC075 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL OUTLINE
PLASTIC DIP
(N)
TSSOP
(PWP)
†
†
(D)
TLC074CD
TLC075CD
TLC074CN
TLC075CN
TLC074CPWP
TLC075CPWP
0°C to 70°C
TLC074ID
TLC075ID
TLC074IN
TLC075IN
TLC074IPWP
TLC075IPWP
−40°C to 125°C
TLC074AID
TLC075AID
TLC074AIN
TLC075AIN
TLC074AIPWP
TLC075AIPWP
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g.,
TLC074CDR).
2
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TLC07x PACKAGE PINOUTS
TLC070
D, DGN OR P PACKAGE
(TOP VIEW)
TLC071
D, DGN OR P PACKAGE
(TOP VIEW)
TLC072
D, DGN, OR P PACKAGE
(TOP VIEW)
NULL
IN−
SHDN
NULL
NC
1OUT
1IN−
1IN+
GND
V
DD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
IN−
IN+
V
2OUT
2IN−
2IN+
DD
DD
IN+
OUT
OUT
GND
NULL
GND
NULL
TLC074
TLC073
TLC073
D OR N PACKAGE
D OR N PACKAGE
DGQ PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
1OUT
1IN−
1IN+
GND
1SHDN
V
10
DD
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
1OUT
1IN−
1IN+
GND
NC
V
DD
2OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
2
3
4
5
2OUT
2IN−
2IN+
9
8
7
6
2IN−
2IN+
NC
V
DD
2SHDN
2IN+
2IN−
1SHDN
NC
2SHDN
NC
8
2OUT
8
TLC074
TLC075
TLC075
PWP PACKAGE
PWP PACKAGE
D OR N PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
NC
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
NC
1OUT
1IN−
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
NC
1OUT
1IN−
1IN+
4OUT
4IN−
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1IN+
4IN+
VDD
V
GND
DD
2IN+
2IN+
2IN−
3IN+
2IN−
3IN−
2OUT
1/2SHDN
NC
2OUT
3OUT
3/4SHDN
1/2SHDN
NC
NC
NC
NC
NC
NC
NC − No internal connection
TYPICAL PIN 1 INDICATORS
Pin 1
Pin 1
Pin 1
Printed or
Pin 1
Bevel Edges
Molded Dot
Stripe
Molded ”U” Shape
3
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Differential input voltage range, V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
ID
DD
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
θ
θ
T ≤ 25°C
A
POWER RATING
JC
JA
PACKAGE
(°C/W)
(°C/W)
D (8)
38.3
176
710 mW
D (14)
D (16)
26.9
25.7
4.7
122.3
114.7
52.7
52.3
78
1022 mW
1090 mW
2.37 W
DGN (8)
DGQ (10)
N (14, 16)
P (8)
4.7
2.39 W
32
1600 mW
1200 mW
4.79 W
41
104
PWP (20)
1.40
26.1
recommended operating conditions
MIN
4.5
MAX
16
UNIT
Single supply
Split supply
Supply voltage, V
DD
V
V
V
2.25
+0.5
2
8
Common-mode input voltage, V
ICR
V
−0.8
DD
V
V
IH
‡
Shutdown on/off voltage level
0.8
70
OL
C-suffix
I-suffix
0
Operating free-air temperature, T
°C
A
−40
125
‡
Relative to the voltage on the GND terminal of the device.
4
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ꢚ
ꢀ
ꢕ
ꢓ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
ꢜ
ꢏ
ꢝ
ꢔ
ꢞ
ꢏ
ꢗ
ꢙ
ꢁ
ꢔ
ꢞ
ꢚ
ꢛ
ꢛ
ꢁ
ꢐ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1900
3000
1400
2000
T
A
UNIT
25°C
Full range
25°C
390
TLC070/1/2/3,
TLC074/5
V
V
V
= 5 V,
DD
IC
O
V
IO
Input offset voltage
µV
390
= 2.5 V,
= 2.5 V,
= 50 Ω
TLC070/1/2/3A,
TLC074/5A
Full range
R
S
Temperature coefficient of input
offset voltage
α
VIO
1.2
0.7
µV/°C
25°C
50
100
700
50
TLC07XC
TLC07XI
I
IO
Input offset current
Input bias current
pA
V
DD
= 5 V,
= 2.5 V,
Full range
V
V
R
IC
O
= 2.5 V,
25°C
1.5
= 50 Ω
S
TLC07XC
TLC07XI
100
700
I
pA
V
IB
Full range
0.5
to
4.2
25°C
V
ICR
Common-mode input voltage
R
= 50 Ω
S
0.5
to
Full range
4.2
25°C
Full range
25°C
4.1
3.9
3.7
3.5
3.4
3.2
3.2
4.3
4
I
I
I
= −1 mA
= −20 mA
= −35 mA
OH
OH
OH
Full range
25°C
V
OH
High-level output voltage
V
= 2.5 V
V
3.8
3.6
IC
Full range
25°C
I
= −50 mA
−40°C to
85°C
OH
3
25°C
Full range
25°C
0.18
0.35
0.43
0.48
0.25
0.35
0.39
0.45
0.55
0.7
I
I
I
= 1 mA
OL
OL
OL
= 20 mA
= 35 mA
Full range
25°C
V
OL
Low-level output voltage
V
IC
= 2.5 V
V
Full range
25°C
0.63
I
= 50 mA
−40°C to
85°C
OL
0.7
Sourcing
Sinking
25°C
25°C
25°C
25°C
100
100
57
I
I
Short-circuit output current
Output current
mA
mA
OS
V
V
= 1.5 V from positive rail
= 0.5 V from negative rail
OH
O
55
OL
†
Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
5
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢀ ꢁ ꢂ ꢃꢄ ꢆꢅ ꢀꢁ ꢂꢃ ꢄ ꢇ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢈ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢋꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
(continued)
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
100
100
TYP
MAX
T
A
UNIT
25°C
Full range
25°C
120
Large-signal differential voltage
amplification
A
VD
V
= 3 V,
dB
GΩ
pF
Ω
R
= 10 kΩ
O(PP)
L
r
Differential input resistance
1000
22.9
i(d)
Common-mode input
capacitance
C
f = 10 kHz
f = 10 kHz,
25°C
IC
z
Closed-loop output impedance
Common-mode rejection ratio
Supply voltage rejection ratio
A
V
= 10
25°C
25°C
0.25
95
o
80
80
80
80
CMRR
V
V
= 1 to 3 V,
R
= 50 Ω
dB
dB
IC
S
Full range
25°C
100
1.9
= 4.5 V to 16 V,
V
IC
= V /2,
DD
DD
k
SVR
(∆V
DD
/∆V
IO
)
No load
Full range
25°C
2.5
3.5
I
Supply current (per channel)
V
O
= 2.5 V,
No load
mA
DD
Full range
Supply current in shutdown
mode (per channel)
(TLC070, TLC073, TLC075)
25°C
125
200
250
I
µA
SHDN ≤ 0.8 V
DD(SHDN)
Full range
†
Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
6
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢈꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢉꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀꢁ ꢂꢃ ꢄꢋ ꢌ
ꢕ
ꢍꢌ
ꢎ
ꢏ
ꢁꢐ
ꢑ
ꢍ
ꢒ
ꢏ
ꢓ
ꢔ
ꢕ
ꢖ
ꢌ
ꢗ
ꢓ
ꢒ
ꢏ
ꢓ
ꢀ
ꢘ
ꢘ
ꢏ
ꢙꢘ
ꢑꢚ
ꢀ
ꢛ
ꢚ
ꢀ
ꢕ
ꢓ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
ꢜ
ꢏ
ꢝ
ꢔ
ꢞ
ꢏ
ꢗ
ꢙ
ꢁ
ꢔ
ꢞ
ꢚ
ꢛ
ꢛ
ꢁ
ꢐ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX
UNIT
T
A
25°C
Full range
25°C
16
V
R
= 0.8 V,
= 10 kΩ
C
= 50 pF,
O(PP)
L
L
L
SR+
SR−
Positive slew rate at unity gain
V/µs
9.5
12.5
10
19
V
R
= 0.8 V,
= 10 kΩ
C
= 50 pF,
O(PP)
Negative slew rate at unity gain
V/µs
Full range
25°C
L
f = 100 Hz
f = 1 kHz
f = 1 kHz
12
7
nV/√Hz
fA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
n
25°C
25°C
0.6
n
A
= 1
0.002%
0.012%
0.085%
0.15
V
V
R
= 3 V,
= 10 kΩ and 250 Ω,
O(PP)
L
A
V
= 10
= 100
THD + N Total harmonic distortion plus noise
‡
25°C
f = 1 kHz
A
V
t
t
Amplifier turnon time
Amplifier turnoff time
25°C
25°C
25°C
µs
µs
(on)
R
= 10 kΩ
L
‡
1.3
(off)
Gain-bandwidth product
10
MHz
f = 10 kHz,
R
= 10 kΩ
L
V
= 1 V,
= 1 V,
(STEP)PP
0.1%
0.18
0.39
0.18
0.39
A
= −1,
V
C
R
= 10 pF,
= 10 kΩ
L
L
0.01%
0.1%
t
s
Settling time
25°C
µs
V
(STEP)PP
A
= −1,
V
C
R
= 47 pF,
= 10 kΩ
L
L
0.01%
32°
40°
2.2
3.3
R
R
R
R
= 10 kΩ,
= 10 kΩ,
= 10 kΩ,
= 10 kΩ,
C
C
C
C
= 50 pF
= 0 pF
= 50 pF
= 0 pF
L
L
L
L
L
L
L
L
φ
m
Phase margin
Gain margin
25°C
25°C
dB
†
‡
Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
7
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢀ ꢁ ꢂ ꢃꢄ ꢆꢅ ꢀꢁ ꢂꢃ ꢄ ꢇ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢈ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢋꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 12 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1900
3000
1400
2000
T
A
UNIT
25°C
Full range
25°C
390
TLC070/1/2/3,
TLC074/5
V
V
V
= 12 V
DD
IC
O
V
IO
Input offset voltage
µV
390
= 6 V,
= 6 V,
= 50 Ω
TLC070/1/2/3A,
TLC074/5A
Full range
R
S
Temperature coefficient of input
offset voltage
α
VIO
1.2
0.7
µV/°C
25°C
50
100
700
50
TLC07xC
TLC07xI
I
IO
Input offset current
Input bias current
pA
V
DD
= 12 V
Full range
V
V
R
= 6 V,
= 6 V,
IC
O
25°C
1.5
= 50 Ω
S
TLC07xC
TLC07xI
100
700
I
pA
V
IB
Full range
0.5
to
11.2
25°C
V
ICR
Common-mode input voltage
R
= 50 Ω
S
0.5
to
Full range
11.2
25°C
Full range
25°C
11.1
11
11.2
10.9
10.7
10.5
I
I
I
= −1 mA
= −20 mA
= −35 mA
OH
OH
OH
10.8
10.7
10.6
10.3
10.4
Full range
25°C
V
OH
High-level output voltage
V
= 6 V
V
IC
Full range
25°C
I
= −50 mA
−40°C to
85°C
OH
10.3
25°C
Full range
25°C
0.17
0.35
0.4
0.25
0.35
0.45
0.5
I
I
I
= 1 mA
OL
OL
OL
= 20 mA
= 35 mA
Full range
25°C
V
OL
Low-level output voltage
V
IC
= 6 V
V
0.52
0.6
Full range
25°C
0.45
0.6
I
= 50 mA
−40°C to
85°C
OL
0.65
Sourcing
Sinking
25°C
25°C
25°C
25°C
150
150
57
I
I
Short-circuit output current
Output current
mA
mA
OS
V
V
= 1.5 V from positive rail
= 0.5 V from negative rail
OH
O
55
OL
†
Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
8
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢈꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢉꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀꢁ ꢂꢃ ꢄꢋ ꢌ
ꢕ
ꢍꢌ
ꢎ
ꢏ
ꢁꢐ
ꢑ
ꢍ
ꢒ
ꢏ
ꢓ
ꢔ
ꢕ
ꢖ
ꢌ
ꢗ
ꢓ
ꢒ
ꢏ
ꢓ
ꢀ
ꢘ
ꢘ
ꢏ
ꢙꢘ
ꢑꢚ
ꢀ
ꢛ
ꢚ
ꢀ
ꢕ
ꢓ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
ꢜ
ꢏ
ꢝ
ꢔ
ꢞ
ꢏ
ꢗ
ꢙ
ꢁ
ꢔ
ꢞ
ꢚ
ꢛ
ꢛ
ꢁ
ꢐ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
(continued)
= 12 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
120
120
TYP
MAX
T
A
UNIT
25°C
Full range
25°C
140
Large-signal differential voltage
amplification
A
VD
V
= 8 V,
dB
GΩ
pF
Ω
R
= 10 kΩ
O(PP)
L
r
Differential input resistance
1000
21.6
i(d)
Common-mode input
capacitance
C
f = 10 kHz
f = 10 kHz,
25°C
IC
z
Closed-loop output impedance
Common-mode rejection ratio
Supply voltage rejection ratio
A
V
= 10
25°C
25°C
0.25
100
o
80
80
80
80
CMRR
V
V
= 1 to 10 V,
R
= 50 Ω
dB
dB
IC
S
Full range
25°C
100
2.1
= 4.5 V to 16 V,
V
IC
= V /2,
DD
DD
k
SVR
(∆V
DD
/∆V
IO
)
No load
Full range
25°C
2.9
3.5
I
Supply current (per channel)
V
O
= 7.5 V,
No load
mA
DD
Full range
Supply current in shutdown
mode (TLC070, TLC073,
TLC075) (per channel)
25°C
125
200
250
I
µA
SHDN ≤ 0.8 V
DD(SHDN)
Full range
†
Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
9
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢀ ꢁ ꢂ ꢃꢄ ꢆꢅ ꢀꢁ ꢂꢃ ꢄ ꢇ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢈ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢋꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 12 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX
UNIT
T
A
25°C
Full range
25°C
16
V
R
= 2 V,
= 10 kΩ
C
= 50 pF,
O(PP)
L
L
L
SR+
SR−
Positive slew rate at unity gain
V/µs
9.5
12.5
10
19
V
R
= 2 V,
= 10 kΩ
C
= 50 pF,
O(PP)
Negative slew rate at unity gain
V/µs
Full range
25°C
L
f = 100 Hz
f = 1 kHz
f = 1 kHz
12
7
nV/√Hz
fA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
n
25°C
25°C
0.6
n
A
= 1
0.002%
0.005%
0.022%
0.47
V
V
R
= 8 V,
= 10 kΩ and 250 Ω,
O(PP)
L
A
V
= 10
= 100
THD + N Total harmonic distortion plus noise
‡
25°C
f = 1 kHz
A
V
t
t
Amplifier turnon time
Amplifier turnoff time
25°C
25°C
25°C
µs
µs
(on)
R
= 10 kΩ
L
‡
2.5
(off)
Gain-bandwidth product
10
MHz
f = 10 kHz,
R
= 10 kΩ
L
V
= 1 V,
= 1 V,
(STEP)PP
0.1%
0.17
0.22
0.17
0.29
A
= −1,
V
C
R
= 10 pF,
= 10 kΩ
L
L
0.01%
0.1%
t
s
Settling time
25°C
µs
V
(STEP)PP
A
= −1,
V
C
R
= 47 pF,
= 10 kΩ
L
L
0.01%
37°
42°
3.1
4
R
R
R
R
= 10 kΩ,
= 10 kΩ,
= 10 kΩ,
= 10 kΩ,
C
C
C
C
= 50 pF
= 0 pF
= 50 pF
= 0 pF
L
L
L
L
L
L
L
L
φ
m
Phase margin
Gain margin
25°C
25°C
dB
†
‡
Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
10
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢈꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢉꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀꢁ ꢂꢃ ꢄꢋ ꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑ ꢍ ꢒ ꢏꢓꢔ ꢕꢖꢌꢗꢓꢒ ꢏ ꢓꢀ ꢘ ꢘꢏ ꢙꢘ ꢕꢑꢚ ꢀꢛ ꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞ ꢚꢛ ꢛ ꢁꢐ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input offset voltage
Input offset current
Input bias current
vs Common-mode input voltage
vs Free-air temperature
1, 2
3, 4
3, 4
5, 7
6, 8
9
IO
I
I
IO
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
IB
V
V
High-level output voltage
Low-level output voltage
Output impedance
OH
OL
o
Z
I
Supply current
vs Supply voltage
vs Frequency
10
DD
PSRR
CMRR
Power supply rejection ratio
Common-mode rejection ratio
Equivalent input noise voltage
Peak-to-peak output voltage
Crosstalk
11
vs Frequency
12
V
V
vs Frequency
13
n
vs Frequency
14, 15
16
O(PP)
vs Frequency
Differential voltage gain
Phase
vs Frequency
17, 18
17, 18
19, 20
21, 22
23
vs Frequency
φ
m
Phase margin
vs Load capacitance
vs Load capacitance
vs Supply voltage
Gain margin
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
24
25, 26
SR
Slew rate
vs Frequency
27, 28
29, 30
31, 32
33
THD + N
Total harmonic distortion plus noise
vs Peak-to-peak output voltage
Large-signal follower pulse response
Small-signal follower pulse response
Large-signal inverting pulse response
Small-signal inverting pulse response
Shutdown forward isolation
34, 35
36
vs Frequency
37, 38
39, 40
41
Shutdown reverse isolation
vs Frequency
vs Supply voltage
vs Free-air temperature
Shutdown supply current
Shutdown pulse
42
43, 44
11
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ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
250
0
20
V
= 12 V
DD
= 25° C
225
−25
−50
T
A
V
= 5 V
0
I
IO
DD
= 25° C
200
175
150
125
100
75
T
A
−75
−20
−40
−60
−80
−100
−125
−150
−175
I
IB
50
25
−200
−225
−250
−275
V
= 5V
DD
−100
0
−25
−120
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
1
2
3
4
5
6
7
8
9
10 11 12
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
V
− Common-Mode Input Voltage − V
V
− Common-Mode Input Voltage − V
T − Free−Air Temperature − °C
A
ICR
ICR
Figure 1
Figure 2
Figure 3
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
20
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 5 V
I
DD
V
= 5 V
DD
IO
T
= 70°C
−20
−40
A
T
= 25°C
A
T
= 125°C
A
−60
T
= 70°C
A
T
= −40°C
A
T
= 25°C
A
−80
T
= 125°C
A
−100
−120
−140
I
IB
T
= −40°C
A
V
= 12 V
DD
−160
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
- Low-Level Output Current - mA
Figure 6
T
− Free-Air Temperature − °C
I
- High-Level Output Current - mA
I
A
OH
OL
Figure 4
Figure 5
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT IMPEDANCE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
12.0
11.5
11.0
10.5
10.0
9.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1000
V
= 5 V and 12 V
= 25°C
T
= 125°C
DD
A
T
A
T
= 70°C
A
100
10
T
= 125°C
A
T
= 70°C
A
A
= 100
V
T
= 25°C
A
T
= −40°C
A
T
= 25°C
A
1
0.10
0.01
A
= 1
V
T
= −40°C
A
A
= 10
V
V
= 12 V
DD
V
= 12 V
DD
5
9.0
0
5
10 15 20 25 30 35 40 45 50
- High-Level Output Current - mA
Figure 7
0
10 15 20 25 30 35 40 45 50
- Low-Level Output Current - mA
Figure 8
100
1k
10k
100k
1M
10M
I
I
f - Frequency - Hz
OH
OL
Figure 9
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ꢍꢌꢎ ꢏ ꢁꢐ ꢑ ꢍ ꢒ ꢏꢓꢔ ꢕꢖꢌꢗꢓꢒ ꢏ ꢓꢀ ꢘ ꢘꢏ ꢙꢘ ꢕꢑꢚ ꢀꢛ ꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞ ꢚꢛ ꢛ ꢁꢐ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
140
vs
FREQUENCY
140
SUPPLY VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0.0
T
= 25°C
A
V
= 5 V and 12 V
DD
= 25°C
120
120
100
80
60
40
20
0
T
A
T
= −40°C
A
T
V
= 12 V
DD
100
80
60
40
20
0
T
= 125°C
A
= 70°C
A
V
= 5 V
DD
A
= 1
V
SHDN = V
Per Channel
DD
0
10 100
1k
10k 100k 1M 10M
4
5
6
7
8
9
10 11 12 13 14 15 16
100
1k
10k
100k
1M
10M
V
− Supply Voltage - V
f − Frequency − Hz
f - Frequency - Hz
DD
Figure 10
Figure 11
Figure 12
PEAK-TO-PEAK OUTPUT
PEAK-TO-PEAK OUTPUT
EQUIVALENT INPUT NOISE VOLTAGE
vs
VOLTAGE
vs
VOLTAGE
vs
FREQUENCY
FREQUENCY
FREQUENCY
40
12
10
8
12
10
8
V
= 12 V
DD
35
30
25
20
15
10
5
V
= 12 V
DD
V
= 12 V
DD
6
6
V
= 5 V
DD
V
= 5 V
DD
4
4
V
= 5 V
DD
THD+N < = 5%
= 10 kΩ
= 25°C
THD+N < = 5%
= 600 Ω
= 25°C
2
2
R
T
R
T
L
A
L
A
0
0
0
10
100
1k
10k
100k
10k
100k
1M
10M
10k
100k
1M
10M
f − Frequency − Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 13
Figure 14
Figure 15
CROSSTALK
vs
FREQUENCY
0
V
A
R
V
= 5 V and 12 V
= 1
DD
V
L
−20
= 10 kΩ
−40
−60
−80
= 2 V
I(PP)
For All Channels
−100
−120
−140
−160
10
100
1k
10k
100k
f − Frequency − Hz
Figure 16
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ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN AND
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
PHASE
vs
FREQUENCY
FREQUENCY
80
70
0
80
70
0
Gain
60
50
−45
60
50
Gain
−45
Phase
Phase
40
−90
40
−90
30
30
20
−135
−180
−225
20
−135
−180
−225
10
10
V
=
2.5 V
V
= 6 V
= 10 kΩ
= 0 pF
DD
L
L
DD
L
L
0
0
R
C
T
= 10 kΩ
= 0 pF
= 25°C
R
C
T
−10
−10
= 25°C
A
A
−20
−20
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
f − Frequency − Hz
f − Frequency − Hz
Figure 17
Figure 18
PHASE MARGIN
vs
PHASE MARGIN
vs
GAIN MARGIN
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
LOAD CAPACITANCE
45°
40°
35°
4
R
R
= 0 Ω
= 100 Ω
R
= 0 Ω
null
null
null
R
= 0 Ω
null
40°
35°
3.5
3
R
= 100 Ω
null
30°
R
= 50 Ω
null
30°
25°
20°
2.5
25°
20°
15°
R
= 100 Ω
null
R
= 50 Ω
null
2
R
= 50 Ω
null
R
= 20 Ω
R
= 20 Ω
null
null
1.5
15°
10°
1
0.5
0
V
= 5 V
V
R
= 12 V
V
= 5 V
DD
DD
DD
10°
5°
R
= 20 Ω
null
R
= 10 kΩ
= 25°C
= 10 kΩ
= 25°C
R
= 10 kΩ
= 25°C
L
L
L
5°
0°
T
T
T
A
A
A
0°
10
10
100
100
10
100
C
− Load Capacitance − pF
C
− Load Capacitance − pF
C − Load Capacitance − pF
L
L
L
Figure 19
Figure 20
Figure 21
GAIN MARGIN
vs
LOAD CAPACITANCE
GAIN BANDWIDTH PRODUCT
SLEW RATE
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
5
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9.0
22
21
20
19
18
17
16
15
14
13
12
R
= 0 Ω
null
4.5
4
R
= 600 Ω and 10 kΩ
C
= 11 pF
L
L
L
C
A
= 50 pF
= 1
R
= 100 Ω
null
T
= 25°C
A
V
3.5
3
Slew Rate −
R
= 10 kΩ
L
2.5
2
R
= 50 Ω
null
R
= 20 Ω
null
R
= 600 Ω
L
Slew Rate +
1.5
V
= 12 V
DD
1
0.5
0
R
T
= 10 kΩ
= 25°C
L
A
10
100
4
5
6
7
8
9
10 11 12 13 14 15 16
4
5
6
7
8
9
10 11 12 13 14 15 16
C
− Load Capacitance − pF
L
V
- Supply Voltage - V
V
DD
- Supply Voltage - V
DD
Figure 22
Figure 23
Figure 24
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ꢍꢌꢎ ꢏ ꢁꢐ ꢑ ꢍ ꢒ ꢏꢓꢔ ꢕꢖꢌꢗꢓꢒ ꢏ ꢓꢀ ꢘ ꢘꢏ ꢙꢘ ꢕꢑꢚ ꢀꢛ ꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞ ꢚꢛ ꢛ ꢁꢐ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SLEW RATE
vs
SLEW RATE
vs
PLUS NOISE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
FREQUENCY
1
25
20
15
10
5
25
V
= 5 V
DD
R
C
= 600 Ω and 10 kΩ
L
L
V
R
V
= 5 V
DD
Slew Rate −
= 50 pF
= 1
Slew Rate −
= 10 kΩ
L
20
A
V
= 2 V
O(PP)
A
= 100
V
0.1
0.01
15
Slew Rate +
Slew Rate +
A
A
= 10
= 1
V
V
10
V
= 12 V
DD
5
0
R
C
= 600 Ω and 10 kΩ
L
L
= 50 pF
A
= 1
V
0
0.001
−55 −35 −15
5
25 45 65 85 105 125
−55 −35 −15
5
25 45 65 85 105 125
100
1k
10k
100k
T
- Free-Air Temperature - °C
T
- Free-Air Temperature - °C
A
f − Frequency − Hz
A
Figure 25
Figure 26
Figure 27
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
0.1
10
10
V
A
= 12 V
V
R
V
= 12 V
DD
= 1
V
A
= 5 V
DD
L
DD
= 1
= 10 kΩ
V
R
= 250 Ω
L
V
f = 1 kHz
= 12 V
f = 1 kHz
O(PP)
1
1
A
= 100
R
= 250 Ω
V
L
0.1
0.1
0.01
R
= 600 Ω
L
R
= 600 Ω
L
A
A
= 10
= 1
0.01
V
V
0.01
R
= 10 kΩ
0.001
L
R
= 10 kΩ
0.001
L
0.001
0.0001
0.0001
100
1k
10k
100k
0.5
2.5
4.5
6.5
8.5
10.5
0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75
f − Frequency − Hz
V
− Peak-to-Peak Output Voltage − V
O(PP)
V
− Peak-to-Peak Output Voltage − V
O(PP)
Figure 28
Figure 30
Figure 29
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
SMALL SIGNAL FOLLOWER PULSE
RESPONSE
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
V (1 V/Div)
I
V (5 V/Div)
I
V (100mV/Div)
I
V
(2 V/Div)
O
V
(500 mV/Div)
= 5 V
O
V
(50mV/Div)
O
V
V
= 12 V
DD
DD
R
= 600 Ω
and 10 kΩ
= 8 pF
= 25°C
R
= 600 Ω
and 10 kΩ
= 8 pF
= 25°C
L
L
V
= 5 V and 12 V
= 600 Ω and 10 kΩ
= 8 pF
DD
L
L
R
C
T
C
T
C
T
L
L
= 25°C
A
A
A
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − µs
t − Time − µs
t − Time − µs
Figure 31
Figure 33
Figure 32
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ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
LARGE SIGNAL INVERTING
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
SMALL SIGNAL INVERTING
PULSE RESPONSE
V (5 V/div)
I
V (2 V/div)
I
V (100 mV/div)
I
V
R
C
= 5 & 12 V
= 600 Ω and 10 kΩ
= 8 pF
DD
L
L
V
R
= 5 V
= 600 Ω
and 10 kΩ
= 8 pF
V
R
= 12 V
= 600 Ω
and 10 kΩ
= 8 pF
DD
L
DD
L
T
A
= 25°C
C
T
C
T
L
L
= 25°C
= 25°C
A
A
V
(50 mV/Div)
O
V
(2 V/Div)
O
V
(500 mV/Div)
O
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − µs
t − Time − µs
t − Time − µs
Figure 34
Figure 35
Figure 36
SHUTDOWN FORWARD
ISOLATION
SHUTDOWN FORWARD
ISOLATION
SHUTDOWN REVERSE
ISOLATION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
140
120
100
80
140
120
100
80
140
120
100
80
V
= 5 V
V
= 5 V
DD
C = 0 pF
DD
C = 0 pF
V
= 12 V
DD
C = 0 pF
L
L
L
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
V
= 0.1, 2.5, and 5 V
V
= 0.1, 2.5, and 5 V
I(PP)
I(PP)
V
= 0.1, 8, and 12 V
I(PP)
R
= 600 Ω
L
R
= 600 Ω
L
R
= 600 Ω
L
60
60
R
= 10 kΩ
60
L
R
= 10 kΩ
R
= 10 kΩ
L
L
40
40
40
20
20
20
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
Figure 37
Figure 38
Figure 39
SHUTDOWN REVERSE
ISOLATION
SHUTDOWN SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
FREQUENCY
140
120
100
80
136
134
132
130
128
126
124
122
120
118
180
160
140
120
100
80
A
V
= 1
= V
V
V
= 12 V
Shutdown On
DD
C = 0 pF
IN
DD/2
R
= open
L
L
V
= V
DD/2
IN
T
= 25°C
A
V
= 0.1, 8, and 12 V
I(PP)
V
= 12 V
DD
R
= 600 Ω
L
V
= 5 V
DD
60
R
= 10 kΩ
L
40
20
60
4
5
6
7
8
9
10 11 12 13 14 15 16
−55
−25
5
35
65
95
125
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
V
- Supply Voltage - V
T
- Free-Air Temperature - °C
A
DD
Figure 40
Figure 41
Figure 42
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ꢕ
ꢍꢌ
ꢎ
ꢏ
ꢁꢐ
ꢑ
ꢍ
ꢒ
ꢏ
ꢓ
ꢔ
ꢕ
ꢖ
ꢌ
ꢗ
ꢓ
ꢒ
ꢏ
ꢓ
ꢀ
ꢘ
ꢘ
ꢏ
ꢙꢘ
ꢑꢚ
ꢀ
ꢛ
ꢚ
ꢀ
ꢕ
ꢓ
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ꢜ
ꢏ
ꢝ
ꢔ
ꢞ
ꢏ
ꢗ
ꢙ
ꢁ
ꢔ
ꢞ
ꢚ
ꢛ
ꢛ
ꢁ
ꢐ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SHUTDOWN PULSE
SHUTDOWN PULSE
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6
4
6
SD Off
SD Off
4
Shutdown Pulse
Shutdown Pulse
2
0
2
V
= 5 V
V
= 12 V
DD
C = 8 pF
DD
C = 8 pF
L
L
T
A
= 25°C
T = 25°C
A
0
I
R
= 10 kΩ
I
R = 10 kΩ
L
DD
DD
L
DD
−2
−4
−6
−2
−4
−6
I
R
L
= 600 Ω
I
R = 600 Ω
L
DD
0
10 20 30 40 50 60 70 80
t - Time - µs
0
10 20 30 40 50 60 70 80
t - Time - µs
Figure 43
Figure 44
PARAMETER MEASUREMENT INFORMATION
R
_
+
null
R
L
C
L
Figure 45
APPLICATION INFORMATION
input offset voltage null circuit
The TLC070 and TLC071 has an input offset nulling function. Refer to Figure 46 for the diagram.
−
IN−
OUT
+
N2
IN+
N1
100 kΩ
R1
DD−
V
NOTE A: R1 = 5.6 kΩ for offset voltage adjustment of 10 mV.
R1 = 20 kΩ for offset voltage adjustment of 3 mV.
Figure 46. Input Offset Voltage Null Circuit
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
) with the output of the amplifier, as
NULL
shown in Figure 47. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
R
NULL
Input
Output
LOAD
+
C
Figure 47. Driving a Capacitive Load
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
R
R
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB–
F
R
R
G
G
Figure 48. Output Offset Voltage Model
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
high speed CMOS input amplifiers
The TLC07x is a family of high-speed low-noise CMOS input operational amplifiers that has an input
capacitance of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function
equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance.
For example, a gain of −10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional
pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their
greater input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC07x with its 10-MHz bandwidth means that this pole normally occurs
at frequencies where there is on the order of 5 dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180_ phase shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC07x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC073 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only.
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC07x.
2
V
10 pF
IN
1
0
With
10 kΩ
C
= 10 pF
F
1.5
−1
_
+
1
IN
V
A
R
R
C
=
= +1
= 10 kΩ
= 600 Ω
= 22 pF
5 V
0.5
DD
V
F
L
L
600 Ω
22 pF
V
OUT
50 Ω
0
−0.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6
t - Time - µs
Figure 49. 1-V Step Response
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 50).
R
R
F
G
−
V
1
O
+
V
I
R1
V
C1
f
+
–3dB
2pR1C1
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
Figure 50. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
Figure 51. 2-Pole Low-Pass Sallen-Key Filter
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
shutdown function
Three members of the TLC07x family (TLC070/3/5) have a shutdown terminal (SHDN) for conserving battery
life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 125
µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply voltages (e.g. 2.5 V), the shutdown terminal needs to be pulled to V − (not system ground) to disable
DD
the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 43 and 44. The amplifier is powered with a
single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are
measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the
single, dual, and quad are listed in the data tables.
Figures 37, 38, 39, and 40 show the amplifier’s forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (A = 1). The isolation performance is plotted across frequency
V
using 0.1 V , 2.5 V , and 5 V input signals at 2.5 V supplies and 0.1 V , 8 V , and 12 V input signals
PP
PP
PP
PP
PP
PP
at 6 V supplies.
circuit layout considerations
To achieve the levels of high performance of the TLC07x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D
Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D
Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general PowerPAD design considerations
The TLC07x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 52. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
Thermal Pad Area
Quad
Single or Dual
68 mils x 70 mils with 5 vias
78 mils x 94 mils with 9 vias
(Via diameter = 13 mils)
(Via diameter = 13 mils)
Figure 53. PowerPAD PCB Etch and Via Pattern
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
1. Prepare the PCB with a top side etch pattern as shown in Figure 53. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils
in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC07x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLC07x PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC07x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θ , the maximum power dissipation is shown in Figure 54 and is calculated by the following formula:
JA
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
= Maximum power dissipation of TLC07x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
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ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
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SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
6
5
4
3
2
PWP Package
T
= 150°C
J
Low-K Test PCB
= 29.7°C/W
θ
JA
SOT-23 Package
Low-K Test PCB
= 324°C/W
θ
JA
DGN Package
Low-K Test PCB
θ
= 52.3°C/W
JA
SOIC Package
Low-K Test PCB
= 176°C/W
θ
JA
PDIP Package
Low-K Test PCB
θ
= 104°C/W
JA
1
0
−55 −40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 54. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around
the device, θ decreases and the heat dissipation capability increases. The currents and voltages shown in
JA
these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output
currents and voltages should be used to choose the proper package.
24
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢈꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢉꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀꢁ ꢂꢃ ꢄꢋ ꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑ ꢍ ꢒ ꢏꢓꢔ ꢕꢖꢌꢗꢓꢒ ꢏ ꢓꢀ ꢘ ꢘꢏ ꢙꢘ ꢕꢑꢚ ꢀꢛ ꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞ ꢚꢛ ꢛ ꢁꢐ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 55 are generated using
the TLC07x typical electrical and operating characteristics at T = 25°C. Using this information, output
A
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
PSpice and Parts are trademarks of MicroSim Corporation.
25
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢀ ꢁ ꢂ ꢃꢄ ꢆꢅ ꢀꢁ ꢂꢃ ꢄ ꢇ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢈ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢋꢌ
ꢓ
ꢍ
ꢌ
ꢎ
ꢏ
ꢁ
ꢐ
ꢑ
ꢍ
ꢒ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
ꢏ
ꢓ
ꢔ
ꢕ
ꢖ
ꢌ
ꢗ
ꢓ
ꢒ
ꢏ
ꢓ
ꢀꢘ
ꢘ
ꢏ
ꢙ
ꢘ
ꢕ
ꢑ
ꢚ
ꢀ
ꢛ
ꢚ
ꢀꢕ
ꢜ
ꢏ
ꢝ
ꢔ
ꢞ
ꢏ
ꢗ
ꢙ
ꢁ
ꢔ
ꢞ
ꢚ
ꢛ
ꢛ
ꢁꢐ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
99
DLN
3
EGND
+
−
V
DD+
92
9
FB
+
91
90
RSS
ISS
RO2
−
+
−
+
VB
DLP
RP
2
VLP
VLN
HLIM
−
+
−
10
+
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
−
DE
VAD
5
54
V
DD−
−
+
4
VE
OUT
*DEVICE=TLC07X_5V, OPAMP, PJF, INT
ga
6
0
3
0
0
6
11 12 457.42E−6
10 99 1.1293E−6
gcm
iss
* TLC07X − 5V operational amplifier ”macromodel” subcircuit
* created using Parts release 8.0 on 12/16/99 at 08:38
* Parts is a MicroSim product.
10 dc 183.67E−6
ioff
6 dc .806E−6
hlim 90 0 vlim 1K
*
j1
11 2 10 jx1
12 1 10 jx2
* connections:
non-inverting input
inverting input
j2
*
*
*
*
*
r2
6
4
4
8
7
3
9
100.00E3
2.1862E3
2.1862E3
positive power supply
negative power supply
output
rd1
rd2
ro1
ro2
rp
11
12
5
10
99 10
4
2.4728E3
1.0889E6
0
.subckt TLC07X_5V 1 2 3 4 5
*
rss
vb
vc
ve
vlim
vlp
vln
10 99
9
3
0 dc
53 dc 1.5410
c1
11 12 4.8697E−12
8.0000E−12
10 99 4.0063E−12
53 dy
c2
6
7
54 4 dc .84403
css
dc
7
8
dc
91 0 dc 119
92 dc 119
0
5
de
dlp
dln
dp
54 5 dy
90 91 dx
92 90 dx
0
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 PJF(Is=117.50E−15 Beta=1.1391E−3 Vto=−1)
.model jx2 PJF(Is=117.50E−15 Beta=1.1391E−3 Vto=−1)
.ends
4
3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 99 poly(5) vb vc ve vlp vln 0 6.9132E6 −1E3 1E3
6E6 −6E6
7
Figure 55. Boyle Macromodel and Subcircuit
26
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢈꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢉꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀꢁ ꢂꢃ ꢄꢋ ꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑ ꢍ ꢒ ꢏꢓꢔ ꢕꢖꢌꢗꢓꢒ ꢏ ꢓꢀ ꢘ ꢘꢏ ꢙꢘ ꢕꢑꢚ ꢀꢛ ꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞ ꢚꢛ ꢛ ꢁꢐ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
THERMAL PAD MECHANICAL DATA
PowerPADt PLASTIC SMALL-OUTLINE
DGQ (S−PDSO−G10)
27
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢀ ꢁ ꢂ ꢃꢄ ꢆꢅ ꢀꢁ ꢂꢃ ꢄ ꢇ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢈ ꢅ ꢀꢁ ꢂꢃ ꢄ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢋꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑꢍ ꢒꢏ ꢓ ꢔ ꢕꢖꢌꢗꢓ ꢒ ꢏ ꢓꢀꢘ ꢘꢏ ꢙ ꢘꢕꢑ ꢚꢀ ꢛꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞꢚ ꢛꢛꢁꢐ
ꢑꢛ ꢔ ꢜꢌꢀ ꢏ ꢑꢗ ꢌ ꢁ ꢌꢎ ꢛꢁ ꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
THERMAL PAD MECHANICAL DATA
PowerPADt PLASTIC SMALL-OUTLINE
DGN (S−PDSO−G8)
Top View
8
5
Exposed Pad
1,73 MAX
1
4
1,78 MAX
Not to Scale
PPTD041
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to
Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application
Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.
PowerPAD is a trademark of Texas Instruments
28
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢈꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢉꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢊꢅ ꢀꢁ ꢂꢃ ꢄꢋ ꢌ
ꢍꢌꢎ ꢏ ꢁꢐ ꢑ ꢍ ꢒ ꢏꢓꢔ ꢕꢖꢌꢗꢓꢒ ꢏ ꢓꢀ ꢘ ꢘꢏ ꢙꢘ ꢕꢑꢚ ꢀꢛ ꢚꢀꢕꢓꢜꢏ ꢝꢔ ꢞꢏ ꢗꢙ ꢁ ꢔ ꢞ ꢚꢛ ꢛ ꢁꢐ
ꢑ ꢛꢔꢜ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢛ ꢁꢏ ꢍꢏ ꢔꢜ ꢞ
SLOS219D − JUNE 1999 − REVISED FEBRUARY 2004
THERMAL PAD MECHANICAL DATA
PWP (R−PDSO−G20)
PowerPADt PLASTIC SMALL−OUTLINE
PPTD027
29
WWW.TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
PACKAGING INFORMATION
Orderable Device
TLC070AID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070AIDR
TLC070AIDRG4
TLC070AIP
SOIC
SOIC
PDIP
PDIP
SOIC
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC070AIPE4
TLC070CD
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070CDGN
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070CDGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070CDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070CDR
TLC070CDRG4
TLC070CP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
D
D
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC070CPE4
TLC070ID
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070IDGNG4
MSOP-
Power
PAD
DGN
TBD
Call TI
Call TI
TLC070IDGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070IDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC070IDR
TLC070IDRG4
TLC070IP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
D
D
P
P
D
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC070IPE4
TLC071AID
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
Orderable Device
TLC071AIDG4
TLC071AIP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
PDIP
SOIC
SOIC
P
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC071AIPE4
TLC071CD
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071CDG4
TLC071CDGN
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071CDGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071CDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071CDR
TLC071CDRG4
TLC071CP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
D
D
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
Call TI
Level-NC-NC-NC
TLC071CPE4
TLC071ID
P
50
Pb-Free
(RoHS)
Call TI
Level-NC-NC-NC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071IDGN
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071IDGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071IDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC071IDR
TLC071IDRG4
TLC071IP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
D
D
P
P
D
D
D
8
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC071IPE4
TLC072AID
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072AIDG4
TLC072AIDR
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
Orderable Device
TLC072AIDRG4
TLC072AIP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
PDIP
SOIC
SOIC
P
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC072AIPE4
TLC072CD
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072CDG4
TLC072CDGN
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072CDGNG4
TLC072CDGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072CDR
TLC072CDRG4
TLC072CP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
D
8
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC072CPE4
TLC072ID
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072IDG4
TLC072IDGN
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072IDGNG4
TLC072IDGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072IDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC072IDR
TLC072IDRG4
TLC072IP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
D
D
P
P
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC072IPE4
TLC073AID
8
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
Orderable Device
TLC073AIDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
10
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC073AIDRG4
TLC073CD
SOIC
SOIC
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC073CDGQ
MSOP-
Power
PAD
DGQ
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC073CDR
TLC073CDRG4
TLC073CN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
D
D
14
14
14
14
10
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC073CNE4
TLC073IDGQ
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
MSOP-
Power
PAD
DGQ
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC073IDGQR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGQ
DGQ
10
10
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC073IDGQRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC073IN
TLC073INE4
TLC074AID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
N
N
14
14
14
14
14
14
14
20
20
14
14
14
14
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
PDIP
Pb-Free
(RoHS)
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC074AIDR
TLC074AIDRG4
TLC074AIN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TLC074AINE4
TLC074AIPWP
TLC074AIPWPG4
TLC074CD
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
HTSSOP
HTSSOP
SOIC
PWP
PWP
D
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC074CDR
TLC074CDRG4
TLC074CN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
Orderable Device
TLC074CNE4
TLC074CPWP
TLC074CPWPR
TLC074CPWPRG4
TLC074ID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
14
20
20
20
14
14
14
14
14
14
20
16
16
16
16
16
20
16
16
16
20
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
D
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC074IDG4
TLC074IDR
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC074IDRG4
TLC074IN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TLC074INE4
TLC074IPWP
TLC075AID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
HTSSOP
SOIC
PWP
D
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC075AIDR
TLC075AIDRG4
TLC075AIN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC075AINE4
TLC075AIPWP
TLC075CD
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
HTSSOP
SOIC
PWP
D
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC075CN
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC075CNE4
TLC075CPWP
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
HTSSOP
PWP
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC075CPWPRG4
TLC075IDG4
ACTIVE
ACTIVE
ACTIVE
HTSSOP
SOIC
PWP
D
20
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
TLC075IDR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC075IN
TLC075INE4
TLC075IPWP
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
N
N
16
16
20
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
HTSSOP
PWP
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TLC075IPWPRG4
ACTIVE
HTSSOP
PWP
20
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 6
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dsp.ti.com
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Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
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Microcontrollers
power.ti.com
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Security
www.ti.com/opticalnetwork
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microcontroller.ti.com
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Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
TLC071CP CAD模型
引脚图
封装焊盘图
TLC071CP 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| TLC071AIP | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 类似代替 |
|
| TLC071IP | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 类似代替 |
|
| TLC071AIPE4 | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 类似代替 |
|
TLC071CP 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| TLC071CPE4 | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071ID | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071ID | ROCHESTER | OP-AMP, 3000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8 | 获取价格 |
|
| TLC071IDG4 | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071IDGN | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071IDGNG4 | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071IDGNR | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071IDGNRG4 | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071IDR | TI | FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| TLC071IDR | ROCHESTER | OP-AMP, 3000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8 | 获取价格 |
|
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