TLC084-Q1 [TI]
汽车级四路 16V 10MHz 运算放大器;
| 型号： | TLC084-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级四路 16V 10MHz 运算放大器 放大器 运算放大器 放大器电路 |
| 文件： | 总31页 (文件大小：778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE-SUPPLY
OPERATIONAL AMPLIFIERS
Check for Samples: TLC080-Q1, TLC081-Q1, TLC082-Q1, TLC083-Q1, TLC084-Q1, TLC085-Q1
1
FEATURES
•
•
•
Low Input Noise Voltage...8.5 nV√Hz
Input Offset Voltage...60 μV
23
•
Wide Bandwidth...10 MHz
High Output Drive
Ultra-Small Packages
8- or 10-Pin MSOP (TLC080/081/082/083)
•
(1)
–
–
IOH...57 mA at VDD –1.5 V
IOL...55 mA at 0.5 V
Operational Amplifier
•
High Slew Rate
–
–
SR+...16 V/μs
SR−...19 V/μs
−
+
•
•
•
Wide Supply Range...4.5 V to 16 V
Supply Current...1.9 mA/Channel
Ultralow-Power Shutdown Mode
IDD...125 μ/Channel
(1) TLC080/081/083 in Product Preview
DESCRIPTION
The first members of TI’s new BiMOS general-purpose operational amplifier family are the TLC08x. The BiMOS
family concept is simple—provide an upgrade path for BiFET users who are moving away from dual-supply to
single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16 V
across an automotive temperature range (–40°C to 125°C), BiMOS suits a wide range of audio, automotive,
industrial, and instrumentation applications. Familiar features, such as offset nulling pins, and new features, such
as MSOP PowerPAD™ packages and shutdown modes, enable higher levels of performance in a variety of
applications.
Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input
impedance, low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum
performance features of both. AC performance improvements over the TL08x BiFET predecessors include a
bandwidth of 10 MHz (an increase of 300%) and voltage noise of 8.5 nV/√Hz (an improvement of 60%). DC
improvements include an ensured VICR that includes ground, a factor of 4 reduction in input offset voltage down
to 1.5 mV (maximum), and a power-supply rejection improvement of greater than 40 dB to 130 dB. Added to this
list of impressive features is the ability to drive ±50-mA loads comfortably from an ultra-small-footprint MSOP
PowerPAD package, which positions the TLC08x as the ideal high-performance general-purpose operational
amplifier family.
Table 1. FAMILY PACKAGES
PACKAGE
UNIVERSAL EVM
BOARD
DEVICE
NO. OF CHANNELS
SHUTDOWN
MSOP
SOIC
8
TSSOP
—
TLC080(1)
TLC081(1)
TLC082
1
1
2
2
4
4
8
8
Yes
—
8
—
Refer to the EVM
Selection Guide
(literature number
SLOU060)
8
8
—
—
TLC083(1)
10
—
—
14
14
16
—
Yes
—
TLC084
TLC085(1)
20
20
Yes
(1) Product Preview
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
3
Parts, PSpice are trademarks of MicroSim Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
Table 2. TLC080 and TLC081 AVAILABLE OPTIONS(1) (2)
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)(3)
SMALL OUTLINE
(DGN)(3)
TLC080QDRQ1
TLC081QDRQ1
TLC080QDGNRQ1
TLC081QDGNRQ1
–40°C to 125°C
(1) Product Preview
(2) For the most current package and ordering information, see the Package Option Addendum at the end
of this data sheet, or see the TI web site at www.ti.com.
(3) This package is available taped and reeled.
(1)
Table 3. TLC082 and TLC083 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)(2)
MSOP
MSOP
(DGN)(2)
(DGQ)(2)
TLC082QDRQ1(3)
–40°C to 125°C
TLC082QDGNRQ1
TLC083QDGQRQ1(3)
TLC083QDRQ1(3)
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this data sheet, or see the TI web site at www.ti.com.
(2) This package is available taped and reeled.
(3) Product Preview
Table 4. TLC084 and TLC085 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)(2)
TSSOP
(PWP)(2)
TLC084QDRQ1(3)
TLC084QPWPRQ1
–40°C to 125°C
TLC085QDRQ1(3)
TLC085QPWPRQ1(3)
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this data sheet, or see the TI web site at www.ti.com.
(2) This package is available taped and reeled.
(3) Product Preview
2
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
Figure 1. TLC08x PACKAGE PINOUTS
TLC080
D OR DGN PACKAGE
(TOP VIEW)
TLC081
D OR DGN PACKAGE
(TOP VIEW)
TLC082
D OR DGN PACKAGE
(TOP VIEW)
NULL
IN−
IN+
SHDN
VDD
OUT
NULL
IN−
IN+
NC
1OUT
1IN−
1IN+
GND
VDD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VDD
OUT
NULL
2OUT
2IN−
2IN+
GND
NULL
GND
TLC084
D PACKAGE
(TOP VIEW)
TLC083
D PACKAGE
(TOP VIEW)
TLC083
DGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1OUT
1IN−
1IN+
GND
NC
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
1
1OUT
1IN−
1IN+
GND
1SHDN
VDD
10
2OUT
2IN−
2IN+
NC
2
3
4
5
2OUT
2IN−
2IN+
9
8
7
6
2SHDN
1SHDN
NC
2SHDN
NC
8
8
TLC084
TLC085
TLC085
PWP PACKAGE
(TOP VIEW)
PWP PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
NC
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
NC
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
2IN+
VDD
2IN+
GND
3IN+
2IN−
2IN−
3IN−
2OUT
1/2SHDN
NC
2OUT
1/2SHDN
3OUT
3/4SHDN
NC
NC
NC
NC
NC
NC
NC − No internal connection
Figure 2. Typical Pin 1 Indicators
Pin 1
Pin 1
Pin 1
Pin 1
Printed or
Molded Dot
Stripe
Bevel Edges
Molded ”U” Shape
Copyright © 2006–2011, Texas Instruments Incorporated
3
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
17
UNIT
V
VDD
VID
Supply voltage(2)
Differential input voltage
±VDD
V
See Dissipation
Rating Table
Continuous total power dissipation
TJ
Operating junction temperature range
Operating ambient temperature range
Maximum junction temperature
–40
–40
125
125
150
260
°C
°C
°C
°C
TA
TJ(max)
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND .
Dissipation Ratings
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
PACKAGE
D (8)
D (14)
38.3
26.9
25.7
4.7
176
122.3
114.7
52.7
710 mW
1022 mW
1090 mW
2.37 W
D (16)
DGN (8)
DGQ (10)
PWP (20)
4.7
52.3
2.39 W
1.4
26.1
4.79 W
Recommended Operating Conditions
MIN
MAX
16
UNIT
V
Single supply
Split supply
4.5
±2.25
GND
2
VDD
Supply voltage
±8
VICR
Common-mode input voltage
Shutdown on/off voltage level(1)
Operating junction temperature
V
DD – 2
V
VIH
VIL
V
0.8
TJ
–40
125
°C
(1) Relative to the voltage on the GND terminal of the device
4
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
Electrical Characteristics
VDD = 5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TJ
MIN
TYP
MAX
1900
3300
UNIT
25°C
390
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
VIO
αVIO
IIO
Input offset voltage
μV
Full range
Temperature coefficient of input
offset voltage
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
1.2
1.9
μV/°C
25°C
Full range
25°C
50
700
50
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
Input offset current
pA
3
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω
IIB
Input bias current
pA
V
Full range
25°C
700
0 to 3 0 to 3.5
0 to 3 0 to 3.5
VICR
Common-mode input voltage
RS = 50 Ω
Full range
25°C
4.1
3.9
3.7
3.5
3.4
3.2
3.2
3
4.3
IOH = –1 mA
Full range
25°C
4
IOH = –20 mA
VIC = 2.5 V
Full range
25°C
VOH
High-level output voltage
V
3.8
IOH = –35 mA
Full range
25°C
3.6
IOH = –50 mA
Full range
25°C
0.18
0.35
0.43
0.45
0.25
0.35
0.39
0.45
0.55
0.7
IOL = 1 mA
Full range
25°C
IOL = 20 mA
VIC = 2.5 V
Full range
25°C
VOL
Low-level output voltage
V
IOL = 35 mA
Full range
25°C
0.63
0.7
IOL = 50 mA
Full range
Sourcing
100
100
57
IOS
Short-circuit output current
Output current
25°C
25°C
mA
mA
dB
Sinking
VOH = 1.5 V from positive rail
VOL = 0.5 V from negative rail
IO
55
25°C
Full range
25°C
100
100
120
Large-signal differential voltage
amplification
AVD
VO(PP) = 3 V, RL = 10 kΩ
rj(d)
CIC
ZO
Differential input resistance
1000
22.9
0.25
110
GΩ
pF
Ω
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
25°C
f = 10 kHz, AV = 10
25°C
25°C
70
70
80
80
CMRR
kSVR
IDD
Common-mode rejection ratio
VIC = 0 to 3 V, RS = 50 Ω
dB
dB
Full range
25°C
100
1.8
Supply voltage rejection ratio
VDD = 4.5 V to 16 V,
VIC = VDD/2, No load
(ΔVDD/ΔVIO
)
Full range
25°C
2.5
3.5
Supply current (per channel)
VO = 2.5 V, No load
mA
Full range
25°C
Supply current in shutdown mode
125
200
IDD(SHDN) (per channel) (TLC080, TLC083,
TLC085)
SHDN ≤ 0.8 V
μA
Full range
250
(1) Full range is –40°C to 125°C.
Copyright © 2006–2011, Texas Instruments Incorporated
5
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
Operating Characteristics
VDD = 5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TJ
MIN
10
9
TYP
MAX
UNIT
25°C
Full range
25°C
16
Positive slew rate at unity
gain
SR+
VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ
VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ
V/μs
11
8.5
19
Negative slew rate at unity
gain
SR–
V/μs
Full range
f = 100 Hz
f = 1 kHz
12
8.5
Equivalent input noise
voltage
Vn
In
25°C
25°C
nV/√Hz
fA/√Hz
Equivalent input noise current f = 1 kHz
0.6
AV = 1
0.002
0.012
0.085
0.15
1.3
VO(PP) = 3 V,
RL = 10 kΩ and 250 Ω,
f = 1 kHz
Total harmonic distortion plus
noise
THD+N
AV = 10
AV = 100
25°C
%
t(on)
t(off)
Amplifier turn-on time(2)
Amplifier turn-off time(2)
Gain-bandwidth product
RL = 10 kΩ
25°C
25°C
25°C
μs
μs
RL = 10 kΩ
f = 10 kHz, RL = 10 kΩ
10
MHz
0.1%
0.18
0.39
0.18
0.39
32
V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ
0.01%
ts
Settling time
25°C
μs
0.1%
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ
0.01%
CL = 50 pF
CL = 0 pF
CL = 50 pF
CL = 0 pF
φm
Phase margin
Gain margin
RL = 10 kΩ
RL = 10 kΩ
25°C
25°C
deg
dB
40
2.2
3.3
(1) Full range is –40°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
6
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
Electrical Characteristics
VDD = 12 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TJ
MIN
TYP
MAX
1900
3300
UNIT
25°C
390
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
VIO
αVIO
IIO
Input offset voltage
μV
Full range
Temperature coefficient of input
offset voltage
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
1.2
1.5
μV/°C
25°C
Full range
25°C
50
700
50
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
Input offset current
pA
3
VDD = 12 V, VIC = 6 V,
VO = 6 V, RS = 50 Ω
IIB
Input bias current
pA
V
Full range
25°C
700
0 to 10 0 to 10.5
0 to 10 0 to 10.5
VICR
Common-mode input voltage
RS = 50 Ω
Full range
25°C
11.1
11
11.2
IOH = –1 mA
Full range
25°C
10.8
10.7
10.6
10.3
10.3
10.1
11
IOH = –20 mA
VIC = 6 V
Full range
25°C
VOH
High-level output voltage
V
10.7
10.5
0.17
0.35
0.4
IOH = –35 mA
Full range
25°C
IOH = –50 mA
Full range
25°C
0.25
0.35
0.45
0.55
0.52
0.6
IOL = 1 mA
Full range
25°C
IOL = 20 mA
Full range
25°C
VOL
Low-level output voltage
VIC = 6 V
V
IOL = 35 mA
Full range
25°C
0.45
0.6
IOL = 50 mA
Full range
0.7
Sourcing
150
150
57
IOS
Short-circuit output current
Output current
25°C
25°C
mA
mA
dB
Sinking
VOH = 1.5 V from positive rail
VOL = 0.5 V from negative rail
IO
55
25°C
Full range
25°C
110
110
130
Large-signal differential voltage
amplification
AVD
VO(PP) = 8 V, RL = 10 kΩ
rj(d)
CIC
ZO
Differential input resistance
1000
21.6
0.25
110
GΩ
pF
Ω
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
25°C
f = 10 kHz, AV = 10
25°C
25°C
80
80
80
80
CMRR
kSVR
IDD
Common-mode rejection ratio
VIC = 0 to 10 V, RS = 50 Ω
dB
dB
Full range
25°C
100
1.9
Supply voltage rejection ratio
VDD = 4.5 V to 16 V,
VIC = VDD/2, No load
(ΔVDD/ΔVIO
)
Full range
25°C
2.9
3.5
Supply current (per channel)
VO = 7.5 V, No load
mA
Full range
25°C
Supply current in shutdown mode
125
200
IDD(SHDN) (per channel) (TLC080, TLC083,
TLC085)
SHDN ≤ 0.8 V
μA
Full range
250
(1) Full range is –40°C to 125°C.
Copyright © 2006–2011, Texas Instruments Incorporated
7
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
Operating Characteristics
VDD = 12 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TJ
MIN
10
TYP
MAX
UNIT
25°C
Full range
25°C
16
Positive slew rate at unity
gain
SR+
VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ
VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ
V/μs
9.5
12.5
10
19
Negative slew rate at unity
gain
SR–
V/μs
Full range
f = 100 Hz
f = 1 kHz
14
8.5
Equivalent input noise
voltage
Vn
In
25°C
25°C
nV/√Hz
fA/√Hz
Equivalent input noise current f = 1 kHz
0.6
AV = 1
0.002
0.005
0.022
0.47
2.5
VO(PP) = 8 V,
RL = 10 kΩ and 250 Ω,
f = 1 kHz
Total harmonic distortion plus
noise
THD+N
AV = 10
AV = 100
25°C
%
t(on)
t(off)
Amplifier turn-on time(2)
Amplifier turn-off time(2)
Gain-bandwidth product
RL = 10 kΩ
25°C
25°C
25°C
μs
μs
RL = 10 kΩ
f = 10 kHz, RL = 10 kΩ
10
MHz
0.1%
0.17
0.22
0.17
0.29
37
V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ
0.01%
ts
Settling time
25°C
μs
0.1%
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ
0.01%
CL = 50 pF
CL = 0 pF
CL = 50 pF
CL = 0 pF
φm
Phase margin
Gain margin
RL = 10 kΩ
RL = 10 kΩ
25°C
25°C
deg
dB
42
3.1
4
(1) Full range is –40°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
8
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
TYPICAL CHARACTERISTICS
Table 5. Table of Graphs
FIGURE
VIO
Input offset voltage
Input offset current
Input bias current
vs Common-mode input voltage
1, 2
3, 4
IIO
vs Free-air temperature
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
IIB
3, 4
VOH
VOL
ZO
High-level output voltage
Low-level output voltage
Output impedance
Supply current
5, 7
6, 8
9
IDD
vs Supply voltage
vs Frequency
10
PSRR
CMRR
Vn
Power supply rejection ratio
Common-mode rejection ratio
Equivalent input noise voltage
Peak-to-peak output voltage
Crosstalk
11
vs Frequency
12
vs Frequency
13
VO(PP)
vs Frequency
14, 15
16
vs Frequency
Differential voltage gain
Phase
vs Frequency
17, 18
17, 18
19, 20
21, 22
23
vs Frequency
φm
Phase margin
vs Load capacitance
vs Load capacitance
vs Supply voltage
vs Supply voltage
vs Free-air temperature
vs Frequency
Gain margin
Gain-bandwidth product
24
SR
Slew rate
25, 26
27, 28
29, 30
31, 32
33
THD+N
Total harmonic distortion plus noise
vs Peak-to-peak output voltage
Large-signal follower pulse response
Small-signal follower pulse response
Large-signal inverting pulse response
Small-signal inverting pulse response
Shutdown forward isolation
34, 35
36
vs Frequency
37, 38
39, 40
41
Shutdown reverse isolation
vs Frequency
vs Supply voltage
vs Free-air temperature
Shutdown supply current
Shutdown pulse
42
43, 44
Copyright © 2006–2011, Texas Instruments Incorporated
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TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
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INPUT OFFSET VOLTAGE
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
INPUT OFFSET VOLTAGE
vs
vs
COMMON-MODE INPUT VOLTAGE
1000
COMMON-MODE INPUT VOLTAGE
FREE-AIR TEMPERATURE
1500
1300
1100
900
V
= 12 V
DD
= 25° C
300
250
V
= 5 V
DD
T = 25° C
A
T
A
800
600
400
200
0
V
= 5 V
DD
200
150
700
500
300
100
50
I
IB
100
−100
−300
−500
−200
−400
−600
0
I
IO
−50
0
1
2
3
4
5
6
7
8
9 10 11 12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−100
−55 −40 −25 −10
5 20 35 50 65 80 95 110 125
V
− Common-Mode Input Voltage − V
ICR
V
− Common-Mode Input Voltage − V
ICR
T
A
− Free-Air Temperature − °C
Figure 3.
Figure 4.
Figure 5.
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
20
0
V
= 5 V
DD
V
= 5 V
DD
I
IO
T
A
= 70°C
−20
−40
T
A
= 25°C
T
A
= 125°C
−60
T
= 70°C
A
T
A
= −40°C
T
A
= 25°C
−80
T
A
= 125°C
−100
−120
−140
T
A
= −40°C
I
IB
V
= 12 V
DD
−160
−55 −40 −25 −10
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
5 20 35 50 65 80 95 110 125
I
- High-Level Output Current - mA
I
- Low-Level Output Current - mA
OL
OH
T
A
− Free-Air Temperature − °C
Figure 6.
Figure 7.
Figure 8.
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT IMPEDANCE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
1000
12.0
11.5
11.0
10.5
10.0
9.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 5 V and 12 V
T
= 125°C
DD
A
T
A
= 25°C
T
= 70°C
A
100
10
T
= 125°C
A
T
A
= 70°C
A
= 100
V
T
= 25°C
A
T
A
= −40°C
T
A
= 25°C
1
0.10
0.01
A
A
= 1
V
T
A
= −40°C
= 10
V
V
= 12 V
DD
V
= 12 V
DD
9.0
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
100
1k
10k
100k
1M
10M
I
- High-Level Output Current - mA
I
- Low-Level Output Current - mA
OL
f - Frequency - Hz
OH
Figure 9.
Figure 10.
Figure 11.
10
Copyright © 2006–2011, Texas Instruments Incorporated
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TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
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SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
POWER-SUPPLY REJECTION RATIO
SUPPLY CURRENT
vs
COMMON-MODE REJECTION RATIO
vs
vs
FREQUENCY
140
FREQUENCY
SUPPLY VOLTAGE
140
2.4
2.2
2.0
1.8
1.6
1.4
1.2
V
= 5 V and 12 V
= 25°C
DD
120
100
80
60
40
20
0
T
= 25°C
A
120
100
80
60
40
20
0
T
A
V
= 12 V
DD
T
= −40°C
A
T
A
= 125°C
T
A
= 70°C
V
= 5 V
DD
A
= 1
V
SHDN = V
DD
Per Channel
1.0
4
0
10 100
1k
10k 100k 1M 10M
5
6
7
8
9 10 11 12 13 14 15
100
1k
10k
100k
1M
10M
f − Frequency − Hz
V
− Supply Voltage - V
f - Frequency - Hz
DD
Figure 12.
Figure 13.
Figure 14.
PEAK-TO-PEAK OUTPUT
VOLTAGE
PEAK-TO-PEAK OUTPUT
VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
vs
vs
40
FREQUENCY
FREQUENCY
12
10
8
12
10
8
35
30
25
20
V
= 12 V
DD
V
= 12 V
DD
6
6
15
10
5
V
= 12 V
DD
V
= 5 V
DD
V
= 5 V
DD
4
4
V
= 5 V
DD
THD+N ≤ 5%
THD+N ≤ 5%
2
2
R = 10 kΩ
R
T
= 600 Ω
= 25°C
L
L
0
10
T
A
= 25°C
A
100
1k
10k
100k
0
0
f − Frequency − Hz
10k
100k
1M
10M
10k
100k
1M
10M
f - Frequency - Hz
f - Frequency - Hz
Figure 15.
Figure 16.
Figure 17.
DIFFERENTIAL VOLTAGE GAIN AND
DIFFERENTIAL VOLTAGE GAIN AND
CROSSTALK
vs
FREQUENCY
PHASE
vs
PHASE
vs
FREQUENCY
FREQUENCY
0
−20
80
70
0
80
70
0
V
A
= 5 V and 12 V
DD
= 1
V
R
= 10 kΩ
= 2 V
L
Gain
60
50
−45
60
50
Gain
−45
−40
V
I(PP)
For All Channels
−60
Phase
Phase
40
−90
40
−90
−80
30
30
20
−135
−180
−225
20
−135
−180
−225
−100
−120
−140
−160
10
10
V
R
C
T
= ±2.5 V
= 10 kΩ
= 0 pF
V
= ±6 V
= 10 kΩ
= 0 pF
DD
DD
0
0
R
C
T
L
L
L
L
−10
−10
= 25°C
= 25°C
A
A
−20
1k
−20
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 18.
Figure 19.
Figure 20.
Copyright © 2006–2011, Texas Instruments Incorporated
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TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
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PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
GAIN MARGIN
vs
LOAD CAPACITANCE
vs
LOAD CAPACITANCE
40°
45°
4
R
null
= 0 Ω
R
R
= 0 Ω
null
R
null
= 0 Ω
40°
35°
= 100 Ω
3.5
3
35°
30°
null
R
null
= 100 Ω
R
null
= 50 Ω
30°
25°
20°
2.5
R
V
= 100 Ω
25°
20°
15°
null
R
null
= 50 Ω
2
R
null
= 50 Ω
R
null
= 20 Ω
R
= 20 Ω
null
1.5
15°
1
0.5
0
10°
= 12 V
V
= 5 V
DD
V
= 5 V
DD
DD
10°
5°
R
null
= 20 Ω
R
T
= 10 kΩ
= 25°C
R
T
= 10 kΩ
= 25°C
R
T
= 10 kΩ
= 25°C
L
L
L
5°
0°
A
A
A
0°
10
100
10
100
10
100
C
L
− Load Capacitance − pF
C
L
− Load Capacitance − pF
C
L
− Load Capacitance − pF
Figure 21.
Figure 22.
Figure 23.
GAIN-BANDWIDTH PRODUCT
GAIN MARGIN
vs
SLEW RATE
vs
vs
LOAD CAPACITANCE
SUPPLY VOLTAGE
SUPPLY VOLTAGE
5
10.0
22
21
20
19
18
17
16
15
14
13
12
R
null
= 0 Ω
C
= 11 pF
L
R
= 600 Ω and 10 kΩ
= 50 pF
= 1
4.5
4
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9.0
L
L
C
A
T
= 25°C
A
R
null
= 100 Ω
V
3.5
3
R
L
= 10 kΩ
Slew Rate −
2.5
2
R
= 50 Ω
null
R
= 600 Ω
L
R
null
= 20 Ω
Slew Rate +
1.5
V
= 12 V
DD
1
0.5
0
R
T
= 10 kΩ
= 25°C
L
A
4
5
6
7
8
9
10 11 12 13 14 15 16
10
100
4
5
6
7
8
9 10 11 12 13 14 15 16
V
- Supply Voltage - V
DD
C
L
− Load Capacitance − pF
V
- Supply Voltage - V
DD
Figure 24.
Figure 25.
Figure 26.
SLEW RATE
vs
SLEW RATE
vs
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
25
20
15
10
5
25
FREQUENCY
V
= 5 V
DD
L
L
V
1
R = 600 Ω and 10 kΩ
Slew Rate −
C
A
= 50 pF
= 1
V
V
R
= 5 V
= 2 V
DD
O(PP)
= 10 kΩ
Slew Rate −
20
15
10
5
L
A
= 100
V
0.1
0.01
Slew Rate +
Slew Rate +
A
A
= 10
= 1
V
V
V
= 12 V
DD
L
L
V
R = 600 Ω and 10 kΩ
C
A
= 50 pF
= 1
0
0
−55 −35 −15
5
25 45 65 85 105 125
−55 −35 −15
5
25 45 65 85 105 125
0.001
T
A
- Free-Air Temperature - °C
T
A
- Free-Air Temperature - °C
100
1k
10k
100k
f − Frequency − Hz
Figure 27.
Figure 28.
Figure 29.
12
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TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
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TOTAL HARMONIC DISTORTION
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PLUS NOISE
vs
PLUS NOISE
vs
FREQUENCY
PEAK-TO-PEAK OUTPUT VOLTAGE
PEAK-TO-PEAK OUTPUT VOLTAGE
0.1
10
10
V
A
=
5
V
V
A
= 12 V
DD
= 1
V
V
V
= 12 V
DD
= 1
DD
R
L
= 250 Ω
= 8 V
V
O(PP)
f = 1 kHz
f = 1 kHz
R
L
= 10 kΩ
1
1
A
= 100
R
L
= 250 Ω
V
0.1
0.1
0.01
R
L
= 600 Ω
R = 600 Ω
L
A
A
= 10
= 1
0.01
0.01
V
V
R
L
= 10 kΩ
0.001
0.001
R
L
= 10 kΩ
0.001
0.0001
0.0001
100
1k
10k
100k
0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75
0.5
2.5
4.5
6.5
8.5
10.5
f − Frequency − Hz
V
− Peak-to-Peak Output Voltage − V
V
− Peak-to-Peak Output Voltage − V
O(PP)
O(PP)
Figure 30.
Figure 31.
Figure 32.
SMALL-SIGNAL FOLLOWER PULSE
RESPONSE
LARGE-SIGNAL FOLLOWER
PULSE RESPONSE
LARGE-SIGNAL FOLLOWER
PULSE RESPONSE
V
(1 V/Div)
I
V
(5 V/Div)
I
V (100mV/Div)
I
V
(2 V/Div)
O
V
(500 mV/Div)
O
V
(50mV/Div)
O
V
R
= 5 V
= 600 Ω
DD
V
R
= 12 V
= 600 Ω
and 10 kΩ
= 8 pF
DD
L
L
and 10 kΩ
C
T
A
V
R
C
= 5 V and 12 V
= 600 Ω and 10 kΩ
= 8 pF
DD
= 8 pF
= 25°C
L
L
L
C
T
A
L
= 25°C
T
A
= 25°C
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t − Time − µs
t − Time − µs
t − Time − µs
Figure 33.
Figure 34.
Figure 35.
LARGE-SIGNAL INVERTING
PULSE RESPONSE
LARGE-SIGNAL INVERTING
PULSE RESPONSE
SMALL-SIGNAL INVERTING
PULSE RESPONSE
V (5 V/div)
I
V (2 V/div)
I
V (100 mV/div)
I
V
R
C
= 5 V and 12 V
= 600 Ω and 10 kΩ
= 8 pF
DD
L
L
V
= 5 V
V
= 12 V
DD
DD
R
= 600 Ω
R
L
= 600 Ω
and 10 kΩ
L
T
A
= 25°C
and 10 kΩ
C
T
A
= 8 pF
= 25°C
C
T
= 8 pF
= 25°C
L
L
A
V
(50 mV/Div)
O
V
(2 V/Div)
O
V
(500 mV/Div)
O
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
t − Time − µs
t − Time − µs
t − Time − µs
Figure 36.
Figure 37.
Figure 38.
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13
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
SHUTDOWN REVERSE
SHUTDOWN FORWARD
SHUTDOWN FORWARD
ISOLATION
ISOLATION
vs
ISOLATION
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
140
140
120
100
80
140
120
100
80
V
= 5 V
DD
C = 0 pF
V
= 5 V
DD
C = 0 pF
V
= 12 V
DD
C = 0 pF
L
L
120
100
80
L
T
A
= 25°C
T = 25°C
A
T
A
= 25°C
V
= 0.1, 2.5, and 5 V
I(PP)
V
= 0.1, 2.5, and 5 V
I(PP)
V
= 0.1, 8, 12 V
I(PP)
R
L
= 600 Ω
R
L
= 600 Ω
R
L
= 600 Ω
60
60
R
L
= 10 kΩ
60
R
L
= 10 kΩ
R
L
= 10 kΩ
40
40
40
20
20
20
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
Figure 39.
Figure 40.
Figure 41.
SHUTDOWN REVERSE
ISOLATION
SHUTDOWN SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
136
180
160
140
120
100
80
FREQUENCY
A
V
= 1
= V
V
IN
Shutdown On
140
120
100
80
134
132
130
128
126
124
122
120
118
DD/2
R
= open
L
V
= 12 V
DD
C = 0 pF
V
= V
DD/2
IN
L
T
A
= 25°C
V
= 0.1, 8, 12 V
I(PP)
V
= 12 V
DD
R
L
= 600 Ω
V
= 5 V
DD
60
R
L
= 10 kΩ
40
60
4
5
6
7
8
9
10 11 12 13 14 15 16
−55
−25
5
35
65
95
125
20
V
- Supply Voltage - V
T
A
- Free-Air Temperature - °C
DD
100
1k
10k 100k 1M
f - Frequency - Hz
10M
100M
Figure 42.
Figure 43.
Figure 44.
SHUTDOWN PULSE
SHUTDOWN PULSE
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6
4
6
4
SD Off
SD Off
Shutdown Pulse
Shutdown Pulse
2
0
2
0
V
= 5 V
V
= 12 V
DD
C = 8 pF
DD
C = 8 pF
L
L
T
A
= 25°C
T = 25°C
A
I
R
L
= 10 kΩ
I
R
= 10 kΩ
= 600 Ω
DD
DD
L
−2
−4
−6
−2
−4
−6
I
R
L
= 600 Ω
I
R
DD L
DD
0
10 20 30 40 50 60 70 80
t - Time - µs
0
10 20 30 40 50 60 70 80
t - Time - µs
Figure 45.
Figure 46.
14
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
PARAMETER MEASUREMENT INFORMATION
R
null
_
+
R
L
C
L
Figure 47.
Copyright © 2006–2011, Texas Instruments Incorporated
15
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
APPLICATION INFORMATION
Input Offset Voltage Null Circuit
The TLC080 and TLC081 have an input offset nulling function (see Figure 48).
−
IN−
OUT
+
N2
IN+
N1
100 kΩ
R1
V
DD−
A. R1 = 5.6 kΩ for offset voltage adjustment of ±10 mV
R1 = 20 kΩ for offset voltage adjustment of ±3 mV
Figure 48. Input Offset Voltage Null Circuit
Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10
pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in
Figure 49. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
R
NULL
Input
Output
+
C
LOAD
Figure 49. Driving a Capacitive Load
Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The schematic and formula in Figure 50 can be used to calculate the output offset
voltage.
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
R
R
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB–
F
R
R
G
G
Figure 50. Output Offset Voltage Model
16
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
High-Speed CMOS Input Amplifiers
The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance
on the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to
the input capacitance multiplied by the combination of source resistance and feedback resistance. For example,
a gain of –10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional pole at
approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater
input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs at
frequencies where there is on the order of 5-dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180° phase shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC08x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 51). The 10-pF capacitor was chosen for convenience only.
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC08x.
2
V
10 pF
IN
1
0
With
10 kΩ
C
F
= 10 pF
1.5
−1
_
+
1
IN
V
A
R
R
C
= ±5 V
= +1
= 10 kΩ
= 600 Ω
= 22 pF
0.5
DD
V
F
L
L
600 Ω
22 pF
V
OUT
50 Ω
0
−0.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6
t - Time - µs
Figure 51. 1-V Step Response
Copyright © 2006–2011, Texas Instruments Incorporated
17
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 52).
R
G
R
F
−
+
V
1
O
V
I
R1
V
C1
f
+
–3dB
2pR1C1
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
Figure 52. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
R
G
=
1
R
F
2 −
)
(
R
G
Q
Figure 53. 2-Pole Low-Pass Sallen-Key Filter
Shutdown Function
Three members of the TLC08x family (TLC080/3/5) have a shutdown (SHDN) terminal for conserving battery life
in portable applications. When SHDN is tied low, the supply current is reduced to 125 μA/channel, the amplifier is
disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, SHDN can either be left
floating or pulled high. When SHDN is left floating, care should be taken to ensure that parasitic leakage current
at SHDN does not inadvertently place the operational amplifier into shutdown. SHDN threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply voltages (e.g. ±2.5 V), SHDN needs to be pulled to VDD– (not system ground) to disable the operational
amplifier.
The amplifier’s output with a shutdown pulse is shown in Figure 45 and Figure 46. The amplifier is powered with
a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turn-on and turn-off times
are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for
the single, dual, and quad are listed in the data tables.
Figure 39 through Figure 42 show the amplifier’s forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency using
0.1-VPP, 2.5-VPP, and 5-VPP input signals at ±2.5-V supplies and 0.1-VPP, 8-VPP, and 12-VPP input signals at ±6-V
supplies.
18
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
Circuit Layout Considerations
To achieve the levels of high performance of the TLC08x, follow proper printed circuit board (PCB) design
techniques. A general set of guidelines is given in the following.
•
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power-supply decoupling – Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
•
•
Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the PCB is the best
implementation.
Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This helps minimize stray capacitance at the input of
the amplifier.
•
Surface-mount passive components – Using surface-mount passive components is recommended for
high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
General PowerPAD Design Considerations
The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 54(a) and Figure 54(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 54(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
DIE
Thermal
Pad
Side View (a)
DIE
Bottom View (c)
End View (b)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 54. Views of Thermally-Enhanced DGN Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the PCB is always required, even with applications that have low power
dissipation. This soldering provides the necessary thermal and mechanical connection between the lead frame
die pad and the PCB.
Although there are many ways to properly heatsink the PowerPAD package, the following steps list the
recommended approach.
Copyright © 2006–2011, Texas Instruments Incorporated
19
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
The PowerPAD must be connected to the most negative supply voltage (GND pin potential) of the device.
1. Prepare the PCB with a top-side etch pattern (see the landing patterns at the end of this data sheet). There
should be etch for the leads, as well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil diameter
vias directly under the thermal pad. They can be larger because they are not in the thermal-pad area to be
soldered, so that wicking is not a problem.
4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device.
5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLC08x PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal-pad area. This prevents solder from being pulled away from the thermal-pad area during the
reflow process.
7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 55 and is calculated by the following formula:
TMAX * TA
qJA
P + ǒ Ǔ
D
Where:
P
= Maximum power dissipation of TLC08x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
= Thermal coefficient from case to ambient air (°C/W)
JC
CA
(1)
20
Copyright © 2006–2011, Texas Instruments Incorporated
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
www.ti.com
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
6
5
4
3
2
PWP Package
Low-K Test PCB
T
= 150°C
J
θ
= 29.7°C/W
JA
SOT-23 Package
Low-K Test PCB
= 324°C/W
θ
JA
DGN Package
Low-K Test PCB
θ
= 52.3°C/W
JA
SOIC Package
Low-K Test PCB
θ
= 176°C/W
JA
PDIP Package
Low-K Test PCB
θ
= 104°C/W
JA
1
0
−55 −40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
A. Results are with no airflow and using JEDEC Standard Low-K test PCB.
Figure 55. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in Typical
Characteristics are for the total package. For the dual or quad amplifier packages, the sum of the RMS output
currents and voltages should be used to choose the proper package.
Macromodel Information
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™. The Boyle macromodel(1) and subcircuit in Figure 56 are generated using the TLC08x typical
electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following
key parameters can be generated to a tolerance of 20% (in most cases):
(1) G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers,"
IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
•
•
•
•
•
•
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Copyright © 2006–2011, Texas Instruments Incorporated
21
TLC080-Q1, TLC081-Q1
TLC082-Q1, TLC083-Q1
TLC084-Q1, TLC085-Q1
SLOS510B –SEPTEMBER 2006–REVISED MAY 2011
www.ti.com
99
DLN
3
EGND
+
−
V
DD
92
9
FB
+
91
90
RSS
ISS
RO2
+
−
+
−
VB
DLP
RP
2
VLP
VLN
HLIM
−
+
−
10
+
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
−
DE
VAD
5
54
GND
−
+
4
VE
OUT
*DEVICE=TLC08X_5V, OPAMP, PJF, INT
ga
6
0
0
3
0
6
6
11 12 402.12E−6
10 99 1.5735E−6
dc 1.212E−6
gcm
ioff
iss
* TLC08X_5V − 5V operational amplifier ”macromodel” subcir-
cuit
10 dc 130.40E−6
* created using Parts release 8.0 on 12/16/99 at 14:03
hlim 90
0
vlim 1K
10 jx1
10 jx2
* Parts is a MicroSim product.
*
j1
11
12
6
2
j2
1
* connections:
non-inverting input
inverting input
r2
9
100.00E3
*
*
*
*
*
rd1
rd2
ro1
ro2
rp
4
11
12
5
2.4868E3
2.4868E3
positive power supply
negative power supply
output
4
8
10
7
99 10
4
3
2.8249E3
1.5337E6
0
.subckt TLC08X_5V 1 2 3 4 5
*
rss
vb
vc
ve
vlim
vlp
vln
10 99
9
3
0 dc
53 dc 1.5537
c1
11 12 4.6015E−12
8.0000E−12
c2
6
7
54
7
4
8
0
dc .84373
dc
dc 117.60
css
dc
de
dlp
dln
dp
10 99 986.29E−15
0
5
54
53 dy
dy
91
0
5
92 dc 117.60
90 91 dx
92 90 dx
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1)
.model jx2 PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1)
.ends
4
3
0
dx
egnd 99
fb
poly(2) (3,0) (4,0) 0 .5 .5
7
99 poly(5) vb vc ve vlp vln 0 13.984E6 −1E3 1E3
14E6 −14E6
Figure 56. Boyle Macromodel and Subcircuit
22
Copyright © 2006–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLC082QDGNRQ1
TLC084QPWPRQ1
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
PWP
8
2500
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
HTSSOP
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC082-Q1, TLC084-Q1 :
Catalog: TLC082, TLC084
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2011
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC082QDGNRQ1
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
MSOP-PowerPAD DGN
SPQ
Length (mm) Width (mm) Height (mm)
358.0 335.0 35.0
TLC082QDGNRQ1
8
2500
Pack Materials-Page 2
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相关型号：
TLC084AIPWPR
QUAD OP-AMP, 2000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO20, GREEN, PLASTIC, HTSSOP-20
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