TLC1542 [TI]
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS; 10位模拟数字转换器带串行控制和11个模拟输入
| 型号： | TLC1542 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 文件： | 总27页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
10-Bit Resolution A/D Converter
DB, DW, J, OR N PACKAGE
(TOP VIEW)
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample-and-Hold Function
Total Unadjusted Error . . . ±1 LSB Max
On-Chip System Clock
A0
A1
V
CC
EOC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
A2
I/O CLOCK
ADDRESS
DATA OUT
A3
A4
End-of-Conversion (EOC) Output
Terminal Compatible With TLC542
CMOS Technology
A5
15 CS
14
13
12
11
A6
REF+
REF–
A10
A7
A8
description
GND
A9
The TLC1542C, TLC1542I, TLC1542M, TLC1542Q,
TLC1543C, TLC1543I, and TLC1543Q are CMOS
10-bit switched-capacitor successive-approximation
analog-to-digital converters. These devices have three
inputs and a 3-state output [chip select (CS),
input-output clock (I/O CLOCK), address input
(ADDRESS), and data output (DATA OUT)] that
provide a direct 4-wire interface to the serial port of a
host processor. These devices allow high-speed data
transfers from the host.
FK OR FN PACKAGE
(TOP VIEW)
3
2
1
20 19
18
I/O CLOCK
ADDRESS
DATA OUT
CS
A3
A4
A5
A6
A7
4
5
6
7
8
17
16
15
14
REF+
In addition to a high-speed A/D converter and versatile
control capability, these devices have an on-chip
14-channel multiplexer that can select any one of 11
analog inputs or any one of three internal self-test
voltages. The sample-and-hold function is automatic.
At the end of A/D conversion, the end-of-conversion
(EOC) output goes high to indicate that conversion is
complete. The converter incorporated in the devices
features differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise.
A switched-capacitor design allows low-error conver-
sion over the full operating free-air temperature range.
9 10 11 12 13
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(DB)
T
A
SMALL OUTLINE
(DW)
CHIP CARRIER
(FN)
PLASTIC DIP
(N)
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
TLC1542CDW
TLC1543CDW
TLC1542IDW
TLC1543IDW
TLC1542QDW
TLC1543QDW
TLC1542CFN
TLC1543CFN
TLC1542IFN
TLC1543IFN
TLC1542QFN
TLC1543QFN
TLC1542CN
TLC1543CN
TLC1542IN
TLC1543IN
TLC1542QN
TLC1543QN
0°C to 70°C
TLC1543CDB
–40°C to 85°C
TLC1543IDB
TLC1542QDB
TLC1543QDB
–40°C to 125°C
–55°C to 125°C
TLC1542MFK
TLC1542MJ
functional block diagram
REF+
14
REF–
13
1
A0
10-Bit
Analog-to-Digital
Converter
2
Sample and
Hold
A1
3
A2
4
(switched capacitors)
A3
5
A4
6
14-Channel
A5
10
7
8
Analog
Multiplexer
A6
A7
Output
Data
Register
10-to-1 Data
Selector and
Driver
10
16
9
DATA
OUT
A8
11
12
4
A9
Input Address
Register
A10
4
3
System
Clock,
Control Logic,
and I/O
Self-Test
Reference
19
EOC
Counters
17
ADDRESS
18
15
I/O CLOCK
CS
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
A0–A10
A0–A10
C = 60 pF TYP
i
(equivalent input
capacitance)
5 MΩ TYP
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
ADDRESS
17
I
Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to
be converted next. The address data is presented with the MSB first and shifts in on the first four rising
edges of I/O CLOCK. After the four address bits have been read into the address register, this input
is ignored for the remainder of the current conversion period.
A0–A10
CS
1–9, 11, 12
15
I
I
Analogsignalinputs.The11analoginputsareappliedtotheseterminalsandareinternallymultiplexed.
The driving source impedance should be less than or equal to 1 kΩ.
Chip select. A high-to-low transition on this input resets the internal counters and controls and enables
DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup
time plus two falling edges of the internal system clock.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when
CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB value of the previous
conversionresult. ThenextfallingedgeofI/OCLOCKdrivesthisoutputtothelogiclevelcorresponding
to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the
ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low
logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused
LSBs.
EOC
19
10
18
O
I
End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O
CLOCK and remains low until the conversion is complete and data are ready for transfer.
GND
The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements
are with respect to this terminal.
I/O CLOCK
I
Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of the I/O
CLOCK with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input
begins charging the capacitor array and continues to do so until the tenth falling edge of
I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth
clock.
REF+
REF–
14
I
The upper reference voltage value (nominally V ) is applied to this terminal. The maximum input
CC
voltage range is determined by the difference between the voltage applied to this terminal and the
voltage applied to the REF– terminal.
13
20
I
I
The lower reference voltage value (nominally ground) is applied to this terminal.
Positive supply voltage
V
CC
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O
CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired
analog channel, and the next six clocks providing the control timing for sampling the analog input.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
detailed description (continued)
Therearesixbasicserial-interfacetimingmodesthatcanbeusedwiththedevice. Thesemodesaredetermined
by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with
a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer
andCSactive(low)continuously, (3)afastmodewithan11-to16-clocktransferand CSinactive(high)between
conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slow mode
with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with
a 16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in
mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data
are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also
depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On
the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is
complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes
DATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten
clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
NO. OF
I/O CLOCKS
TIMING
DIAGRAM
†
MODES
MSB AT DATA OUT
CS
Mode 1 High between conversion cycles
Mode 2 Low continuously
10
10
CS falling edge
EOC rising edge
CS falling edge
EOC rising edge
CS falling edge
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Fast Modes
‡
‡
Mode 3 High between conversion cycles
Mode 4 Low continuously
11 to 16
‡
16
Mode 5 High between conversion cycles
Mode 6 Low continuously
11 to 16
Slow Modes
‡
16
16th clock falling edge
†
‡
These edges also initiate serial-interface communication.
No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the tenth I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must
occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial
interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must
occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or three internal test inputs).
analog inputs and test modes
The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according
to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
analog inputs and test modes (continued)
Table 2. Analog-Channel-Select Address
VALUE SHIFTED INTO
ANALOG INPUT
SELECTED
ADDRESS INPUT
BINARY
0000
0001
0010
0011
0100
0101
0110
0111
HEX
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1
2
3
4
5
6
7
1000
1001
1010
8
9
A
Table 3. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
VALUE SHIFTED INTO
ADDRESS INPUT
‡
OUTPUT RESULT (HEX)
†
SELECTED
BINARY
HEX
V
ref+
– V
ref–
1011
B
200
2
V
1100
1101
C
D
000
3FF
ref–
V
ref+
†
‡
V
isthevoltageappliedtotheREF+input,andV isthevoltageappliedtotheREF–
ref–
ref+
input.
The output results shown are the ideal values and vary with the reference stability and
with internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S switch and all S switches simultaneously.
C
T
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S and S switches are opened and the threshold detector
T
C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half V ), a 0 bit is placed in
CC
the output register and the 512-weight capacitor is switched to REF–. If the voltage at the summing node is less
than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to REF+ through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
converter and analog input (continued)
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
S
C
Threshold
Detector
To Output
Latches
512
Node 512
256
128
16
8
4
2
1
1
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
S
S
S
S
S
S
S
S
S
T
T
T
T
T
T
T
T
T
V
I
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage inputs
Therearetworeferenceinputsusedwiththedevice:REF+andREF–. Thesevoltagevaluesestablishtheupper
and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF+,
REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with the
specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher
than REF+ and at zero when the input signal is equal to or lower than REF–.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.1 V
I
CC
CC
CC
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Positive reference voltage, V
Negative reference voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
ref+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V
ref–
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
Operating free-air temperature range, T : TLC1542C, TLC1543C . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC1542I, TLC1543I . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC1542Q, TLC1543Q . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
TLC1542M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
V
Supply voltage, V
4.5
5
CC
Positive reference voltage, V
(see Note 2)
(see Note 2)
– V (see Note 2)
V
V
ref+
Negative reference voltage, V
CC
0
V
ref–
Differential reference voltage, V
2.5
0
V
CC
V +0.2
CC
V
ref+
ref–
Analog input voltage (see Note 2)
High-level control input voltage, V
V
CC
V
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
2
V
IH
CC
Low-level control input voltage, V
0.8
V
IL
CC
Setup time, address bits at data input before I/O CLOCK↑, t
(see Figure 4)
100
0
ns
ns
ns
µs
MHz
ns
ns
µs
µs
su(A)
(see Figure 4)
Hold time, address bits after I/O CLOCK↑, t
h(A)
Hold time, CS low after last I/O CLOCK↓, t
(see Figure 5)
0
h(CS)
Setup time, CS low before clocking in first address bit, t
Clock frequency at I/O CLOCK (see Note 4)
(see Note 3 and Figure 5)
1.425
0
su(CS)
2.1
Pulse duration, I/O CLOCK high, t
190
190
wH(I/O)
Pulse duration, I/O CLOCK low, t
wL(I/O)
Transition time, I/O CLOCK, t
(see Note 5 and Figure 6)
t(CS)
1
10
70
85
t(I/O)
Transition time, ADDRESS and CS, t
TLC1542C, TLC1543C
0
–40
–40
–55
TLC1542I, TLC1543I
TLC1542Q, TLC1543Q
TLC1542M
Operating free-air temperature, T
°C
A
125
125
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
the electrical specifications are no longer applicable.
– V ); however,
ref–
ref+
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from V min to V max or to rise from V max to V min. In the vicinity of
IH
IL
IL
IH
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
8
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range,
V
= V
= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
CC
ref+
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
I
I
I
I
= –1.6 mA
= –20 µA
= 1.6 mA
= 20 µA
2.4
OH
OH
OL
OL
V
High-level output voltage
Low-level output voltage
V
OH
= 4.5 V to 5.5 V,
= 4.5 V,
V
–0.1
CC
0.4
0.1
V
OL
V
= 4.5 V to 5.5 V,
Off-state
(high-impedance-state)
output current
V
O
V
O
= V
,
CS at V
10
CC
CC
CC
I
µA
OZ
= 0,
CS at V
–10
I
I
I
High-level input current
Low-level input current
Operating supply current
V = V
CC
0.005
–0.005
0.8
2.5
–2.5
2.5
µA
µA
IH
I
V = 0
I
IL
CS at 0 V
mA
CC
Selected channel leakage
current TLC1542/TLC1543
C, I, or Q
Selected channel at V
,
,
Unselected channel at 0 V
Unselected channel at V
1
CC
Selected channel at 0 V,
Selected channel at V
µA
–1
CC
Unselected channel at 0 V,
CC
1
T
= 25°C
A
Selected channel at 0 V,
= 25°C
Unselected channel at V
,
CC
Selected channel leakage
current TLC1542M
–1
µA
T
A
Selected channel at V
CC
,
Unselected channel at 0 V
Unselected channel at V
2.5
Selected channel at 0 V,
–2.5
CC
Maximum static analog
reference current into REF+
V
ref+
= V
,
V = GND
ref–
10
µA
CC
Analog inputs
Control inputs
7
5
Input
capacitance
C
pF
i
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
9
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
operating characteristics over recommended operating free-air temperature range,
V
= V
= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
CC
ref+
†
TEST CONDITIONS
MIN TYP
MAX
±0.5
±1
UNIT
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
E
L
Linearity error (see Note 6)
±1
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
See Note 2
±1
E
Zero-scale error (see Note 7)
Full-scale error (see Note 7)
Total unadjusted error (see Note 8)
±1
ZS
±1
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
±1
E
FS
±1
±1
TLC1542C, I, or Q
TLC1543C, I, or Q
TLC1542M
±1
±1
±1
ADDRESS = 1011
ADDRESS = 1100
ADDRESS = 1101
See timing diagrams
512
0
Self-test output code (see Table 3 and Note 9)
1023
t
t
Conversion time
21
µs
µs
conv
21
See timing diagrams
and Note 10
+10 I/O
CLOCK
periods
Total cycle time (access, sample, and conversion)
c
I/O
CLOCK
periods
See timing diagrams
and Note 10
t
Channel acquisition time (sample)
6
acq
t
t
t
t
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Delay time, tenth I/O CLOCK↓ to EOC↓
See Figure 6
See Figure 6
See Figure 7
See Figure 8
10
ns
ns
ns
ns
v
240
240
100
d(I/O-DATA)
d(I/O-EOC)
70
Delay time, EOC↑ to DATA OUT (MSB)
d(EOC-DATA)
†
All typical values are at T = 25°C.
A
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
the electrical specifications are no longer applicable.
– V ); however,
ref–
ref+
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
10
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10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
operating characteristics over recommended operating free-air temperature range,
V
= V
= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) (continued)
CC
ref+
†
TEST CONDITIONS
See Figure 3
See Figure 3
See Figure 8
See Figure 7
See Figure 6
See Figure 6
MIN TYP
MAX
1.3
UNIT
µs
t
t
t
t
t
t
, t
Enable time, CS↓ to DATA OUT (MSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, EOC
PZH PZL
, t
150
300
300
300
300
ns
PHZ PLZ
ns
r(EOC)
f(EOC)
r(DATA)
f(DATA)
Fall time, EOC
ns
Rise time, data bus
ns
Fall time, data bus
ns
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note 11)
t
9
µs
d(I/O-CS)
†
All typical values are at T = 25°C.
A
NOTE 11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
Test Point
Test Point
R
= 2.18 kΩ
R
= 2.18 kΩ
L
L
DATA OUT
EOC
12 kΩ
12 kΩ
C
= 50 pF
C = 100 pF
L
L
Figure 2. Load Circuits
Address
Valid
2 V
2 V
0.8 V
CS
ADDRESS
0.8 V
t
, t
PZH PZL
t
t
, t
h(A)
PHZ PLZ
t
su(A)
2.4 V
0.4 V
90%
10%
I/O CLOCK
DATA
OUT
0.8 V
Figure 3. DATA OUT Enable and Disable
Voltage Waveforms
Figure 4. ADDRESS Setup and Hold TIme
Voltage Waveforms
11
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
2 V
CS
0.8 V
t
su(CS)
t
h(CS)
I/O CLOCK
First
Clock
Last
Clock
0.8 V
0.8 V
Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms
t
t(I/O)
t
t(I/O)
2 V
2 V
0.8 V
I/O CLOCK
0.8 V
0.8 V
I/O CLOCK Period
t
d(I/O-DATA)
t
v
2.4 V
0.4 V
2.4 V
0.4 V
DATA OUT
t
, t
r(DATA) f(DATA)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
10th
0.8 V
Clock
t
d(I/O-EOC)
2.4 V
0.4 V
EOC
t
f(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
t
r(EOC)
2.4 V
EOC
0.4 V
t
d(EOC-DATA)
2.4 V
0.4 V
DATA OUT
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
1
Access Cycle B
Sample Cycle B
Hi-Z State
DATA
OUT
A9
A8
B2
A7
B1
A6
A5
A4
A3
A2
A1
A0
B9
Previous Conversion Data
MSB
LSB
ADDRESS
EOC
B3
MSB
B0
LSB
C3
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS
13
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
1
Access Cycle B
Sample Cycle B
DATA
OUT
A9
A8
B2
A7
A6
A5
A4
A3
A2
A1
A0
B9
Low Level
Previous Conversion Data
MSB
LSB
ADDRESS
EOC
B3
MSB
B1
B0
LSB
C3
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
14
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
See Note B
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
11
16
1
Access Cycle B
Sample Cycle B
Low
Level
Hi-Z
DATA
OUT
A9
A8
B2
A7
B1
A6
A5
A4
A3
A2
A1
A0
B9
Previous Conversion Data
MSB
LSB
ADDRESS
EOC
B3
MSB
B0
LSB
C3
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
15
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Must Be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
14
15
16
1
Access Cycle B
Sample Cycle B
See Note B
DATA
OUT
Low Level
A9
A8
B2
A7
A6
A5
A4
A3
A2
A1
A0
B9
C3
Previous Conversion Data
MSB
LSB
ADDRESS
EOC
B3
MSB
B1
B0
LSB
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The first I/O CLOCK must occur after the rising edge of EOC.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
16
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
11
16
1
See Note B
Access Cycle B
Sample Cycle B
Hi-Z State
Low
Level
DATA
OUT
A9
A8
B2
A7
A6
A5
A4
A3
A2
A1
A0
B9
Previous Conversion Data
MSB
LSB
ADDRESS
EOC
B3
MSB
B1
B0
LSB
C3
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)
17
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
14
15
16
1
Access Cycle B
Sample Cycle B
See Note B
Low Level
See Note C
DATA
OUT
A9
A8
B2
A7
B1
A6
A5
A4
A3
A2
A1
A0
B9
Previous Conversion Data
MSB
LSB
ADDRESS
EOC
B3
MSB
B0
C3
LSB
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
C. The I/O CLOCK sequence is exactly 16 clock pulses long.
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
18
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
APPLICATION INFORMATION
1023
1111111111
1111111110
1111111101
See Notes A and B
1022
1021
V
FS
V
FT
= V
– 1/2 LSB
FS
513
512
1000000001
1000000000
V
ZT
=V
+ 1/2 LSB
ZS
511
0111111111
V
ZS
2
1
0
0000000010
0000000001
0000000000
0
0.0048 0.0096
2.4528 2.4576 2.4624
V – Analog Input Voltage – V
4.9056
4.9104 4.9152
I
NOTES: A. This curve is based on the assumption that V
ref+
and V have been adjusted so that the voltage at the transition from digital 0
ref–
to 1 (V ) is 0.0024 V and the transition to full scale (V ) is 4.908 V. 1 LSB = 4.8 mV.
ZT FT
B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is
FS
ZS
the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
TLC1542/43
15
18
17
1
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS
I/O CLOCK
ADDRESS
3
Control
Circuit
4
Processor
5
16
19
DATA OUT
EOC
6
Analog
Inputs
7
8
9
14
13
5-V DC Regulator
REF+
REF–
11
12
GND
10
To Source
Ground
Figure 16. Serial Interface
19
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:
S
The capacitance charging voltage is given by
–t /R C
c
t i
(1)
V = V 1–e
(
)
C
S
where
R = R + r
i
t
s
The final voltage to 1/2 LSB is given by
V (1/2 LSB) = V – (V /2048)
(2)
C
S
S
Equating equation 1 to equation 2 and solving for time t gives
c
–t /R C
c
t i
V –(V /2048) = V 1–e
(3)
(4)
(
)
S
S
S
and
t (1/2 LSB) = R × C × ln(2048)
c
t
i
Therefore, with the values given the time for the analog input signal to settle is
t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(2048)
(5)
c
s
This time must be less than the converter sample time shown in the timing diagrams.
†
Driving Source
TLC1542/3
R
r
i
s
V
I
V
S
V
C
1 kΩ MAX
C
i
50 pF MAX
V
V
= Input Voltage at A0–A10
= External Driving Source Voltage
I
S
s
R = Source Resistance
r
= Input Resistance
i
C = Equivalent Input Capacitance
i
†
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the
resolution of the converter.
•
R must be real at the input frequency.
s
Figure 17. Equivalent Input Circuit Including the Driving Source
20
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,65
28
M
0,15
0,22
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
14
PINS **
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /D 02/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
21
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
0.610
DIM
0.410
0.510
A MAX
(10,41) (12,95) (15,49)
0.400
0.500
0.600
A MIN
(10,16) (12,70) (15,24)
4040000/D 02/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
0.785
0.910
0.975
(19,94) (19,94) (23,10) (24,77)
C
0.755
(19,18) (19,18)
0.755
0.930
(23,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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