TLC1549C_14 [TI]

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL;


型号：	TLC1549C_14
厂家：	TEXAS INSTRUMENTS
描述：	10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
文件：	总17页 (文件大小：254K)
中文：	中文翻译
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TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

D, JG, OR P PACKAGE

(TOP VIEW)

10-Bit-Resolution A/D Converter

Inherent Sample and Hold

Total Unadjusted Error . . . ±1 LSB Max

On-Chip System Clock

REF+

ANALOG IN

REF–

I/O CLOCK

DATA OUT

Terminal Compatible With TLC549 and

TLV1549

GND

CMOS Technology

FK PACKAGE

(TOP VIEW)

description

The TLC1549C, TLC1549I, and TLC1549M

are 10-bit, switched-capacitor, successive-

2 1 20 19

approximation

analog-to-digital

converters.

I/O CLOCK

ANALOG IN

These devices have two digital inputs and a

3-state output [chip select(CS), input-outputclock

(I/O CLOCK), and data output (DATA OUT)] that

provide a three-wire interface to the serial port of

a host processor.

DATA OUT

REF–

9 10 11 12 13

The sample-and-hold function is automatic. The

converter incorporated in these devices features

differential high-impedance reference inputs that

facilitate ratiometric conversion, scaling, and

isolation of analog circuitry from logic and supply

noise. A switched-capacitor design allows low-

error conversion over the full operating free-air

temperature range.

NC – No internal connection

The TLC1549C is characterized for operation from 0°C to 70°C. The TLC1549I is characterized for operation

from –40°C to 85°C. The TLC1549M is characterized for operation over the full military temperature range of

–55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

CHIP CARRIER

(FK)

CERAMIC DIP

(JG)

PLASTIC DIP

(P)

0°C to 70°C

–40°C to 85°C

–55°C to 125°C

TLC1549CD

TLC1549ID

—

TLC1549CP

TLC1549IP

—

TLC1549MFK

TLC1549MJG

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

functional block diagram

REF+

REF–

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

Output

Data

10-to-1 Data

Selector and

Driver

Sample and

Hold

DATA OUT

ANALOG IN

System Clock,

Control Logic,

and I/O

Counters

I/O CLOCK

Terminal numbers shown are for the D, JG, and P packages only.

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

ANALOG IN

C = 60 pF TYP

(equivalent input

capacitance)

5 MΩ TYP

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

ANALOG IN

Analog signal input. The driving source impedance should be ≤ 1 kΩ. The external driving source to ANALOG IN

should have a current capability ≥ 10 mA.

Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT and

I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high

transition disables I/O CLOCK within a setup time plus two falling edges of the internal system clock.

DATA OUT

This 3-state serial output for the A/D conversion result is in the high-impedance state when CS is high and active

when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to

the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O

CLOCK drives DATAOUT to the logic level corresponding to the next most significant bit, and the remaining bits

are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge

of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks

produce zeroes as the unused LSBs.

GND

Theground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

I/O CLOCK

Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following three functions:

1) On the third falling edge of I/O CLOCK, the analog input voltage begins charging the capacitor array and

continues to do so until the tenth falling edge of I/O CLOCK.

2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

REF+

REF–

The upper reference voltage value (nominally V ) is applied to REF+. The maximum input voltage range is

determined by the difference between the voltage applied to REF+ and the voltage applied to REF–.

The lower reference voltage value (nominally ground) is applied to REF–.

Positive supply voltage

detailed description

With chip select (CS) inactive (high), I/O CLOCK is initially disabled and DATA OUT is in the high impedance

state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O

CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then provides the

I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DATA OUT. I/O CLOCK

receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first ten

I/O clocks provide the control timing for sampling the analog input.

There are six basic serial interface timing modes that can be used with the TLC1549. These modes are

determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a

fast mode with a 10-clock transfer and CS inactive (high) between transfers, (2) a fast mode with a 10-clock

transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)

between transfers, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with

an11-to16-clocktransferandCSinactive(high)betweentransfers, and(6)aslowmodewitha16-clocktransfer

and CS active (low) continuously.

The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and

mode 5, within 21 µs from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the

sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of

I/O CLOCK. Ten bits of data are transmitted to the host serial interface through DATA OUT. The number of serial

clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for

conversion to begin. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the

remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that

can be used, and the timing on which the MSB of the previous conversion appears at the output.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

detailed description

Table 1. Mode Operation

NO. OF

I/O CLOCKS

TIMING

DIAGRAM

†

MODES

MSB AT Terminal 6

Mode 1 High between conversion cycles

Mode 2 Low continuously

CS falling edge

Within 21 µs

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Fast Modes

‡

Mode 3 High between conversion cycles

Mode 4 Low continuously

11 to 16

CS falling edge

Within 21 µs

‡

Mode 5 High between conversion cycles

Mode 6 Low continuously

11 to 16

CS falling edge

Slow Modes

‡

16th clock falling edge

†

‡

This timing also initiates serial interface communication.

No more than 16 clocks should be used.

All the modes require a minimum period of 21 µs after the falling edge of the tenth I/O CLOCK before a new

transfer sequence can begin. During a serial I/O CLOCK data transfer, CS must be active (low) so that I/O

CLOCK is enabled. When CS is toggled between data transfers (modes 1, 3, and 5), the transitions at CS are

recognized as valid only if the level is maintained for a minimum period of 1.425 µs after the transition. If the

transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within

9.5 µs after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with the

host serial interface and CS has to be toggled to restore proper operation.

fast modes

TheTLC1549isinafastmodewhentheserialI/OCLOCKdatatransferiscompletedwithin21µsfromthefalling

edge of the tenth I/O CLOCK. With a ten-clock serial transfer, the device can only run in a fast mode.

mode 1: fast mode, CS inactive (high) between transfers, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The

falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge

of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the internal system

clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After

the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 µs after the falling

edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the

internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. Within 21 µs after

the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

slow modes

In a slow mode, the serial I/O CLOCK data transfer is completed after 21 µs from the falling edge of the tenth

I/O CLOCK.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

mode 5: slow mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables I/O CLOCK within a setup time plus two falling edges of the

internal system clock.

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of

the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the

MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16

clock transfer initiated by the serial interface.

analog input sampling

Sampling of the analog input starts on the falling edge of the third I/O CLOCK, and sampling continues for seven

I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK.

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the S switch and all S switches simultaneously.

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all S and S switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector

looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing

node is greater than the trip point of the threshold detector (approximately one-half V ), a bit 0 is placed in the

output register and the 512-weight capacitor is switched to REF–. If the voltage at the summing node is less

than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains

connected to REF+ through the remainder of the successive-approximation process. The process is repeated

for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

Threshold

Detector

To Output

Latches

512

NODE 512

256

128

REF+

REF–

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.

A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device

returns to the initial state (the contents of the output data register remain at the previous conversion result). Care

should be exercised to prevent CS from being taken low close to completion of conversion because the output

data may be corrupted.

reference voltage inputs

There are two reference inputs used with the TLC1549: REF+ and REF–. These voltage values establish the

upper and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of

REF+, REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with

the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or

higher than REF+ and at zero when the input signal is equal to or lower than REF–.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1): TLC1549C, TLC1549I . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V

TLC1549M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V

Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

+ 0.1 V

Output voltage range, V

Positive reference voltage, V

Negative reference voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

ref+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V

ref–

Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA

Operating free-air temperature range, T : TLC1549C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

TLC1549I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

TLC1549M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to ground with REF– and GND wired together (unless otherwise noted).

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

4.5

5.5

Positive reference voltage, V

(see Note 2)

– V (see Note 2)

ref+

Negative reference voltage, V

ref–

Differential reference voltage, V

2.5

V +0.2

ref+

ref–

Analog input voltage (see Note 2)

High-level control input voltage, V

= 4.5 V to 5.5 V

Low-level control input voltage, V

0.8

2.1

Clock frequency at I/O CLOCK (see Note 3)

1.425

MHz

µs

Setup time, CS low before first I/O CLOCK↑, t

(see Note 4)

su(CS)

Hold time, CS low after last I/O CLOCK↓, t

h(CS)

Pulse duration, I/O CLOCK high, t

190

wH(I/O)

Pulse duration, I/O CLOCK low, t

Transition time, I/O CLOCK, t

wL(I/O)

(see Note 5 and Figure 5)

t(I/O)

Transition time, CS, t

t(CS)

TLC1549C

–40

–55

Operating free-air temperature, T

TLC1549I

°C

TLC1549M

125

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

toREF–convertasallzeros(0000000000).TheTLC1549isfunctionalwithreferencevoltagesdownto1V(V

the electrical specifications are no longer applicable.

–V );however,

ref–

ref+

3. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within

9.5 µs.

4. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

5. This is the time required for the clock input signal to fall from V min to V max or to rise from V max to V min. In the vicinity of

normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,

= V

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)

ref+

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

= 4.5 V,

= –1.6 mA

= –20 µA

= 1.6 mA

= 20 µA

2.4

High-level output voltage

= 4.5 V to 5.5 V,

= 4.5 V,

–0.1

0.4

0.1

Low-level output voltage

= 4.5 V to 5.5 V,

= V

= 0,

CS at V

Off-state (high-impedance-state) output current

µA

CS at V

–10

2.5

–2.5

2.5

High-level input current

Low-level input current

Operating supply current

V = V

I CC

0.005

–0.005

0.8

µA

V = 0

CS at 0 V

V = V

Analog input leakage current

µA

V = 0

–1

Maximum static analog reference

current into REF+

ref+

= V

V = GND

ref–

TLC1549C, I (Analog) During sample cycle

TLC1549M (Analog) During sample cycle

TLC1549C, I (Control)

TLC1549M (Control)

= 5 V, T = 25°C.

Input capacitance

†

All typical values are at V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,

= V = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz

ref+

PARAMETER

Linearity error (see Note 6)

TEST CONDITIONS

MIN

MAX

±1

UNIT

LSB

µs

Zero-scale error (see Note 7)

Full-scale error (see Note 7)

Total unadjusted error (see Note 8)

Conversion time

See Note 2

±1

See Figures 6–10

conv

See Figures 6–10,

See Note 9

+10 I/O

CLOCK

periods

Total cycle time (access, sample, and conversion)

µs

Valid time, DATA OUT remains valid after I/O CLOCK↓

Delay time, I/O CLOCK↓ to DATA OUT valid

Enable time, CS↓ to DATA OUT (MSB driven)

Disable time, CS↑ to DATA OUT (high impedance)

Rise time, data bus

See Figure 5

See Figure 3

See Figure 5

µs

240

1.3

d(I/O-DATA)

, t

PZH PZL

, t

180

300

PHZ PLZ

r(bus)

f(bus)

Fall time, data bus

Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion

(see Note10)

µs

d(I/O-CS)

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

toREF–convertasallzeros(0000000000).TheTLC1549isfunctionalwithreferencevoltagesdownto1V(V

the electrical specifications are no longer applicable.

–V );however,

ref–

ref+

6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference

between 1111111111 and the converted output for full-scale input voltage.

8. Total unadjusted error comprises linearity, zero, and full-scale errors.

9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven

I/O CLOCK periods, and ends on the falling edge of the 10th I/O CLOCK (see Figure 5).

10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of

the internal clock (1.425 µs) after the transition.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

Test Point

= 2.18 kΩ

DATA OUT

12 kΩ

= 100 pF

Figure 2. Load Circuit

2 V

0.8 V

, t

PZH PZL

, t

PHZ PLZ

2.4 V

0.4 V

90%

10%

DATA

OUT

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

2 V

0.8 V

su(CS)

h(CS)

I/O CLOCK

First

Clock

Last

Clock

0.8 V

Figure 4. CS to I/O CLOCK Voltage Waveforms

t(I/O)

2 V

0.8 V

2 V

0.8 V

I/O CLOCK

0.8 V

I/O CLOCK Period

d(I/O-DATA)

2.4 V

0.4 V

2.4 V

0.4 V

DATA OUT

, t

r(bus) f(bus)

Figure 5. I/O CLOCK and DATA OUT Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

(see Note A)

I/O

CLOCK

Sample Cycle B

Hi-Z State

DATA

OUT

A/D

Previous Conversion Data

Conversion

Interval

(≤ 21 µs)

MSB

Initialize

LSB

Initialize

Figure 6. Timing for 10-Clock Transfer Using CS

Must Be High on Power Up

(see Note A)

I/O

CLOCK

Sample Cycle B

See Note C

DATA

OUT

Low Level

Previous Conversion Data

A/D Conversion

Interval

MSB

LSB

(≤ 21 µs)

Initialize

Figure 7. Timing for 10-Clock Transfer Not Using CS

See Note B

(see Note A)

I/O

CLOCK

Sample Cycle B

Low

Level

Hi-Z

DATA

OUT

A/D

Conversion

Interval

(≤ 21 µs)

Previous Conversion Data

MSB

Initialize

LSB

Initialize

Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

Must Be High on Power Up

(see Note A)

I/O

CLOCK

Sample Cycle B

See Note C

DATA

OUT

Low Level

A/D Conversion

Interval

Previous Conversion Data

MSB

Initialize

LSB

(≤ 21 µs)

Initialize

Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21 µs)

(see Note A)

I/O

CLOCK

See Note B

Sample Cycle B

Hi-Z State

Low

Level

DATA

OUT

Previous Conversion Data

A/D

Conversion

MSB

LSB

Interval

Initialize

(≤ 21 µs)

Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21 µs)

Must Be High on Power Up

(see Note A)

I/O

CLOCK

Sample Cycle B

See Note B

Low Level

See Note C

DATA

OUT

Previous Conversion Data

MSB

LSB

A/D Conversion Interval

(≤ 21 µs)

Initialize

Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21 µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

APPLICATION INFORMATION

1023

1022

1021

1111111111

1111111110

1111111101

See Notes A and B

= V

– 1/2 LSB

513

512

1000000001

1000000000

+ 1/2 LSB

511

0111111111

0000000010

0000000001

0000000000

0.0048 0.0096

2.4528 2.4576 2.4624

V – Analog Input Voltage – V

4.9056

4.9104 4.9152

NOTES: A. This curve is based on the assumption that V

ref+

and V have been adjusted so that the voltage at the transition from digital 0

ref–

to 1 (V ) is 0.0024 V and the transition to full scale (V ) is 4.908 V. 1 LSB = 4.8 mV.

ZT FT

B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is

the step whose nominal midstep value equals zero.

Figure 12. Ideal Conversion Characteristics

TLC1549

Analog Input

ANALOG IN

I/O CLOCK

Control

Circuit

Processor

DATA OUT

5-V DC Regulated

REF+

REF–

GND

To Source

Ground

Figure 13. Typical Serial Interface

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 V to

V within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

–t R C

(1)

(2)

1–e

where

R = R + r

The final voltage to 1/2 LSB is given by

V (1/2 LSB) = V – (V /2048)

Equating equation 1 to equation 2 and solving for time t gives

–t R C

2048

1–e

(3)

(4)

and

t (1/2 LSB) = R × C × ln(2048)

Therefore, with the values given the time for the analog input signal to settle is

t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(2048)

(5)

This time must be less than the converter sample time shown in the timing diagrams.

†

Driving Source

TLC1549

1 kΩ MAX

50 pF MAX

= Input Voltage at ANALOG IN

= External Driving Source Voltage

R = Source Resistance

= Input Resistance

C = Input Capacitance

†

Driving source requirements:

•

Noise and distortion for the source must be equivalent to the

resolution of the converter.

•

R must be real at the input frequency.

Figure 14. Equivalent Input Circuit Including the Driving Source

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

TLC1549CD

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

C1549C

TLC1549CDG4

TLC1549CDR

TLC1549CDRG4

TLC1549CP

ACTIVE

Green (RoHS

& no Sb/Br)

C1549C

2500

Green (RoHS

& no Sb/Br)

C1549C

Green (RoHS

& no Sb/Br)

C1549C

Green (RoHS

& no Sb/Br)

TLC1549CP

C1549I

TLC1549CPE4

TLC1549ID

Green (RoHS

& no Sb/Br)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

TLC1549IDG4

TLC1549IDR

TLC1549IDRG4

TLC1549IP

Green (RoHS

& no Sb/Br)

C1549I

2500

Green (RoHS

& no Sb/Br)

C1549I

Green (RoHS

& no Sb/Br)

C1549I

Green (RoHS

& no Sb/Br)

TLC1549IP

TLC1549IPE4

Green (RoHS

& no Sb/Br)

N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TLC1549C_14 [TI]

相关型号：

TLC1549I

TLC1549ID

TLC1549IDG4

TLC1549IDR

TLC1549IDRG4

TLC1549IP

TLC1549IPE4

TLC1549M

TLC1549MFK

TLC1549MFKR

TLC1549MJG

TLC154D