TLC2264A-Q1 [TI]
Advanced LinCMOS⢠RAIL-TO-RAIL OPERATIONAL ANPLIFIERS; 高级LinCMOSâ ?? ¢轨到轨运算ANPLIFIERS
| 型号： | TLC2264A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Advanced LinCMOS⢠RAIL-TO-RAIL OPERATIONAL ANPLIFIERS |
| 文件： | 总37页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
D
Qualified for Automotive Applications
D
D
D
Low Power . . . 500 µA Max
Common-Mode Input Voltage Range
Includes Negative Rail
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Low Input Offset Voltage
D
D
D
D
Output Swing includes Both Supply Rails
Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
950 µV Max at T = 25°C (TLC2262A)
A
D
Macromodel Included
D
Performance Upgrade for the TS27M2/M4
and TLC27M2/M4
Fully Specified for Both Single-Supply and
Split-Supply Operation
EQUIVALENT INPUT NOISE VOLTAGE
description
vs
FREQUENCY
The TLC2262 and TLC2264 are dual and
60
quadruple operational amplifiers from Texas
Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLC226x family offers a compromise between the
micropower TLC225x and the ac performance of
the TLC227x. It has low supply current for
battery-powered applications, while still having
adequate ac performance for applications that
demand it. The noise performance has been
dramatically improved over previous generations
of CMOS amplifiers. Figure 1 depicts the low level
of noise voltage for this CMOS amplifier, which
has only 200 µA (typ) of supply current per
amplifier.
V
R
T
A
= 5 V
= 20 Ω
= 25°C
DD
S
50
40
30
20
10
0
The TLC226x, exhibiting high input impedance
and low noise, are excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the micro-
power dissipation levels, these devices work well
in hand-held monitoring and remote-sensing
2
3
4
10
10
10
10
f − Frequency − Hz
Figure 1
applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great
choice when interfacing with analog-to-digital converters (ADCs). For precision applications, the TLC226xA
family is available and has a maximum input offset voltage of 950 µV. This family is fully characterized at 5 V
and 5 V.
The TLC2262/4 also makes great upgrades to the TLC27M2/L4 or TS27M2/L4 in standard designs. They offer
increased output dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set
allows them to be used in a wider range of applications. For applications that require higher output drive and
wider input voltage range, see the TLV2432 and TLV2442. If your design requires single amplifiers, please see
the TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package.
Their small size and low power consumption, make them ideal for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
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Copyright 2008 Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
†
ORDERING INFORMATION
V
max
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
IO
}
T
PACKAGE
A
AT 25°C
950 µV
2.5 mV
950 µV
2.5 mV
950 µV
2.5 mV
950 µV
2.5 mV
§
SOIC (D)
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
TLC2262AQDRQ1
2262AQ1
§
SOIC (D)
TLC2262QDRQ1
TLC2262AQPWRQ1
2262Q1
2262AQ1
2262Q1
2264AQ1
2264Q1
2264AQ1
2264Q1
§
TSSOP (PW)
TSSOP (PW)
SOIC (D)
§
TLC2262QPWRQ1
TLC2264AQDRQ1
TLC2264QDRQ1
−40°C to 125°C
SOIC (D)
TSSOP (PW)
TSSOP (PW)
TLC2264AQPWRQ1
TLC2264QPWRQ1
†
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Product Preview.
‡
§
TLC2262, TLC2262A
D OR PW PACKAGE
(TOP VIEW)
TLC2264, TLC2264A
D OR PW PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
V
DD+
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
2OUT
2IN−
2IN+
V
/GND
DD−
V
V
/GND
DD+
DD−
2IN+
2IN−
2OUT
3IN+
3IN−
3OUT
8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
equivalent schematic (each amplifier)
V
DD+
Q3
Q6
Q9
Q12
Q14
Q16
IN+
IN−
OUT
C1
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
R3
Q5
R4
Q7
Q8
Q10
Q11
R1
R2
V
DD−/GND
†
ACTUAL DEVICE COMPONENT COUNT
COMPONENT
Transistors
TLC2262
TLC2264
38
28
9
76
56
18
6
Resistors
Diodes
Capacitors
3
†
Includes both amplifiers and all ESD, bias, and trim circuitry
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V
DD+
DD−
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
ID
Input voltage, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
− 0.3 V to V
I
DD−
DD+
Input current, I (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
DD+
DD−
Total current out of V
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or PW package . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V
and V .
DD+
DD −
2. Differential voltages are at IN+ with respect to IN−. Excessive current flows if input is brought below V
− 0.3 V.
DD−
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D−8
D−14
725 mW
5.8 mW/°C
7.6 mW/°C
6.0 mW/°C
464 mW
377 mW
145 mW
950 mW
608 mW
494 mW
190 mW
PW−14
750 mW
480 mW
389 mW
150 mW
recommended operating conditions
MIN
MAX
UNIT
Supply voltage, V
DD
2.2
8
V
V
Input voltage range, V
V
V
V
V
−1.5
−1.5
I
DD−
DD+
Common-mode input voltage, V
IC
V
DD−
−40
DD+
125
Operating free-air temperature, T
°C
A
4
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLC2262-Q1
TLC2262A-Q1
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
300 2500
3000
MIN
TYP MAX
25°C
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
α
VIO
Full range
5
5
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
=
2.5 V,
V
R
= 0,
= 50 Ω
S
DD
= 0,
IC
25°C
0.003
0.003
0.5
µV/mo
O
25°C
125°C
25°C
0.5
800
1
I
I
Input offset current
Input bias current
pA
pA
IO
800
800
1
IB
125°C
800
−0.3
to 4.2
−0.3
to 4.2
25°C
0 to 4
0 to 4
Common-mode input
voltage range
V
R
= 50 Ω,
|V | ≤5 mV
IO
V
V
ICR
OH
S
0 to
3.5
0 to
3.5
Full range
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
OH
4.85
4.82
4.7
4.85
4.82
4.7
= −100 µA
High-level output
voltage
OH
Full range
25°C
V
4.85
4.85
I
= −400 µA
= 2.5 V,
OH
Full range
25°C
4.5
4.5
V
I
I
= 50 µA
0.01
0.01
0.09
IC
IC
OL
25°C
0.09
0.8
0.15
0.15
1
0.15
0.15
1
V
= 2.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
V
V
OL
0.7
170
550
V
IC
= 2.5 V,
I
= 4 mA
OL
Full range
25°C
1.2
1.2
80
50
100
80
50
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
550
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
240
83
240
83
25°C
Full range
25°C
70
70
80
80
70
70
80
80
Common-mode
rejection ratio
V
R
= 0 to 2.7 V,
= 50 Ω
V
= 2.5 V,
O
IC
S
CMRR
dB
95
95
Supply-voltage rejection
V
V
= 4.4 V to 16 V,
DD
IC
k
dB
SVR
ratio (∆V
DD
/∆V
IO
)
= V
/2,
No load
Full range
25°C
DD
400
500
500
400
500
500
I
Supply current
V
O
= 2.5 V,
No load
µA
DD
Full range
†
‡
Full range is −40°C to 125°C for Q suffix.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC2262-Q1
TLC2262A-Q1
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX MIN
TYP
MAX
0.35
0.55
0.35
0.55
25°C
‡
Slew rate at unity
gain
V
C
= 0.5 V to 3.5 V,
‡
= 100 pF
R
= 50 kΩ ,
O
L
L
SR
V/µs
Full
range
0.25
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
40
12
40
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.3
0.7
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.017%
0.03%
0.017%
0.03%
O
V
f = 20 kHz,
THD + N
‡
A
V
= 10
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.82
185
0.82
185
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
V
= 1,
O(PP)
L
B
OM
‡
‡
C = 100 pF
L
A
= −1,
V
To 0.1%
6.4
6.4
Step = 0.5 V to 2.5 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
14.1
14.1
‡
Phase margin at
unity gain
φ
m
25°C
25°C
56°
56°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is −40°C to 125°C for Q suffix.
Referenced to 2.5 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂ ꢃꢃ ꢄꢅ ꢊꢆ ꢇ ꢈ
ꢛ
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ꢎ
ꢏ
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ꢁ
ꢑ
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ꢕꢊꢖ ꢁꢆ ꢀꢓ ꢆꢕ ꢊ ꢖꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLC2262-Q1
TLC2262A-Q1
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP
MAX
2500
3000
MIN
TYP
MAX
950
25°C
300
300
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient of
input offset voltage
α
Full range
5
5
µV/°C
µV/mo
VIO
Input offset voltage long-
term drift (see Note 4)
V
R
= 0,
= 50 Ω
V
O
= 0,
IC
S
25°C
0.003
0.5
0.003
0.5
25°C
125°C
25°C
I
I
Input offset current
Input bias current
pA
pA
IO
800
800
800
800
1
1
IB
125°C
−5
to 4
−5.3
to 4
−5
−5.3
25°C
to 4 to 4.2
Common-mode input
voltage range
V
R
= 50 Ω,
|V | ≤ 5 mV
IO
V
V
ICR
S
−5
to 3.5
−5
to 3.5
Full range
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
O
4.85
4.82
4.7
4.85
4.82
4.7
= −100 µA
Maximum positive peak
output voltage
O
Full range
25°C
V
OM+
4.85
4.85
I
O
= −400 µA
Full range
25°C
4.5
4.5
V
= 0,
= 0,
I
I
= 50 µA
−4.99
−4.99
IC
IC
O
25°C
−4.85 −4.91
−4.85 −4.91
−4.85
V
= 500 µA
Maximum negative peak
output voltage
O
Full range −4.85
V
OM−
V
25°C
Full range
25°C
−4
−3.8
80
−4.3
200
−4
−3.8
80
−4.3
V
= 0,
I
O
= 4 mA
IC
O
200
R
R
= 50 kΩ
= 1 MΩ
Large-signal differential
voltage amplification
L
L
Full range
25°C
50
50
A
VD
V
=
4 V
V/mV
1000
1000
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
P package
= 10
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
220
88
220
88
25°C
Full range
25°C
75
75
80
80
75
75
80
80
Common-mode
rejection ratio
V
V
= −5 V to 2.7 V,
= 0,
IC
O
CMRR
dB
R = 50 Ω
S
95
95
Supply-voltage rejection
V
DD
V
IC
= 4.4 V to 16 V,
k
dB
SVR
ratio (∆V
DD
/∆V
IO
)
= V
/2, No load
Full range
25°C
DD
425
500
500
425
500
500
I
Supply current
V
O
= 0,
No load
µA
DD
Full range
†
Full range is −40°C to 125°C for Q suffix.
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇꢈꢉ ꢀ ꢁ ꢂꢃ ꢃ ꢄ ꢅ ꢊꢆꢇ ꢈ
ꢛ
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ꢋ
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ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
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ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
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ꢕꢊ ꢖ ꢁꢆꢀꢓ ꢆꢕꢊꢖ ꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2262 operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC2262-Q1
TLC2262A-Q1
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX MIN
TYP
MAX
25°C 0.35
0.55
0.35
0.55
Slew rate at unity
gain
V
C
=
2 V,
R
= 50 kΩ,
L
O
L
SR
V/µs
Full
= 100 pF
0.25
0.25
range
f = 10 Hz
f = 1 kHz
25°C
25°C
43
12
43
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.8
1.3
0.8
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA√Hz
n
Total harmonic
distortion plus
noise
V
=
2.3 V,
R = 50 kΩ,
L
A
= 1
0.014%
0.024%
0.014%
0.024%
O
V
THD + N
A
V
= 10
f = 20 kHz
Gain-bandwidth
product
f =10 kHz,
R
= 50 kΩ,
L
25°C
25°C
0.73
85
0.73
85
MHz
kHz
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 4.6 V,
A
= 1,
= 100 pF
L
O(PP)
= 50 kΩ,
V
B
OM
C
L
A
= −1,
V
To 0.1%
7.1
7.1
Step = −2.3 V to 2.3 V,
R
C
t
s
Settling time
25°C
µs
= 50 kΩ,
= 100 pF
L
L
To 0.01%
16.5
16.5
Phase margin at
unity gain
φ
m
25°C
25°C
57°
57°
R
= 50 kΩ,
C = 100 pF
L
L
Gain margin
11
11
dB
†
Full range is −40°C to 125°C for Q suffix.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋ
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ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
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ꢕꢊꢖ ꢁꢆ ꢀꢓ ꢆꢕ ꢊ ꢖꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLC2264-Q1
TLC2264A-Q1
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
300 2500
3000
MIN
TYP MAX
25°C
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
α
VIO
Full range
2
2
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
=
2.5 V,
V
R
= 0,
= 50 Ω
S
DD
= 0,
IC
25°C
0.003
0.003
0.5
µV/mo
O
25°C
125°C
25°C
0.5
800
1
I
I
Input offset current
Input bias current
pA
pA
IO
800
800
1
IB
125°C
800
−0.3
to 4 to 4.2
0
0
−0.3
to 4 to 4.2
25°C
Common-mode input
voltage range
V
R
= 50 Ω,
|V | ≤5 mV
IO
V
V
ICR
OH
S
0
0
Full range
to 3.5
to 3.5
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
OH
4.85
4.82
4.7
4.85
4.82
4.7
= −100 µA
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
4.85
4.85
I
= −400 µA
= 2.5 V,
OH
Full range
25°C
4.5
4.5
V
I
I
= 50 µA
0.01
0.09
0.01
0.09
IC
IC
OL
25°C
0.15
0.15
1
0.15
0.15
1
V
= 2.5 V,
= 500 µA
OL
Full range
25°C
V
V
OL
0.8
100
550
0.7
170
550
V
IC
= 2.5 V,
I
= 4 mA
OL
Full range
25°C
1.2
1.2
80
50
80
50
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
N package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
240
83
240
83
25°C
70
70
70
70
Common-mode rejection
ratio
V
R
= 0 to 2.7 V,
= 50 Ω
V
O
= 2.5 V,
IC
S
CMRR
dB
dB
Full range
Supply-voltage rejection
k
25°C
80
95
80
95
SVR
ratio (∆V
DD
/∆V )
IO
V
DD
= 4.4 V to 16 V,
25°C
0.8
1
1
0.8
1
1
Supply current
(four amplifiers)
I
V
O
= 2.5 V,
No load
mA
DD
Full range
†
‡
Full range is −40°C to 125°C for Q suffix.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢊ
ꢆ
ꢇ
ꢈ
ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
ꢎ
ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
ꢒ
ꢓ
ꢔ
ꢕ
ꢊ
ꢖ
ꢁ
ꢆ
ꢀ
ꢓ
ꢆ
ꢕ
ꢊ
ꢖ
ꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC2264-Q1
TLC2264A-Q1
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX MIN TYP MAX
0.35
0.55
0.35
0.25
0.55
25°C
‡
Slew rate at unity
gain
V
= 0.5 V to 3.5 V,
R
= 50 kΩ ,
L
O
SR
V/µs
Full
range
‡
C = 100 pF
L
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
40
12
40
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.3
0.7
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.017%
0.03%
0.017%
0.03%
O
V
f = 20 kHz,
THD + N
‡
A
V
= 10
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.71
185
0.71
185
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
V
= 1,
O(PP)
L
B
OM
‡
‡
C = 100 pF
L
A
= −1,
V
To 0.1%
6.4
6.4
Step = 0.5 V to 2.5 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
14.1
14.1
‡
Phase margin at
unity gain
φ
m
25°C
25°C
56°
56°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is −40°C to 125°C for Q suffix.
Referenced to 2.5 V
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂ ꢃꢃ ꢄꢅ ꢊꢆ ꢇ ꢈ
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ꢂ
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ꢁ
ꢆ
ꢀ
ꢓ
ꢆ
ꢕ
ꢊ
ꢖ
ꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLC2264-Q1
TLC2264A-Q1
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
300 2500
3000
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient of
input offset voltage
α
VIO
Full range
2
2
µV/°C
Input offset voltage
long-term drift (see Note 4)
V
R
= 0,
= 50 Ω
V
O
= 0,
IC
S
25°C
0.003
0.003
0.5
µV/mo
25°C
125°C
25°C
0.5
1
I
I
Input offset current
Input bias current
pA
pA
IO
800
800
800
800
1
IB
125°C
−5
−5.3
−5
−5.3
25°C
to 4 to 4.2
to 4 to 4.2
Common-mode input
voltage range
R
= 50 Ω,
IO
S
V
V
V
ICR
|V | ≤5 mV
−5
to 3.5
−5
to 3.5
Full range
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
O
4.85
4.82
4.7
4.85
4.82
4.7
= −100 µA
Maximum positive peak
output voltage
O
Full range
25°C
V
OM+
4.85
4.85
I
O
= −400 µA
Full range
25°C
4.5
4.5
V
= 0,
= 0,
I
I
= 50 µA
−4.99
−4.99
IC
IC
O
25°C
−4.85 −4.91
−4.85 −4.91
−4.85
V
= 500 µA
Maximum negative peak
output voltage
O
Full range −4.85
V
OM−
V
25°C
Full range
25°C
−4
−3.8
80
−4.3
200
−4
−3.8
80
−4.3
V
= 0,
I
O
= 4 mA
IC
O
200
R
R
= 50 kΩ
= 1 MΩ
Large-signal differential
voltage amplification
L
L
Full range
25°C
50
50
A
VD
V
=
4 V
V/mV
1000
1000
12
10
12
10
r
r
Differential input resistance
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
25°C
25°C
25°C
Common-mode input
capacitance
c
z
f = 10 kHz,
N package
8
8
pF
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
220
88
220
88
Ω
V
V
V
V
= −5 V to 2.7 V,
25°C
Full range
25°C
75
75
80
80
75
75
80
80
Common-mode
rejection ratio
IC
CMRR
dB
dB
= 0,
R
= 50 Ω
O
S
=
ā2.2 V to ā8 V,
95
95
Supply-voltage rejection
DD
k
SVR
ratio (∆V
DD
/∆V )
IO
= V
/2, No load
Full range
25°C
IC
O
DD
0.85
1
1
0.85
1
1
Supply current
(four amplifiers)
I
V
= 0,
No load
mA
DD
Full range
†
Full range is −40°C to 125°C for Q suffix.
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇꢈꢉ ꢀ ꢁ ꢂꢃ ꢃ ꢄ ꢅ ꢊꢆꢇ ꢈ
ꢛ
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ꢋ
ꢌ
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ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
ꢎ
ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
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ꢕ
ꢊ
ꢖ
ꢁ
ꢆ
ꢀ
ꢓ
ꢆ
ꢕ
ꢊ
ꢖ
ꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TLC2264 operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC2264-Q1
TLC2264A-Q1
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX MIN
TYP
MAX
25°C
0.35
0.55
0.35
0.55
Slew rate at unity
gain
V
=
2 V,
C = 100 pF
L
R
= 50 kΩ,
L
O
SR
V/µs
Full
range
0.25
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
43
12
43
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.8
1.3
0.8
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
R
=
2.3 V,
A
= 1
0.014%
0.024%
0.014%
0.024%
O
V
= 50 kΩ,
THD + N
L
A
V
= 10
f = 20 kHz
Gain-bandwidth
product
f =10 kHz,
R
= 50 kΩ,
L
25°C
25°C
0.73
70
0.73
70
MHz
kHz
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 4.6 V,
A
= 1,
= 100 pF
L
O(PP)
= 50 kΩ,
V
B
OM
C
L
A
= −1,
V
To 0.1%
7.1
7.1
Step = −2.3 V to 2.3 V,
R
C
t
s
Settling time
25°C
µs
= 50 kΩ,
= 100 pF
L
L
To 0.01%
16.5
16.5
Phase margin at
unity gain
φ
m
25°C
25°C
57°
57°
R
= 50 kΩ,
C = 100 pF
L
L
Gain margin
11
11
dB
†
Full range is −40°C to 125°C for Q suffix.
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution
vs Common-mode input voltage
2 − 5
V
Input offset voltage
IO
6, 7
8 − 11
12
α
VIO
Input offset voltage temperature coefficient
Input bias and input offset currents
Distribution
I
/I
vs Free-air temperature
IB IO
vs Supply voltage
vs Free-air temperature
13
14
V
I
Input voltage range
V
V
V
V
V
High-level output voltage
vs High-level output current
vs Low-level output current
vs Output current
15
16, 17
18
OH
Low-level output voltage
OL
Maximum positive output voltage
Maximum negative output voltage
Maximum peak-to-peak output voltage
OM+
OM−
O(PP)
vs Output current
19
vs Frequency
20
vs Supply voltage
vs Free-air temperature
21
22
I
Short-circuit output current
OS
V
O
Output voltage
Differential gain
vs Differential input voltage
vs Load resistance
23, 24
25
vs Frequency
vs Free-air temperature
26, 27
28, 29
A
Large-signal differential voltage amplification
Output impedance
VD
z
vs Frequency
30, 31
o
vs Frequency
vs Free-air temperature
32
33
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36
k
Supply-voltage rejection ratio
Supply current
SVR
vs Supply voltage
vs Free-air temperature
37, 38
39, 40
I
DD
vs Load capacitance
vs Free-air temperature
41
42
SR
Slew rate
Inverting large-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Voltage-follower small-signal pulse response
Equivalent input noise voltage
43, 44
45, 46
47, 48
49, 50
51, 52
53
V
V
O
vs Frequency
n
Noise voltage (referred to input)
Over a 10-second period
vs Frequency
Integrated noise voltage
54
THD + N
Total harmonic distortion plus noise
vs Frequency
55
vs Supply voltage
vs Free-air temperature
56
57
Gain-bandwidth product
vs Frequency
vs Load capacitance
26, 27
58
φ
m
Phase margin
Gain margin
vs Load capacitance
59
B
1
Unity-gain bandwidth
vs Load capacitance
vs Load capacitance
60
61
Overestimation of phase margin
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2262
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2262
INPUT OFFSET VOLTAGE
25
20
15
25
20
15
1274 Amplifiers From 2 Wafer Lots
1274 Amplifiers From 2 Wafer Lots
V
T
=
2.5 V
V
DD
=
5 V
T = 25°C
A
DD
= 25°C
A
10
5
10
5
0
−1.6
0
−1.6
−0.8
0
0.8
1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 2
Figure 3
DISTRIBUTION OF TLC2264
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2264
INPUT OFFSET VOLTAGE
20
16
12
20
2272 Amplifiers From 2 Wafer Lots
2272 Amplifiers From 2 Wafer Lots
V
T
=
2.5 V
V
T
=
5 V
DD
DD
= 25°C
= 25°C
A
A
16
12
8
8
4
0
4
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 4
Figure 5
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
1
V
R
T
= 5 V
= 50 Ω
= 25°C
V
= 5 V
= 50 Ω
= 25°C
DD
S
A
DD
S
R
T
A
0.5
0.5
0
0
−0.5
−1
−0.5
−1
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
−1
0
1
2
3
4
5
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
†
For curves where V
= 5 V, all loads are referenced to 2.5 V.
DD
Figure 6
Figure 7
DISTRIBUTION OF TLC2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
†
†
30
25
20
15
10
5
30
25
20
15
10
5
128 Amplifiers From 2 Wafer Lots
128 Amplifiers From 2 Wafer Lots
V
=
2.5 V
P Package
= 25°C to 125°C
V
DD
=
5 V
P Package
T = 25°C to 125°C
A
DD
T
A
0
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
α
α
− Temperature Coefficient − µV/°C
− Temperature Coefficient − µV/°C
VIO
VIO
Figure 8
Figure 9
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
†
†
35
30
25
20
15
10
35
30
25
20
15
10
128 Amplifiers From
2 Wafer Lots
128 Amplifiers From
2 Wafer Lots
V
=
5 V
N Package
= 25°C
V
=
2.5 V
N Package
= 25°C to 125°C
DD
DD
T
A
T
A
to 125°C
5
0
5
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
α
VIO
− Temperature Coefficient of
Input Offset Voltage − µV/°C
α
VIO
− Temperature Coefficient of
Input Offset Voltage − µV/°C
Figure 10
Figure 11
†
INPUT BIAS AND INPUT OFFSET CURRENTS
INPUT VOLTAGE RANGE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
450
400
350
300
250
200
150
100
50
10
V
V
V
= 2.5 V
= 0 V
= 0
DD
IC
O
R
T
A
= 50 Ω
= 25°C
S
8
6
R
= 50 Ω
S
4
2
I
IB
0
| V | ≤ 5 mV
IO
−2
−4
−6
−8
I
IO
−10
0
25
45
65
85
105
125
2
3
4
5
6
7
8
T
A
− Free-Air Temperature − °C
| V
DD
| − Supply Voltage − V
Figure 12
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†‡
INPUT VOLTAGE RANGE
vs
†‡
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
5
4
3
2
1
6
5
4
3
V
DD
= 5 V
V
= 5 V
DD
T
A
= 125°C
= 25°C
T
= −55°C
A
| V | ≤5 mV
IO
T
A
2
1
0
T
A
= −40°C
0
−1
−75 −55 −35 −15
5
25 45 65 85 105 125
0
500
1000 1500 2000 2500 3000 3500
T
A
− Free-Air Temperature − °C
|I
OH
| − High-Level Output Current − µA
Figure 14
Figure 15
†‡
‡
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
1.4
1.2
1.2
1
V
V
= 5 V
DD
= 2.5 V
V
T
A
= 5 V
= 25°C
DD
IC
T
A
= 125°C
V
= 1.25 V
IC
V
= 0
IC
1
0.8
0.6
0.4
0.8
0.6
0.4
0.2
0
T
= 25°C
A
V
= 2.5 V
IC
T
= −40°C
A
T
A
= −55°C
0.2
0
0
1
2
3
4
5
6
0
1
2
3
4
5
I − Low-Level Output Current − mA
OL
I
− Low-Level Output Current − mA
OL
Figure 16
Figure 17
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For curves where V = 5 V, all loads are referenced to 2.5 V.
DD
17
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ꢄ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†
MAXIMUM POSITIVE OUTPUT VOLTAGE
†
MAXIMUM NEGATIVE OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
−3.8
−4
6
V
V
= 5 V
DD
= 0
V
= 5 V
DD
IC
5
4
3
T
A
= −55°C
T
A
= 125°C
−4.2
−4.4
T
A
= 25°C
T
A
= 125°C
T
= −40°C
A
T
A
= −55°C
T
A
= 25°C
−4.6
−4.8
−5
2
1
0
T
A
= −40°C
0
1
2
3
4
5
6
0
500
1000 1500 2000 2500 3000 3500
I
O
− Output Current − mA
| I | − Output Current − µA
O
Figure 19
Figure 18
SHORT-CIRCUIT OUTPUT CURRENT
†‡
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
FREQUENCY
12
10
9
R
T
= 10 kΩ
= 25°C
L
A
V
= 5 V
DD
10
8
V
ID
= −100 mV
8
7
6
V
T
A
= 0
= 25°C
6
4
2
0
O
V
DD
= 5 V
5
4
3
2
V
ID
= 100 mV
−2
−4
1
0
2
3
4
5
6
7
8
3
10
4
5
10
6
10
10
| V
DD
| − Supply Voltage − V
f − Frequency − Hz
‡
For curves where V
DD
= 5 V, all loads are referenced to 2.5 V.
Figure 20
Figure 21
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†
SHORT-CIRCUIT OUTPUT CURRENT
‡
OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL INPUT VOLTAGE
13
12
11
10
9
5
4
3
2
V
V
= 0
V
R
= 5 V
= 50 kΩ
= 2.5 V
O
DD
L
=
5 V
DD
V
T
IC
A
= 25°C
V
ID
= −100 mV
8
7
1
0
−1
−2
V
ID
= 100 mV
1
0
−3
−4
−75 −50
−25
0
25
50
75 100 125
0
250 500 750 1000
−1000 −750 −500 −250
T
A
− Free-Air Temperature − °C
V
ID
− Differential Input Voltage − µV
Figure 22
Figure 23
‡
DIFFERENTIAL GAIN
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
vs
LOAD RESISTANCE
4
10
5
3
V
V
= 5 V
DD
= 0 V
V
T
= 2 V
O(PP)
IC
= 25°C
R
T
= 50 kΩ
= 25°C
A
L
A
3
V
DD
=
5 V
DD
10
10
1
V
= 5 V
2
−1
10
−3
−5
1
10
3
4
10
5
10
6
10
0
250 500 750 1000
−1000 −750 −500 −250
R
− Load Resistance − kΩ
L
V
ID
− Differential Input Voltage − µV
Figure 24
Figure 25
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For curves where V = 5 V, all loads are referenced to 2.5 V.
DD
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
180°
135°
V
= 5 V
DD
C = 100 pF
L
T
A
= 25°C
40
90°
45°
Phase Margin
20
0
Gain
0°
−20
−40
−45°
−90°
3
4
5
6
7
10
10
10
10
10
f − Frequency − Hz
†
For curves where V
DD
= 5 V, all loads are referenced to 2.5 V.
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
180°
135°
V
C
T
A
= 5 V
= 100 pF
= 25°C
DD
L
40
20
90°
45°
Phase Margin
Gain
0
−20
−40
0°
−45°
−90°
3
4
5
6
7
10
10
10
10
10
f − Frequency − Hz
Figure 27
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
†‡
†
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4
3
4
10
10
10
V
V
V
= 5 V
= 2.5 V
= 1 V to 4 V
V
V
V
= 5 V
= 0 V
DD
IC
O
DD
IC
O
=
4 V
R
= 1 MΩ
L
R
= 1 MΩ
L
3
10
R
= 50 kΩ
L
R
= 50 kΩ
L
2
1
2
10
10
10
R
= 10 kΩ
L
R
= 10 kΩ
L
1
10
−75 −50 −25
0
25
50
75
100 125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 28
Figure 29
‡
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
1000
100
10
1000
100
10
V
T
= 5 V
= 25°C
V
T
= 5 V
DD
A
DD
= 25°C
A
A
= 100
V
A
V
= 100
A
= 10
= 1
V
A
= 10
= 1
V
1
1
A
V
A
V
0.1
10
0.1
10
2
3
10
4
5
10
6
10
2
3
10
4
5
10
6
10
10
f − Frequency − Hz
10
f − Frequency − Hz
Figure 30
Figure 31
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For curves where V = 5 V, all loads are referenced to 2.5 V.
DD
21
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ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
ꢎ
ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†‡
†
COMMON-MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
90
100
V
DD
= 5 V
V
DD
= 5 V
80
60
40
20
0
88
86
84
V
DD
= 5 V
V
DD
= 5 V
82
80
1
10
2
10
3
10
4
10
5
10
6
10
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 32
Figure 33
†
SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
80
60
40
20
100
80
60
40
20
V
T
A
= 5 V
= 25°C
DD
V
T
A
=
5 V
DD
= 25°C
k
k
SVR+
SVR+
k
k
SVR−
SVR−
0
0
−20
−20
1
2
10
3
10
4
10
5
10
6
10
10
1
2
10
3
10
4
10
5
10
6
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 34
Figure 35
†
‡
For curves where V
= 5 V, all loads are referenced to 2.5 V.
DD
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
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ꢛ
ꢊ
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ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TLC2262
SUPPLY CURRENT
†
†
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
600
500
400
300
200
100
0
110
105
V
= 0
O
V
V
=
2.2 V to 8 V
DD
= 0
No Load
O
T
= −55°C
A
T
= 25°C
A
T
= 125°C
A
T
= 40°C
A
100
95
90
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75
100 125
| V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 36
Figure 37
TLC2264
SUPPLY CURRENT
TLC2262
SUPPLY CURRENT
vs
†
†‡
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
1200
1000
800
600
400
200
0
600
500
400
300
200
100
0
V
= 0
O
No Load
V
= 5 V
DD
= 0
T
= −55°C
V
O
A
T
= 25°C
A
T
= 125°C
V
V
= 5 V
A
DD
= 2.5 V
T
= 40°C
A
O
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75 100 125
| V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 38
Figure 39
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For curves where V = 5 V, all loads are referenced to 2.5 V.
DD
23
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ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
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ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TLC2264
SUPPLY CURRENT
vs
†‡
‡
SLEW RATE
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
1
1200
1000
800
600
400
200
0
V
= 5 V
DD
= −1
A
V
A
T
= 25°C
V
V
=
5 V
DD
= 0
0.8
0.6
O
SR−
V
V
= 5 V
DD
= 2.5 V
O
SR+
0.4
0.2
0
1
2
10
3
10
4
10
−75 −50 −25
0 25
50
75 100 125
10
T
A
− Free-Air Temperature − °C
C
− Load Capacitance − pF
L
Figure 40
Figure 41
†‡
SLEW RATE
INVERTING LARGE-SIGNAL PULSE
vs
‡
RESPONSE
FREE-AIR TEMPERATURE
5
4
1.2
1
V
R
C
= 5 V
= 50 kΩ
= 100 pF
= −1
DD
L
L
A
V
A
T
= 25°C
SR−
SR+
0.8
0.6
0.4
0.2
0
3
2
V
R
C
= 5 V
DD
L
L
1
0
= 50 kΩ
= 100 pF
= 1
A
V
0
2
4
6
8
10 12 14 16 18 20
−75 −50 −25
0
25
50
75
100 125
t − Time − µs
T
A
− Free-Air Temperature − °C
Figure 42
Figure 43
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For curves where V = 5 V, all loads are referenced to 2.5 V.
DD
24
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ꢛ
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ꢍ
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ꢋ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
INVERTING LARGE-SIGNAL PULSE
RESPONSE
†
PULSE RESPONSE
5
4
5
4
V
= 5 V
V
= 5 V
DD
L
L
DD
L
L
R
C
A
= 50 kΩ
= 100 pF
= 1
R
C
A
= 50 kΩ
= 100 pF
= −1
3
V
A
V
A
T
= 25°C
T
= 25°C
2
3
2
1
0
−1
−2
−3
1
0
−4
−5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 44
Figure 45
INVERTING SMALL-SIGNAL
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
†
PULSE RESPONSE
2.65
2.6
5
4
V
= 5 V
V
R
= 5 V
DD
L
L
DD
L
L
R
C
A
= 50 kΩ
= 100 pF
= 1
= 50 kΩ
= 100 pF
= −1
C
A
3
V
A
V
A
T
= 25°C
T
= 25°C
2
2.55
2.5
1
0
−1
−2
−3
2.45
2.4
−4
−5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 46
Figure 47
†
For curves where V
DD
= 5 V, all loads are referenced to 2.5 V.
25
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ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
ꢎ
ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER SMALL-SIGNAL
†
PULSE RESPONSE
100
50
0
2.65
2.6
V
= 5 V
V
= 5 V
DD
L
L
DD
L
L
R
C
A
= 50 kΩ
= 100 pF
= −1
R
C
A
= 50 kΩ
= 100 pF
= 1
V
A
V
A
T
= 25°C
T
= 25°C
2.55
2.5
−50
2.45
2.4
−100
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 48
Figure 49
†
EQUIVALENT INPUT NOISE VOLTAGE
vs
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
FREQUENCY
60
50
40
30
20
10
100
50
V
R
C
= 5 V
V
= 5 V
= 20 Ω
= 25°C
DD
L
L
DD
S
= 50 kΩ
= 100 pF
= 1
R
T
A
A
V
A
T
= 25°C
0
−50
0
10
−100
1
2
10
3
10
4
10
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
f − Frequency − Hz
Figure 50
Figure 51
†
For curves where V
= 5 V, all loads are referenced to 2.5 V.
DD
26
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ꢛ
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ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE OVER
vs
†
A 10-SECOND PERIOD
FREQUENCY
1000
750
500
250
0
60
50
V
=
5 V
DD
S
R
T
= 20 Ω
= 25°C
A
40
30
−250
−500
20
10
0
V
= 5 V
DD
f = 0.1 Hz to 10 Hz
−750
T
A
= 25°C
−1000
0
2
4
6
8
10
1
2
10
3
10
4
10
10
t − Time − s
f − Frequency − Hz
Figure 52
Figure 53
†
TOTAL HARMONIC DISTORTION PLUS NOISE
INTEGRATED NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
0.1
100
Calculated Using Ideal Pass-Band Filter
Low Frequency = 1 Hz
A
V
= 100
T
= 25°C
A
10
0.01
A
= 10
= 1
V
1
A
V
V
R
T
A
= 5 V
= 50 kΩ
= 25°C
DD
L
0.001
0.1
10
1
2
10
3
4
10
5
10
10
10
f − Frequency − Hz
0
1
10
2
3
4
10
5
10
10
10
f − Frequency − Hz
Figure 54
Figure 55
†
For curves where V
DD
= 5 V, all loads are referenced to 2.5 V.
27
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ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
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ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†‡
GAIN-BANDWIDTH PRODUCT
GAIN-BANDWIDTH PRODUCT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
1200
1000
940
900
860
f = 10 kHz
V
= 5 V
DD
f = 10 kHz
= 100 pF
R
C
T
= 50 kΩ
L
L
= 100 pF
C
L
= 25°C
A
800
600
820
780
740
400
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75
100 125
| V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 56
Figure 57
GAIN MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
LOAD CAPACITANCE
20
15
10
75°
T
A
= 25°C
T
A
= 25°C
60°
45°
30°
R
= 100 Ω
null
R
= 100 Ω
null
R
= 50 Ω
null
R
= 50 Ω
null
R
= 20 Ω
null
50 kΩ
R
= 20 Ω
5
0
null
V
15°
0°
DD +
R
= 10 Ω
null
50 kΩ
R
null
V
−
+
I
R
= 10 Ω
C
null
L
R
= 0
null
V
R
= 0
DD −
null
1
2
3
4
10
10
10
10
1
2
3
4
10
10
10
10
C
− Load Capacitance − pF
L
C
− Load Capacitance − pF
L
Figure 58
Figure 59
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For curves where V = 5 V, all loads are referenced to 2.5 V.
DD
28
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ꢋ
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
†
†
UNITY-GAIN BANDWIDTH
vs
OVERESTIMATION OF PHASE MARGIN
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
14°
T
A
= 25°C
T = 25°C
A
12°
10°
8°
R
= 100 Ω
null
800
600
400
200
R
= 50 Ω
null
6°
4°
2°
0
R
= 10 Ω
null
R
= 20 Ω
null
1
10
2
3
4
10
1
10
2
3
4
10
10
10
10
10
C
− Load Capacitance − pF
C
− Load Capacitance − pF
L
L
Figure 60
Figure 61
†
See application information
29
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SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
driving large capacitive loads
The TLC226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 58
and Figure 59 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (R
= 0).
null
A smaller series resistor (R ) at the output of the device (see Figure 62) improves the gain and phase margins
null
when driving large capacitive loads. Figure 58 and Figure 59 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
–1
ǒ2 × π × UGBW × R
LǓ
∆Θ
+ tan
× C
(1)
m1
null
Where :
∆Θ
+ improvement inphasemargin
m1
UGBW + unity-gainbandwidthfrequency
R
+ output seriesresistance
+ loadcapacitance
null
C
L
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 60). To
use equation 1, UGBW must be approximated from Figure 60.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 61. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
1
F +
(2)
1 ) g × R
m
null
Where :
F + factor reducingfrequencyof pole
–3
g
+ small-signaloutput transconductance (typically 4.83 × 10 mhos)
+ output series resistance
m
R
null
For the TLC226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with C : at C = 10 pF, use 70 MHz, at C = 1000 pF, use 700 kHz, and so on.
L
L
L
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation in equation 1 to better approximate the
improvement in phase margin.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢊ
ꢆ
ꢇ
ꢈ
ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
ꢎ
ꢓ ꢗꢘꢕ ꢊꢀ ꢖꢓ ꢙꢊꢁ ꢊꢒ ꢗ ꢁꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
ꢒ
ꢓ
ꢔ
ꢕꢊꢖ ꢁꢆ ꢀꢓ ꢆꢕ ꢊ ꢖꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
driving large capacitive loads (continued)
ȱUGBW
ȳ
UGBW
–1
–1ȧ
ȧ
∆Θ
+ tan
– tan ǒ Ǔ
(3)
m2
P
ǒF×P
Ǔ
2
Ȳ
2 ȴ
Where :
∆Θ
+ reduction in phase margin
m2
UGBW + unity-gain bandwidth frequency
F + factor from equation 2
P
+ unadjusted pole (70 MHz@10 pF, 7 MHz@100 pF, etc.)
2
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
50 kΩ
V
DD+
50 kΩ
R
null
V
I
−
+
C
L
V
DD−/GND
Figure 62. Series-Resistance Circuit
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇꢈꢉ ꢀ ꢁ ꢂꢃ ꢃ ꢄ ꢅ ꢊꢆꢇ ꢈ
ꢛ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢁ
ꢑ
ꢎ
ꢓꢗ ꢘ ꢕꢊꢀ ꢖ ꢓꢙ ꢊ ꢁ ꢊꢒ ꢗꢁ ꢖ ꢚꢖ ꢘꢕ ꢔ
ꢂ
ꢒ
ꢓ
ꢔ
ꢕꢊ ꢖ ꢁꢆꢀꢓ ꢆꢕꢊꢖ ꢁ
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 63 are generated using
the TLC226x typical electrical and operating characteristics at T = 25°C. Using this information, output
A
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
DLN
3
EGND
+
−
V
CC+
92
9
FB
+
91
90
RSS
ISS
RO2
−
+
−
+
VB
DLP
RP
2
VLP
VLN
HLIM
−
+
−
10
+
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
−
DE
VAD
5
54
V
CC−
−
+
4
VE
OUT
.SUBCKT TLC226x 1 2 3 4 5
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
60
60
8
11
12
5
21.22E3
21.22E3
120
C1
11
6
12
7
3.560E−12
C2
15.00E−12
DC
5
53
5
DX
DX
DX
DX
DX
7
99
4
120
DE
54
90
92
4
3
26.04E3
24.24E6
−.6
DLP
DLN
DP
91
90
3
10
60
9
99
4
0
DC 0
EGND
FB
99
7
0
99
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
3
53
4
DC .65
DC .65
DC 0
54
7
+ VLN 0 21.04E6 −30E6 30E6 30E6 −30E6
VLIM
VLP
VLN
8
GA
6
0
6
11
10
12 47.12E−6
99 4.9E−9
91
0
0
DC 1.4
DC 9.4
GCM
ISS
HLIM
J1
0
92
3
10
0
DC 8.250E−6
VLIM 1K
10 JX
10 JX
100.0E3
.MODEL DX D (IS=800.0E−18)
90
11
12
6
.MODEL JX PJF (IS=500.0E−15 BETA=281E−6
2
1
+ VTO=−.065)
.ENDS
J2
R2
9
Figure 63. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLC2264AQPWRG4Q1
TLC2264AQPWRQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2264A-Q1 :
Catalog: TLC2264A
•
Military: TLC2264AM
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2010
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 2
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